[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2013-05-20  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
	* ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
	XLS_MASK, PPCVSX2): New defines.
	(powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
	fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
	mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
	mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
	mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
	vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
	vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
	vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
	vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
	vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
	vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
	vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
	vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
	vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
	xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
	xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
	xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
	xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
	<lxvx, stxvx>: New extended mnemonics.

2013-05-17  Alan Modra  <amodra@gmail.com>

	* ia64-raw.tbl: Replace non-ASCII char.
	* ia64-waw.tbl: Likewise.
	* ia64-asmtab.c: Regenerate.

2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>

	* i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
	* i386-init.h: Regenerated.

2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
	* aarch64-opc.c (operand_general_constraint_met_p): Relax the range
	check from [0, 255] to [-128, 255].

2013-05-09  Andrew Pinski  <apinski@cavium.com>

	* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
	Add INSN_VIRT and INSN_VIRT64 to mips64r2.
	(parse_mips_dis_option): Handle the virt option.
	(print_insn_args): Handle "+J".
	(print_mips_disassembler_options): Print out message about virt64.
	* mips-opc.c (IVIRT): New define.
	(IVIRT64): New define.
	(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
	tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
	Move rfe to the bottom as it conflicts with tlbgp.

2013-05-09  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (extract_vlesi): Properly sign extend.
	(extract_vlensi): Likewise.  Comment reason for setting invalid.

2013-05-02  Nick Clifton  <nickc@redhat.com>

	* msp430-dis.c: Add support for MSP430X instructions.

2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>

	* nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
	to "eccinj".

2013-04-17  Wei-chen Wang  <cole945@gmail.com>

	PR binutils/15369
	* cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
	of CGEN_CPU_ENDIAN.
	(hash_insns_list): Likewise.

2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>

	* rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
	warning workaround.

2013-04-08  Jan Beulich <jbeulich@suse.com>

	* i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
	* i386-tbl.h: Re-generate.

2013-04-06  David S. Miller  <davem@davemloft.net>

	* sparc-dis.c (compare_opcodes): When encountering multiple aliases
	of an opcode, prefer the one with F_PREFERRED set.
	* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
	lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
	ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
	mark existing mnenomics as aliases.  Add "cc" suffix to edge
	instructions generating condition codes, mark existing mnenomics
	as aliases.  Add "fp" prefix to VIS compare instructions, mark
	existing mnenomics as aliases.

2013-04-03  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
	destination address by subtracting the operand from the current
	address.
	* v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
	a positive value in the insn.
	(extract_u16_loop): Do not negate the returned value.
	(D16_LOOP): Add V850_INVERSE_PCREL flag.

	(ceilf.sw): Remove duplicate entry.
	(cvtf.hs): New entry.
	(cvtf.sh): Likewise.
	(fmaf.s): Likewise.
	(fmsf.s): Likewise.
	(fnmaf.s): Likewise.
	(fnmsf.s): Likewise.
	(maddf.s): Restrict to E3V5 architectures.
	(msubf.s): Likewise.
	(nmaddf.s): Likewise.
	(nmsubf.s): Likewise.

2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (get_sib): Add the sizeflag argument.  Properly
	check address mode.
	(print_insn): Pass sizeflag to get_sib.

2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>

	PR binutils/15068
	* tic6x-dis.c: Add support for displaying 16-bit insns.

2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>

	PR gas/15095
	* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
	individual msb and lsb halves in src1 & src2 fields.  Discard the
	src1 (lsb) value and only use src2 (msb), discarding bit 0, to
	follow what Ti SDK does in that case as any value in the src1
	field yields the same output with SDK disassembler.

2013-03-12  Michael Eager <eager@eagercon.com>

	* opcodes/mips-dis.c (print_insn_args): Modify def of reg.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.

2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	(thumb32_opcodes): Likewise.
	(print_insn_thumb32): Handle 'S' control char.

2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>

	* lm32-desc.c: Regenerate.

2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-reg.tbl (riz): Add RegRex64.
	* i386-tbl.h: Regenerated.

2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	(aarch64_feature_crc): New static.
	(CRC): New macro.
	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Ditto.
	* aarch64-opc-2.c: Ditto.

2013-02-27  Alan Modra  <amodra@gmail.com>

	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	* rl78-decode.c: Regenerate.

2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>

	* rl78-decode.opc: Fix encoding of DIVWU insn.
	* rl78-decode.c: Regenerate.

2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/15159
	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.

	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	(cpu_flags): Add CpuSMAP.

	* i386-opc.h (CpuSMAP): New.
	(i386_cpu_flags): Add cpusmap.

	* i386-opc.tbl: Add clac and stac.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>

	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	which also makes the disassembler output be in little
	endian like it should be.

2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	fields to NULL.
	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.

2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	section disassembled.

2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c: Update strht pattern.

2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	single-float.  Disable ll, lld, sc and scd for EE.  Disable the
	trunc.w.s macro for EE.

2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
            Andrew Jenner <andrew@codesourcery.com>

	Based on patches from Altera Corporation.

	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	nios2-opc.c.
	* Makefile.in: Regenerated.
	* configure.in: Add case for bfd_nios2_arch.
	* configure: Regenerated.
	* disassemble.c (ARCH_nios2): Define.
	(disassembler): Add case for bfd_arch_nios2.
	* nios2-dis.c: New file.
	* nios2-opc.c: New file.

2013-02-04  Alan Modra  <amodra@gmail.com>

	* po/POTFILES.in: Regenerate.
	* rl78-decode.c: Regenerate.
	* rx-decode.c: Regenerate.

2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
	* aarch64-asm.c (convert_xtl_to_shll): New function.
	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_xtl_to_shll.
	* aarch64-dis.c (convert_shll_to_xtl): New function.
	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_shll_to_xtl.
	* aarch64-gen.c: Update copyright year.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Re-generate.
	* aarch64-opc-2.c: Re-generate.

2013-01-24  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c: Add support for e3v5 architecture.
	* v850-opc.c: Likewise.

2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): For
	AARCH64_MOD_LSL, move the range check on the shift amount before the
	alignment check; change to call set_sft_amount_out_of_range_error
	instead of set_imm_out_of_range_error.
	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	SIMD_IMM_SFT.

2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-01-15  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	values.
	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.

2013-01-14  Will Newton <will.newton@imgtec.com>

	* metag-dis.c (REG_WIDTH): Increase to 64.

2013-01-10  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	(SH6): Update.
	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.

2013-01-10  Will Newton <will.newton@imgtec.com>

	* Makefile.am: Add Meta.
	* configure.in: Add Meta.
	* disassemble.c: Add Meta support.
	* metag-dis.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	(match_opcode): Rename to cr16_match_opcode.

2013-01-04  Juergen Urban <JuergenUrban@gmx.de>

	* mips-dis.c: Add names for CP0 registers of r5900.
	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	instructions sq and lq.
	Add support for MIPS r5900 CPU.
	Add support for 128 bit MMI (Multimedia Instructions).
	Add support for EE instructions (Emotion Engine).
	Disable unsupported floating point instructions (64 bit and
	undefined compare operations).
	Enable instructions of MIPS ISA IV which are supported by r5900.
	Disable 64 bit co processor instructions.
	Disable 64 bit multiplication and division instructions.
	Disable instructions for co-processor 2 and 3, because these are
	not supported (preparation for later VU0 support (Vector Unit)).
	Disable cvt.w.s because this behaves like trunc.w.s and the
	correct execution can't be ensured on r5900.
	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	will confuse less developers and compilers.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Change to print
	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	in comment.
	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	OP_MOV_IMM_WIDE.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.

2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright year to 2013.

2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (match_opcode,make_instruction): Remove static
	declaration.
	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.

For older changes see ChangeLog-2012
\f
Copyright (C) 2013 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
c0637f3a PB	1	2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
	2
	3	* ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
	4	* ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
	5	XLS_MASK, PPCVSX2): New defines.
	6	(powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
	7	fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
	8	mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
	9	mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
	10	mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
	11	vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
	12	vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
	13	vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
	14	vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
	15	vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
	16	vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
	17	vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
	18	vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
	19	vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
	20	xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
	21	xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
	22	xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
	23	xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
	24	<lxvx, stxvx>: New extended mnemonics.
	25
4934fdaf AM	26	2013-05-17 Alan Modra <amodra@gmail.com>
	27
	28	* ia64-raw.tbl: Replace non-ASCII char.
	29	* ia64-waw.tbl: Likewise.
	30	* ia64-asmtab.c: Regenerate.
	31
6091d651 SE	32	2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
	33
	34	* i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
	35	* i386-init.h: Regenerated.
	36
d2865ed3 YZ	37	2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
	38
	39	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
	40	* aarch64-opc.c (operand_general_constraint_met_p): Relax the range
	41	check from [0, 255] to [-128, 255].
	42
b015e599 AP	43	2013-05-09 Andrew Pinski <apinski@cavium.com>
	44
	45	* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
	46	Add INSN_VIRT and INSN_VIRT64 to mips64r2.
	47	(parse_mips_dis_option): Handle the virt option.
	48	(print_insn_args): Handle "+J".
	49	(print_mips_disassembler_options): Print out message about virt64.
	50	* mips-opc.c (IVIRT): New define.
	51	(IVIRT64): New define.
	52	(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
	53	tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
	54	Move rfe to the bottom as it conflicts with tlbgp.
	55
9f0682fe AM	56	2013-05-09 Alan Modra <amodra@gmail.com>
	57
	58	* ppc-opc.c (extract_vlesi): Properly sign extend.
	59	(extract_vlensi): Likewise. Comment reason for setting invalid.
	60
13761a11 NC	61	2013-05-02 Nick Clifton <nickc@redhat.com>
	62
	63	* msp430-dis.c: Add support for MSP430X instructions.
	64
e3031850 SL	65	2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
	66
	67	* nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
	68	to "eccinj".
	69
17310e56 NC	70	2013-04-17 Wei-chen Wang <cole945@gmail.com>
	71
	72	PR binutils/15369
	73	* cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
	74	of CGEN_CPU_ENDIAN.
	75	(hash_insns_list): Likewise.
	76
731df338 JK	77	2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
	78
	79	* rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
	80	warning workaround.
	81
5f77db52 JB	82	2013-04-08 Jan Beulich <jbeulich@suse.com>
	83
	84	* i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
	85	* i386-tbl.h: Re-generate.
	86
0afd1215 DM	87	2013-04-06 David S. Miller <davem@davemloft.net>
	88
	89	* sparc-dis.c (compare_opcodes): When encountering multiple aliases
	90	of an opcode, prefer the one with F_PREFERRED set.
	91	* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
	92	lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
	93	ops. Make 64-bit VIS logical ops have "d" suffix in their names,
	94	mark existing mnenomics as aliases. Add "cc" suffix to edge
	95	instructions generating condition codes, mark existing mnenomics
	96	as aliases. Add "fp" prefix to VIS compare instructions, mark
	97	existing mnenomics as aliases.
	98
41702d50 NC	99	2013-04-03 Nick Clifton <nickc@redhat.com>
	100
	101	* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
	102	destination address by subtracting the operand from the current
	103	address.
	104	* v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
	105	a positive value in the insn.
	106	(extract_u16_loop): Do not negate the returned value.
	107	(D16_LOOP): Add V850_INVERSE_PCREL flag.
	108
	109	(ceilf.sw): Remove duplicate entry.
	110	(cvtf.hs): New entry.
	111	(cvtf.sh): Likewise.
	112	(fmaf.s): Likewise.
	113	(fmsf.s): Likewise.
	114	(fnmaf.s): Likewise.
	115	(fnmsf.s): Likewise.
	116	(maddf.s): Restrict to E3V5 architectures.
	117	(msubf.s): Likewise.
	118	(nmaddf.s): Likewise.
	119	(nmsubf.s): Likewise.
	120
55cf16e1 L	121	2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
	122
	123	* i386-dis.c (get_sib): Add the sizeflag argument. Properly
	124	check address mode.
	125	(print_insn): Pass sizeflag to get_sib.
	126
51dcdd4d NC	127	2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
	128
	129	PR binutils/15068
	130	* tic6x-dis.c: Add support for displaying 16-bit insns.
	131
795b8e6b NC	132	2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
	133
	134	PR gas/15095
	135	* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
	136	individual msb and lsb halves in src1 & src2 fields. Discard the
	137	src1 (lsb) value and only use src2 (msb), discarding bit 0, to
	138	follow what Ti SDK does in that case as any value in the src1
	139	field yields the same output with SDK disassembler.
	140
314d60dd ME	141	2013-03-12 Michael Eager <eager@eagercon.com>
314d60dd ME	142
795b8e6b	143	* opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd	144
dad60f8e SL	145	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	146
	147	* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
	148
f5cb796a SL	149	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	150
	151	* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
	152
21fde85c SL	153	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	154
	155	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
	156
dd5181d5 KT	157	2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	158
	159	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	160	(thumb32_opcodes): Likewise.
	161	(print_insn_thumb32): Handle 'S' control char.
	162
87a8d6cb NC	163	2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
	164
	165	* lm32-desc.c: Regenerate.
	166
99dce992 L	167	2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
	168
	169	* i386-reg.tbl (riz): Add RegRex64.
	170	* i386-tbl.h: Regenerated.
	171
e60bb1dd YZ	172	2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
	173
	174	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	175	(aarch64_feature_crc): New static.
	176	(CRC): New macro.
	177	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	178	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	179	* aarch64-asm-2.c: Re-generate.
	180	* aarch64-dis-2.c: Ditto.
	181	* aarch64-opc-2.c: Ditto.
	182
c7570fcd AM	183	2013-02-27 Alan Modra <amodra@gmail.com>
	184
	185	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	186	* rl78-decode.c: Regenerate.
	187
151fa98f NC	188	2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
	189
	190	* rl78-decode.opc: Fix encoding of DIVWU insn.
	191	* rl78-decode.c: Regenerate.
	192
5c111e37 L	193	2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
	194
	195	PR gas/15159
	196	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
	197
	198	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	199	(cpu_flags): Add CpuSMAP.
	200
	201	* i386-opc.h (CpuSMAP): New.
	202	(i386_cpu_flags): Add cpusmap.
	203
	204	* i386-opc.tbl: Add clac and stac.
	205
	206	* i386-init.h: Regenerated.
	207	* i386-tbl.h: Likewise.
	208
9d1df426 NC	209	2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
	210
	211	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	212	which also makes the disassembler output be in little
	213	endian like it should be.
	214
a1ccaec9 YZ	215	2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
	216
	217	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	218	fields to NULL.
	219	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
	220
ef068ef4	221	2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e MR	222
	223	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	224	section disassembled.
	225
6fe6ded9 RE	226	2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	227
	228	* arm-dis.c: Update strht pattern.
	229
0aa27725 RS	230	2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
	231
	232	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	233	single-float. Disable ll, lld, sc and scd for EE. Disable the
	234	trunc.w.s macro for EE.
	235
36591ba1 SL	236	2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
	237	Andrew Jenner <andrew@codesourcery.com>
	238
	239	Based on patches from Altera Corporation.
	240
	241	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	242	nios2-opc.c.
	243	* Makefile.in: Regenerated.
	244	* configure.in: Add case for bfd_nios2_arch.
	245	* configure: Regenerated.
	246	* disassemble.c (ARCH_nios2): Define.
	247	(disassembler): Add case for bfd_arch_nios2.
	248	* nios2-dis.c: New file.
	249	* nios2-opc.c: New file.
	250
545093a4 AM	251	2013-02-04 Alan Modra <amodra@gmail.com>
	252
	253	* po/POTFILES.in: Regenerate.
	254	* rl78-decode.c: Regenerate.
	255	* rx-decode.c: Regenerate.
	256
e30181a5 YZ	257	2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
	258
	259	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	260	ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
	261	* aarch64-asm.c (convert_xtl_to_shll): New function.
	262	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	263	calling convert_xtl_to_shll.
	264	* aarch64-dis.c (convert_shll_to_xtl): New function.
	265	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	266	calling convert_shll_to_xtl.
	267	* aarch64-gen.c: Update copyright year.
	268	* aarch64-asm-2.c: Re-generate.
	269	* aarch64-dis-2.c: Re-generate.
	270	* aarch64-opc-2.c: Re-generate.
	271
78c8d46c NC	272	2013-01-24 Nick Clifton <nickc@redhat.com>
	273
	274	* v850-dis.c: Add support for e3v5 architecture.
	275	* v850-opc.c: Likewise.
	276
f5555712 YZ	277	2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
	278
	279	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	280	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	281	* aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c	282	AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712 YZ	283	alignment check; change to call set_sft_amount_out_of_range_error
	284	instead of set_imm_out_of_range_error.
	285	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	286	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	287	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	288	SIMD_IMM_SFT.
	289
2f81ff92 L	290	2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
	291
	292	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
	293
	294	* i386-init.h: Regenerated.
	295	* i386-tbl.h: Likewise.
	296
dd42f060 NC	297	2013-01-15 Nick Clifton <nickc@redhat.com>
	298
	299	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	300	values.
	301	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
	302
a4533ed8 NC	303	2013-01-14 Will Newton <will.newton@imgtec.com>
	304
	305	* metag-dis.c (REG_WIDTH): Increase to 64.
	306
5817ffd1 PB	307	2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
	308
	309	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	310	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	311	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	312	(SH6): Update.
	313	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	314	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	315	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	316	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
	317
a3c62988 NC	318	2013-01-10 Will Newton <will.newton@imgtec.com>
	319
	320	* Makefile.am: Add Meta.
	321	* configure.in: Add Meta.
	322	* disassemble.c: Add Meta support.
	323	* metag-dis.c: New file.
	324	* Makefile.in: Regenerate.
	325	* configure: Regenerate.
	326
73335eae NC	327	2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
	328
	329	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	330	(match_opcode): Rename to cr16_match_opcode.
	331
e407c74b NC	332	2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
	333
	334	* mips-dis.c: Add names for CP0 registers of r5900.
	335	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	336	instructions sq and lq.
	337	Add support for MIPS r5900 CPU.
	338	Add support for 128 bit MMI (Multimedia Instructions).
	339	Add support for EE instructions (Emotion Engine).
	340	Disable unsupported floating point instructions (64 bit and
	341	undefined compare operations).
	342	Enable instructions of MIPS ISA IV which are supported by r5900.
	343	Disable 64 bit co processor instructions.
	344	Disable 64 bit multiplication and division instructions.
	345	Disable instructions for co-processor 2 and 3, because these are
	346	not supported (preparation for later VU0 support (Vector Unit)).
	347	Disable cvt.w.s because this behaves like trunc.w.s and the
	348	correct execution can't be ensured on r5900.
	349	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	350	will confuse less developers and compilers.
	351
a32c3ff8 NC	352	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
a32c3ff8 NC	353
fb098a1e YZ	354	* aarch64-opc.c (aarch64_print_operand): Change to print
	355	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	356	in comment.
	357	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	358	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	359	OP_MOV_IMM_WIDE.
	360
	361	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
	362
	363	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	364	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8	365
62658407 L	366	2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
	367
	368	* i386-gen.c (process_copyright): Update copyright year to 2013.
	369
bab4becb	370	2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7	371
bab4becb NC	372	* cr16-dis.c (match_opcode,make_instruction): Remove static
	373	declaration.
	374	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	375	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7	376
bab4becb	377	For older changes see ChangeLog-2012
252b5132	378	\f
bab4becb	379	Copyright (C) 2013 Free Software Foundation, Inc.
752937aa NC	380
	381	Copying and distribution of this file, with or without modification,
	382	are permitted in any medium without royalty provided the copyright
	383	notice and this notice are preserved.
	384
252b5132	385	Local Variables:
2f6d2f85 NC	386	mode: change-log
	387	left-margin: 8
	388	fill-column: 74
252b5132 RH	389	version-control: never
252b5132 RH	390	End: