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Remove some superfluous code in corelow.c
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
43e379d7
MC		 12017-05-01 Michael Clark <michaeljclark@mac.com>
2
3 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
4 register.
5
a4ddc54e
MR		 62017-05-02 Maciej W. Rozycki <macro@imgtec.com>
7
8 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
9 and branches and not synthetic data instructions.
10
fe50e98c
BE		 112017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
12
13 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
14
126124cc
CZ		 152017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
16
17 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
18 * arc-opc.c (insert_r13el): New function.
19 (R13_EL): Define.
20 * arc-tbl.h: Add new enter/leave variants.
21
be6a24d8
CZ		 222017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
23
24 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
25
0348fd79
MR		 262017-04-25 Maciej W. Rozycki <macro@imgtec.com>
27
28 * mips-dis.c (print_mips_disassembler_options): Add
29 `no-aliases'.
30
6e3d1f07
MR		 312017-04-25 Maciej W. Rozycki <macro@imgtec.com>
32
33 * mips16-opc.c (AL): New macro.
34 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
35 of "ld" and "lw" as aliases.
36
957f6b39
TC		 372017-04-24 Tamar Christina <tamar.christina@arm.com>
38
39 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
40 arguments.
41
a8cc8a54
AM		 422017-04-22 Alexander Fedotov <alfedotov@gmail.com>
43 Alan Modra <amodra@gmail.com>
44
45 * ppc-opc.c (ELEV): Define.
46 (vle_opcodes): Add se_rfgi and e_sc.
47 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
48 for E200Z4.
49
3ab87b68
JM		 502017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
51
52 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
53
792f174f
NC		 542017-04-21 Nick Clifton <nickc@redhat.com>
55
56 PR binutils/21380
57 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
58 LD3R and LD4R.
59
42742084
AM		 602017-04-13 Alan Modra <amodra@gmail.com>
61
62 * epiphany-desc.c: Regenerate.
63 * fr30-desc.c: Regenerate.
64 * frv-desc.c: Regenerate.
65 * ip2k-desc.c: Regenerate.
66 * iq2000-desc.c: Regenerate.
67 * lm32-desc.c: Regenerate.
68 * m32c-desc.c: Regenerate.
69 * m32r-desc.c: Regenerate.
70 * mep-desc.c: Regenerate.
71 * mt-desc.c: Regenerate.
72 * or1k-desc.c: Regenerate.
73 * xc16x-desc.c: Regenerate.
74 * xstormy16-desc.c: Regenerate.
75
9a85b496
AM		 762017-04-11 Alan Modra <amodra@gmail.com>
77
ef85eab0 78 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 79 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
80 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 81 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
82 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 83 (PPCVSX2): Define as PPC_OPCODE_POWER8.
84 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 85 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 86 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 87
62adc510
AM		 882017-04-10 Alan Modra <amodra@gmail.com>
89
90 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
91 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
92 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
93 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
94
aa808707
PC		 952017-04-09 Pip Cet <pipcet@gmail.com>
96
97 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
98 appropriate floating-point precision directly.
99
ac8f0f72
AM		 1002017-04-07 Alan Modra <amodra@gmail.com>
101
102 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
103 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
104 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
105 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
106 vector instructions with E6500 not PPCVEC2.
107
62ecb94c
PC		 1082017-04-06 Pip Cet <pipcet@gmail.com>
109
110 * Makefile.am: Add wasm32-dis.c.
111 * configure.ac: Add wasm32-dis.c to wasm32 target.
112 * disassemble.c: Add wasm32 disassembler code.
113 * wasm32-dis.c: New file.
114 * Makefile.in: Regenerate.
115 * configure: Regenerate.
116 * po/POTFILES.in: Regenerate.
117 * po/opcodes.pot: Regenerate.
118
f995bbe8
PA		 1192017-04-05 Pedro Alves <palves@redhat.com>
120
121 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
122 * arm-dis.c (parse_arm_disassembler_options): Constify.
123 * ppc-dis.c (powerpc_init_dialect): Constify local.
124 * vax-dis.c (parse_disassembler_options): Constify.
125
b5292032
PD		 1262017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
127
128 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
129 RISCV_GP_SYMBOL.
130
f96bd6c2
PC		 1312017-03-30 Pip Cet <pipcet@gmail.com>
132
133 * configure.ac: Add (empty) bfd_wasm32_arch target.
134 * configure: Regenerate
135 * po/opcodes.pot: Regenerate.
136
f7c514a3
JM		 1372017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
138
139 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
140 OSA2015.
141 * opcodes/sparc-opc.c (asi_table): New ASIs.
142
52be03fd
AM		 1432017-03-29 Alan Modra <amodra@gmail.com>
144
145 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
146 "raw" option.
147 (lookup_powerpc): Don't special case -1 dialect. Handle
148 PPC_OPCODE_RAW.
149 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
150 lookup_powerpc call, pass it on second.
151
9b753937
AM		 1522017-03-27 Alan Modra <amodra@gmail.com>
153
154 PR 21303
155 * ppc-dis.c (struct ppc_mopt): Comment.
156 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
157
c0c31e91
RZ		 1582017-03-27 Rinat Zelig <rinat@mellanox.com>
159
160 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
161 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
162 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
163 (insert_nps_misc_imm_offset): New function.
164 (extract_nps_misc imm_offset): New function.
165 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
166 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
167
2253c8f0
AK		 1682017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
169
170 * s390-mkopc.c (main): Remove vx2 check.
171 * s390-opc.txt: Remove vx2 instruction flags.
172
645d3342
RZ		 1732017-03-21 Rinat Zelig <rinat@mellanox.com>
174
175 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
176 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
177 (insert_nps_imm_offset): New function.
178 (extract_nps_imm_offset): New function.
179 (insert_nps_imm_entry): New function.
180 (extract_nps_imm_entry): New function.
181
4b94dd2d
AM		 1822017-03-17 Alan Modra <amodra@gmail.com>
183
184 PR 21248
185 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
186 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
187 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
188
b416fe87
KC		 1892017-03-14 Kito Cheng <kito.cheng@gmail.com>
190
191 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
192 <c.andi>: Likewise.
193 <c.addiw> Likewise.
194
03b039a5
KC		 1952017-03-14 Kito Cheng <kito.cheng@gmail.com>
196
197 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
198
2c232b83
AW		 1992017-03-13 Andrew Waterman <andrew@sifive.com>
200
201 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
202 <srl> Likewise.
203 <srai> Likewise.
204 <sra> Likewise.
205
86fa6981
L		 2062017-03-09 H.J. Lu <hongjiu.lu@intel.com>
207
208 * i386-gen.c (opcode_modifiers): Replace S with Load.
209 * i386-opc.h (S): Removed.
210 (Load): New.
211 (i386_opcode_modifier): Replace s with load.
212 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
213 and {evex}. Replace S with Load.
214 * i386-tbl.h: Regenerated.
215
c1fe188b
L		 2162017-03-09 H.J. Lu <hongjiu.lu@intel.com>
217
218 * i386-opc.tbl: Use CpuCET on rdsspq.
219 * i386-tbl.h: Regenerated.
220
4b8b687e
PB		 2212017-03-08 Peter Bergner <bergner@vnet.ibm.com>
222
223 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
224 <vsx>: Do not use PPC_OPCODE_VSX3;
225
1437d063
PB		 2262017-03-08 Peter Bergner <bergner@vnet.ibm.com>
227
228 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
229
603555e5
L		 2302017-03-06 H.J. Lu <hongjiu.lu@intel.com>
231
232 * i386-dis.c (REG_0F1E_MOD_3): New enum.
233 (MOD_0F1E_PREFIX_1): Likewise.
234 (MOD_0F38F5_PREFIX_2): Likewise.
235 (MOD_0F38F6_PREFIX_0): Likewise.
236 (RM_0F1E_MOD_3_REG_7): Likewise.
237 (PREFIX_MOD_0_0F01_REG_5): Likewise.
238 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
239 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
240 (PREFIX_0F1E): Likewise.
241 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
242 (PREFIX_0F38F5): Likewise.
243 (dis386_twobyte): Use PREFIX_0F1E.
244 (reg_table): Add REG_0F1E_MOD_3.
245 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
246 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
247 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
248 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
249 (three_byte_table): Use PREFIX_0F38F5.
250 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
251 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
252 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
253 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
254 PREFIX_MOD_3_0F01_REG_5_RM_2.
255 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
256 (cpu_flags): Add CpuCET.
257 * i386-opc.h (CpuCET): New enum.
258 (CpuUnused): Commented out.
259 (i386_cpu_flags): Add cpucet.
260 * i386-opc.tbl: Add Intel CET instructions.
261 * i386-init.h: Regenerated.
262 * i386-tbl.h: Likewise.
263
73f07bff
AM		 2642017-03-06 Alan Modra <amodra@gmail.com>
265
266 PR 21124
267 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
268 (extract_raq, extract_ras, extract_rbx): New functions.
269 (powerpc_operands): Use opposite corresponding insert function.
270 (Q_MASK): Define.
271 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
272 register restriction.
273
65b48a81
PB		 2742017-02-28 Peter Bergner <bergner@vnet.ibm.com>
275
276 * disassemble.c Include "safe-ctype.h".
277 (disassemble_init_for_target): Handle s390 init.
278 (remove_whitespace_and_extra_commas): New function.
279 (disassembler_options_cmp): Likewise.
280 * arm-dis.c: Include "libiberty.h".
281 (NUM_ELEM): Delete.
282 (regnames): Use long disassembler style names.
283 Add force-thumb and no-force-thumb options.
284 (NUM_ARM_REGNAMES): Rename from this...
285 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
286 (get_arm_regname_num_options): Delete.
287 (set_arm_regname_option): Likewise.
288 (get_arm_regnames): Likewise.
289 (parse_disassembler_options): Likewise.
290 (parse_arm_disassembler_option): Rename from this...
291 (parse_arm_disassembler_options): ...to this. Make static.
292 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
293 (print_insn): Use parse_arm_disassembler_options.
294 (disassembler_options_arm): New function.
295 (print_arm_disassembler_options): Handle updated regnames.
296 * ppc-dis.c: Include "libiberty.h".
297 (ppc_opts): Add "32" and "64" entries.
298 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
299 (powerpc_init_dialect): Add break to switch statement.
300 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
301 (disassembler_options_powerpc): New function.
302 (print_ppc_disassembler_options): Use ARRAY_SIZE.
303 Remove printing of "32" and "64".
304 * s390-dis.c: Include "libiberty.h".
305 (init_flag): Remove unneeded variable.
306 (struct s390_options_t): New structure type.
307 (options): New structure.
308 (init_disasm): Rename from this...
309 (disassemble_init_s390): ...to this. Add initializations for
310 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
311 (print_insn_s390): Delete call to init_disasm.
312 (disassembler_options_s390): New function.
313 (print_s390_disassembler_options): Print using information from
314 struct 'options'.
315 * po/opcodes.pot: Regenerate.
316
15c7c1d8
JB		 3172017-02-28 Jan Beulich <jbeulich@suse.com>
318
319 * i386-dis.c (PCMPESTR_Fixup): New.
320 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
321 (prefix_table): Use PCMPESTR_Fixup.
322 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
323 PCMPESTR_Fixup.
324 (vex_w_table): Delete VPCMPESTR{I,M} entries.
325 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
326 Split 64-bit and non-64-bit variants.
327 * opcodes/i386-tbl.h: Re-generate.
328
582e12bf
RS		 3292017-02-24 Richard Sandiford <richard.sandiford@arm.com>
330
331 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
332 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
333 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
334 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
335 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
336 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
337 (OP_SVE_V_HSD): New macros.
338 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
339 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
340 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
341 (aarch64_opcode_table): Add new SVE instructions.
342 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
343 for rotation operands. Add new SVE operands.
344 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
345 (ins_sve_quad_index): Likewise.
346 (ins_imm_rotate): Split into...
347 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
348 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
349 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
350 functions.
351 (aarch64_ins_sve_addr_ri_s4): New function.
352 (aarch64_ins_sve_quad_index): Likewise.
353 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
354 * aarch64-asm-2.c: Regenerate.
355 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
356 (ext_sve_quad_index): Likewise.
357 (ext_imm_rotate): Split into...
358 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
359 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
360 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
361 functions.
362 (aarch64_ext_sve_addr_ri_s4): New function.
363 (aarch64_ext_sve_quad_index): Likewise.
364 (aarch64_ext_sve_index): Allow quad indices.
365 (do_misc_decoding): Likewise.
366 * aarch64-dis-2.c: Regenerate.
367 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
368 aarch64_field_kinds.
369 (OPD_F_OD_MASK): Widen by one bit.
370 (OPD_F_NO_ZR): Bump accordingly.
371 (get_operand_field_width): New function.
372 * aarch64-opc.c (fields): Add new SVE fields.
373 (operand_general_constraint_met_p): Handle new SVE operands.
374 (aarch64_print_operand): Likewise.
375 * aarch64-opc-2.c: Regenerate.
376
f482d304
RS		 3772017-02-24 Richard Sandiford <richard.sandiford@arm.com>
378
379 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
380 (aarch64_feature_compnum): ...this.
381 (SIMD_V8_3): Replace with...
382 (COMPNUM): ...this.
383 (CNUM_INSN): New macro.
384 (aarch64_opcode_table): Use it for the complex number instructions.
385
7db2c588
JB		 3862017-02-24 Jan Beulich <jbeulich@suse.com>
387
388 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
389
1e9d41d4
SL		 3902017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
391
392 Add support for associating SPARC ASIs with an architecture level.
393 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
394 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
395 decoding of SPARC ASIs.
396
53c4d625
JB		 3972017-02-23 Jan Beulich <jbeulich@suse.com>
398
399 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
400 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
401
11648de5
JB		 4022017-02-21 Jan Beulich <jbeulich@suse.com>
403
404 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
405 1 (instead of to itself). Correct typo.
406
f98d33be
AW		 4072017-02-14 Andrew Waterman <andrew@sifive.com>
408
409 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
410 pseudoinstructions.
411
773fb663
RS		 4122017-02-15 Richard Sandiford <richard.sandiford@arm.com>
413
414 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
415 (aarch64_sys_reg_supported_p): Handle them.
416
cc07cda6
CZ		 4172017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
418
419 * arc-opc.c (UIMM6_20R): Define.
420 (SIMM12_20): Use above.
421 (SIMM12_20R): Define.
422 (SIMM3_5_S): Use above.
423 (UIMM7_A32_11R_S): Define.
424 (UIMM7_9_S): Use above.
425 (UIMM3_13R_S): Define.
426 (SIMM11_A32_7_S): Use above.
427 (SIMM9_8R): Define.
428 (UIMM10_A32_8_S): Use above.
429 (UIMM8_8R_S): Define.
430 (W6): Use above.
431 (arc_relax_opcodes): Use all above defines.
432
66a5a740
VG		 4332017-02-15 Vineet Gupta <vgupta@synopsys.com>
434
435 * arc-regs.h: Distinguish some of the registers different on
436 ARC700 and HS38 cpus.
437
7e0de605
AM		 4382017-02-14 Alan Modra <amodra@gmail.com>
439
440 PR 21118
441 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
442 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
443
54064fdb
AM		 4442017-02-11 Stafford Horne <shorne@gmail.com>
445 Alan Modra <amodra@gmail.com>
446
447 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
448 Use insn_bytes_value and insn_int_value directly instead. Don't
449 free allocated memory until function exit.
450
dce75bf9
NP		 4512017-02-10 Nicholas Piggin <npiggin@gmail.com>
452
453 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
454
1b7e3d2f
NC		 4552017-02-03 Nick Clifton <nickc@redhat.com>
456
457 PR 21096
458 * aarch64-opc.c (print_register_list): Ensure that the register
459 list index will fir into the tb buffer.
460 (print_register_offset_address): Likewise.
461 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
462
8ec5cf65
AD		 4632017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
464
465 PR 21056
466 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
467 instructions when the previous fetch packet ends with a 32-bit
468 instruction.
469
a1aa5e81
DD		 4702017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
471
472 * pru-opc.c: Remove vague reference to a future GDB port.
473
add3afb2
NC		 4742017-01-20 Nick Clifton <nickc@redhat.com>
475
476 * po/ga.po: Updated Irish translation.
477
c13a63b0
SN		 4782017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
479
480 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
481
9608051a
YQ		 4822017-01-13 Yao Qi <yao.qi@linaro.org>
483
484 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
485 if FETCH_DATA returns 0.
486 (m68k_scan_mask): Likewise.
487 (print_insn_m68k): Update code to handle -1 return value.
488
f622ea96
YQ		 4892017-01-13 Yao Qi <yao.qi@linaro.org>
490
491 * m68k-dis.c (enum print_insn_arg_error): New.
492 (NEXTBYTE): Replace -3 with
493 PRINT_INSN_ARG_MEMORY_ERROR.
494 (NEXTULONG): Likewise.
495 (NEXTSINGLE): Likewise.
496 (NEXTDOUBLE): Likewise.
497 (NEXTDOUBLE): Likewise.
498 (NEXTPACKED): Likewise.
499 (FETCH_ARG): Likewise.
500 (FETCH_DATA): Update comments.
501 (print_insn_arg): Update comments. Replace magic numbers with
502 enum.
503 (match_insn_m68k): Likewise.
504
620214f7
IT		 5052017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
506
507 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
508 * i386-dis-evex.h (evex_table): Updated.
509 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
510 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
511 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
512 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
513 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
514 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
515 * i386-init.h: Regenerate.
516 * i386-tbl.h: Ditto.
517
d95014a2
YQ		 5182017-01-12 Yao Qi <yao.qi@linaro.org>
519
520 * msp430-dis.c (msp430_singleoperand): Return -1 if
521 msp430dis_opcode_signed returns false.
522 (msp430_doubleoperand): Likewise.
523 (msp430_branchinstr): Return -1 if
524 msp430dis_opcode_unsigned returns false.
525 (msp430x_calla_instr): Likewise.
526 (print_insn_msp430): Likewise.
527
0ae60c3e
NC		 5282017-01-05 Nick Clifton <nickc@redhat.com>
529
530 PR 20946
531 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
532 could not be matched.
533 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
534 NULL.
535
d74d4880
SN		 5362017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
537
538 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
539 (aarch64_opcode_table): Use RCPC_INSN.
540
cc917fd9
KC		 5412017-01-03 Kito Cheng <kito.cheng@gmail.com>
542
543 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
544 extension.
545 * riscv-opcodes/all-opcodes: Likewise.
546
b52d3cfc
DP		 5472017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
548
549 * riscv-dis.c (print_insn_args): Add fall through comment.
550
f90c58d5
NC		 5512017-01-03 Nick Clifton <nickc@redhat.com>
552
553 * po/sr.po: New Serbian translation.
554 * configure.ac (ALL_LINGUAS): Add sr.
555 * configure: Regenerate.
556
f47b0d4a
AM		 5572017-01-02 Alan Modra <amodra@gmail.com>
558
559 * epiphany-desc.h: Regenerate.
560 * epiphany-opc.h: Regenerate.
561 * fr30-desc.h: Regenerate.
562 * fr30-opc.h: Regenerate.
563 * frv-desc.h: Regenerate.
564 * frv-opc.h: Regenerate.
565 * ip2k-desc.h: Regenerate.
566 * ip2k-opc.h: Regenerate.
567 * iq2000-desc.h: Regenerate.
568 * iq2000-opc.h: Regenerate.
569 * lm32-desc.h: Regenerate.
570 * lm32-opc.h: Regenerate.
571 * m32c-desc.h: Regenerate.
572 * m32c-opc.h: Regenerate.
573 * m32r-desc.h: Regenerate.
574 * m32r-opc.h: Regenerate.
575 * mep-desc.h: Regenerate.
576 * mep-opc.h: Regenerate.
577 * mt-desc.h: Regenerate.
578 * mt-opc.h: Regenerate.
579 * or1k-desc.h: Regenerate.
580 * or1k-opc.h: Regenerate.
581 * xc16x-desc.h: Regenerate.
582 * xc16x-opc.h: Regenerate.
583 * xstormy16-desc.h: Regenerate.
584 * xstormy16-opc.h: Regenerate.
585
2571583a
AM		 5862017-01-02 Alan Modra <amodra@gmail.com>
587
588 Update year range in copyright notice of all files.
589
5c1ad6b5 590For older changes see ChangeLog-2016
3499769a 591\f
5c1ad6b5 592Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 593
594Copying and distribution of this file, with or without modification,
595are permitted in any medium without royalty provided the copyright
596notice and this notice are preserved.
597
598Local Variables:
599mode: change-log
600left-margin: 8
601fill-column: 74
602version-control: never
603End:
GDB Binutils - Deliverables
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