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Catch exceptions thrown from gdbarch_skip_prologue
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
7684e580
JW		 12017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
2 Jiong Wang <jiong.wang@arm.com>
3
4 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
5 correct the print.
6 * aarch64-dis-2.c: Regenerated.
7
47826cdb
AK		 82017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
9
10 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
11 table.
12
2d2dbad0
NC		 132017-07-20 Nick Clifton <nickc@redhat.com>
14
15 * po/de.po: Updated German translation.
16
70b448ba 172017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
18
19 * arc-regs.h (sec_stat): New aux register.
20 (aux_kernel_sp): Likewise.
21 (aux_sec_u_sp): Likewise.
22 (aux_sec_k_sp): Likewise.
23 (sec_vecbase_build): Likewise.
24 (nsc_table_top): Likewise.
25 (nsc_table_base): Likewise.
26 (ersec_stat): Likewise.
27 (aux_sec_except): Likewise.
28
7179e0e6
CZ		 292017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
30
31 * arc-opc.c (extract_uimm12_20): New function.
32 (UIMM12_20): New operand.
33 (SIMM3_5_S): Adjust.
34 * arc-tbl.h (sjli): Add new instruction.
35
684d5a10
JEM		 362017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
37 John Eric Martin <John.Martin@emmicro-us.com>
38
39 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
40 (UIMM3_23): Adjust accordingly.
41 * arc-regs.h: Add/correct jli_base register.
42 * arc-tbl.h (jli_s): Likewise.
43
de194d85
YC		 442017-07-18 Nick Clifton <nickc@redhat.com>
45
46 PR 21775
47 * aarch64-opc.c: Fix spelling typos.
48 * i386-dis.c: Likewise.
49
0f6329bd
RB		 502017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
51
52 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
53 max_addr_offset and octets variables to size_t.
54
429d795d
AM		 552017-07-12 Alan Modra <amodra@gmail.com>
56
57 * po/da.po: Update from translationproject.org/latest/opcodes/.
58 * po/de.po: Likewise.
59 * po/es.po: Likewise.
60 * po/fi.po: Likewise.
61 * po/fr.po: Likewise.
62 * po/id.po: Likewise.
63 * po/it.po: Likewise.
64 * po/nl.po: Likewise.
65 * po/pt_BR.po: Likewise.
66 * po/ro.po: Likewise.
67 * po/sv.po: Likewise.
68 * po/tr.po: Likewise.
69 * po/uk.po: Likewise.
70 * po/vi.po: Likewise.
71 * po/zh_CN.po: Likewise.
72
4162bb66
AM		 732017-07-11 Yao Qi <yao.qi@linaro.org>
74 Alan Modra <amodra@gmail.com>
75
76 * cgen.sh: Mark generated files read-only.
77 * epiphany-asm.c: Regenerate.
78 * epiphany-desc.c: Regenerate.
79 * epiphany-desc.h: Regenerate.
80 * epiphany-dis.c: Regenerate.
81 * epiphany-ibld.c: Regenerate.
82 * epiphany-opc.c: Regenerate.
83 * epiphany-opc.h: Regenerate.
84 * fr30-asm.c: Regenerate.
85 * fr30-desc.c: Regenerate.
86 * fr30-desc.h: Regenerate.
87 * fr30-dis.c: Regenerate.
88 * fr30-ibld.c: Regenerate.
89 * fr30-opc.c: Regenerate.
90 * fr30-opc.h: Regenerate.
91 * frv-asm.c: Regenerate.
92 * frv-desc.c: Regenerate.
93 * frv-desc.h: Regenerate.
94 * frv-dis.c: Regenerate.
95 * frv-ibld.c: Regenerate.
96 * frv-opc.c: Regenerate.
97 * frv-opc.h: Regenerate.
98 * ip2k-asm.c: Regenerate.
99 * ip2k-desc.c: Regenerate.
100 * ip2k-desc.h: Regenerate.
101 * ip2k-dis.c: Regenerate.
102 * ip2k-ibld.c: Regenerate.
103 * ip2k-opc.c: Regenerate.
104 * ip2k-opc.h: Regenerate.
105 * iq2000-asm.c: Regenerate.
106 * iq2000-desc.c: Regenerate.
107 * iq2000-desc.h: Regenerate.
108 * iq2000-dis.c: Regenerate.
109 * iq2000-ibld.c: Regenerate.
110 * iq2000-opc.c: Regenerate.
111 * iq2000-opc.h: Regenerate.
112 * lm32-asm.c: Regenerate.
113 * lm32-desc.c: Regenerate.
114 * lm32-desc.h: Regenerate.
115 * lm32-dis.c: Regenerate.
116 * lm32-ibld.c: Regenerate.
117 * lm32-opc.c: Regenerate.
118 * lm32-opc.h: Regenerate.
119 * lm32-opinst.c: Regenerate.
120 * m32c-asm.c: Regenerate.
121 * m32c-desc.c: Regenerate.
122 * m32c-desc.h: Regenerate.
123 * m32c-dis.c: Regenerate.
124 * m32c-ibld.c: Regenerate.
125 * m32c-opc.c: Regenerate.
126 * m32c-opc.h: Regenerate.
127 * m32r-asm.c: Regenerate.
128 * m32r-desc.c: Regenerate.
129 * m32r-desc.h: Regenerate.
130 * m32r-dis.c: Regenerate.
131 * m32r-ibld.c: Regenerate.
132 * m32r-opc.c: Regenerate.
133 * m32r-opc.h: Regenerate.
134 * m32r-opinst.c: Regenerate.
135 * mep-asm.c: Regenerate.
136 * mep-desc.c: Regenerate.
137 * mep-desc.h: Regenerate.
138 * mep-dis.c: Regenerate.
139 * mep-ibld.c: Regenerate.
140 * mep-opc.c: Regenerate.
141 * mep-opc.h: Regenerate.
142 * mt-asm.c: Regenerate.
143 * mt-desc.c: Regenerate.
144 * mt-desc.h: Regenerate.
145 * mt-dis.c: Regenerate.
146 * mt-ibld.c: Regenerate.
147 * mt-opc.c: Regenerate.
148 * mt-opc.h: Regenerate.
149 * or1k-asm.c: Regenerate.
150 * or1k-desc.c: Regenerate.
151 * or1k-desc.h: Regenerate.
152 * or1k-dis.c: Regenerate.
153 * or1k-ibld.c: Regenerate.
154 * or1k-opc.c: Regenerate.
155 * or1k-opc.h: Regenerate.
156 * or1k-opinst.c: Regenerate.
157 * xc16x-asm.c: Regenerate.
158 * xc16x-desc.c: Regenerate.
159 * xc16x-desc.h: Regenerate.
160 * xc16x-dis.c: Regenerate.
161 * xc16x-ibld.c: Regenerate.
162 * xc16x-opc.c: Regenerate.
163 * xc16x-opc.h: Regenerate.
164 * xstormy16-asm.c: Regenerate.
165 * xstormy16-desc.c: Regenerate.
166 * xstormy16-desc.h: Regenerate.
167 * xstormy16-dis.c: Regenerate.
168 * xstormy16-ibld.c: Regenerate.
169 * xstormy16-opc.c: Regenerate.
170 * xstormy16-opc.h: Regenerate.
171
7639175c
AM		 1722017-07-07 Alan Modra <amodra@gmail.com>
173
174 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
175 * m32c-dis.c: Regenerate.
176 * mep-dis.c: Regenerate.
177
e4bdd679
BP		 1782017-07-05 Borislav Petkov <bp@suse.de>
179
180 * i386-dis.c: Enable ModRM.reg /6 aliases.
181
60c96dbf
RR		 1822017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
183
184 * opcodes/arm-dis.c: Support MVFR2 in disassembly
185 with vmrs and vmsr.
186
0d702cfe
TG		 1872017-07-04 Tristan Gingold <gingold@adacore.com>
188
189 * configure: Regenerate.
190
15e6ed8c
TG		 1912017-07-03 Tristan Gingold <gingold@adacore.com>
192
193 * po/opcodes.pot: Regenerate.
194
b1d3c886
MR		 1952017-06-30 Maciej W. Rozycki <macro@imgtec.com>
196
197 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
198 entries to the MSA ASE instruction block.
199
909b4e3d
MR		 2002017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
201 Maciej W. Rozycki <macro@imgtec.com>
202
203 * micromips-opc.c (XPA, XPAVZ): New macros.
204 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
205 "mthgc0".
206
f5b2fd52
MR		 2072017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
208 Maciej W. Rozycki <macro@imgtec.com>
209
210 * micromips-opc.c (I36): New macro.
211 (micromips_opcodes): Add "eretnc".
212
9785fc2a
MR		 2132017-06-30 Maciej W. Rozycki <macro@imgtec.com>
214 Andrew Bennett <andrew.bennett@imgtec.com>
215
216 * mips-dis.c (mips_calculate_combination_ases): Handle the
217 ASE_XPA_VIRT flag.
218 (parse_mips_ase_option): New function.
219 (parse_mips_dis_option): Factor out ASE option handling to the
220 new function. Call `mips_calculate_combination_ases'.
221 * mips-opc.c (XPAVZ): New macro.
222 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
223 "mfhgc0", "mthc0" and "mthgc0".
224
60804c53
MR		 2252017-06-29 Maciej W. Rozycki <macro@imgtec.com>
226
227 * mips-dis.c (mips_calculate_combination_ases): New function.
228 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
229 calculation to the new function.
230 (set_default_mips_dis_options): Call the new function.
231
2e74f9dd
AK		 2322017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
233
234 * arc-dis.c (parse_disassembler_options): Use
235 FOR_EACH_DISASSEMBLER_OPTION.
236
e1e94c49
AK		 2372017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
238
239 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
240 disassembler option strings.
241 (parse_cpu_option): Likewise.
242
65a55fbb
TC		 2432017-06-28 Tamar Christina <tamar.christina@arm.com>
244
245 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
246 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
247 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
248 (aarch64_feature_dotprod, DOT_INSN): New.
249 (udot, sdot): New.
250 * aarch64-dis-2.c: Regenerated.
251
c604a79a
JW		 2522017-06-28 Jiong Wang <jiong.wang@arm.com>
253
254 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
255
38bf472a
MR		 2562017-06-28 Maciej W. Rozycki <macro@imgtec.com>
257 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 258 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 259
260 * mips-formats.h (INT_BIAS): New macro.
261 (INT_ADJ): Redefine in INT_BIAS terms.
262 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
263 (mips_print_save_restore): New function.
264 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
265 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
266 call.
267 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
268 (print_mips16_insn_arg): Call `mips_print_save_restore' for
269 OP_SAVE_RESTORE_LIST handling, factored out from here.
270 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
271 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
272 (mips_builtin_opcodes): Add "restore" and "save" entries.
273 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
274 (IAMR2): New macro.
275 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
276
9bdfdbf9
AW		 2772017-06-23 Andrew Waterman <andrew@sifive.com>
278
279 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
280 alias; do not mark SLTI instruction as an alias.
281
2234eee6
L		 2822017-06-21 H.J. Lu <hongjiu.lu@intel.com>
283
284 * i386-dis.c (RM_0FAE_REG_5): Removed.
285 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
286 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
287 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
288 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
289 PREFIX_MOD_3_0F01_REG_5_RM_0.
290 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
291 PREFIX_MOD_3_0FAE_REG_5.
292 (mod_table): Update MOD_0FAE_REG_5.
293 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
294 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
295 * i386-tbl.h: Regenerated.
296
c2f76402
L		 2972017-06-21 H.J. Lu <hongjiu.lu@intel.com>
298
299 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
300 * i386-opc.tbl: Likewise.
301 * i386-tbl.h: Regenerated.
302
9fef80d6
L		 3032017-06-21 H.J. Lu <hongjiu.lu@intel.com>
304
305 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
306 and "jmp{&|}".
307 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
308 prefix.
309
0f6d864d
NC		 3102017-06-19 Nick Clifton <nickc@redhat.com>
311
312 PR binutils/21614
313 * score-dis.c (score_opcodes): Add sentinel.
314
e197589b
AM		 3152017-06-16 Alan Modra <amodra@gmail.com>
316
317 * rx-decode.c: Regenerate.
318
0d96e4df
L		 3192017-06-15 H.J. Lu <hongjiu.lu@intel.com>
320
321 PR binutils/21594
322 * i386-dis.c (OP_E_register): Check valid bnd register.
323 (OP_G): Likewise.
324
cd3ea7c6
NC		 3252017-06-15 Nick Clifton <nickc@redhat.com>
326
327 PR binutils/21595
328 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
329 range value.
330
63323b5b
NC		 3312017-06-15 Nick Clifton <nickc@redhat.com>
332
333 PR binutils/21588
334 * rl78-decode.opc (OP_BUF_LEN): Define.
335 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
336 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
337 array.
338 * rl78-decode.c: Regenerate.
339
08c7881b
NC		 3402017-06-15 Nick Clifton <nickc@redhat.com>
341
342 PR binutils/21586
343 * bfin-dis.c (gregs): Clip index to prevent overflow.
344 (regs): Likewise.
345 (regs_lo): Likewise.
346 (regs_hi): Likewise.
347
e64519d1
NC		 3482017-06-14 Nick Clifton <nickc@redhat.com>
349
350 PR binutils/21576
351 * score7-dis.c (score_opcodes): Add sentinel.
352
6394c606
YQ		 3532017-06-14 Yao Qi <yao.qi@linaro.org>
354
355 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
356 * arm-dis.c: Likewise.
357 * ia64-dis.c: Likewise.
358 * mips-dis.c: Likewise.
359 * spu-dis.c: Likewise.
360 * disassemble.h (print_insn_aarch64): New declaration, moved from
361 include/dis-asm.h.
362 (print_insn_big_arm, print_insn_big_mips): Likewise.
363 (print_insn_i386, print_insn_ia64): Likewise.
364 (print_insn_little_arm, print_insn_little_mips): Likewise.
365
db5fa770
NC		 3662017-06-14 Nick Clifton <nickc@redhat.com>
367
368 PR binutils/21587
369 * rx-decode.opc: Include libiberty.h
370 (GET_SCALE): New macro - validates access to SCALE array.
371 (GET_PSCALE): New macro - validates access to PSCALE array.
372 (DIs, SIs, S2Is, rx_disp): Use new macros.
373 * rx-decode.c: Regenerate.
374
05c966f3
AV		 3752017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
376
377 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
378
10045478
AK		 3792017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
380
381 * arc-dis.c (enforced_isa_mask): Declare.
382 (cpu_types): Likewise.
383 (parse_cpu_option): New function.
384 (parse_disassembler_options): Use it.
385 (print_insn_arc): Use enforced_isa_mask.
386 (print_arc_disassembler_options): Document new options.
387
88c1242d
YQ		 3882017-05-24 Yao Qi <yao.qi@linaro.org>
389
390 * alpha-dis.c: Include disassemble.h, don't include
391 dis-asm.h.
392 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
393 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
394 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
395 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
396 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
397 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
398 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
399 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
400 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
401 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
402 * moxie-dis.c, msp430-dis.c, mt-dis.c:
403 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
404 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
405 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
406 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
407 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
408 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
409 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
410 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
411 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
412 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
413 * z80-dis.c, z8k-dis.c: Likewise.
414 * disassemble.h: New file.
415
ab20fa4a
YQ		 4162017-05-24 Yao Qi <yao.qi@linaro.org>
417
418 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
419 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
420
003ca0fd
YQ		 4212017-05-24 Yao Qi <yao.qi@linaro.org>
422
423 * disassemble.c (disassembler): Add arguments a, big and mach.
424 Use them.
425
04ef582a
L		 4262017-05-22 H.J. Lu <hongjiu.lu@intel.com>
427
428 * i386-dis.c (NOTRACK_Fixup): New.
429 (NOTRACK): Likewise.
430 (NOTRACK_PREFIX): Likewise.
431 (last_active_prefix): Likewise.
432 (reg_table): Use NOTRACK on indirect call and jmp.
433 (ckprefix): Set last_active_prefix.
434 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
435 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
436 * i386-opc.h (NoTrackPrefixOk): New.
437 (i386_opcode_modifier): Add notrackprefixok.
438 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
439 Add notrack.
440 * i386-tbl.h: Regenerated.
441
64517994
JM		 4422017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
443
444 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
445 (X_IMM2): Define.
446 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
447 bfd_mach_sparc_v9m8.
448 (print_insn_sparc): Handle new operand types.
449 * sparc-opc.c (MASK_M8): Define.
450 (v6): Add MASK_M8.
451 (v6notlet): Likewise.
452 (v7): Likewise.
453 (v8): Likewise.
454 (v9): Likewise.
455 (v9a): Likewise.
456 (v9b): Likewise.
457 (v9c): Likewise.
458 (v9d): Likewise.
459 (v9e): Likewise.
460 (v9v): Likewise.
461 (v9m): Likewise.
462 (v9andleon): Likewise.
463 (m8): Define.
464 (HWS_VM8): Define.
465 (HWS2_VM8): Likewise.
466 (sparc_opcode_archs): Add entry for "m8".
467 (sparc_opcodes): Add OSA2017 and M8 instructions
468 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
469 fpx{ll,ra,rl}64x,
470 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
471 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
472 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
473 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
474 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
475 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
476 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
477 ASI_CORE_SELECT_COMMIT_NHT.
478
535b785f
AM		 4792017-05-18 Alan Modra <amodra@gmail.com>
480
481 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
482 * aarch64-dis.c: Likewise.
483 * aarch64-gen.c: Likewise.
484 * aarch64-opc.c: Likewise.
485
25499ac7
MR		 4862017-05-15 Maciej W. Rozycki <macro@imgtec.com>
487 Matthew Fortune <matthew.fortune@imgtec.com>
488
489 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
490 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
491 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
492 (print_insn_arg) <OP_REG28>: Add handler.
493 (validate_insn_args) <OP_REG28>: Handle.
494 (print_mips16_insn_arg): Handle MIPS16 instructions that require
495 32-bit encoding and 9-bit immediates.
496 (print_insn_mips16): Handle MIPS16 instructions that require
497 32-bit encoding and MFC0/MTC0 operand decoding.
498 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
499 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
500 (RD_C0, WR_C0, E2, E2MT): New macros.
501 (mips16_opcodes): Add entries for MIPS16e2 instructions:
502 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
503 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
504 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
505 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
506 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
507 instructions, "swl", "swr", "sync" and its "sync_acquire",
508 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
509 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
510 regular/extended entries for original MIPS16 ISA revision
511 instructions whose extended forms are subdecoded in the MIPS16e2
512 ISA revision: "li", "sll" and "srl".
513
fdfb4752
MR		 5142017-05-15 Maciej W. Rozycki <macro@imgtec.com>
515
516 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
517 reference in CP0 move operand decoding.
518
a4f89915
MR		 5192017-05-12 Maciej W. Rozycki <macro@imgtec.com>
520
521 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
522 type to hexadecimal.
523 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
524
99e2d67a
MR		 5252017-05-11 Maciej W. Rozycki <macro@imgtec.com>
526
527 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
528 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
529 "sync_rmb" and "sync_wmb" as aliases.
530 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
531 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
532
53a346d8
CZ		 5332017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
534
535 * arc-dis.c (parse_option): Update quarkse_em option..
536 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
537 QUARKSE1.
538 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
539
f91d48de
KC		 5402017-05-03 Kito Cheng <kito.cheng@gmail.com>
541
542 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
543
43e379d7
MC		 5442017-05-01 Michael Clark <michaeljclark@mac.com>
545
546 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
547 register.
548
a4ddc54e
MR		 5492017-05-02 Maciej W. Rozycki <macro@imgtec.com>
550
551 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
552 and branches and not synthetic data instructions.
553
fe50e98c
BE		 5542017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
555
556 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
557
126124cc
CZ		 5582017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
559
560 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
561 * arc-opc.c (insert_r13el): New function.
562 (R13_EL): Define.
563 * arc-tbl.h: Add new enter/leave variants.
564
be6a24d8
CZ		 5652017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
566
567 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
568
0348fd79
MR		 5692017-04-25 Maciej W. Rozycki <macro@imgtec.com>
570
571 * mips-dis.c (print_mips_disassembler_options): Add
572 `no-aliases'.
573
6e3d1f07
MR		 5742017-04-25 Maciej W. Rozycki <macro@imgtec.com>
575
576 * mips16-opc.c (AL): New macro.
577 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
578 of "ld" and "lw" as aliases.
579
957f6b39
TC		 5802017-04-24 Tamar Christina <tamar.christina@arm.com>
581
582 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
583 arguments.
584
a8cc8a54
AM		 5852017-04-22 Alexander Fedotov <alfedotov@gmail.com>
586 Alan Modra <amodra@gmail.com>
587
588 * ppc-opc.c (ELEV): Define.
589 (vle_opcodes): Add se_rfgi and e_sc.
590 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
591 for E200Z4.
592
3ab87b68
JM		 5932017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
594
595 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
596
792f174f
NC		 5972017-04-21 Nick Clifton <nickc@redhat.com>
598
599 PR binutils/21380
600 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
601 LD3R and LD4R.
602
42742084
AM		 6032017-04-13 Alan Modra <amodra@gmail.com>
604
605 * epiphany-desc.c: Regenerate.
606 * fr30-desc.c: Regenerate.
607 * frv-desc.c: Regenerate.
608 * ip2k-desc.c: Regenerate.
609 * iq2000-desc.c: Regenerate.
610 * lm32-desc.c: Regenerate.
611 * m32c-desc.c: Regenerate.
612 * m32r-desc.c: Regenerate.
613 * mep-desc.c: Regenerate.
614 * mt-desc.c: Regenerate.
615 * or1k-desc.c: Regenerate.
616 * xc16x-desc.c: Regenerate.
617 * xstormy16-desc.c: Regenerate.
618
9a85b496
AM		 6192017-04-11 Alan Modra <amodra@gmail.com>
620
ef85eab0 621 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 622 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
623 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 624 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
625 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 626 (PPCVSX2): Define as PPC_OPCODE_POWER8.
627 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 628 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 629 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 630
62adc510
AM		 6312017-04-10 Alan Modra <amodra@gmail.com>
632
633 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
634 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
635 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
636 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
637
aa808707
PC		 6382017-04-09 Pip Cet <pipcet@gmail.com>
639
640 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
641 appropriate floating-point precision directly.
642
ac8f0f72
AM		 6432017-04-07 Alan Modra <amodra@gmail.com>
644
645 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
646 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
647 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
648 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
649 vector instructions with E6500 not PPCVEC2.
650
62ecb94c
PC		 6512017-04-06 Pip Cet <pipcet@gmail.com>
652
653 * Makefile.am: Add wasm32-dis.c.
654 * configure.ac: Add wasm32-dis.c to wasm32 target.
655 * disassemble.c: Add wasm32 disassembler code.
656 * wasm32-dis.c: New file.
657 * Makefile.in: Regenerate.
658 * configure: Regenerate.
659 * po/POTFILES.in: Regenerate.
660 * po/opcodes.pot: Regenerate.
661
f995bbe8
PA		 6622017-04-05 Pedro Alves <palves@redhat.com>
663
664 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
665 * arm-dis.c (parse_arm_disassembler_options): Constify.
666 * ppc-dis.c (powerpc_init_dialect): Constify local.
667 * vax-dis.c (parse_disassembler_options): Constify.
668
b5292032
PD		 6692017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
670
671 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
672 RISCV_GP_SYMBOL.
673
f96bd6c2
PC		 6742017-03-30 Pip Cet <pipcet@gmail.com>
675
676 * configure.ac: Add (empty) bfd_wasm32_arch target.
677 * configure: Regenerate
678 * po/opcodes.pot: Regenerate.
679
f7c514a3
JM		 6802017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
681
682 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
683 OSA2015.
684 * opcodes/sparc-opc.c (asi_table): New ASIs.
685
52be03fd
AM		 6862017-03-29 Alan Modra <amodra@gmail.com>
687
688 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
689 "raw" option.
690 (lookup_powerpc): Don't special case -1 dialect. Handle
691 PPC_OPCODE_RAW.
692 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
693 lookup_powerpc call, pass it on second.
694
9b753937
AM		 6952017-03-27 Alan Modra <amodra@gmail.com>
696
697 PR 21303
698 * ppc-dis.c (struct ppc_mopt): Comment.
699 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
700
c0c31e91
RZ		 7012017-03-27 Rinat Zelig <rinat@mellanox.com>
702
703 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
704 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
705 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
706 (insert_nps_misc_imm_offset): New function.
707 (extract_nps_misc imm_offset): New function.
708 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
709 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
710
2253c8f0
AK		 7112017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
712
713 * s390-mkopc.c (main): Remove vx2 check.
714 * s390-opc.txt: Remove vx2 instruction flags.
715
645d3342
RZ		 7162017-03-21 Rinat Zelig <rinat@mellanox.com>
717
718 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
719 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
720 (insert_nps_imm_offset): New function.
721 (extract_nps_imm_offset): New function.
722 (insert_nps_imm_entry): New function.
723 (extract_nps_imm_entry): New function.
724
4b94dd2d
AM		 7252017-03-17 Alan Modra <amodra@gmail.com>
726
727 PR 21248
728 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
729 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
730 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
731
b416fe87
KC		 7322017-03-14 Kito Cheng <kito.cheng@gmail.com>
733
734 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
735 <c.andi>: Likewise.
736 <c.addiw> Likewise.
737
03b039a5
KC		 7382017-03-14 Kito Cheng <kito.cheng@gmail.com>
739
740 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
741
2c232b83
AW		 7422017-03-13 Andrew Waterman <andrew@sifive.com>
743
744 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
745 <srl> Likewise.
746 <srai> Likewise.
747 <sra> Likewise.
748
86fa6981
L		 7492017-03-09 H.J. Lu <hongjiu.lu@intel.com>
750
751 * i386-gen.c (opcode_modifiers): Replace S with Load.
752 * i386-opc.h (S): Removed.
753 (Load): New.
754 (i386_opcode_modifier): Replace s with load.
755 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
756 and {evex}. Replace S with Load.
757 * i386-tbl.h: Regenerated.
758
c1fe188b
L		 7592017-03-09 H.J. Lu <hongjiu.lu@intel.com>
760
761 * i386-opc.tbl: Use CpuCET on rdsspq.
762 * i386-tbl.h: Regenerated.
763
4b8b687e
PB		 7642017-03-08 Peter Bergner <bergner@vnet.ibm.com>
765
766 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
767 <vsx>: Do not use PPC_OPCODE_VSX3;
768
1437d063
PB		 7692017-03-08 Peter Bergner <bergner@vnet.ibm.com>
770
771 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
772
603555e5
L		 7732017-03-06 H.J. Lu <hongjiu.lu@intel.com>
774
775 * i386-dis.c (REG_0F1E_MOD_3): New enum.
776 (MOD_0F1E_PREFIX_1): Likewise.
777 (MOD_0F38F5_PREFIX_2): Likewise.
778 (MOD_0F38F6_PREFIX_0): Likewise.
779 (RM_0F1E_MOD_3_REG_7): Likewise.
780 (PREFIX_MOD_0_0F01_REG_5): Likewise.
781 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
782 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
783 (PREFIX_0F1E): Likewise.
784 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
785 (PREFIX_0F38F5): Likewise.
786 (dis386_twobyte): Use PREFIX_0F1E.
787 (reg_table): Add REG_0F1E_MOD_3.
788 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
789 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
790 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
791 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
792 (three_byte_table): Use PREFIX_0F38F5.
793 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
794 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
795 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
796 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
797 PREFIX_MOD_3_0F01_REG_5_RM_2.
798 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
799 (cpu_flags): Add CpuCET.
800 * i386-opc.h (CpuCET): New enum.
801 (CpuUnused): Commented out.
802 (i386_cpu_flags): Add cpucet.
803 * i386-opc.tbl: Add Intel CET instructions.
804 * i386-init.h: Regenerated.
805 * i386-tbl.h: Likewise.
806
73f07bff
AM		 8072017-03-06 Alan Modra <amodra@gmail.com>
808
809 PR 21124
810 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
811 (extract_raq, extract_ras, extract_rbx): New functions.
812 (powerpc_operands): Use opposite corresponding insert function.
813 (Q_MASK): Define.
814 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
815 register restriction.
816
65b48a81
PB		 8172017-02-28 Peter Bergner <bergner@vnet.ibm.com>
818
819 * disassemble.c Include "safe-ctype.h".
820 (disassemble_init_for_target): Handle s390 init.
821 (remove_whitespace_and_extra_commas): New function.
822 (disassembler_options_cmp): Likewise.
823 * arm-dis.c: Include "libiberty.h".
824 (NUM_ELEM): Delete.
825 (regnames): Use long disassembler style names.
826 Add force-thumb and no-force-thumb options.
827 (NUM_ARM_REGNAMES): Rename from this...
828 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
829 (get_arm_regname_num_options): Delete.
830 (set_arm_regname_option): Likewise.
831 (get_arm_regnames): Likewise.
832 (parse_disassembler_options): Likewise.
833 (parse_arm_disassembler_option): Rename from this...
834 (parse_arm_disassembler_options): ...to this. Make static.
835 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
836 (print_insn): Use parse_arm_disassembler_options.
837 (disassembler_options_arm): New function.
838 (print_arm_disassembler_options): Handle updated regnames.
839 * ppc-dis.c: Include "libiberty.h".
840 (ppc_opts): Add "32" and "64" entries.
841 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
842 (powerpc_init_dialect): Add break to switch statement.
843 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
844 (disassembler_options_powerpc): New function.
845 (print_ppc_disassembler_options): Use ARRAY_SIZE.
846 Remove printing of "32" and "64".
847 * s390-dis.c: Include "libiberty.h".
848 (init_flag): Remove unneeded variable.
849 (struct s390_options_t): New structure type.
850 (options): New structure.
851 (init_disasm): Rename from this...
852 (disassemble_init_s390): ...to this. Add initializations for
853 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
854 (print_insn_s390): Delete call to init_disasm.
855 (disassembler_options_s390): New function.
856 (print_s390_disassembler_options): Print using information from
857 struct 'options'.
858 * po/opcodes.pot: Regenerate.
859
15c7c1d8
JB		 8602017-02-28 Jan Beulich <jbeulich@suse.com>
861
862 * i386-dis.c (PCMPESTR_Fixup): New.
863 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
864 (prefix_table): Use PCMPESTR_Fixup.
865 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
866 PCMPESTR_Fixup.
867 (vex_w_table): Delete VPCMPESTR{I,M} entries.
868 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
869 Split 64-bit and non-64-bit variants.
870 * opcodes/i386-tbl.h: Re-generate.
871
582e12bf
RS		 8722017-02-24 Richard Sandiford <richard.sandiford@arm.com>
873
874 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
875 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
876 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
877 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
878 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
879 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
880 (OP_SVE_V_HSD): New macros.
881 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
882 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
883 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
884 (aarch64_opcode_table): Add new SVE instructions.
885 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
886 for rotation operands. Add new SVE operands.
887 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
888 (ins_sve_quad_index): Likewise.
889 (ins_imm_rotate): Split into...
890 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
891 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
892 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
893 functions.
894 (aarch64_ins_sve_addr_ri_s4): New function.
895 (aarch64_ins_sve_quad_index): Likewise.
896 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
897 * aarch64-asm-2.c: Regenerate.
898 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
899 (ext_sve_quad_index): Likewise.
900 (ext_imm_rotate): Split into...
901 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
902 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
903 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
904 functions.
905 (aarch64_ext_sve_addr_ri_s4): New function.
906 (aarch64_ext_sve_quad_index): Likewise.
907 (aarch64_ext_sve_index): Allow quad indices.
908 (do_misc_decoding): Likewise.
909 * aarch64-dis-2.c: Regenerate.
910 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
911 aarch64_field_kinds.
912 (OPD_F_OD_MASK): Widen by one bit.
913 (OPD_F_NO_ZR): Bump accordingly.
914 (get_operand_field_width): New function.
915 * aarch64-opc.c (fields): Add new SVE fields.
916 (operand_general_constraint_met_p): Handle new SVE operands.
917 (aarch64_print_operand): Likewise.
918 * aarch64-opc-2.c: Regenerate.
919
f482d304
RS		 9202017-02-24 Richard Sandiford <richard.sandiford@arm.com>
921
922 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
923 (aarch64_feature_compnum): ...this.
924 (SIMD_V8_3): Replace with...
925 (COMPNUM): ...this.
926 (CNUM_INSN): New macro.
927 (aarch64_opcode_table): Use it for the complex number instructions.
928
7db2c588
JB		 9292017-02-24 Jan Beulich <jbeulich@suse.com>
930
931 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
932
1e9d41d4
SL		 9332017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
934
935 Add support for associating SPARC ASIs with an architecture level.
936 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
937 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
938 decoding of SPARC ASIs.
939
53c4d625
JB		 9402017-02-23 Jan Beulich <jbeulich@suse.com>
941
942 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
943 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
944
11648de5
JB		 9452017-02-21 Jan Beulich <jbeulich@suse.com>
946
947 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
948 1 (instead of to itself). Correct typo.
949
f98d33be
AW		 9502017-02-14 Andrew Waterman <andrew@sifive.com>
951
952 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
953 pseudoinstructions.
954
773fb663
RS		 9552017-02-15 Richard Sandiford <richard.sandiford@arm.com>
956
957 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
958 (aarch64_sys_reg_supported_p): Handle them.
959
cc07cda6
CZ		 9602017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
961
962 * arc-opc.c (UIMM6_20R): Define.
963 (SIMM12_20): Use above.
964 (SIMM12_20R): Define.
965 (SIMM3_5_S): Use above.
966 (UIMM7_A32_11R_S): Define.
967 (UIMM7_9_S): Use above.
968 (UIMM3_13R_S): Define.
969 (SIMM11_A32_7_S): Use above.
970 (SIMM9_8R): Define.
971 (UIMM10_A32_8_S): Use above.
972 (UIMM8_8R_S): Define.
973 (W6): Use above.
974 (arc_relax_opcodes): Use all above defines.
975
66a5a740
VG		 9762017-02-15 Vineet Gupta <vgupta@synopsys.com>
977
978 * arc-regs.h: Distinguish some of the registers different on
979 ARC700 and HS38 cpus.
980
7e0de605
AM		 9812017-02-14 Alan Modra <amodra@gmail.com>
982
983 PR 21118
984 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
985 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
986
54064fdb
AM		 9872017-02-11 Stafford Horne <shorne@gmail.com>
988 Alan Modra <amodra@gmail.com>
989
990 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
991 Use insn_bytes_value and insn_int_value directly instead. Don't
992 free allocated memory until function exit.
993
dce75bf9
NP		 9942017-02-10 Nicholas Piggin <npiggin@gmail.com>
995
996 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
997
1b7e3d2f
NC		 9982017-02-03 Nick Clifton <nickc@redhat.com>
999
1000 PR 21096
1001 * aarch64-opc.c (print_register_list): Ensure that the register
1002 list index will fir into the tb buffer.
1003 (print_register_offset_address): Likewise.
1004 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1005
8ec5cf65
AD		 10062017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1007
1008 PR 21056
1009 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1010 instructions when the previous fetch packet ends with a 32-bit
1011 instruction.
1012
a1aa5e81
DD		 10132017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1014
1015 * pru-opc.c: Remove vague reference to a future GDB port.
1016
add3afb2
NC		 10172017-01-20 Nick Clifton <nickc@redhat.com>
1018
1019 * po/ga.po: Updated Irish translation.
1020
c13a63b0
SN		 10212017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1022
1023 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1024
9608051a
YQ		 10252017-01-13 Yao Qi <yao.qi@linaro.org>
1026
1027 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1028 if FETCH_DATA returns 0.
1029 (m68k_scan_mask): Likewise.
1030 (print_insn_m68k): Update code to handle -1 return value.
1031
f622ea96
YQ		 10322017-01-13 Yao Qi <yao.qi@linaro.org>
1033
1034 * m68k-dis.c (enum print_insn_arg_error): New.
1035 (NEXTBYTE): Replace -3 with
1036 PRINT_INSN_ARG_MEMORY_ERROR.
1037 (NEXTULONG): Likewise.
1038 (NEXTSINGLE): Likewise.
1039 (NEXTDOUBLE): Likewise.
1040 (NEXTDOUBLE): Likewise.
1041 (NEXTPACKED): Likewise.
1042 (FETCH_ARG): Likewise.
1043 (FETCH_DATA): Update comments.
1044 (print_insn_arg): Update comments. Replace magic numbers with
1045 enum.
1046 (match_insn_m68k): Likewise.
1047
620214f7
IT		 10482017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1049
1050 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1051 * i386-dis-evex.h (evex_table): Updated.
1052 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1053 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1054 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1055 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1056 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1057 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1058 * i386-init.h: Regenerate.
1059 * i386-tbl.h: Ditto.
1060
d95014a2
YQ		 10612017-01-12 Yao Qi <yao.qi@linaro.org>
1062
1063 * msp430-dis.c (msp430_singleoperand): Return -1 if
1064 msp430dis_opcode_signed returns false.
1065 (msp430_doubleoperand): Likewise.
1066 (msp430_branchinstr): Return -1 if
1067 msp430dis_opcode_unsigned returns false.
1068 (msp430x_calla_instr): Likewise.
1069 (print_insn_msp430): Likewise.
1070
0ae60c3e
NC		 10712017-01-05 Nick Clifton <nickc@redhat.com>
1072
1073 PR 20946
1074 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1075 could not be matched.
1076 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1077 NULL.
1078
d74d4880
SN		 10792017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1080
1081 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1082 (aarch64_opcode_table): Use RCPC_INSN.
1083
cc917fd9
KC		 10842017-01-03 Kito Cheng <kito.cheng@gmail.com>
1085
1086 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1087 extension.
1088 * riscv-opcodes/all-opcodes: Likewise.
1089
b52d3cfc
DP		 10902017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1091
1092 * riscv-dis.c (print_insn_args): Add fall through comment.
1093
f90c58d5
NC		 10942017-01-03 Nick Clifton <nickc@redhat.com>
1095
1096 * po/sr.po: New Serbian translation.
1097 * configure.ac (ALL_LINGUAS): Add sr.
1098 * configure: Regenerate.
1099
f47b0d4a
AM		 11002017-01-02 Alan Modra <amodra@gmail.com>
1101
1102 * epiphany-desc.h: Regenerate.
1103 * epiphany-opc.h: Regenerate.
1104 * fr30-desc.h: Regenerate.
1105 * fr30-opc.h: Regenerate.
1106 * frv-desc.h: Regenerate.
1107 * frv-opc.h: Regenerate.
1108 * ip2k-desc.h: Regenerate.
1109 * ip2k-opc.h: Regenerate.
1110 * iq2000-desc.h: Regenerate.
1111 * iq2000-opc.h: Regenerate.
1112 * lm32-desc.h: Regenerate.
1113 * lm32-opc.h: Regenerate.
1114 * m32c-desc.h: Regenerate.
1115 * m32c-opc.h: Regenerate.
1116 * m32r-desc.h: Regenerate.
1117 * m32r-opc.h: Regenerate.
1118 * mep-desc.h: Regenerate.
1119 * mep-opc.h: Regenerate.
1120 * mt-desc.h: Regenerate.
1121 * mt-opc.h: Regenerate.
1122 * or1k-desc.h: Regenerate.
1123 * or1k-opc.h: Regenerate.
1124 * xc16x-desc.h: Regenerate.
1125 * xc16x-opc.h: Regenerate.
1126 * xstormy16-desc.h: Regenerate.
1127 * xstormy16-opc.h: Regenerate.
1128
2571583a
AM		 11292017-01-02 Alan Modra <amodra@gmail.com>
1130
1131 Update year range in copyright notice of all files.
1132
5c1ad6b5 1133For older changes see ChangeLog-2016
3499769a 1134\f
5c1ad6b5 1135Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1136
1137Copying and distribution of this file, with or without modification,
1138are permitted in any medium without royalty provided the copyright
1139notice and this notice are preserved.
1140
1141Local Variables:
1142mode: change-log
1143left-margin: 8
1144fill-column: 74
1145version-control: never
1146End:
GDB Binutils - Deliverables
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