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x86: consolidate Disp<NN> handling a little
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
48bcea9f
JB		 12019-12-27 Jan Beulich <jbeulich@suse.com>
2
3 * i386-gen.c (process_i386_operand_type): Don't set Disp32 for
4 Cpu64 templates.
5 * i386-opc.tbl (mov): Fold two templates.
6 (jcxz, jecxz, jrcxz, loop, loope, loopne, loopnz, loopz): Drop
7 Disp16, Disp32, and Disp32S.
8 (xbegin): Add Disp32S.
9 * i386-tbl.h: Re-generate.
10
100b122f
AM		 112019-12-26 Alan Modra <amodra@gmail.com>
12
13 * crx-dis.c (get_number_of_operands): Don't access operands[]
14 out of bounds.
15
6c2ca6c2
AM		 162019-12-26 Alan Modra <amodra@gmail.com>
17
18 * v850-dis.c (disassemble): Avoid signed overflow. Don't use
19 long vars when unsigned int will do.
20
ebd1c6d1
AM		 212019-12-24 Alan Modra <amodra@gmail.com>
22
23 * arm-dis.c (print_insn_arm): Don't shift by 32 on unsigned int var.
24
0e62b37a
JB		 252019-12-23 Jan Beulich <jbeulich@suse.com>
26
27 * ppc-dis.c (print_insn_powerpc): Rename local variable "spaces"
28 to "blanks".
29 * ppc-opc.c (D34, SI34, NSI34): Use UINT64_C().
30
7936714c
AM		 312019-12-23 Alan Modra <amodra@gmail.com>
32
33 * score-dis.c (print_insn_score32): Avoid signed overflow.
34 (print_insn_score48): Likewise. Don't cast to int when printing
35 hex values.
36
3e1056a1
AM		 372019-12-23 Alan Modra <amodra@gmail.com>
38
39 * iq2000-ibld.c: Regenerate.
40
1a1e2852
AM		 412019-12-23 Alan Modra <amodra@gmail.com>
42
43 * d30v-dis.c (extract_value): Make num param a uint64_t, constify
44 oper. Use unsigned vars.
45 (print_insn): Make num var uint64_t. Constify oper and remove now
46 unnecessary casts on extract_value calls.
47 (print_insn_d30v): Use unsigned vars. Adjust printf formats.
48
27c1c427
AM		 492019-12-23 Alan Modra <amodra@gmail.com>
50
51 * wasm32-dis.c (wasm_read_leb128): Don't allow oversize shifts.
52 Catch value overflow. Sign extend only on terminating byte.
53
cda8d785
AM		 542019-12-20 Alan Modra <amodra@gmail.com>
55
56 PR 25281
57 * sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY
58 and MOVY_NOPX insns. For invalid cases include 0xf000 in the word
59 printed. Print .word in more cases.
60
bcd9f578
AM		 612019-12-20 Alan Modra <amodra@gmail.com>
62
63 * or1k-ibld.c: Regenerate.
64
15d2859f
AM		 652019-12-20 Alan Modra <amodra@gmail.com>
66
67 * hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
68 unsigned variables.
69
000fe1a7
AM		 702019-12-20 Alan Modra <amodra@gmail.com>
71
72 * m68hc11-dis.c (read_memory): Delete forward decls.
73 (print_indexed_operand, print_insn): Likewise.
74 (print_indexed_operand): Formatting. Don't rely on short being
75 exactly 16 bits, make sign extension explicit.
76 (print_insn): Likewise. Avoid signed overflow.
77
f0090188
AM		 782019-12-19 Alan Modra <amodra@gmail.com>
79
80 * vax-dis.c (print_insn_mode): Stop index mode recursion.
81
1d29ab86
DF		 822019-12-19 Dr N.W. Filardo <nwf20@cam.ac.uk>
83
84 PR 25277
85 * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
86 fdiv with "mbi_".
87 * microblaze-opc.h (opcodes): Adjust to suit.
88
2480b6fa
AM		 892019-12-18 Alan Modra <amodra@gmail.com>
90
91 * alpha-opc.c (OP): Avoid signed overflow.
92 * arm-dis.c (print_insn): Likewise.
93 * mcore-dis.c (print_insn_mcore): Likewise.
94 * pj-dis.c (get_int): Likewise.
95 * ppc-opc.c (EBD15, EBD15BI): Likewise.
96 * score7-dis.c (s7_print_insn): Likewise.
97 * tic30-dis.c (print_insn_tic30): Likewise.
98 * v850-opc.c (insert_SELID): Likewise.
99 * vax-dis.c (print_insn_vax): Likewise.
100 * arc-ext.c (create_map): Likewise.
101 (struct ExtAuxRegister): Make "address" field unsigned int.
102 (arcExtMap_auxRegName): Pass unsigned address.
103 (dump_ARC_extmap): Adjust.
104 * arc-ext.h (arcExtMap_auxRegName): Update prototype.
105
eb7b5046
AM		 1062019-12-17 Alan Modra <amodra@gmail.com>
107
108 * visium-dis.c (print_insn_visium): Avoid signed overflow.
109
29298bf6
AM		 1102019-12-17 Alan Modra <amodra@gmail.com>
111
112 * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
113 (value_fit_unsigned_field_p): Likewise.
114 (aarch64_wide_constant_p): Likewise.
115 (operand_general_constraint_met_p): Likewise.
116 * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
117
e46d79a7
AM		 1182019-12-17 Alan Modra <amodra@gmail.com>
119
120 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
121 (print_insn_nds32): Use uint64_t for "given" and "given1".
122
5b660084
AM		 1232019-12-17 Alan Modra <amodra@gmail.com>
124
125 * tic80-dis.c: Delete file.
126 * tic80-opc.c: Delete file.
127 * disassemble.c: Remove tic80 support.
128 * disassemble.h: Likewise.
129 * Makefile.am: Likewise.
130 * configure.ac: Likewise.
131 * Makefile.in: Regenerate.
132 * configure: Regenerate.
133 * po/POTFILES.in: Regenerate.
134
62e65990
AM		 1352019-12-17 Alan Modra <amodra@gmail.com>
136
137 * bpf-ibld.c: Regenerate.
138
f81e7e2d
AM		 1392019-12-16 Alan Modra <amodra@gmail.com>
140
141 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
142 conditional.
143 (aarch64_ext_imm): Avoid signed overflow.
144
488d02fe
AM		 1452019-12-16 Alan Modra <amodra@gmail.com>
146
147 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
148
8a92faab
AM		 1492019-12-16 Alan Modra <amodra@gmail.com>
150
151 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
152
e6ced26a
AM		 1532019-12-16 Alan Modra <amodra@gmail.com>
154
155 * xstormy16-ibld.c: Regenerate.
156
84e098cd
AM		 1572019-12-16 Alan Modra <amodra@gmail.com>
158
159 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
160 value adjustment so that it doesn't affect reg field too.
161
36bd8ea7
AM		 1622019-12-16 Alan Modra <amodra@gmail.com>
163
164 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
165 (get_number_of_operands, getargtype, getbits, getregname),
166 (getcopregname, getprocregname, gettrapstring, getcinvstring),
167 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
168 (powerof2, match_opcode, make_instruction, print_arguments),
169 (print_arg): Delete forward declarations, moving static to..
170 (getregname, getcopregname, getregliststring): ..these definitions.
171 (build_mask): Return unsigned int mask.
172 (match_opcode): Use unsigned int vars.
173
cedfc774
AM		 1742019-12-16 Alan Modra <amodra@gmail.com>
175
176 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
177
4bdb25fe
AM		 1782019-12-16 Alan Modra <amodra@gmail.com>
179
180 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
181 (struct objdump_disasm_info): Delete.
182 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
183 N32_IMMS to unsigned before shifting left.
184
cf950fd4
AM		 1852019-12-16 Alan Modra <amodra@gmail.com>
186
187 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
188 (print_insn_moxie): Remove unnecessary cast.
189
967354c3
AM		 1902019-12-12 Alan Modra <amodra@gmail.com>
191
192 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
193 mask.
194
1d61b032
AM		 1952019-12-11 Alan Modra <amodra@gmail.com>
196
197 * arc-dis.c (BITS): Don't truncate high bits with shifts.
198 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
199 * tic54x-dis.c (print_instruction): Likewise.
200 * tilegx-opc.c (parse_insn_tilegx): Likewise.
201 * tilepro-opc.c (parse_insn_tilepro): Likewise.
202 * visium-dis.c (disassem_class0): Likewise.
203 * pdp11-dis.c (sign_extend): Likewise.
204 (SIGN_BITS): Delete.
205 * epiphany-ibld.c: Regenerate.
206 * lm32-ibld.c: Regenerate.
207 * m32c-ibld.c: Regenerate.
208
5afa80e9
AM		 2092019-12-11 Alan Modra <amodra@gmail.com>
210
211 * ns32k-dis.c (sign_extend): Correct last patch.
212
5c05618a
AM		 2132019-12-11 Alan Modra <amodra@gmail.com>
214
215 * vax-dis.c (NEXTLONG): Avoid signed overflow.
216
2a81ccbb
AM		 2172019-12-11 Alan Modra <amodra@gmail.com>
218
219 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
220 sign extend using shifts.
221
b84f6152
AM		 2222019-12-11 Alan Modra <amodra@gmail.com>
223
224 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
225
66152f16
AM		 2262019-12-11 Alan Modra <amodra@gmail.com>
227
228 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
229 on NULL registertable entry.
230 (tic4x_hash_opcode): Use unsigned arithmetic.
231
205c426a
AM		 2322019-12-11 Alan Modra <amodra@gmail.com>
233
234 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
235
fb4cb4e2
AM		 2362019-12-11 Alan Modra <amodra@gmail.com>
237
238 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
239 (bit_extract_simple, sign_extend): Likewise.
240
96f1f604
AM		 2412019-12-11 Alan Modra <amodra@gmail.com>
242
243 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
244
8c9b4171
AM		 2452019-12-11 Alan Modra <amodra@gmail.com>
246
247 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
248
334175b6
AM		 2492019-12-11 Alan Modra <amodra@gmail.com>
250
251 * m68k-dis.c (COERCE32): Cast value first.
252 (NEXTLONG, NEXTULONG): Avoid signed overflow.
253
f8a87c78
AM		 2542019-12-11 Alan Modra <amodra@gmail.com>
255
256 * h8300-dis.c (extract_immediate): Avoid signed overflow.
257 (bfd_h8_disassemble): Likewise.
258
159653d8
AM		 2592019-12-11 Alan Modra <amodra@gmail.com>
260
261 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
262 past end of operands array.
263
d93bba9e
AM		 2642019-12-11 Alan Modra <amodra@gmail.com>
265
266 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
267 overflow when collecting bytes of a number.
268
c202f69e
AM		 2692019-12-11 Alan Modra <amodra@gmail.com>
270
271 * cris-dis.c (print_with_operands): Avoid signed integer
272 overflow when collecting bytes of a 32-bit integer.
273
0ef562a4
AM		 2742019-12-11 Alan Modra <amodra@gmail.com>
275
276 * cr16-dis.c (EXTRACT, SBM): Rewrite.
277 (cr16_match_opcode): Delete duplicate bcond test.
278
2fd2b153
AM		 2792019-12-11 Alan Modra <amodra@gmail.com>
280
281 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
282 (SIGNBIT): New.
283 (MASKBITS, SIGNEXTEND): Rewrite.
284 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
285 unsigned arithmetic, instead assign result of SIGNEXTEND back
286 to x.
287 (fmtconst_val): Use 1u in shift expression.
288
a11db3e9
AM		 2892019-12-11 Alan Modra <amodra@gmail.com>
290
291 * arc-dis.c (find_format_from_table): Use ull constant when
292 shifting by up to 32.
293
9d48687b
AM		 2942019-12-11 Alan Modra <amodra@gmail.com>
295
296 PR 25270
297 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
298 false when field is zero for sve_size_tsz_bhs.
299
b8e61daa
AM		 3002019-12-11 Alan Modra <amodra@gmail.com>
301
302 * epiphany-ibld.c: Regenerate.
303
20135676
AM		 3042019-12-10 Alan Modra <amodra@gmail.com>
305
306 PR 24960
307 * disassemble.c (disassemble_free_target): New function.
308
103ebbc3
AM		 3092019-12-10 Alan Modra <amodra@gmail.com>
310
311 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
312 * disassemble.c (disassemble_init_for_target): Likewise.
313 * bpf-dis.c: Regenerate.
314 * epiphany-dis.c: Regenerate.
315 * fr30-dis.c: Regenerate.
316 * frv-dis.c: Regenerate.
317 * ip2k-dis.c: Regenerate.
318 * iq2000-dis.c: Regenerate.
319 * lm32-dis.c: Regenerate.
320 * m32c-dis.c: Regenerate.
321 * m32r-dis.c: Regenerate.
322 * mep-dis.c: Regenerate.
323 * mt-dis.c: Regenerate.
324 * or1k-dis.c: Regenerate.
325 * xc16x-dis.c: Regenerate.
326 * xstormy16-dis.c: Regenerate.
327
6f0e0752
AM		 3282019-12-10 Alan Modra <amodra@gmail.com>
329
330 * ppc-dis.c (private): Delete variable.
331 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
332 (powerpc_init_dialect): Don't use global private.
333
e7c22a69
AM		 3342019-12-10 Alan Modra <amodra@gmail.com>
335
336 * s12z-opc.c: Formatting.
337
0a6aef6b
AM		 3382019-12-08 Alan Modra <amodra@gmail.com>
339
340 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
341 registers.
342
2dc4b12f
JB		 3432019-12-05 Jan Beulich <jbeulich@suse.com>
344
345 * aarch64-tbl.h (aarch64_feature_crypto,
346 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
347 CRYPTO_V8_2_INSN): Delete.
348
378fd436
AM		 3492019-12-05 Alan Modra <amodra@gmail.com>
350
351 PR 25249
352 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
353 (struct string_buf): New.
354 (strbuf): New function.
355 (get_field): Use strbuf rather than strdup of local temp.
356 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
357 (get_field_rfsl, get_field_imm15): Likewise.
358 (get_field_rd, get_field_r1, get_field_r2): Update macros.
359 (get_field_special): Likewise. Don't strcpy spr. Formatting.
360 (print_insn_microblaze): Formatting. Init and pass string_buf to
361 get_field functions.
362
0ba59a29
JB		 3632019-12-04 Jan Beulich <jbeulich@suse.com>
364
365 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
366 * i386-tbl.h: Re-generate.
367
77ad8092
JB		 3682019-12-04 Jan Beulich <jbeulich@suse.com>
369
370 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
371
3036c899
JB		 3722019-12-04 Jan Beulich <jbeulich@suse.com>
373
374 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
375 forms.
376 (xbegin): Drop DefaultSize.
377 * i386-tbl.h: Re-generate.
378
8b301fbb
MI		 3792019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
380
381 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
382 Change the coproc CRC conditions to use the extension
383 feature set, second word, base on ARM_EXT2_CRC.
384
6aa385b9
JB		 3852019-11-14 Jan Beulich <jbeulich@suse.com>
386
387 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
388 * i386-tbl.h: Re-generate.
389
0cfa3eb3
JB		 3902019-11-14 Jan Beulich <jbeulich@suse.com>
391
392 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
393 JumpInterSegment, and JumpAbsolute entries.
394 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
395 JUMP_ABSOLUTE): Define.
396 (struct i386_opcode_modifier): Extend jump field to 3 bits.
397 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
398 fields.
399 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
400 JumpInterSegment): Define.
401 * i386-tbl.h: Re-generate.
402
6f2f06be
JB		 4032019-11-14 Jan Beulich <jbeulich@suse.com>
404
405 * i386-gen.c (operand_type_init): Remove
406 OPERAND_TYPE_JUMPABSOLUTE entry.
407 (opcode_modifiers): Add JumpAbsolute entry.
408 (operand_types): Remove JumpAbsolute entry.
409 * i386-opc.h (JumpAbsolute): Move between enums.
410 (struct i386_opcode_modifier): Add jumpabsolute field.
411 (union i386_operand_type): Remove jumpabsolute field.
412 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
413 * i386-init.h, i386-tbl.h: Re-generate.
414
601e8564
JB		 4152019-11-14 Jan Beulich <jbeulich@suse.com>
416
417 * i386-gen.c (opcode_modifiers): Add AnySize entry.
418 (operand_types): Remove AnySize entry.
419 * i386-opc.h (AnySize): Move between enums.
420 (struct i386_opcode_modifier): Add anysize field.
421 (OTUnused): Un-comment.
422 (union i386_operand_type): Remove anysize field.
423 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
424 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
425 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
426 AnySize.
427 * i386-tbl.h: Re-generate.
428
7722d40a
JW		 4292019-11-12 Nelson Chu <nelson.chu@sifive.com>
430
431 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
432 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
433 use the floating point register (FPR).
434
ce760a76
MI		 4352019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
436
437 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
438 cmode 1101.
439 (is_mve_encoding_conflict): Update cmode conflict checks for
440 MVE_VMVN_IMM.
441
51c8edf6
JB		 4422019-11-12 Jan Beulich <jbeulich@suse.com>
443
444 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
445 entry.
446 (operand_types): Remove EsSeg entry.
447 (main): Replace stale use of OTMax.
448 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
449 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
450 (EsSeg): Delete.
451 (OTUnused): Comment out.
452 (union i386_operand_type): Remove esseg field.
453 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
454 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
455 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
456 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
457 * i386-init.h, i386-tbl.h: Re-generate.
458
474da251
JB		 4592019-11-12 Jan Beulich <jbeulich@suse.com>
460
461 * i386-gen.c (operand_instances): Add RegB entry.
462 * i386-opc.h (enum operand_instance): Add RegB.
463 * i386-opc.tbl (RegC, RegD, RegB): Define.
464 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
465 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
466 monitorx, mwaitx): Drop ImmExt and convert encodings
467 accordingly.
468 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
469 (edx, rdx): Add Instance=RegD.
470 (ebx, rbx): Add Instance=RegB.
471 * i386-tbl.h: Re-generate.
472
75e5731b
JB		 4732019-11-12 Jan Beulich <jbeulich@suse.com>
474
475 * i386-gen.c (operand_type_init): Adjust
476 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
477 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
478 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
479 (operand_instances): New.
480 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
481 (output_operand_type): New parameter "instance". Process it.
482 (process_i386_operand_type): New local variable "instance".
483 (main): Adjust static assertions.
484 * i386-opc.h (INSTANCE_WIDTH): Define.
485 (enum operand_instance): New.
486 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
487 (union i386_operand_type): Replace acc, inoutportreg, and
488 shiftcount by instance.
489 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
490 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
491 Add Instance=.
492 * i386-init.h, i386-tbl.h: Re-generate.
493
91802f3c
JB		 4942019-11-11 Jan Beulich <jbeulich@suse.com>
495
496 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
497 smaxp/sminp entries' "tied_operand" field to 2.
498
4f5fc85d
JB		 4992019-11-11 Jan Beulich <jbeulich@suse.com>
500
501 * aarch64-opc.c (operand_general_constraint_met_p): Replace
502 "index" local variable by that of the already existing "num".
503
dc2be329
L		 5042019-11-08 H.J. Lu <hongjiu.lu@intel.com>
505
506 PR gas/25167
507 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
508 * i386-tbl.h: Regenerated.
509
f74a6307
JB		 5102019-11-08 Jan Beulich <jbeulich@suse.com>
511
512 * i386-gen.c (operand_type_init): Add Class= to
513 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
514 OPERAND_TYPE_REGBND entry.
515 (operand_classes): Add RegMask and RegBND entries.
516 (operand_types): Drop RegMask and RegBND entry.
517 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
518 (RegMask, RegBND): Delete.
519 (union i386_operand_type): Remove regmask and regbnd fields.
520 * i386-opc.tbl (RegMask, RegBND): Define.
521 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
522 Class=RegBND.
523 * i386-init.h, i386-tbl.h: Re-generate.
524
3528c362
JB		 5252019-11-08 Jan Beulich <jbeulich@suse.com>
526
527 * i386-gen.c (operand_type_init): Add Class= to
528 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
529 OPERAND_TYPE_REGZMM entries.
530 (operand_classes): Add RegMMX and RegSIMD entries.
531 (operand_types): Drop RegMMX and RegSIMD entries.
532 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
533 (RegMMX, RegSIMD): Delete.
534 (union i386_operand_type): Remove regmmx and regsimd fields.
535 * i386-opc.tbl (RegMMX): Define.
536 (RegXMM, RegYMM, RegZMM): Add Class=.
537 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
538 Class=RegSIMD.
539 * i386-init.h, i386-tbl.h: Re-generate.
540
4a5c67ed
JB		 5412019-11-08 Jan Beulich <jbeulich@suse.com>
542
543 * i386-gen.c (operand_type_init): Add Class= to
544 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
545 entries.
546 (operand_classes): Add RegCR, RegDR, and RegTR entries.
547 (operand_types): Drop Control, Debug, and Test entries.
548 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
549 (Control, Debug, Test): Delete.
550 (union i386_operand_type): Remove control, debug, and test
551 fields.
552 * i386-opc.tbl (Control, Debug, Test): Define.
553 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
554 Class=RegDR, and Test by Class=RegTR.
555 * i386-init.h, i386-tbl.h: Re-generate.
556
00cee14f
JB		 5572019-11-08 Jan Beulich <jbeulich@suse.com>
558
559 * i386-gen.c (operand_type_init): Add Class= to
560 OPERAND_TYPE_SREG entry.
561 (operand_classes): Add SReg entry.
562 (operand_types): Drop SReg entry.
563 * i386-opc.h (enum operand_class): Add SReg.
564 (SReg): Delete.
565 (union i386_operand_type): Remove sreg field.
566 * i386-opc.tbl (SReg): Define.
567 * i386-reg.tbl: Replace SReg by Class=SReg.
568 * i386-init.h, i386-tbl.h: Re-generate.
569
bab6aec1
JB		 5702019-11-08 Jan Beulich <jbeulich@suse.com>
571
572 * i386-gen.c (operand_type_init): Add Class=. New
573 OPERAND_TYPE_ANYIMM entry.
574 (operand_classes): New.
575 (operand_types): Drop Reg entry.
576 (output_operand_type): New parameter "class". Process it.
577 (process_i386_operand_type): New local variable "class".
578 (main): Adjust static assertions.
579 * i386-opc.h (CLASS_WIDTH): Define.
580 (enum operand_class): New.
581 (Reg): Replace by Class. Adjust comment.
582 (union i386_operand_type): Replace reg by class.
583 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
584 Class=.
585 * i386-reg.tbl: Replace Reg by Class=Reg.
586 * i386-init.h: Re-generate.
587
1f4cd317
MM		 5882019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
589
590 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
591 (aarch64_opcode_table): Add data gathering hint mnemonic.
592 * opcodes/aarch64-dis-2.c: Account for new instruction.
593
616ce08e
MM		 5942019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
595
596 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
597
598
8382113f
MM		 5992019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
600
601 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
602 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
603 aarch64_feature_f64mm): New feature sets.
604 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
605 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
606 instructions.
607 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
608 macros.
609 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
610 (OP_SVE_QQQ): New qualifier.
611 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
612 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
613 the movprfx constraint.
614 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
615 (aarch64_opcode_table): Define new instructions smmla,
616 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
617 uzip{1/2}, trn{1/2}.
618 * aarch64-opc.c (operand_general_constraint_met_p): Handle
619 AARCH64_OPND_SVE_ADDR_RI_S4x32.
620 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
621 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
622 Account for new instructions.
623 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
624 S4x32 operand.
625 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
626
aab2c27d
MM		 6272019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6282019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
629
630 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
631 Armv8.6-A.
632 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
633 (neon_opcodes): Add bfloat SIMD instructions.
634 (print_insn_coprocessor): Add new control character %b to print
635 condition code without checking cp_num.
636 (print_insn_neon): Account for BFloat16 instructions that have no
637 special top-byte handling.
638
33593eaf
MM		 6392019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6402019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
641
642 * arm-dis.c (print_insn_coprocessor,
643 print_insn_generic_coprocessor): Create wrapper functions around
644 the implementation of the print_insn_coprocessor control codes.
645 (print_insn_coprocessor_1): Original print_insn_coprocessor
646 function that now takes which array to look at as an argument.
647 (print_insn_arm): Use both print_insn_coprocessor and
648 print_insn_generic_coprocessor.
649 (print_insn_thumb32): As above.
650
df678013
MM		 6512019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6522019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
653
654 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
655 in reglane special case.
656 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
657 aarch64_find_next_opcode): Account for new instructions.
658 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
659 in reglane special case.
660 * aarch64-opc.c (struct operand_qualifier_data): Add data for
661 new AARCH64_OPND_QLF_S_2H qualifier.
662 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
663 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
664 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
665 sets.
666 (BFLOAT_SVE, BFLOAT): New feature set macros.
667 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
668 instructions.
669 (aarch64_opcode_table): Define new instructions bfdot,
670 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
671 bfcvtn2, bfcvt.
672
8ae2d3d9
MM		 6732019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6742019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
675
676 * aarch64-tbl.h (ARMV8_6): New macro.
677
142861df
JB		 6782019-11-07 Jan Beulich <jbeulich@suse.com>
679
680 * i386-dis.c (prefix_table): Add mcommit.
681 (rm_table): Add rdpru.
682 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
683 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
684 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
685 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
686 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
687 * i386-opc.tbl (mcommit, rdpru): New.
688 * i386-init.h, i386-tbl.h: Re-generate.
689
081e283f
JB		 6902019-11-07 Jan Beulich <jbeulich@suse.com>
691
692 * i386-dis.c (OP_Mwait): Drop local variable "names", use
693 "names32" instead.
694 (OP_Monitor): Drop local variable "op1_names", re-purpose
695 "names" for it instead, and replace former "names" uses by
696 "names32" ones.
697
c050c89a
JB		 6982019-11-07 Jan Beulich <jbeulich@suse.com>
699
700 PR/gas 25167
701 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
702 operand-less forms.
703 * opcodes/i386-tbl.h: Re-generate.
704
7abb8d81
JB		 7052019-11-05 Jan Beulich <jbeulich@suse.com>
706
707 * i386-dis.c (OP_Mwaitx): Delete.
708 (prefix_table): Use OP_Mwait for mwaitx entry.
709 (OP_Mwait): Also handle mwaitx.
710
267b8516
JB		 7112019-11-05 Jan Beulich <jbeulich@suse.com>
712
713 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
714 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
715 (prefix_table): Add respective entries.
716 (rm_table): Link to those entries.
717
f8687e93
JB		 7182019-11-05 Jan Beulich <jbeulich@suse.com>
719
720 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
721 (REG_0F1C_P_0_MOD_0): ... this.
722 (REG_0F1E_MOD_3): Rename to ...
723 (REG_0F1E_P_1_MOD_3): ... this.
724 (RM_0F01_REG_5): Rename to ...
725 (RM_0F01_REG_5_MOD_3): ... this.
726 (RM_0F01_REG_7): Rename to ...
727 (RM_0F01_REG_7_MOD_3): ... this.
728 (RM_0F1E_MOD_3_REG_7): Rename to ...
729 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
730 (RM_0FAE_REG_6): Rename to ...
731 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
732 (RM_0FAE_REG_7): Rename to ...
733 (RM_0FAE_REG_7_MOD_3): ... this.
734 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
735 (PREFIX_0F01_REG_5_MOD_0): ... this.
736 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
737 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
738 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
739 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
740 (PREFIX_0FAE_REG_0): Rename to ...
741 (PREFIX_0FAE_REG_0_MOD_3): ... this.
742 (PREFIX_0FAE_REG_1): Rename to ...
743 (PREFIX_0FAE_REG_1_MOD_3): ... this.
744 (PREFIX_0FAE_REG_2): Rename to ...
745 (PREFIX_0FAE_REG_2_MOD_3): ... this.
746 (PREFIX_0FAE_REG_3): Rename to ...
747 (PREFIX_0FAE_REG_3_MOD_3): ... this.
748 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
749 (PREFIX_0FAE_REG_4_MOD_0): ... this.
750 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
751 (PREFIX_0FAE_REG_4_MOD_3): ... this.
752 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
753 (PREFIX_0FAE_REG_5_MOD_0): ... this.
754 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
755 (PREFIX_0FAE_REG_5_MOD_3): ... this.
756 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
757 (PREFIX_0FAE_REG_6_MOD_0): ... this.
758 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
759 (PREFIX_0FAE_REG_6_MOD_3): ... this.
760 (PREFIX_0FAE_REG_7): Rename to ...
761 (PREFIX_0FAE_REG_7_MOD_0): ... this.
762 (PREFIX_MOD_0_0FC3): Rename to ...
763 (PREFIX_0FC3_MOD_0): ... this.
764 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
765 (PREFIX_0FC7_REG_6_MOD_0): ... this.
766 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
767 (PREFIX_0FC7_REG_6_MOD_3): ... this.
768 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
769 (PREFIX_0FC7_REG_7_MOD_3): ... this.
770 (reg_table, prefix_table, mod_table, rm_table): Adjust
771 accordingly.
772
5103274f
NC		 7732019-11-04 Nick Clifton <nickc@redhat.com>
774
775 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
776 of a v850 system register. Move the v850_sreg_names array into
777 this function.
778 (get_v850_reg_name): Likewise for ordinary register names.
779 (get_v850_vreg_name): Likewise for vector register names.
780 (get_v850_cc_name): Likewise for condition codes.
781 * get_v850_float_cc_name): Likewise for floating point condition
782 codes.
783 (get_v850_cacheop_name): Likewise for cache-ops.
784 (get_v850_prefop_name): Likewise for pref-ops.
785 (disassemble): Use the new accessor functions.
786
1820262b
DB		 7872019-10-30 Delia Burduv <delia.burduv@arm.com>
788
789 * aarch64-opc.c (print_immediate_offset_address): Don't print the
790 immediate for the writeback form of ldraa/ldrab if it is 0.
791 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
792 * aarch64-opc-2.c: Regenerated.
793
3cc17af5
JB		 7942019-10-30 Jan Beulich <jbeulich@suse.com>
795
796 * i386-gen.c (operand_type_shorthands): Delete.
797 (operand_type_init): Expand previous shorthands.
798 (set_bitfield_from_shorthand): Rename back to ...
799 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
800 of operand_type_init[].
801 (set_bitfield): Adjust call to the above function.
802 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
803 RegXMM, RegYMM, RegZMM): Define.
804 * i386-reg.tbl: Expand prior shorthands.
805
a2cebd03
JB		 8062019-10-30 Jan Beulich <jbeulich@suse.com>
807
808 * i386-gen.c (output_i386_opcode): Change order of fields
809 emitted to output.
810 * i386-opc.h (struct insn_template): Move operands field.
811 Convert extension_opcode field to unsigned short.
812 * i386-tbl.h: Re-generate.
813
507916b8
JB		 8142019-10-30 Jan Beulich <jbeulich@suse.com>
815
816 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
817 of W.
818 * i386-opc.h (W): Extend comment.
819 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
820 general purpose variants not allowing for byte operands.
821 * i386-tbl.h: Re-generate.
822
efea62b4
NC		 8232019-10-29 Nick Clifton <nickc@redhat.com>
824
825 * tic30-dis.c (print_branch): Correct size of operand array.
826
9adb2591
NC		 8272019-10-29 Nick Clifton <nickc@redhat.com>
828
829 * d30v-dis.c (print_insn): Check that operand index is valid
830 before attempting to access the operands array.
831
993a00a9
NC		 8322019-10-29 Nick Clifton <nickc@redhat.com>
833
834 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
835 locating the bit to be tested.
836
66a66a17
NC		 8372019-10-29 Nick Clifton <nickc@redhat.com>
838
839 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
840 values.
841 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
842 (print_insn_s12z): Check for illegal size values.
843
1ee3542c
NC		 8442019-10-28 Nick Clifton <nickc@redhat.com>
845
846 * csky-dis.c (csky_chars_to_number): Check for a negative
847 count. Use an unsigned integer to construct the return value.
848
bbf9a0b5
NC		 8492019-10-28 Nick Clifton <nickc@redhat.com>
850
851 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
852 operand buffer. Set value to 15 not 13.
853 (get_register_operand): Use OPERAND_BUFFER_LEN.
854 (get_indirect_operand): Likewise.
855 (print_two_operand): Likewise.
856 (print_three_operand): Likewise.
857 (print_oar_insn): Likewise.
858
d1e304bc
NC		 8592019-10-28 Nick Clifton <nickc@redhat.com>
860
861 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
862 (bit_extract_simple): Likewise.
863 (bit_copy): Likewise.
864 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
865 index_offset array are not accessed.
866
dee33451
NC		 8672019-10-28 Nick Clifton <nickc@redhat.com>
868
869 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
870 operand.
871
27cee81d
NC		 8722019-10-25 Nick Clifton <nickc@redhat.com>
873
874 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
875 access to opcodes.op array element.
876
de6d8dc2
NC		 8772019-10-23 Nick Clifton <nickc@redhat.com>
878
879 * rx-dis.c (get_register_name): Fix spelling typo in error
880 message.
881 (get_condition_name, get_flag_name, get_double_register_name)
882 (get_double_register_high_name, get_double_register_low_name)
883 (get_double_control_register_name, get_double_condition_name)
884 (get_opsize_name, get_size_name): Likewise.
885
6207ed28
NC		 8862019-10-22 Nick Clifton <nickc@redhat.com>
887
888 * rx-dis.c (get_size_name): New function. Provides safe
889 access to name array.
890 (get_opsize_name): Likewise.
891 (print_insn_rx): Use the accessor functions.
892
12234dfd
NC		 8932019-10-16 Nick Clifton <nickc@redhat.com>
894
895 * rx-dis.c (get_register_name): New function. Provides safe
896 access to name array.
897 (get_condition_name, get_flag_name, get_double_register_name)
898 (get_double_register_high_name, get_double_register_low_name)
899 (get_double_control_register_name, get_double_condition_name):
900 Likewise.
901 (print_insn_rx): Use the accessor functions.
902
1d378749
NC		 9032019-10-09 Nick Clifton <nickc@redhat.com>
904
905 PR 25041
906 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
907 instructions.
908
d241b910
JB		 9092019-10-07 Jan Beulich <jbeulich@suse.com>
910
911 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
912 (cmpsd): Likewise. Move EsSeg to other operand.
913 * opcodes/i386-tbl.h: Re-generate.
914
f5c5b7c1
AM		 9152019-09-23 Alan Modra <amodra@gmail.com>
916
917 * m68k-dis.c: Include cpu-m68k.h
918
7beeaeb8
AM		 9192019-09-23 Alan Modra <amodra@gmail.com>
920
921 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
922 "elf/mips.h" earlier.
923
3f9aad11
JB		 9242018-09-20 Jan Beulich <jbeulich@suse.com>
925
926 PR gas/25012
927 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
928 with SReg operand.
929 * i386-tbl.h: Re-generate.
930
fd361982
AM		 9312019-09-18 Alan Modra <amodra@gmail.com>
932
933 * arc-ext.c: Update throughout for bfd section macro changes.
934
e0b2a78c
SM		 9352019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
936
937 * Makefile.in: Re-generate.
938 * configure: Re-generate.
939
7e9ad3a3
JW		 9402019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
941
942 * riscv-opc.c (riscv_opcodes): Change subset field
943 to insn_class field for all instructions.
944 (riscv_insn_types): Likewise.
945
bb695960
PB		 9462019-09-16 Phil Blundell <pb@pbcl.net>
947
948 * configure: Regenerated.
949
8063ab7e
MV		 9502019-09-10 Miod Vallat <miod@online.fr>
951
952 PR 24982
953 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
954
60391a25
PB		 9552019-09-09 Phil Blundell <pb@pbcl.net>
956
957 binutils 2.33 branch created.
958
f44b758d
NC		 9592019-09-03 Nick Clifton <nickc@redhat.com>
960
961 PR 24961
962 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
963 greater than zero before indexing via (bufcnt -1).
964
1e4b5e7d
NC		 9652019-09-03 Nick Clifton <nickc@redhat.com>
966
967 PR 24958
968 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
969 (MAX_SPEC_REG_NAME_LEN): Define.
970 (struct mmix_dis_info): Use defined constants for array lengths.
971 (get_reg_name): New function.
972 (get_sprec_reg_name): New function.
973 (print_insn_mmix): Use new functions.
974
c4a23bf8
SP		 9752019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
976
977 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
978 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
979 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
980
a051e2f3
KT		 9812019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
982
983 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
984 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
985 (aarch64_sys_reg_supported_p): Update checks for the above.
986
08132bdd
SP		 9872019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
988
989 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
990 cases MVE_SQRSHRL and MVE_UQRSHLL.
991 (print_insn_mve): Add case for specifier 'k' to check
992 specific bit of the instruction.
993
d88bdcb4
PA		 9942019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
995
996 PR 24854
997 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
998 encountering an unknown machine type.
999 (print_insn_arc): Handle arc_insn_length returning 0. In error
1000 cases return -1 rather than calling abort.
1001
bc750500
JB		 10022019-08-07 Jan Beulich <jbeulich@suse.com>
1003
1004 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
1005 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
1006 IgnoreSize.
1007 * i386-tbl.h: Re-generate.
1008
23d188c7
BW		 10092019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
1010
1011 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
1012 instructions.
1013
c0d6f62f
JW		 10142019-07-30 Mel Chen <mel.chen@sifive.com>
1015
1016 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
1017 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
1018
1019 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
1020 fscsr.
1021
0f3f7167
CZ		 10222019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
1023
1024 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
1025 and MPY class instructions.
1026 (parse_option): Add nps400 option.
1027 (print_arc_disassembler_options): Add nps400 info.
1028
7e126ba3
CZ		 10292019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
1030
1031 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
1032 (bspop): Likewise.
1033 (modapp): Likewise.
1034 * arc-opc.c (RAD_CHK): Add.
1035 * arc-tbl.h: Regenerate.
1036
a028026d
KT		 10372019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1038
1039 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
1040 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
1041
ac79ff9e
NC		 10422019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
1043
1044 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
1045 instructions as UNPREDICTABLE.
1046
231097b0
JM		 10472019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1048
1049 * bpf-desc.c: Regenerated.
1050
1d942ae9
JB		 10512019-07-17 Jan Beulich <jbeulich@suse.com>
1052
1053 * i386-gen.c (static_assert): Define.
1054 (main): Use it.
1055 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
1056 (Opcode_Modifier_Num): ... this.
1057 (Mem): Delete.
1058
dfd69174
JB		 10592019-07-16 Jan Beulich <jbeulich@suse.com>
1060
1061 * i386-gen.c (operand_types): Move RegMem ...
1062 (opcode_modifiers): ... here.
1063 * i386-opc.h (RegMem): Move to opcode modifer enum.
1064 (union i386_operand_type): Move regmem field ...
1065 (struct i386_opcode_modifier): ... here.
1066 * i386-opc.tbl (RegMem): Define.
1067 (mov, movq): Move RegMem on segment, control, debug, and test
1068 register flavors.
1069 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
1070 to non-SSE2AVX flavor.
1071 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
1072 Move RegMem on register only flavors. Drop IgnoreSize from
1073 legacy encoding flavors.
1074 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
1075 flavors.
1076 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
1077 register only flavors.
1078 (vmovd): Move RegMem and drop IgnoreSize on register only
1079 flavor. Change opcode and operand order to store form.
1080 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1081
21df382b
JB		 10822019-07-16 Jan Beulich <jbeulich@suse.com>
1083
1084 * i386-gen.c (operand_type_init, operand_types): Replace SReg
1085 entries.
1086 * i386-opc.h (SReg2, SReg3): Replace by ...
1087 (SReg): ... this.
1088 (union i386_operand_type): Replace sreg fields.
1089 * i386-opc.tbl (mov, ): Use SReg.
1090 (push, pop): Likewies. Drop i386 and x86-64 specific segment
1091 register flavors.
1092 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1093 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1094
3719fd55
JM		 10952019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
1096
1097 * bpf-desc.c: Regenerate.
1098 * bpf-opc.c: Likewise.
1099 * bpf-opc.h: Likewise.
1100
92434a14
JM		 11012019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
1102
1103 * bpf-desc.c: Regenerate.
1104 * bpf-opc.c: Likewise.
1105
43dd7626
HPN		 11062019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
1107
1108 * arm-dis.c (print_insn_coprocessor): Rename index to
1109 index_operand.
1110
98602811
JW		 11112019-07-05 Kito Cheng <kito.cheng@sifive.com>
1112
1113 * riscv-opc.c (riscv_insn_types): Add r4 type.
1114
1115 * riscv-opc.c (riscv_insn_types): Add b and j type.
1116
1117 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1118 format for sb type and correct s type.
1119
01c1ee4a
RS		 11202019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1121
1122 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1123 SVE FMOV alias of FCPY.
1124
83adff69
RS		 11252019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1126
1127 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1128 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1129
89418844
RS		 11302019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1131
1132 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1133 registers in an instruction prefixed by MOVPRFX.
1134
41be57ca
MM		 11352019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
1136
1137 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1138 sve_size_13 icode to account for variant behaviour of
1139 pmull{t,b}.
1140 * aarch64-dis-2.c: Regenerate.
1141 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1142 sve_size_13 icode to account for variant behaviour of
1143 pmull{t,b}.
1144 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1145 (OP_SVE_VVV_Q_D): Add new qualifier.
1146 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1147 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1148 AES and those not.
1149
9d3bf266
JB		 11502019-07-01 Jan Beulich <jbeulich@suse.com>
1151
1152 * opcodes/i386-gen.c (operand_type_init): Remove
1153 OPERAND_TYPE_VEC_IMM4 entry.
1154 (operand_types): Remove Vec_Imm4.
1155 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1156 (union i386_operand_type): Remove vec_imm4.
1157 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1158 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1159
c3949f43
JB		 11602019-07-01 Jan Beulich <jbeulich@suse.com>
1161
1162 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1163 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1164 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1165 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1166 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1167 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1168 * i386-tbl.h: Re-generate.
1169
5641ec01
JB		 11702019-07-01 Jan Beulich <jbeulich@suse.com>
1171
1172 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1173 register operands.
1174 * i386-tbl.h: Re-generate.
1175
79dec6b7
JB		 11762019-07-01 Jan Beulich <jbeulich@suse.com>
1177
1178 * i386-opc.tbl (C): New.
1179 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1180 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1181 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1182 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1183 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1184 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1185 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1186 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1187 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1188 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1189 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1190 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1191 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1192 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1193 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1194 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1195 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1196 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1197 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1198 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1199 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1200 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1201 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1202 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1203 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1204 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1205 flavors.
1206 * i386-tbl.h: Re-generate.
1207
a0a1771e
JB		 12082019-07-01 Jan Beulich <jbeulich@suse.com>
1209
1210 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1211 register operands.
1212 * i386-tbl.h: Re-generate.
1213
cd546e7b
JB		 12142019-07-01 Jan Beulich <jbeulich@suse.com>
1215
1216 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1217 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1218 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1219 * i386-tbl.h: Re-generate.
1220
e3bba3fc
JB		 12212019-07-01 Jan Beulich <jbeulich@suse.com>
1222
1223 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1224 Disp8MemShift from register only templates.
1225 * i386-tbl.h: Re-generate.
1226
36cc073e
JB		 12272019-07-01 Jan Beulich <jbeulich@suse.com>
1228
1229 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1230 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1231 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1232 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1233 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1234 EVEX_W_0F11_P_3_M_1): Delete.
1235 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1236 EVEX_W_0F11_P_3): New.
1237 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1238 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1239 MOD_EVEX_0F11_PREFIX_3 table entries.
1240 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1241 PREFIX_EVEX_0F11 table entries.
1242 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1243 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1244 EVEX_W_0F11_P_3_M_{0,1} table entries.
1245
219920a7
JB		 12462019-07-01 Jan Beulich <jbeulich@suse.com>
1247
1248 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1249 Delete.
1250
e395f487
L		 12512019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1252
1253 PR binutils/24719
1254 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1255 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1256 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1257 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1258 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1259 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1260 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1261 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1262 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1263 PREFIX_EVEX_0F38C6_REG_6 entries.
1264 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1265 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1266 EVEX_W_0F38C7_R_6_P_2 entries.
1267 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1268 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1269 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1270 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1271 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1272 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1273 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1274
2b7bcc87
JB		 12752019-06-27 Jan Beulich <jbeulich@suse.com>
1276
1277 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1278 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1279 VEX_LEN_0F2D_P_3): Delete.
1280 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1281 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1282 (prefix_table): ... here.
1283
c1dc7af5
JB		 12842019-06-27 Jan Beulich <jbeulich@suse.com>
1285
1286 * i386-dis.c (Iq): Delete.
1287 (Id): New.
1288 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1289 TBM insns.
1290 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1291 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1292 (OP_E_memory): Also honor needindex when deciding whether an
1293 address size prefix needs printing.
1294 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1295
d7560e2d
JW		 12962019-06-26 Jim Wilson <jimw@sifive.com>
1297
1298 PR binutils/24739
1299 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1300 Set info->display_endian to info->endian_code.
1301
2c703856
JB		 13022019-06-25 Jan Beulich <jbeulich@suse.com>
1303
1304 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1305 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1306 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1307 OPERAND_TYPE_ACC64 entries.
1308 * i386-init.h: Re-generate.
1309
54fbadc0
JB		 13102019-06-25 Jan Beulich <jbeulich@suse.com>
1311
1312 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1313 Delete.
1314 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1315 of dqa_mode.
1316 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1317 entries here.
1318 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1319 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1320
a280ab8e
JB		 13212019-06-25 Jan Beulich <jbeulich@suse.com>
1322
1323 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1324 variables.
1325
e1a1babd
JB		 13262019-06-25 Jan Beulich <jbeulich@suse.com>
1327
1328 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1329 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1330 movnti.
d7560e2d 1331 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1332 * i386-tbl.h: Re-generate.
1333
b8364fa7
JB		 13342019-06-25 Jan Beulich <jbeulich@suse.com>
1335
1336 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1337 * i386-tbl.h: Re-generate.
1338
ad692897
L		 13392019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1340
1341 * i386-dis-evex.h: Break into ...
1342 * i386-dis-evex-len.h: New file.
1343 * i386-dis-evex-mod.h: Likewise.
1344 * i386-dis-evex-prefix.h: Likewise.
1345 * i386-dis-evex-reg.h: Likewise.
1346 * i386-dis-evex-w.h: Likewise.
1347 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1348 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1349 i386-dis-evex-mod.h.
1350
f0a6222e
L		 13512019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1352
1353 PR binutils/24700
1354 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1355 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1356 EVEX_W_0F385B_P_2.
1357 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1358 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1359 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1360 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1361 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1362 EVEX_LEN_0F385B_P_2_W_1.
1363 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1364 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1365 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1366 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1367 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1368 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1369 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1370 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1371 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1372 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1373
6e1c90b7
L		 13742019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1375
1376 PR binutils/24691
1377 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1378 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1379 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1380 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1381 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1382 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1383 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1384 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1385 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1386 EVEX_LEN_0F3A43_P_2_W_1.
1387 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1388 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1389 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1390 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1391 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1392 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1393 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1394 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1395 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1396 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1397 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1398 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1399
bcc5a6eb
NC		 14002019-06-14 Nick Clifton <nickc@redhat.com>
1401
1402 * po/fr.po; Updated French translation.
1403
e4c4ac46
SH		 14042019-06-13 Stafford Horne <shorne@gmail.com>
1405
1406 * or1k-asm.c: Regenerated.
1407 * or1k-desc.c: Regenerated.
1408 * or1k-desc.h: Regenerated.
1409 * or1k-dis.c: Regenerated.
1410 * or1k-ibld.c: Regenerated.
1411 * or1k-opc.c: Regenerated.
1412 * or1k-opc.h: Regenerated.
1413 * or1k-opinst.c: Regenerated.
1414
a0e44ef5
PB		 14152019-06-12 Peter Bergner <bergner@linux.ibm.com>
1416
1417 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1418
12efd68d
L		 14192019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1420
1421 PR binutils/24633
1422 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1423 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1424 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1425 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1426 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1427 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1428 EVEX_LEN_0F3A1B_P_2_W_1.
1429 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1430 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1431 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1432 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1433 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1434 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1435 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1436 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1437
63c6fc6c
L		 14382019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1439
1440 PR binutils/24626
1441 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1442 EVEX.vvvv when disassembling VEX and EVEX instructions.
1443 (OP_VEX): Set vex.register_specifier to 0 after readding
1444 vex.register_specifier.
1445 (OP_Vex_2src_1): Likewise.
1446 (OP_Vex_2src_2): Likewise.
1447 (OP_LWP_E): Likewise.
1448 (OP_EX_Vex): Don't check vex.register_specifier.
1449 (OP_XMM_Vex): Likewise.
1450
9186c494
L		 14512019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1452 Lili Cui <lili.cui@intel.com>
1453
1454 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1455 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1456 instructions.
1457 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1458 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1459 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1460 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1461 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1462 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1463 * i386-init.h: Regenerated.
1464 * i386-tbl.h: Likewise.
1465
5d79adc4
L		 14662019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1467 Lili Cui <lili.cui@intel.com>
1468
1469 * doc/c-i386.texi: Document enqcmd.
1470 * testsuite/gas/i386/enqcmd-intel.d: New file.
1471 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1472 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1473 * testsuite/gas/i386/enqcmd.d: Likewise.
1474 * testsuite/gas/i386/enqcmd.s: Likewise.
1475 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1476 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1477 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1478 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1479 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1480 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1481 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1482 and x86-64-enqcmd.
1483
a9d96ab9
AH		 14842019-06-04 Alan Hayward <alan.hayward@arm.com>
1485
1486 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1487
4f6d070a
AM		 14882019-06-03 Alan Modra <amodra@gmail.com>
1489
1490 * ppc-dis.c (prefix_opcd_indices): Correct size.
1491
a2f4b66c
L		 14922019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1493
1494 PR gas/24625
1495 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1496 Disp8ShiftVL.
1497 * i386-tbl.h: Regenerated.
1498
405b5bd8
AM		 14992019-05-24 Alan Modra <amodra@gmail.com>
1500
1501 * po/POTFILES.in: Regenerate.
1502
8acf1435
PB		 15032019-05-24 Peter Bergner <bergner@linux.ibm.com>
1504 Alan Modra <amodra@gmail.com>
1505
1506 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1507 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1508 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1509 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1510 XTOP>): Define and add entries.
1511 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1512 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1513 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1514 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1515
dd7efa79
PB		 15162019-05-24 Peter Bergner <bergner@linux.ibm.com>
1517 Alan Modra <amodra@gmail.com>
1518
1519 * ppc-dis.c (ppc_opts): Add "future" entry.
1520 (PREFIX_OPCD_SEGS): Define.
1521 (prefix_opcd_indices): New array.
1522 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1523 (lookup_prefix): New function.
1524 (print_insn_powerpc): Handle 64-bit prefix instructions.
1525 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1526 (PMRR, POWERXX): Define.
1527 (prefix_opcodes): New instruction table.
1528 (prefix_num_opcodes): New constant.
1529
79472b45
JM		 15302019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1531
1532 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1533 * configure: Regenerated.
1534 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1535 and cpu/bpf.opc.
1536 (HFILES): Add bpf-desc.h and bpf-opc.h.
1537 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1538 bpf-ibld.c and bpf-opc.c.
1539 (BPF_DEPS): Define.
1540 * Makefile.in: Regenerated.
1541 * disassemble.c (ARCH_bpf): Define.
1542 (disassembler): Add case for bfd_arch_bpf.
1543 (disassemble_init_for_target): Likewise.
1544 (enum epbf_isa_attr): Define.
1545 * disassemble.h: extern print_insn_bpf.
1546 * bpf-asm.c: Generated.
1547 * bpf-opc.h: Likewise.
1548 * bpf-opc.c: Likewise.
1549 * bpf-ibld.c: Likewise.
1550 * bpf-dis.c: Likewise.
1551 * bpf-desc.h: Likewise.
1552 * bpf-desc.c: Likewise.
1553
ba6cd17f
SD		 15542019-05-21 Sudakshina Das <sudi.das@arm.com>
1555
1556 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1557 and VMSR with the new operands.
1558
e39c1607
SD		 15592019-05-21 Sudakshina Das <sudi.das@arm.com>
1560
1561 * arm-dis.c (enum mve_instructions): New enum
1562 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1563 and cneg.
1564 (mve_opcodes): New instructions as above.
1565 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1566 csneg and csel.
1567 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1568
23d00a41
SD		 15692019-05-21 Sudakshina Das <sudi.das@arm.com>
1570
1571 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1572 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1573 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1574 uqshl, urshrl and urshr.
1575 (is_mve_okay_in_it): Add new instructions to TRUE list.
1576 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1577 (print_insn_mve): Updated to accept new %j,
1578 %<bitfield>m and %<bitfield>n patterns.
1579
cd4797ee
FS		 15802019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1581
1582 * mips-opc.c (mips_builtin_opcodes): Change source register
1583 constraint for DAUI.
1584
999b073b
NC		 15852019-05-20 Nick Clifton <nickc@redhat.com>
1586
1587 * po/fr.po: Updated French translation.
1588
14b456f2
AV		 15892019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1590 Michael Collison <michael.collison@arm.com>
1591
1592 * arm-dis.c (thumb32_opcodes): Add new instructions.
1593 (enum mve_instructions): Likewise.
1594 (enum mve_undefined): Add new reasons.
1595 (is_mve_encoding_conflict): Handle new instructions.
1596 (is_mve_undefined): Likewise.
1597 (is_mve_unpredictable): Likewise.
1598 (print_mve_undefined): Likewise.
1599 (print_mve_size): Likewise.
1600
f49bb598
AV		 16012019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1602 Michael Collison <michael.collison@arm.com>
1603
1604 * arm-dis.c (thumb32_opcodes): Add new instructions.
1605 (enum mve_instructions): Likewise.
1606 (is_mve_encoding_conflict): Handle new instructions.
1607 (is_mve_undefined): Likewise.
1608 (is_mve_unpredictable): Likewise.
1609 (print_mve_size): Likewise.
1610
56858bea
AV		 16112019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1612 Michael Collison <michael.collison@arm.com>
1613
1614 * arm-dis.c (thumb32_opcodes): Add new instructions.
1615 (enum mve_instructions): Likewise.
1616 (is_mve_encoding_conflict): Likewise.
1617 (is_mve_unpredictable): Likewise.
1618 (print_mve_size): Likewise.
1619
e523f101
AV		 16202019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1621 Michael Collison <michael.collison@arm.com>
1622
1623 * arm-dis.c (thumb32_opcodes): Add new instructions.
1624 (enum mve_instructions): Likewise.
1625 (is_mve_encoding_conflict): Handle new instructions.
1626 (is_mve_undefined): Likewise.
1627 (is_mve_unpredictable): Likewise.
1628 (print_mve_size): Likewise.
1629
66dcaa5d
AV		 16302019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1631 Michael Collison <michael.collison@arm.com>
1632
1633 * arm-dis.c (thumb32_opcodes): Add new instructions.
1634 (enum mve_instructions): Likewise.
1635 (is_mve_encoding_conflict): Handle new instructions.
1636 (is_mve_undefined): Likewise.
1637 (is_mve_unpredictable): Likewise.
1638 (print_mve_size): Likewise.
1639 (print_insn_mve): Likewise.
1640
d052b9b7
AV		 16412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1642 Michael Collison <michael.collison@arm.com>
1643
1644 * arm-dis.c (thumb32_opcodes): Add new instructions.
1645 (print_insn_thumb32): Handle new instructions.
1646
ed63aa17
AV		 16472019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1648 Michael Collison <michael.collison@arm.com>
1649
1650 * arm-dis.c (enum mve_instructions): Add new instructions.
1651 (enum mve_undefined): Add new reasons.
1652 (is_mve_encoding_conflict): Handle new instructions.
1653 (is_mve_undefined): Likewise.
1654 (is_mve_unpredictable): Likewise.
1655 (print_mve_undefined): Likewise.
1656 (print_mve_size): Likewise.
1657 (print_mve_shift_n): Likewise.
1658 (print_insn_mve): Likewise.
1659
897b9bbc
AV		 16602019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1661 Michael Collison <michael.collison@arm.com>
1662
1663 * arm-dis.c (enum mve_instructions): Add new instructions.
1664 (is_mve_encoding_conflict): Handle new instructions.
1665 (is_mve_unpredictable): Likewise.
1666 (print_mve_rotate): Likewise.
1667 (print_mve_size): Likewise.
1668 (print_insn_mve): Likewise.
1669
1c8f2df8
AV		 16702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1671 Michael Collison <michael.collison@arm.com>
1672
1673 * arm-dis.c (enum mve_instructions): Add new instructions.
1674 (is_mve_encoding_conflict): Handle new instructions.
1675 (is_mve_unpredictable): Likewise.
1676 (print_mve_size): Likewise.
1677 (print_insn_mve): Likewise.
1678
d3b63143
AV		 16792019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1680 Michael Collison <michael.collison@arm.com>
1681
1682 * arm-dis.c (enum mve_instructions): Add new instructions.
1683 (enum mve_undefined): Add new reasons.
1684 (is_mve_encoding_conflict): Handle new instructions.
1685 (is_mve_undefined): Likewise.
1686 (is_mve_unpredictable): Likewise.
1687 (print_mve_undefined): Likewise.
1688 (print_mve_size): Likewise.
1689 (print_insn_mve): Likewise.
1690
14925797
AV		 16912019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1692 Michael Collison <michael.collison@arm.com>
1693
1694 * arm-dis.c (enum mve_instructions): Add new instructions.
1695 (is_mve_encoding_conflict): Handle new instructions.
1696 (is_mve_undefined): Likewise.
1697 (is_mve_unpredictable): Likewise.
1698 (print_mve_size): Likewise.
1699 (print_insn_mve): Likewise.
1700
c507f10b
AV		 17012019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1702 Michael Collison <michael.collison@arm.com>
1703
1704 * arm-dis.c (enum mve_instructions): Add new instructions.
1705 (enum mve_unpredictable): Add new reasons.
1706 (enum mve_undefined): Likewise.
1707 (is_mve_okay_in_it): Handle new isntructions.
1708 (is_mve_encoding_conflict): Likewise.
1709 (is_mve_undefined): Likewise.
1710 (is_mve_unpredictable): Likewise.
1711 (print_mve_vmov_index): Likewise.
1712 (print_simd_imm8): Likewise.
1713 (print_mve_undefined): Likewise.
1714 (print_mve_unpredictable): Likewise.
1715 (print_mve_size): Likewise.
1716 (print_insn_mve): Likewise.
1717
bf0b396d
AV		 17182019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1719 Michael Collison <michael.collison@arm.com>
1720
1721 * arm-dis.c (enum mve_instructions): Add new instructions.
1722 (enum mve_unpredictable): Add new reasons.
1723 (enum mve_undefined): Likewise.
1724 (is_mve_encoding_conflict): Handle new instructions.
1725 (is_mve_undefined): Likewise.
1726 (is_mve_unpredictable): Likewise.
1727 (print_mve_undefined): Likewise.
1728 (print_mve_unpredictable): Likewise.
1729 (print_mve_rounding_mode): Likewise.
1730 (print_mve_vcvt_size): Likewise.
1731 (print_mve_size): Likewise.
1732 (print_insn_mve): Likewise.
1733
ef1576a1
AV		 17342019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1735 Michael Collison <michael.collison@arm.com>
1736
1737 * arm-dis.c (enum mve_instructions): Add new instructions.
1738 (enum mve_unpredictable): Add new reasons.
1739 (enum mve_undefined): Likewise.
1740 (is_mve_undefined): Handle new instructions.
1741 (is_mve_unpredictable): Likewise.
1742 (print_mve_undefined): Likewise.
1743 (print_mve_unpredictable): Likewise.
1744 (print_mve_size): Likewise.
1745 (print_insn_mve): Likewise.
1746
aef6d006
AV		 17472019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1748 Michael Collison <michael.collison@arm.com>
1749
1750 * arm-dis.c (enum mve_instructions): Add new instructions.
1751 (enum mve_undefined): Add new reasons.
1752 (insns): Add new instructions.
1753 (is_mve_encoding_conflict):
1754 (print_mve_vld_str_addr): New print function.
1755 (is_mve_undefined): Handle new instructions.
1756 (is_mve_unpredictable): Likewise.
1757 (print_mve_undefined): Likewise.
1758 (print_mve_size): Likewise.
1759 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1760 (print_insn_mve): Handle new operands.
1761
04d54ace
AV		 17622019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1763 Michael Collison <michael.collison@arm.com>
1764
1765 * arm-dis.c (enum mve_instructions): Add new instructions.
1766 (enum mve_unpredictable): Add new reasons.
1767 (is_mve_encoding_conflict): Handle new instructions.
1768 (is_mve_unpredictable): Likewise.
1769 (mve_opcodes): Add new instructions.
1770 (print_mve_unpredictable): Handle new reasons.
1771 (print_mve_register_blocks): New print function.
1772 (print_mve_size): Handle new instructions.
1773 (print_insn_mve): Likewise.
1774
9743db03
AV		 17752019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1776 Michael Collison <michael.collison@arm.com>
1777
1778 * arm-dis.c (enum mve_instructions): Add new instructions.
1779 (enum mve_unpredictable): Add new reasons.
1780 (enum mve_undefined): Likewise.
1781 (is_mve_encoding_conflict): Handle new instructions.
1782 (is_mve_undefined): Likewise.
1783 (is_mve_unpredictable): Likewise.
1784 (coprocessor_opcodes): Move NEON VDUP from here...
1785 (neon_opcodes): ... to here.
1786 (mve_opcodes): Add new instructions.
1787 (print_mve_undefined): Handle new reasons.
1788 (print_mve_unpredictable): Likewise.
1789 (print_mve_size): Handle new instructions.
1790 (print_insn_neon): Handle vdup.
1791 (print_insn_mve): Handle new operands.
1792
143275ea
AV		 17932019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1794 Michael Collison <michael.collison@arm.com>
1795
1796 * arm-dis.c (enum mve_instructions): Add new instructions.
1797 (enum mve_unpredictable): Add new values.
1798 (mve_opcodes): Add new instructions.
1799 (vec_condnames): New array with vector conditions.
1800 (mve_predicatenames): New array with predicate suffixes.
1801 (mve_vec_sizename): New array with vector sizes.
1802 (enum vpt_pred_state): New enum with vector predication states.
1803 (struct vpt_block): New struct type for vpt blocks.
1804 (vpt_block_state): Global struct to keep track of state.
1805 (mve_extract_pred_mask): New helper function.
1806 (num_instructions_vpt_block): Likewise.
1807 (mark_outside_vpt_block): Likewise.
1808 (mark_inside_vpt_block): Likewise.
1809 (invert_next_predicate_state): Likewise.
1810 (update_next_predicate_state): Likewise.
1811 (update_vpt_block_state): Likewise.
1812 (is_vpt_instruction): Likewise.
1813 (is_mve_encoding_conflict): Add entries for new instructions.
1814 (is_mve_unpredictable): Likewise.
1815 (print_mve_unpredictable): Handle new cases.
1816 (print_instruction_predicate): Likewise.
1817 (print_mve_size): New function.
1818 (print_vec_condition): New function.
1819 (print_insn_mve): Handle vpt blocks and new print operands.
1820
f08d8ce3
AV		 18212019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1822
1823 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1824 8, 14 and 15 for Armv8.1-M Mainline.
1825
73cd51e5
AV		 18262019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1827 Michael Collison <michael.collison@arm.com>
1828
1829 * arm-dis.c (enum mve_instructions): New enum.
1830 (enum mve_unpredictable): Likewise.
1831 (enum mve_undefined): Likewise.
1832 (struct mopcode32): New struct.
1833 (is_mve_okay_in_it): New function.
1834 (is_mve_architecture): Likewise.
1835 (arm_decode_field): Likewise.
1836 (arm_decode_field_multiple): Likewise.
1837 (is_mve_encoding_conflict): Likewise.
1838 (is_mve_undefined): Likewise.
1839 (is_mve_unpredictable): Likewise.
1840 (print_mve_undefined): Likewise.
1841 (print_mve_unpredictable): Likewise.
1842 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1843 (print_insn_mve): New function.
1844 (print_insn_thumb32): Handle MVE architecture.
1845 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1846
3076e594
NC		 18472019-05-10 Nick Clifton <nickc@redhat.com>
1848
1849 PR 24538
1850 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1851 end of the table prematurely.
1852
387e7624
FS		 18532019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1854
1855 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1856 macros for R6.
1857
0067be51
AM		 18582019-05-11 Alan Modra <amodra@gmail.com>
1859
1860 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1861 when -Mraw is in effect.
1862
42e6288f
MM		 18632019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1864
1865 * aarch64-dis-2.c: Regenerate.
1866 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1867 (OP_SVE_BBB): New variant set.
1868 (OP_SVE_DDDD): New variant set.
1869 (OP_SVE_HHH): New variant set.
1870 (OP_SVE_HHHU): New variant set.
1871 (OP_SVE_SSS): New variant set.
1872 (OP_SVE_SSSU): New variant set.
1873 (OP_SVE_SHH): New variant set.
1874 (OP_SVE_SBBU): New variant set.
1875 (OP_SVE_DSS): New variant set.
1876 (OP_SVE_DHHU): New variant set.
1877 (OP_SVE_VMV_HSD_BHS): New variant set.
1878 (OP_SVE_VVU_HSD_BHS): New variant set.
1879 (OP_SVE_VVVU_SD_BH): New variant set.
1880 (OP_SVE_VVVU_BHSD): New variant set.
1881 (OP_SVE_VVV_QHD_DBS): New variant set.
1882 (OP_SVE_VVV_HSD_BHS): New variant set.
1883 (OP_SVE_VVV_HSD_BHS2): New variant set.
1884 (OP_SVE_VVV_BHS_HSD): New variant set.
1885 (OP_SVE_VV_BHS_HSD): New variant set.
1886 (OP_SVE_VVV_SD): New variant set.
1887 (OP_SVE_VVU_BHS_HSD): New variant set.
1888 (OP_SVE_VZVV_SD): New variant set.
1889 (OP_SVE_VZVV_BH): New variant set.
1890 (OP_SVE_VZV_SD): New variant set.
1891 (aarch64_opcode_table): Add sve2 instructions.
1892
28ed815a
MM		 18932019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1894
1895 * aarch64-asm-2.c: Regenerated.
1896 * aarch64-dis-2.c: Regenerated.
1897 * aarch64-opc-2.c: Regenerated.
1898 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1899 for SVE_SHLIMM_UNPRED_22.
1900 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1901 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1902 operand.
1903
fd1dc4a0
MM		 19042019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1905
1906 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1907 sve_size_tsz_bhs iclass encode.
1908 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1909 sve_size_tsz_bhs iclass decode.
1910
31e36ab3
MM		 19112019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1912
1913 * aarch64-asm-2.c: Regenerated.
1914 * aarch64-dis-2.c: Regenerated.
1915 * aarch64-opc-2.c: Regenerated.
1916 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1917 for SVE_Zm4_11_INDEX.
1918 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1919 (fields): Handle SVE_i2h field.
1920 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1921 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1922
1be5f94f
MM		 19232019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1924
1925 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1926 sve_shift_tsz_bhsd iclass encode.
1927 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1928 sve_shift_tsz_bhsd iclass decode.
1929
3c17238b
MM		 19302019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1931
1932 * aarch64-asm-2.c: Regenerated.
1933 * aarch64-dis-2.c: Regenerated.
1934 * aarch64-opc-2.c: Regenerated.
1935 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1936 (aarch64_encode_variant_using_iclass): Handle
1937 sve_shift_tsz_hsd iclass encode.
1938 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1939 sve_shift_tsz_hsd iclass decode.
1940 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1941 for SVE_SHRIMM_UNPRED_22.
1942 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1943 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1944 operand.
1945
cd50a87a
MM		 19462019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1947
1948 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1949 sve_size_013 iclass encode.
1950 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1951 sve_size_013 iclass decode.
1952
3c705960
MM		 19532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1954
1955 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1956 sve_size_bh iclass encode.
1957 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1958 sve_size_bh iclass decode.
1959
0a57e14f
MM		 19602019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1961
1962 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1963 sve_size_sd2 iclass encode.
1964 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1965 sve_size_sd2 iclass decode.
1966 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1967 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1968
c469c864
MM		 19692019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1970
1971 * aarch64-asm-2.c: Regenerated.
1972 * aarch64-dis-2.c: Regenerated.
1973 * aarch64-opc-2.c: Regenerated.
1974 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1975 for SVE_ADDR_ZX.
1976 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1977 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1978
116adc27
MM		 19792019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1980
1981 * aarch64-asm-2.c: Regenerated.
1982 * aarch64-dis-2.c: Regenerated.
1983 * aarch64-opc-2.c: Regenerated.
1984 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1985 for SVE_Zm3_11_INDEX.
1986 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1987 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1988 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1989 fields.
1990 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1991
3bd82c86
MM		 19922019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1993
1994 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1995 sve_size_hsd2 iclass encode.
1996 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1997 sve_size_hsd2 iclass decode.
1998 * aarch64-opc.c (fields): Handle SVE_size field.
1999 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
2000
adccc507
MM		 20012019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2002
2003 * aarch64-asm-2.c: Regenerated.
2004 * aarch64-dis-2.c: Regenerated.
2005 * aarch64-opc-2.c: Regenerated.
2006 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
2007 for SVE_IMM_ROT3.
2008 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
2009 (fields): Handle SVE_rot3 field.
2010 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
2011 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
2012
5cd99750
MM		 20132019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2014
2015 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
2016 instructions.
2017
7ce2460a
MM		 20182019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2019
2020 * aarch64-tbl.h
2021 (aarch64_feature_sve2, aarch64_feature_sve2aes,
2022 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
2023 aarch64_feature_sve2bitperm): New feature sets.
2024 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
2025 for feature set addresses.
2026 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
2027 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2028
41cee089
FS		 20292019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
2030 Faraz Shahbazker <fshahbazker@wavecomp.com>
2031
2032 * mips-dis.c (mips_calculate_combination_ases): Add ISA
2033 argument and set ASE_EVA_R6 appropriately.
2034 (set_default_mips_dis_options): Pass ISA to above.
2035 (parse_mips_dis_option): Likewise.
2036 * mips-opc.c (EVAR6): New macro.
2037 (mips_builtin_opcodes): Add llwpe, scwpe.
2038
b83b4b13
SD		 20392019-05-01 Sudakshina Das <sudi.das@arm.com>
2040
2041 * aarch64-asm-2.c: Regenerated.
2042 * aarch64-dis-2.c: Regenerated.
2043 * aarch64-opc-2.c: Regenerated.
2044 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
2045 AARCH64_OPND_TME_UIMM16.
2046 (aarch64_print_operand): Likewise.
2047 * aarch64-tbl.h (QL_IMM_NIL): New.
2048 (TME): New.
2049 (_TME_INSN): New.
2050 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2051
4a90ce95
JD		 20522019-04-29 John Darrington <john@darrington.wattle.id.au>
2053
2054 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
2055
a45328b9
AB		 20562019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
2057 Faraz Shahbazker <fshahbazker@wavecomp.com>
2058
2059 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2060
d10be0cb
JD		 20612019-04-24 John Darrington <john@darrington.wattle.id.au>
2062
2063 * s12z-opc.h: Add extern "C" bracketing to help
2064 users who wish to use this interface in c++ code.
2065
a679f24e
JD		 20662019-04-24 John Darrington <john@darrington.wattle.id.au>
2067
2068 * s12z-opc.c (bm_decode): Handle bit map operations with the
2069 "reserved0" mode.
2070
32c36c3c
AV		 20712019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2072
2073 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
2074 specifier. Add entries for VLDR and VSTR of system registers.
2075 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
2076 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
2077 of %J and %K format specifier.
2078
efd6b359
AV		 20792019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2080
2081 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2082 Add new entries for VSCCLRM instruction.
2083 (print_insn_coprocessor): Handle new %C format control code.
2084
6b0dd094
AV		 20852019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2086
2087 * arm-dis.c (enum isa): New enum.
2088 (struct sopcode32): New structure.
2089 (coprocessor_opcodes): change type of entries to struct sopcode32 and
2090 set isa field of all current entries to ANY.
2091 (print_insn_coprocessor): Change type of insn to struct sopcode32.
2092 Only match an entry if its isa field allows the current mode.
2093
4b5a202f
AV		 20942019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2095
2096 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
2097 CLRM.
2098 (print_insn_thumb32): Add logic to print %n CLRM register list.
2099
60f993ce
AV		 21002019-04-15 Sudakshina Das <sudi.das@arm.com>
2101
2102 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2103 and %Q patterns.
2104
f6b2b12d
AV		 21052019-04-15 Sudakshina Das <sudi.das@arm.com>
2106
2107 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2108 (print_insn_thumb32): Edit the switch case for %Z.
2109
1889da70
AV		 21102019-04-15 Sudakshina Das <sudi.das@arm.com>
2111
2112 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2113
65d1bc05
AV		 21142019-04-15 Sudakshina Das <sudi.das@arm.com>
2115
2116 * arm-dis.c (thumb32_opcodes): New instruction bfl.
2117
1caf72a5
AV		 21182019-04-15 Sudakshina Das <sudi.das@arm.com>
2119
2120 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2121
f1c7f421
AV		 21222019-04-15 Sudakshina Das <sudi.das@arm.com>
2123
2124 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2125 Arm register with r13 and r15 unpredictable.
2126 (thumb32_opcodes): New instructions for bfx and bflx.
2127
4389b29a
AV		 21282019-04-15 Sudakshina Das <sudi.das@arm.com>
2129
2130 * arm-dis.c (thumb32_opcodes): New instructions for bf.
2131
e5d6e09e
AV		 21322019-04-15 Sudakshina Das <sudi.das@arm.com>
2133
2134 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2135
e12437dc
AV		 21362019-04-15 Sudakshina Das <sudi.das@arm.com>
2137
2138 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2139
031254f2
AV		 21402019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2141
2142 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2143
e5a557ac
JD		 21442019-04-12 John Darrington <john@darrington.wattle.id.au>
2145
2146 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2147 "optr". ("operator" is a reserved word in c++).
2148
bd7ceb8d
SD		 21492019-04-11 Sudakshina Das <sudi.das@arm.com>
2150
2151 * aarch64-opc.c (aarch64_print_operand): Add case for
2152 AARCH64_OPND_Rt_SP.
2153 (verify_constraints): Likewise.
2154 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2155 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2156 to accept Rt|SP as first operand.
2157 (AARCH64_OPERANDS): Add new Rt_SP.
2158 * aarch64-asm-2.c: Regenerated.
2159 * aarch64-dis-2.c: Regenerated.
2160 * aarch64-opc-2.c: Regenerated.
2161
e54010f1
SD		 21622019-04-11 Sudakshina Das <sudi.das@arm.com>
2163
2164 * aarch64-asm-2.c: Regenerated.
2165 * aarch64-dis-2.c: Likewise.
2166 * aarch64-opc-2.c: Likewise.
2167 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2168
7e96e219
RS		 21692019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2170
2171 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2172
6f2791d5
L		 21732019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2174
2175 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2176 * i386-init.h: Regenerated.
2177
e392bad3
AM		 21782019-04-07 Alan Modra <amodra@gmail.com>
2179
2180 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2181 op_separator to control printing of spaces, comma and parens
2182 rather than need_comma, need_paren and spaces vars.
2183
dffaa15c
AM		 21842019-04-07 Alan Modra <amodra@gmail.com>
2185
2186 PR 24421
2187 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2188 (print_insn_neon, print_insn_arm): Likewise.
2189
d6aab7a1
XG		 21902019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2191
2192 * i386-dis-evex.h (evex_table): Updated to support BF16
2193 instructions.
2194 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2195 and EVEX_W_0F3872_P_3.
2196 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2197 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2198 * i386-opc.h (enum): Add CpuAVX512_BF16.
2199 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2200 * i386-opc.tbl: Add AVX512 BF16 instructions.
2201 * i386-init.h: Regenerated.
2202 * i386-tbl.h: Likewise.
2203
66e85460
AM		 22042019-04-05 Alan Modra <amodra@gmail.com>
2205
2206 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2207 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2208 to favour printing of "-" branch hint when using the "y" bit.
2209 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2210
c2b1c275
AM		 22112019-04-05 Alan Modra <amodra@gmail.com>
2212
2213 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2214 opcode until first operand is output.
2215
aae9718e
PB		 22162019-04-04 Peter Bergner <bergner@linux.ibm.com>
2217
2218 PR gas/24349
2219 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2220 (valid_bo_post_v2): Add support for 'at' branch hints.
2221 (insert_bo): Only error on branch on ctr.
2222 (get_bo_hint_mask): New function.
2223 (insert_boe): Add new 'branch_taken' formal argument. Add support
2224 for inserting 'at' branch hints.
2225 (extract_boe): Add new 'branch_taken' formal argument. Add support
2226 for extracting 'at' branch hints.
2227 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2228 (BOE): Delete operand.
2229 (BOM, BOP): New operands.
2230 (RM): Update value.
2231 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2232 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2233 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2234 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2235 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2236 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2237 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2238 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2239 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2240 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2241 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2242 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2243 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2244 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2245 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2246 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2247 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2248 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2249 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2250 bttarl+>: New extended mnemonics.
2251
96a86c01
AM		 22522019-03-28 Alan Modra <amodra@gmail.com>
2253
2254 PR 24390
2255 * ppc-opc.c (BTF): Define.
2256 (powerpc_opcodes): Use for mtfsb*.
2257 * ppc-dis.c (print_insn_powerpc): Print fields with both
2258 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2259
796d6298
TC		 22602019-03-25 Tamar Christina <tamar.christina@arm.com>
2261
2262 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2263 (mapping_symbol_for_insn): Implement new algorithm.
2264 (print_insn): Remove duplicate code.
2265
60df3720
TC		 22662019-03-25 Tamar Christina <tamar.christina@arm.com>
2267
2268 * aarch64-dis.c (print_insn_aarch64):
2269 Implement override.
2270
51457761
TC		 22712019-03-25 Tamar Christina <tamar.christina@arm.com>
2272
2273 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2274 order.
2275
53b2f36b
TC		 22762019-03-25 Tamar Christina <tamar.christina@arm.com>
2277
2278 * aarch64-dis.c (last_stop_offset): New.
2279 (print_insn_aarch64): Use stop_offset.
2280
89199bb5
L		 22812019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2282
2283 PR gas/24359
2284 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2285 CPU_ANY_AVX2_FLAGS.
2286 * i386-init.h: Regenerated.
2287
97ed31ae
L		 22882019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2289
2290 PR gas/24348
2291 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2292 vmovdqu16, vmovdqu32 and vmovdqu64.
2293 * i386-tbl.h: Regenerated.
2294
0919bfe9
AK		 22952019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2296
2297 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2298 from vstrszb, vstrszh, and vstrszf.
2299
23002019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2301
2302 * s390-opc.txt: Add instruction descriptions.
2303
21820ebe
JW		 23042019-02-08 Jim Wilson <jimw@sifive.com>
2305
2306 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2307 <bne>: Likewise.
2308
f7dd2fb2
TC		 23092019-02-07 Tamar Christina <tamar.christina@arm.com>
2310
2311 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2312
6456d318
TC		 23132019-02-07 Tamar Christina <tamar.christina@arm.com>
2314
2315 PR binutils/23212
2316 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2317 * aarch64-opc.c (verify_elem_sd): New.
2318 (fields): Add FLD_sz entr.
2319 * aarch64-tbl.h (_SIMD_INSN): New.
2320 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2321 fmulx scalar and vector by element isns.
2322
4a83b610
NC		 23232019-02-07 Nick Clifton <nickc@redhat.com>
2324
2325 * po/sv.po: Updated Swedish translation.
2326
fc60b8c8
AK		 23272019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2328
2329 * s390-mkopc.c (main): Accept arch13 as cpu string.
2330 * s390-opc.c: Add new instruction formats and instruction opcode
2331 masks.
2332 * s390-opc.txt: Add new arch13 instructions.
2333
e10620d3
TC		 23342019-01-25 Sudakshina Das <sudi.das@arm.com>
2335
2336 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2337 (aarch64_opcode): Change encoding for stg, stzg
2338 st2g and st2zg.
2339 * aarch64-asm-2.c: Regenerated.
2340 * aarch64-dis-2.c: Regenerated.
2341 * aarch64-opc-2.c: Regenerated.
2342
20a4ca55
SD		 23432019-01-25 Sudakshina Das <sudi.das@arm.com>
2344
2345 * aarch64-asm-2.c: Regenerated.
2346 * aarch64-dis-2.c: Likewise.
2347 * aarch64-opc-2.c: Likewise.
2348 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2349
550fd7bf
SD		 23502019-01-25 Sudakshina Das <sudi.das@arm.com>
2351 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2352
2353 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2354 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2355 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2356 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2357 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2358 case for ldstgv_indexed.
2359 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2360 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2361 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2362 * aarch64-asm-2.c: Regenerated.
2363 * aarch64-dis-2.c: Regenerated.
2364 * aarch64-opc-2.c: Regenerated.
2365
d9938630
NC		 23662019-01-23 Nick Clifton <nickc@redhat.com>
2367
2368 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2369
375cd423
NC		 23702019-01-21 Nick Clifton <nickc@redhat.com>
2371
2372 * po/de.po: Updated German translation.
2373 * po/uk.po: Updated Ukranian translation.
2374
57299f48
CX		 23752019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2376 * mips-dis.c (mips_arch_choices): Fix typo in
2377 gs464, gs464e and gs264e descriptors.
2378
f48dfe41
NC		 23792019-01-19 Nick Clifton <nickc@redhat.com>
2380
2381 * configure: Regenerate.
2382 * po/opcodes.pot: Regenerate.
2383
f974f26c
NC		 23842018-06-24 Nick Clifton <nickc@redhat.com>
2385
2386 2.32 branch created.
2387
39f286cd
JD		 23882019-01-09 John Darrington <john@darrington.wattle.id.au>
2389
448b8ca8
JD		 2390 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2391 if it is null.
2392 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2393 zero.
2394
3107326d
AP		 23952019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2396
2397 * configure: Regenerate.
2398
7e9ca91e
AM		 23992019-01-07 Alan Modra <amodra@gmail.com>
2400
2401 * configure: Regenerate.
2402 * po/POTFILES.in: Regenerate.
2403
ef1ad42b
JD		 24042019-01-03 John Darrington <john@darrington.wattle.id.au>
2405
2406 * s12z-opc.c: New file.
2407 * s12z-opc.h: New file.
2408 * s12z-dis.c: Removed all code not directly related to display
2409 of instructions. Used the interface provided by the new files
2410 instead.
2411 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2412 * Makefile.in: Regenerate.
ef1ad42b 2413 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2414 * configure: Regenerate.
ef1ad42b 2415
82704155
AM		 24162019-01-01 Alan Modra <amodra@gmail.com>
2417
2418 Update year range in copyright notice of all files.
2419
d5c04e1b 2420For older changes see ChangeLog-2018
3499769a 2421\f
d5c04e1b 2422Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2423
2424Copying and distribution of this file, with or without modification,
2425are permitted in any medium without royalty provided the copyright
2426notice and this notice are preserved.
2427
2428Local Variables:
2429mode: change-log
2430left-margin: 8
2431fill-column: 74
2432version-control: never
2433End:
GDB Binutils - Deliverables
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