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Change boolean options to bool instead of int
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
bb695960
PB		 12019-09-16 Phil Blundell <pb@pbcl.net>
2
3 * configure: Regenerated.
4
8063ab7e
MV		 52019-09-10 Miod Vallat <miod@online.fr>
6
7 PR 24982
8 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
9
60391a25
PB		 102019-09-09 Phil Blundell <pb@pbcl.net>
11
12 binutils 2.33 branch created.
13
f44b758d
NC		 142019-09-03 Nick Clifton <nickc@redhat.com>
15
16 PR 24961
17 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
18 greater than zero before indexing via (bufcnt -1).
19
1e4b5e7d
NC		 202019-09-03 Nick Clifton <nickc@redhat.com>
21
22 PR 24958
23 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
24 (MAX_SPEC_REG_NAME_LEN): Define.
25 (struct mmix_dis_info): Use defined constants for array lengths.
26 (get_reg_name): New function.
27 (get_sprec_reg_name): New function.
28 (print_insn_mmix): Use new functions.
29
c4a23bf8
SP		 302019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
31
32 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
33 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
34 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
35
a051e2f3
KT		 362019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
37
38 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
39 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
40 (aarch64_sys_reg_supported_p): Update checks for the above.
41
08132bdd
SP		 422019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
43
44 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
45 cases MVE_SQRSHRL and MVE_UQRSHLL.
46 (print_insn_mve): Add case for specifier 'k' to check
47 specific bit of the instruction.
48
d88bdcb4
PA		 492019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
50
51 PR 24854
52 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
53 encountering an unknown machine type.
54 (print_insn_arc): Handle arc_insn_length returning 0. In error
55 cases return -1 rather than calling abort.
56
bc750500
JB		 572019-08-07 Jan Beulich <jbeulich@suse.com>
58
59 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
60 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
61 IgnoreSize.
62 * i386-tbl.h: Re-generate.
63
23d188c7
BW		 642019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
65
66 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
67 instructions.
68
c0d6f62f
JW		 692019-07-30 Mel Chen <mel.chen@sifive.com>
70
71 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
72 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
73
74 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
75 fscsr.
76
0f3f7167
CZ		 772019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
78
79 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
80 and MPY class instructions.
81 (parse_option): Add nps400 option.
82 (print_arc_disassembler_options): Add nps400 info.
83
7e126ba3
CZ		 842019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
85
86 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
87 (bspop): Likewise.
88 (modapp): Likewise.
89 * arc-opc.c (RAD_CHK): Add.
90 * arc-tbl.h: Regenerate.
91
a028026d
KT		 922019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
93
94 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
95 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
96
ac79ff9e
NC		 972019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
98
99 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
100 instructions as UNPREDICTABLE.
101
231097b0
JM		 1022019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
103
104 * bpf-desc.c: Regenerated.
105
1d942ae9
JB		 1062019-07-17 Jan Beulich <jbeulich@suse.com>
107
108 * i386-gen.c (static_assert): Define.
109 (main): Use it.
110 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
111 (Opcode_Modifier_Num): ... this.
112 (Mem): Delete.
113
dfd69174
JB		 1142019-07-16 Jan Beulich <jbeulich@suse.com>
115
116 * i386-gen.c (operand_types): Move RegMem ...
117 (opcode_modifiers): ... here.
118 * i386-opc.h (RegMem): Move to opcode modifer enum.
119 (union i386_operand_type): Move regmem field ...
120 (struct i386_opcode_modifier): ... here.
121 * i386-opc.tbl (RegMem): Define.
122 (mov, movq): Move RegMem on segment, control, debug, and test
123 register flavors.
124 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
125 to non-SSE2AVX flavor.
126 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
127 Move RegMem on register only flavors. Drop IgnoreSize from
128 legacy encoding flavors.
129 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
130 flavors.
131 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
132 register only flavors.
133 (vmovd): Move RegMem and drop IgnoreSize on register only
134 flavor. Change opcode and operand order to store form.
135 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
136
21df382b
JB		 1372019-07-16 Jan Beulich <jbeulich@suse.com>
138
139 * i386-gen.c (operand_type_init, operand_types): Replace SReg
140 entries.
141 * i386-opc.h (SReg2, SReg3): Replace by ...
142 (SReg): ... this.
143 (union i386_operand_type): Replace sreg fields.
144 * i386-opc.tbl (mov, ): Use SReg.
145 (push, pop): Likewies. Drop i386 and x86-64 specific segment
146 register flavors.
147 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
148 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
149
3719fd55
JM		 1502019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
151
152 * bpf-desc.c: Regenerate.
153 * bpf-opc.c: Likewise.
154 * bpf-opc.h: Likewise.
155
92434a14
JM		 1562019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
157
158 * bpf-desc.c: Regenerate.
159 * bpf-opc.c: Likewise.
160
43dd7626
HPN		 1612019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
162
163 * arm-dis.c (print_insn_coprocessor): Rename index to
164 index_operand.
165
98602811
JW		 1662019-07-05 Kito Cheng <kito.cheng@sifive.com>
167
168 * riscv-opc.c (riscv_insn_types): Add r4 type.
169
170 * riscv-opc.c (riscv_insn_types): Add b and j type.
171
172 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
173 format for sb type and correct s type.
174
01c1ee4a
RS		 1752019-07-02 Richard Sandiford <richard.sandiford@arm.com>
176
177 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
178 SVE FMOV alias of FCPY.
179
83adff69
RS		 1802019-07-02 Richard Sandiford <richard.sandiford@arm.com>
181
182 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
183 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
184
89418844
RS		 1852019-07-02 Richard Sandiford <richard.sandiford@arm.com>
186
187 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
188 registers in an instruction prefixed by MOVPRFX.
189
41be57ca
MM		 1902019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
191
192 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
193 sve_size_13 icode to account for variant behaviour of
194 pmull{t,b}.
195 * aarch64-dis-2.c: Regenerate.
196 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
197 sve_size_13 icode to account for variant behaviour of
198 pmull{t,b}.
199 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
200 (OP_SVE_VVV_Q_D): Add new qualifier.
201 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
202 (struct aarch64_opcode): Split pmull{t,b} into those requiring
203 AES and those not.
204
9d3bf266
JB		 2052019-07-01 Jan Beulich <jbeulich@suse.com>
206
207 * opcodes/i386-gen.c (operand_type_init): Remove
208 OPERAND_TYPE_VEC_IMM4 entry.
209 (operand_types): Remove Vec_Imm4.
210 * opcodes/i386-opc.h (Vec_Imm4): Delete.
211 (union i386_operand_type): Remove vec_imm4.
212 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
213 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
214
c3949f43
JB		 2152019-07-01 Jan Beulich <jbeulich@suse.com>
216
217 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
218 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
219 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
220 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
221 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
222 monitorx, mwaitx): Drop ImmExt from operand-less forms.
223 * i386-tbl.h: Re-generate.
224
5641ec01
JB		 2252019-07-01 Jan Beulich <jbeulich@suse.com>
226
227 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
228 register operands.
229 * i386-tbl.h: Re-generate.
230
79dec6b7
JB		 2312019-07-01 Jan Beulich <jbeulich@suse.com>
232
233 * i386-opc.tbl (C): New.
234 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
235 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
236 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
237 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
238 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
239 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
240 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
241 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
242 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
243 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
244 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
245 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
246 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
247 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
248 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
249 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
250 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
251 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
252 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
253 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
254 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
255 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
256 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
257 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
258 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
259 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
260 flavors.
261 * i386-tbl.h: Re-generate.
262
a0a1771e
JB		 2632019-07-01 Jan Beulich <jbeulich@suse.com>
264
265 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
266 register operands.
267 * i386-tbl.h: Re-generate.
268
cd546e7b
JB		 2692019-07-01 Jan Beulich <jbeulich@suse.com>
270
271 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
272 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
273 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
274 * i386-tbl.h: Re-generate.
275
e3bba3fc
JB		 2762019-07-01 Jan Beulich <jbeulich@suse.com>
277
278 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
279 Disp8MemShift from register only templates.
280 * i386-tbl.h: Re-generate.
281
36cc073e
JB		 2822019-07-01 Jan Beulich <jbeulich@suse.com>
283
284 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
285 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
286 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
287 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
288 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
289 EVEX_W_0F11_P_3_M_1): Delete.
290 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
291 EVEX_W_0F11_P_3): New.
292 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
293 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
294 MOD_EVEX_0F11_PREFIX_3 table entries.
295 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
296 PREFIX_EVEX_0F11 table entries.
297 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
298 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
299 EVEX_W_0F11_P_3_M_{0,1} table entries.
300
219920a7
JB		 3012019-07-01 Jan Beulich <jbeulich@suse.com>
302
303 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
304 Delete.
305
e395f487
L		 3062019-06-27 H.J. Lu <hongjiu.lu@intel.com>
307
308 PR binutils/24719
309 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
310 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
311 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
312 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
313 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
314 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
315 EVEX_LEN_0F38C7_R_6_P_2_W_1.
316 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
317 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
318 PREFIX_EVEX_0F38C6_REG_6 entries.
319 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
320 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
321 EVEX_W_0F38C7_R_6_P_2 entries.
322 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
323 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
324 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
325 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
326 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
327 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
328 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
329
2b7bcc87
JB		 3302019-06-27 Jan Beulich <jbeulich@suse.com>
331
332 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
333 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
334 VEX_LEN_0F2D_P_3): Delete.
335 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
336 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
337 (prefix_table): ... here.
338
c1dc7af5
JB		 3392019-06-27 Jan Beulich <jbeulich@suse.com>
340
341 * i386-dis.c (Iq): Delete.
342 (Id): New.
343 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
344 TBM insns.
345 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
346 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
347 (OP_E_memory): Also honor needindex when deciding whether an
348 address size prefix needs printing.
349 (OP_I): Remove handling of q_mode. Add handling of d_mode.
350
d7560e2d
JW		 3512019-06-26 Jim Wilson <jimw@sifive.com>
352
353 PR binutils/24739
354 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
355 Set info->display_endian to info->endian_code.
356
2c703856
JB		 3572019-06-25 Jan Beulich <jbeulich@suse.com>
358
359 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
360 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
361 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
362 OPERAND_TYPE_ACC64 entries.
363 * i386-init.h: Re-generate.
364
54fbadc0
JB		 3652019-06-25 Jan Beulich <jbeulich@suse.com>
366
367 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
368 Delete.
369 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
370 of dqa_mode.
371 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
372 entries here.
373 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
374 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
375
a280ab8e
JB		 3762019-06-25 Jan Beulich <jbeulich@suse.com>
377
378 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
379 variables.
380
e1a1babd
JB		 3812019-06-25 Jan Beulich <jbeulich@suse.com>
382
383 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
384 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
385 movnti.
d7560e2d 386 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 387 * i386-tbl.h: Re-generate.
388
b8364fa7
JB		 3892019-06-25 Jan Beulich <jbeulich@suse.com>
390
391 * i386-opc.tbl (and): Mark Imm8S form for optimization.
392 * i386-tbl.h: Re-generate.
393
ad692897
L		 3942019-06-21 H.J. Lu <hongjiu.lu@intel.com>
395
396 * i386-dis-evex.h: Break into ...
397 * i386-dis-evex-len.h: New file.
398 * i386-dis-evex-mod.h: Likewise.
399 * i386-dis-evex-prefix.h: Likewise.
400 * i386-dis-evex-reg.h: Likewise.
401 * i386-dis-evex-w.h: Likewise.
402 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
403 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
404 i386-dis-evex-mod.h.
405
f0a6222e
L		 4062019-06-19 H.J. Lu <hongjiu.lu@intel.com>
407
408 PR binutils/24700
409 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
410 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
411 EVEX_W_0F385B_P_2.
412 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
413 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
414 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
415 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
416 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
417 EVEX_LEN_0F385B_P_2_W_1.
418 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
419 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
420 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
421 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
422 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
423 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
424 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
425 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
426 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
427 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
428
6e1c90b7
L		 4292019-06-17 H.J. Lu <hongjiu.lu@intel.com>
430
431 PR binutils/24691
432 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
433 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
434 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
435 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
436 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
437 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
438 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
439 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
440 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
441 EVEX_LEN_0F3A43_P_2_W_1.
442 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
443 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
444 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
445 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
446 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
447 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
448 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
449 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
450 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
451 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
452 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
453 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
454
bcc5a6eb
NC		 4552019-06-14 Nick Clifton <nickc@redhat.com>
456
457 * po/fr.po; Updated French translation.
458
e4c4ac46
SH		 4592019-06-13 Stafford Horne <shorne@gmail.com>
460
461 * or1k-asm.c: Regenerated.
462 * or1k-desc.c: Regenerated.
463 * or1k-desc.h: Regenerated.
464 * or1k-dis.c: Regenerated.
465 * or1k-ibld.c: Regenerated.
466 * or1k-opc.c: Regenerated.
467 * or1k-opc.h: Regenerated.
468 * or1k-opinst.c: Regenerated.
469
a0e44ef5
PB		 4702019-06-12 Peter Bergner <bergner@linux.ibm.com>
471
472 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
473
12efd68d
L		 4742019-06-05 H.J. Lu <hongjiu.lu@intel.com>
475
476 PR binutils/24633
477 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
478 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
479 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
480 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
481 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
482 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
483 EVEX_LEN_0F3A1B_P_2_W_1.
484 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
485 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
486 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
487 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
488 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
489 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
490 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
491 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
492
63c6fc6c
L		 4932019-06-04 H.J. Lu <hongjiu.lu@intel.com>
494
495 PR binutils/24626
496 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
497 EVEX.vvvv when disassembling VEX and EVEX instructions.
498 (OP_VEX): Set vex.register_specifier to 0 after readding
499 vex.register_specifier.
500 (OP_Vex_2src_1): Likewise.
501 (OP_Vex_2src_2): Likewise.
502 (OP_LWP_E): Likewise.
503 (OP_EX_Vex): Don't check vex.register_specifier.
504 (OP_XMM_Vex): Likewise.
505
9186c494
L		 5062019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
507 Lili Cui <lili.cui@intel.com>
508
509 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
510 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
511 instructions.
512 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
513 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
514 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
515 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
516 (i386_cpu_flags): Add cpuavx512_vp2intersect.
517 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
518 * i386-init.h: Regenerated.
519 * i386-tbl.h: Likewise.
520
5d79adc4
L		 5212019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
522 Lili Cui <lili.cui@intel.com>
523
524 * doc/c-i386.texi: Document enqcmd.
525 * testsuite/gas/i386/enqcmd-intel.d: New file.
526 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
527 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
528 * testsuite/gas/i386/enqcmd.d: Likewise.
529 * testsuite/gas/i386/enqcmd.s: Likewise.
530 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
531 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
532 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
533 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
534 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
535 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
536 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
537 and x86-64-enqcmd.
538
a9d96ab9
AH		 5392019-06-04 Alan Hayward <alan.hayward@arm.com>
540
541 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
542
4f6d070a
AM		 5432019-06-03 Alan Modra <amodra@gmail.com>
544
545 * ppc-dis.c (prefix_opcd_indices): Correct size.
546
a2f4b66c
L		 5472019-05-28 H.J. Lu <hongjiu.lu@intel.com>
548
549 PR gas/24625
550 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
551 Disp8ShiftVL.
552 * i386-tbl.h: Regenerated.
553
405b5bd8
AM		 5542019-05-24 Alan Modra <amodra@gmail.com>
555
556 * po/POTFILES.in: Regenerate.
557
8acf1435
PB		 5582019-05-24 Peter Bergner <bergner@linux.ibm.com>
559 Alan Modra <amodra@gmail.com>
560
561 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
562 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
563 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
564 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
565 XTOP>): Define and add entries.
566 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
567 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
568 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
569 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
570
dd7efa79
PB		 5712019-05-24 Peter Bergner <bergner@linux.ibm.com>
572 Alan Modra <amodra@gmail.com>
573
574 * ppc-dis.c (ppc_opts): Add "future" entry.
575 (PREFIX_OPCD_SEGS): Define.
576 (prefix_opcd_indices): New array.
577 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
578 (lookup_prefix): New function.
579 (print_insn_powerpc): Handle 64-bit prefix instructions.
580 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
581 (PMRR, POWERXX): Define.
582 (prefix_opcodes): New instruction table.
583 (prefix_num_opcodes): New constant.
584
79472b45
JM		 5852019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
586
587 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
588 * configure: Regenerated.
589 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
590 and cpu/bpf.opc.
591 (HFILES): Add bpf-desc.h and bpf-opc.h.
592 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
593 bpf-ibld.c and bpf-opc.c.
594 (BPF_DEPS): Define.
595 * Makefile.in: Regenerated.
596 * disassemble.c (ARCH_bpf): Define.
597 (disassembler): Add case for bfd_arch_bpf.
598 (disassemble_init_for_target): Likewise.
599 (enum epbf_isa_attr): Define.
600 * disassemble.h: extern print_insn_bpf.
601 * bpf-asm.c: Generated.
602 * bpf-opc.h: Likewise.
603 * bpf-opc.c: Likewise.
604 * bpf-ibld.c: Likewise.
605 * bpf-dis.c: Likewise.
606 * bpf-desc.h: Likewise.
607 * bpf-desc.c: Likewise.
608
ba6cd17f
SD		 6092019-05-21 Sudakshina Das <sudi.das@arm.com>
610
611 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
612 and VMSR with the new operands.
613
e39c1607
SD		 6142019-05-21 Sudakshina Das <sudi.das@arm.com>
615
616 * arm-dis.c (enum mve_instructions): New enum
617 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
618 and cneg.
619 (mve_opcodes): New instructions as above.
620 (is_mve_encoding_conflict): Add cases for csinc, csinv,
621 csneg and csel.
622 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
623
23d00a41
SD		 6242019-05-21 Sudakshina Das <sudi.das@arm.com>
625
626 * arm-dis.c (emun mve_instructions): Updated for new instructions.
627 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
628 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
629 uqshl, urshrl and urshr.
630 (is_mve_okay_in_it): Add new instructions to TRUE list.
631 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
632 (print_insn_mve): Updated to accept new %j,
633 %<bitfield>m and %<bitfield>n patterns.
634
cd4797ee
FS		 6352019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
636
637 * mips-opc.c (mips_builtin_opcodes): Change source register
638 constraint for DAUI.
639
999b073b
NC		 6402019-05-20 Nick Clifton <nickc@redhat.com>
641
642 * po/fr.po: Updated French translation.
643
14b456f2
AV		 6442019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
645 Michael Collison <michael.collison@arm.com>
646
647 * arm-dis.c (thumb32_opcodes): Add new instructions.
648 (enum mve_instructions): Likewise.
649 (enum mve_undefined): Add new reasons.
650 (is_mve_encoding_conflict): Handle new instructions.
651 (is_mve_undefined): Likewise.
652 (is_mve_unpredictable): Likewise.
653 (print_mve_undefined): Likewise.
654 (print_mve_size): Likewise.
655
f49bb598
AV		 6562019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
657 Michael Collison <michael.collison@arm.com>
658
659 * arm-dis.c (thumb32_opcodes): Add new instructions.
660 (enum mve_instructions): Likewise.
661 (is_mve_encoding_conflict): Handle new instructions.
662 (is_mve_undefined): Likewise.
663 (is_mve_unpredictable): Likewise.
664 (print_mve_size): Likewise.
665
56858bea
AV		 6662019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
667 Michael Collison <michael.collison@arm.com>
668
669 * arm-dis.c (thumb32_opcodes): Add new instructions.
670 (enum mve_instructions): Likewise.
671 (is_mve_encoding_conflict): Likewise.
672 (is_mve_unpredictable): Likewise.
673 (print_mve_size): Likewise.
674
e523f101
AV		 6752019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
676 Michael Collison <michael.collison@arm.com>
677
678 * arm-dis.c (thumb32_opcodes): Add new instructions.
679 (enum mve_instructions): Likewise.
680 (is_mve_encoding_conflict): Handle new instructions.
681 (is_mve_undefined): Likewise.
682 (is_mve_unpredictable): Likewise.
683 (print_mve_size): Likewise.
684
66dcaa5d
AV		 6852019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
686 Michael Collison <michael.collison@arm.com>
687
688 * arm-dis.c (thumb32_opcodes): Add new instructions.
689 (enum mve_instructions): Likewise.
690 (is_mve_encoding_conflict): Handle new instructions.
691 (is_mve_undefined): Likewise.
692 (is_mve_unpredictable): Likewise.
693 (print_mve_size): Likewise.
694 (print_insn_mve): Likewise.
695
d052b9b7
AV		 6962019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
697 Michael Collison <michael.collison@arm.com>
698
699 * arm-dis.c (thumb32_opcodes): Add new instructions.
700 (print_insn_thumb32): Handle new instructions.
701
ed63aa17
AV		 7022019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
703 Michael Collison <michael.collison@arm.com>
704
705 * arm-dis.c (enum mve_instructions): Add new instructions.
706 (enum mve_undefined): Add new reasons.
707 (is_mve_encoding_conflict): Handle new instructions.
708 (is_mve_undefined): Likewise.
709 (is_mve_unpredictable): Likewise.
710 (print_mve_undefined): Likewise.
711 (print_mve_size): Likewise.
712 (print_mve_shift_n): Likewise.
713 (print_insn_mve): Likewise.
714
897b9bbc
AV		 7152019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
716 Michael Collison <michael.collison@arm.com>
717
718 * arm-dis.c (enum mve_instructions): Add new instructions.
719 (is_mve_encoding_conflict): Handle new instructions.
720 (is_mve_unpredictable): Likewise.
721 (print_mve_rotate): Likewise.
722 (print_mve_size): Likewise.
723 (print_insn_mve): Likewise.
724
1c8f2df8
AV		 7252019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
726 Michael Collison <michael.collison@arm.com>
727
728 * arm-dis.c (enum mve_instructions): Add new instructions.
729 (is_mve_encoding_conflict): Handle new instructions.
730 (is_mve_unpredictable): Likewise.
731 (print_mve_size): Likewise.
732 (print_insn_mve): Likewise.
733
d3b63143
AV		 7342019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
735 Michael Collison <michael.collison@arm.com>
736
737 * arm-dis.c (enum mve_instructions): Add new instructions.
738 (enum mve_undefined): Add new reasons.
739 (is_mve_encoding_conflict): Handle new instructions.
740 (is_mve_undefined): Likewise.
741 (is_mve_unpredictable): Likewise.
742 (print_mve_undefined): Likewise.
743 (print_mve_size): Likewise.
744 (print_insn_mve): Likewise.
745
14925797
AV		 7462019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
747 Michael Collison <michael.collison@arm.com>
748
749 * arm-dis.c (enum mve_instructions): Add new instructions.
750 (is_mve_encoding_conflict): Handle new instructions.
751 (is_mve_undefined): Likewise.
752 (is_mve_unpredictable): Likewise.
753 (print_mve_size): Likewise.
754 (print_insn_mve): Likewise.
755
c507f10b
AV		 7562019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
757 Michael Collison <michael.collison@arm.com>
758
759 * arm-dis.c (enum mve_instructions): Add new instructions.
760 (enum mve_unpredictable): Add new reasons.
761 (enum mve_undefined): Likewise.
762 (is_mve_okay_in_it): Handle new isntructions.
763 (is_mve_encoding_conflict): Likewise.
764 (is_mve_undefined): Likewise.
765 (is_mve_unpredictable): Likewise.
766 (print_mve_vmov_index): Likewise.
767 (print_simd_imm8): Likewise.
768 (print_mve_undefined): Likewise.
769 (print_mve_unpredictable): Likewise.
770 (print_mve_size): Likewise.
771 (print_insn_mve): Likewise.
772
bf0b396d
AV		 7732019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
774 Michael Collison <michael.collison@arm.com>
775
776 * arm-dis.c (enum mve_instructions): Add new instructions.
777 (enum mve_unpredictable): Add new reasons.
778 (enum mve_undefined): Likewise.
779 (is_mve_encoding_conflict): Handle new instructions.
780 (is_mve_undefined): Likewise.
781 (is_mve_unpredictable): Likewise.
782 (print_mve_undefined): Likewise.
783 (print_mve_unpredictable): Likewise.
784 (print_mve_rounding_mode): Likewise.
785 (print_mve_vcvt_size): Likewise.
786 (print_mve_size): Likewise.
787 (print_insn_mve): Likewise.
788
ef1576a1
AV		 7892019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
790 Michael Collison <michael.collison@arm.com>
791
792 * arm-dis.c (enum mve_instructions): Add new instructions.
793 (enum mve_unpredictable): Add new reasons.
794 (enum mve_undefined): Likewise.
795 (is_mve_undefined): Handle new instructions.
796 (is_mve_unpredictable): Likewise.
797 (print_mve_undefined): Likewise.
798 (print_mve_unpredictable): Likewise.
799 (print_mve_size): Likewise.
800 (print_insn_mve): Likewise.
801
aef6d006
AV		 8022019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
803 Michael Collison <michael.collison@arm.com>
804
805 * arm-dis.c (enum mve_instructions): Add new instructions.
806 (enum mve_undefined): Add new reasons.
807 (insns): Add new instructions.
808 (is_mve_encoding_conflict):
809 (print_mve_vld_str_addr): New print function.
810 (is_mve_undefined): Handle new instructions.
811 (is_mve_unpredictable): Likewise.
812 (print_mve_undefined): Likewise.
813 (print_mve_size): Likewise.
814 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
815 (print_insn_mve): Handle new operands.
816
04d54ace
AV		 8172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
818 Michael Collison <michael.collison@arm.com>
819
820 * arm-dis.c (enum mve_instructions): Add new instructions.
821 (enum mve_unpredictable): Add new reasons.
822 (is_mve_encoding_conflict): Handle new instructions.
823 (is_mve_unpredictable): Likewise.
824 (mve_opcodes): Add new instructions.
825 (print_mve_unpredictable): Handle new reasons.
826 (print_mve_register_blocks): New print function.
827 (print_mve_size): Handle new instructions.
828 (print_insn_mve): Likewise.
829
9743db03
AV		 8302019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
831 Michael Collison <michael.collison@arm.com>
832
833 * arm-dis.c (enum mve_instructions): Add new instructions.
834 (enum mve_unpredictable): Add new reasons.
835 (enum mve_undefined): Likewise.
836 (is_mve_encoding_conflict): Handle new instructions.
837 (is_mve_undefined): Likewise.
838 (is_mve_unpredictable): Likewise.
839 (coprocessor_opcodes): Move NEON VDUP from here...
840 (neon_opcodes): ... to here.
841 (mve_opcodes): Add new instructions.
842 (print_mve_undefined): Handle new reasons.
843 (print_mve_unpredictable): Likewise.
844 (print_mve_size): Handle new instructions.
845 (print_insn_neon): Handle vdup.
846 (print_insn_mve): Handle new operands.
847
143275ea
AV		 8482019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
849 Michael Collison <michael.collison@arm.com>
850
851 * arm-dis.c (enum mve_instructions): Add new instructions.
852 (enum mve_unpredictable): Add new values.
853 (mve_opcodes): Add new instructions.
854 (vec_condnames): New array with vector conditions.
855 (mve_predicatenames): New array with predicate suffixes.
856 (mve_vec_sizename): New array with vector sizes.
857 (enum vpt_pred_state): New enum with vector predication states.
858 (struct vpt_block): New struct type for vpt blocks.
859 (vpt_block_state): Global struct to keep track of state.
860 (mve_extract_pred_mask): New helper function.
861 (num_instructions_vpt_block): Likewise.
862 (mark_outside_vpt_block): Likewise.
863 (mark_inside_vpt_block): Likewise.
864 (invert_next_predicate_state): Likewise.
865 (update_next_predicate_state): Likewise.
866 (update_vpt_block_state): Likewise.
867 (is_vpt_instruction): Likewise.
868 (is_mve_encoding_conflict): Add entries for new instructions.
869 (is_mve_unpredictable): Likewise.
870 (print_mve_unpredictable): Handle new cases.
871 (print_instruction_predicate): Likewise.
872 (print_mve_size): New function.
873 (print_vec_condition): New function.
874 (print_insn_mve): Handle vpt blocks and new print operands.
875
f08d8ce3
AV		 8762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
877
878 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
879 8, 14 and 15 for Armv8.1-M Mainline.
880
73cd51e5
AV		 8812019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
882 Michael Collison <michael.collison@arm.com>
883
884 * arm-dis.c (enum mve_instructions): New enum.
885 (enum mve_unpredictable): Likewise.
886 (enum mve_undefined): Likewise.
887 (struct mopcode32): New struct.
888 (is_mve_okay_in_it): New function.
889 (is_mve_architecture): Likewise.
890 (arm_decode_field): Likewise.
891 (arm_decode_field_multiple): Likewise.
892 (is_mve_encoding_conflict): Likewise.
893 (is_mve_undefined): Likewise.
894 (is_mve_unpredictable): Likewise.
895 (print_mve_undefined): Likewise.
896 (print_mve_unpredictable): Likewise.
897 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
898 (print_insn_mve): New function.
899 (print_insn_thumb32): Handle MVE architecture.
900 (select_arm_features): Force thumb for Armv8.1-m Mainline.
901
3076e594
NC		 9022019-05-10 Nick Clifton <nickc@redhat.com>
903
904 PR 24538
905 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
906 end of the table prematurely.
907
387e7624
FS		 9082019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
909
910 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
911 macros for R6.
912
0067be51
AM		 9132019-05-11 Alan Modra <amodra@gmail.com>
914
915 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
916 when -Mraw is in effect.
917
42e6288f
MM		 9182019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
919
920 * aarch64-dis-2.c: Regenerate.
921 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
922 (OP_SVE_BBB): New variant set.
923 (OP_SVE_DDDD): New variant set.
924 (OP_SVE_HHH): New variant set.
925 (OP_SVE_HHHU): New variant set.
926 (OP_SVE_SSS): New variant set.
927 (OP_SVE_SSSU): New variant set.
928 (OP_SVE_SHH): New variant set.
929 (OP_SVE_SBBU): New variant set.
930 (OP_SVE_DSS): New variant set.
931 (OP_SVE_DHHU): New variant set.
932 (OP_SVE_VMV_HSD_BHS): New variant set.
933 (OP_SVE_VVU_HSD_BHS): New variant set.
934 (OP_SVE_VVVU_SD_BH): New variant set.
935 (OP_SVE_VVVU_BHSD): New variant set.
936 (OP_SVE_VVV_QHD_DBS): New variant set.
937 (OP_SVE_VVV_HSD_BHS): New variant set.
938 (OP_SVE_VVV_HSD_BHS2): New variant set.
939 (OP_SVE_VVV_BHS_HSD): New variant set.
940 (OP_SVE_VV_BHS_HSD): New variant set.
941 (OP_SVE_VVV_SD): New variant set.
942 (OP_SVE_VVU_BHS_HSD): New variant set.
943 (OP_SVE_VZVV_SD): New variant set.
944 (OP_SVE_VZVV_BH): New variant set.
945 (OP_SVE_VZV_SD): New variant set.
946 (aarch64_opcode_table): Add sve2 instructions.
947
28ed815a
MM		 9482019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
949
950 * aarch64-asm-2.c: Regenerated.
951 * aarch64-dis-2.c: Regenerated.
952 * aarch64-opc-2.c: Regenerated.
953 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
954 for SVE_SHLIMM_UNPRED_22.
955 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
956 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
957 operand.
958
fd1dc4a0
MM		 9592019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
960
961 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
962 sve_size_tsz_bhs iclass encode.
963 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
964 sve_size_tsz_bhs iclass decode.
965
31e36ab3
MM		 9662019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
967
968 * aarch64-asm-2.c: Regenerated.
969 * aarch64-dis-2.c: Regenerated.
970 * aarch64-opc-2.c: Regenerated.
971 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
972 for SVE_Zm4_11_INDEX.
973 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
974 (fields): Handle SVE_i2h field.
975 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
976 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
977
1be5f94f
MM		 9782019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
979
980 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
981 sve_shift_tsz_bhsd iclass encode.
982 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
983 sve_shift_tsz_bhsd iclass decode.
984
3c17238b
MM		 9852019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
986
987 * aarch64-asm-2.c: Regenerated.
988 * aarch64-dis-2.c: Regenerated.
989 * aarch64-opc-2.c: Regenerated.
990 * aarch64-asm.c (aarch64_ins_sve_shrimm):
991 (aarch64_encode_variant_using_iclass): Handle
992 sve_shift_tsz_hsd iclass encode.
993 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
994 sve_shift_tsz_hsd iclass decode.
995 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
996 for SVE_SHRIMM_UNPRED_22.
997 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
998 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
999 operand.
1000
cd50a87a
MM		 10012019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1002
1003 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1004 sve_size_013 iclass encode.
1005 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1006 sve_size_013 iclass decode.
1007
3c705960
MM		 10082019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1009
1010 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1011 sve_size_bh iclass encode.
1012 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1013 sve_size_bh iclass decode.
1014
0a57e14f
MM		 10152019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1016
1017 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1018 sve_size_sd2 iclass encode.
1019 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1020 sve_size_sd2 iclass decode.
1021 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1022 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1023
c469c864
MM		 10242019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1025
1026 * aarch64-asm-2.c: Regenerated.
1027 * aarch64-dis-2.c: Regenerated.
1028 * aarch64-opc-2.c: Regenerated.
1029 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1030 for SVE_ADDR_ZX.
1031 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1032 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1033
116adc27
MM		 10342019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1035
1036 * aarch64-asm-2.c: Regenerated.
1037 * aarch64-dis-2.c: Regenerated.
1038 * aarch64-opc-2.c: Regenerated.
1039 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1040 for SVE_Zm3_11_INDEX.
1041 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1042 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1043 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1044 fields.
1045 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1046
3bd82c86
MM		 10472019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1048
1049 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1050 sve_size_hsd2 iclass encode.
1051 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1052 sve_size_hsd2 iclass decode.
1053 * aarch64-opc.c (fields): Handle SVE_size field.
1054 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1055
adccc507
MM		 10562019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1057
1058 * aarch64-asm-2.c: Regenerated.
1059 * aarch64-dis-2.c: Regenerated.
1060 * aarch64-opc-2.c: Regenerated.
1061 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1062 for SVE_IMM_ROT3.
1063 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1064 (fields): Handle SVE_rot3 field.
1065 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1066 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1067
5cd99750
MM		 10682019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1069
1070 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1071 instructions.
1072
7ce2460a
MM		 10732019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1074
1075 * aarch64-tbl.h
1076 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1077 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1078 aarch64_feature_sve2bitperm): New feature sets.
1079 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1080 for feature set addresses.
1081 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1082 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1083
41cee089
FS		 10842019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1085 Faraz Shahbazker <fshahbazker@wavecomp.com>
1086
1087 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1088 argument and set ASE_EVA_R6 appropriately.
1089 (set_default_mips_dis_options): Pass ISA to above.
1090 (parse_mips_dis_option): Likewise.
1091 * mips-opc.c (EVAR6): New macro.
1092 (mips_builtin_opcodes): Add llwpe, scwpe.
1093
b83b4b13
SD		 10942019-05-01 Sudakshina Das <sudi.das@arm.com>
1095
1096 * aarch64-asm-2.c: Regenerated.
1097 * aarch64-dis-2.c: Regenerated.
1098 * aarch64-opc-2.c: Regenerated.
1099 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1100 AARCH64_OPND_TME_UIMM16.
1101 (aarch64_print_operand): Likewise.
1102 * aarch64-tbl.h (QL_IMM_NIL): New.
1103 (TME): New.
1104 (_TME_INSN): New.
1105 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1106
4a90ce95
JD		 11072019-04-29 John Darrington <john@darrington.wattle.id.au>
1108
1109 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1110
a45328b9
AB		 11112019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1112 Faraz Shahbazker <fshahbazker@wavecomp.com>
1113
1114 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1115
d10be0cb
JD		 11162019-04-24 John Darrington <john@darrington.wattle.id.au>
1117
1118 * s12z-opc.h: Add extern "C" bracketing to help
1119 users who wish to use this interface in c++ code.
1120
a679f24e
JD		 11212019-04-24 John Darrington <john@darrington.wattle.id.au>
1122
1123 * s12z-opc.c (bm_decode): Handle bit map operations with the
1124 "reserved0" mode.
1125
32c36c3c
AV		 11262019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1127
1128 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1129 specifier. Add entries for VLDR and VSTR of system registers.
1130 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1131 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1132 of %J and %K format specifier.
1133
efd6b359
AV		 11342019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1135
1136 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1137 Add new entries for VSCCLRM instruction.
1138 (print_insn_coprocessor): Handle new %C format control code.
1139
6b0dd094
AV		 11402019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1141
1142 * arm-dis.c (enum isa): New enum.
1143 (struct sopcode32): New structure.
1144 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1145 set isa field of all current entries to ANY.
1146 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1147 Only match an entry if its isa field allows the current mode.
1148
4b5a202f
AV		 11492019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1150
1151 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1152 CLRM.
1153 (print_insn_thumb32): Add logic to print %n CLRM register list.
1154
60f993ce
AV		 11552019-04-15 Sudakshina Das <sudi.das@arm.com>
1156
1157 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1158 and %Q patterns.
1159
f6b2b12d
AV		 11602019-04-15 Sudakshina Das <sudi.das@arm.com>
1161
1162 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1163 (print_insn_thumb32): Edit the switch case for %Z.
1164
1889da70
AV		 11652019-04-15 Sudakshina Das <sudi.das@arm.com>
1166
1167 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1168
65d1bc05
AV		 11692019-04-15 Sudakshina Das <sudi.das@arm.com>
1170
1171 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1172
1caf72a5
AV		 11732019-04-15 Sudakshina Das <sudi.das@arm.com>
1174
1175 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1176
f1c7f421
AV		 11772019-04-15 Sudakshina Das <sudi.das@arm.com>
1178
1179 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1180 Arm register with r13 and r15 unpredictable.
1181 (thumb32_opcodes): New instructions for bfx and bflx.
1182
4389b29a
AV		 11832019-04-15 Sudakshina Das <sudi.das@arm.com>
1184
1185 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1186
e5d6e09e
AV		 11872019-04-15 Sudakshina Das <sudi.das@arm.com>
1188
1189 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1190
e12437dc
AV		 11912019-04-15 Sudakshina Das <sudi.das@arm.com>
1192
1193 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1194
031254f2
AV		 11952019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1196
1197 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1198
e5a557ac
JD		 11992019-04-12 John Darrington <john@darrington.wattle.id.au>
1200
1201 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1202 "optr". ("operator" is a reserved word in c++).
1203
bd7ceb8d
SD		 12042019-04-11 Sudakshina Das <sudi.das@arm.com>
1205
1206 * aarch64-opc.c (aarch64_print_operand): Add case for
1207 AARCH64_OPND_Rt_SP.
1208 (verify_constraints): Likewise.
1209 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1210 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1211 to accept Rt|SP as first operand.
1212 (AARCH64_OPERANDS): Add new Rt_SP.
1213 * aarch64-asm-2.c: Regenerated.
1214 * aarch64-dis-2.c: Regenerated.
1215 * aarch64-opc-2.c: Regenerated.
1216
e54010f1
SD		 12172019-04-11 Sudakshina Das <sudi.das@arm.com>
1218
1219 * aarch64-asm-2.c: Regenerated.
1220 * aarch64-dis-2.c: Likewise.
1221 * aarch64-opc-2.c: Likewise.
1222 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1223
7e96e219
RS		 12242019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1225
1226 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1227
6f2791d5
L		 12282019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1229
1230 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1231 * i386-init.h: Regenerated.
1232
e392bad3
AM		 12332019-04-07 Alan Modra <amodra@gmail.com>
1234
1235 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1236 op_separator to control printing of spaces, comma and parens
1237 rather than need_comma, need_paren and spaces vars.
1238
dffaa15c
AM		 12392019-04-07 Alan Modra <amodra@gmail.com>
1240
1241 PR 24421
1242 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1243 (print_insn_neon, print_insn_arm): Likewise.
1244
d6aab7a1
XG		 12452019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1246
1247 * i386-dis-evex.h (evex_table): Updated to support BF16
1248 instructions.
1249 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1250 and EVEX_W_0F3872_P_3.
1251 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1252 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1253 * i386-opc.h (enum): Add CpuAVX512_BF16.
1254 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1255 * i386-opc.tbl: Add AVX512 BF16 instructions.
1256 * i386-init.h: Regenerated.
1257 * i386-tbl.h: Likewise.
1258
66e85460
AM		 12592019-04-05 Alan Modra <amodra@gmail.com>
1260
1261 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1262 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1263 to favour printing of "-" branch hint when using the "y" bit.
1264 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1265
c2b1c275
AM		 12662019-04-05 Alan Modra <amodra@gmail.com>
1267
1268 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1269 opcode until first operand is output.
1270
aae9718e
PB		 12712019-04-04 Peter Bergner <bergner@linux.ibm.com>
1272
1273 PR gas/24349
1274 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1275 (valid_bo_post_v2): Add support for 'at' branch hints.
1276 (insert_bo): Only error on branch on ctr.
1277 (get_bo_hint_mask): New function.
1278 (insert_boe): Add new 'branch_taken' formal argument. Add support
1279 for inserting 'at' branch hints.
1280 (extract_boe): Add new 'branch_taken' formal argument. Add support
1281 for extracting 'at' branch hints.
1282 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1283 (BOE): Delete operand.
1284 (BOM, BOP): New operands.
1285 (RM): Update value.
1286 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1287 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1288 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1289 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1290 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1291 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1292 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1293 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1294 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1295 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1296 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1297 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1298 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1299 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1300 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1301 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1302 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1303 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1304 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1305 bttarl+>: New extended mnemonics.
1306
96a86c01
AM		 13072019-03-28 Alan Modra <amodra@gmail.com>
1308
1309 PR 24390
1310 * ppc-opc.c (BTF): Define.
1311 (powerpc_opcodes): Use for mtfsb*.
1312 * ppc-dis.c (print_insn_powerpc): Print fields with both
1313 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1314
796d6298
TC		 13152019-03-25 Tamar Christina <tamar.christina@arm.com>
1316
1317 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1318 (mapping_symbol_for_insn): Implement new algorithm.
1319 (print_insn): Remove duplicate code.
1320
60df3720
TC		 13212019-03-25 Tamar Christina <tamar.christina@arm.com>
1322
1323 * aarch64-dis.c (print_insn_aarch64):
1324 Implement override.
1325
51457761
TC		 13262019-03-25 Tamar Christina <tamar.christina@arm.com>
1327
1328 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1329 order.
1330
53b2f36b
TC		 13312019-03-25 Tamar Christina <tamar.christina@arm.com>
1332
1333 * aarch64-dis.c (last_stop_offset): New.
1334 (print_insn_aarch64): Use stop_offset.
1335
89199bb5
L		 13362019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1337
1338 PR gas/24359
1339 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1340 CPU_ANY_AVX2_FLAGS.
1341 * i386-init.h: Regenerated.
1342
97ed31ae
L		 13432019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1344
1345 PR gas/24348
1346 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1347 vmovdqu16, vmovdqu32 and vmovdqu64.
1348 * i386-tbl.h: Regenerated.
1349
0919bfe9
AK		 13502019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1351
1352 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1353 from vstrszb, vstrszh, and vstrszf.
1354
13552019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1356
1357 * s390-opc.txt: Add instruction descriptions.
1358
21820ebe
JW		 13592019-02-08 Jim Wilson <jimw@sifive.com>
1360
1361 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1362 <bne>: Likewise.
1363
f7dd2fb2
TC		 13642019-02-07 Tamar Christina <tamar.christina@arm.com>
1365
1366 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1367
6456d318
TC		 13682019-02-07 Tamar Christina <tamar.christina@arm.com>
1369
1370 PR binutils/23212
1371 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1372 * aarch64-opc.c (verify_elem_sd): New.
1373 (fields): Add FLD_sz entr.
1374 * aarch64-tbl.h (_SIMD_INSN): New.
1375 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1376 fmulx scalar and vector by element isns.
1377
4a83b610
NC		 13782019-02-07 Nick Clifton <nickc@redhat.com>
1379
1380 * po/sv.po: Updated Swedish translation.
1381
fc60b8c8
AK		 13822019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1383
1384 * s390-mkopc.c (main): Accept arch13 as cpu string.
1385 * s390-opc.c: Add new instruction formats and instruction opcode
1386 masks.
1387 * s390-opc.txt: Add new arch13 instructions.
1388
e10620d3
TC		 13892019-01-25 Sudakshina Das <sudi.das@arm.com>
1390
1391 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1392 (aarch64_opcode): Change encoding for stg, stzg
1393 st2g and st2zg.
1394 * aarch64-asm-2.c: Regenerated.
1395 * aarch64-dis-2.c: Regenerated.
1396 * aarch64-opc-2.c: Regenerated.
1397
20a4ca55
SD		 13982019-01-25 Sudakshina Das <sudi.das@arm.com>
1399
1400 * aarch64-asm-2.c: Regenerated.
1401 * aarch64-dis-2.c: Likewise.
1402 * aarch64-opc-2.c: Likewise.
1403 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1404
550fd7bf
SD		 14052019-01-25 Sudakshina Das <sudi.das@arm.com>
1406 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1407
1408 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1409 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1410 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1411 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1412 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1413 case for ldstgv_indexed.
1414 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1415 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1416 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1417 * aarch64-asm-2.c: Regenerated.
1418 * aarch64-dis-2.c: Regenerated.
1419 * aarch64-opc-2.c: Regenerated.
1420
d9938630
NC		 14212019-01-23 Nick Clifton <nickc@redhat.com>
1422
1423 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1424
375cd423
NC		 14252019-01-21 Nick Clifton <nickc@redhat.com>
1426
1427 * po/de.po: Updated German translation.
1428 * po/uk.po: Updated Ukranian translation.
1429
57299f48
CX		 14302019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1431 * mips-dis.c (mips_arch_choices): Fix typo in
1432 gs464, gs464e and gs264e descriptors.
1433
f48dfe41
NC		 14342019-01-19 Nick Clifton <nickc@redhat.com>
1435
1436 * configure: Regenerate.
1437 * po/opcodes.pot: Regenerate.
1438
f974f26c
NC		 14392018-06-24 Nick Clifton <nickc@redhat.com>
1440
1441 2.32 branch created.
1442
39f286cd
JD		 14432019-01-09 John Darrington <john@darrington.wattle.id.au>
1444
448b8ca8
JD		 1445 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1446 if it is null.
1447 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1448 zero.
1449
3107326d
AP		 14502019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1451
1452 * configure: Regenerate.
1453
7e9ca91e
AM		 14542019-01-07 Alan Modra <amodra@gmail.com>
1455
1456 * configure: Regenerate.
1457 * po/POTFILES.in: Regenerate.
1458
ef1ad42b
JD		 14592019-01-03 John Darrington <john@darrington.wattle.id.au>
1460
1461 * s12z-opc.c: New file.
1462 * s12z-opc.h: New file.
1463 * s12z-dis.c: Removed all code not directly related to display
1464 of instructions. Used the interface provided by the new files
1465 instead.
1466 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1467 * Makefile.in: Regenerate.
ef1ad42b 1468 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1469 * configure: Regenerate.
ef1ad42b 1470
82704155
AM		 14712019-01-01 Alan Modra <amodra@gmail.com>
1472
1473 Update year range in copyright notice of all files.
1474
d5c04e1b 1475For older changes see ChangeLog-2018
3499769a 1476\f
d5c04e1b 1477Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1478
1479Copying and distribution of this file, with or without modification,
1480are permitted in any medium without royalty provided the copyright
1481notice and this notice are preserved.
1482
1483Local Variables:
1484mode: change-log
1485left-margin: 8
1486fill-column: 74
1487version-control: never
1488End:
GDB Binutils - Deliverables
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