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* Makefile.am: Bfin support.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
4b7f6baa
CM		 12005-09-30 Catherine Moore <clm@cm00re.com>
2
3 * Makefile.am: Bfin support.
4 * Makefile.in: Regenerated.
5 * aclocal.m4: Regenerated.
6 * bfin-dis.c: New file.
7 * configure.in: Bfin support.
8 * configure: Regenerated.
9 * disassemble.c (ARCH_bfin): Define.
10 (disassembler): Add case for bfd_arch_bfin.
11
1a114b12
JB		 122005-09-28 Jan Beulich <jbeulich@novell.com>
13
14 * i386-dis.c (stack_v_mode): Renamed from branch_v_mode.
15 (indirEv): Use it.
16 (stackEv): New.
17 (Ob64, Ov64): Rename to Ob, Ov. Delete unused original definitions.
18 (dis386): Document and use new 'V' meta character. Use it for
19 single-byte push/pop opcode forms. Use stackEv for mod-r/m push/pop
20 opcode forms. Correct typo in 'pop ss'. Replace Ob64/Ov64 by Ob/Ov.
21 (putop): 'q' suffix for 'T' and 'U' meta depends on DFLAG. Mark
22 data prefix as used whenever DFLAG was examined. Handle 'V'.
23 (intel_operand_size): Use stack_v_mode.
24 (OP_E): Use stack_v_mode, but handle only the special case of
25 64-bit mode without operand size override here; fall through to
26 v_mode case otherwise.
27 (OP_REG): Special case rAX_reg ... rDI_reg only when 64-bit mode
28 and no operand size override is present.
29 (OP_J): Use get32s for obtaining the displacement also when rex64
30 is present.
31
3eb17e6b
PB		 322005-09-08 Paul Brook <paul@codesourcery.com>
33
34 * arm-dis.c (arm_opcodes, thumb32_opcodes): Rename smi to smc.
35
61cc0267
CF		 362005-09-06 Chao-ying Fu <fu@mips.com>
37
38 * mips-opc.c (MT32): New define.
39 (mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the
40 bottom to avoid opcode collision with "mftr" and "mttr".
41 Add MT instructions.
42 * mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
43 (print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
44 formats.
45
b13dd07a
PB		 462005-09-02 Paul Brook <paul@codesourcery.com>
47
48 * arm-dis.c (coprocessor_opcodes): Add null terminator.
49
8f06b2d8
PB		 502005-09-02 Paul Brook <paul@codesourcery.com>
51
52 * arm-dis.c (coprocessor_opcodes): New.
53 (arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
54 (print_insn_coprocessor): New function.
55 (print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
56 format characters.
57 (print_insn_thumb32): Use print_insn_coprocessor.
58
a2dfd01f
PB		 592005-08-30 Paul Brook <paul@codesourcery.com>
60
61 * arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs.
62
3f31e633
JB		 632005-08-26 Jan Beulich <jbeulich@novell.com>
64
65 * i386-dis.c (intel_operand_size): New, broken out from OP_E for
66 re-use.
67 (OP_E): Call intel_operand_size, move call site out of mode
68 dependent code.
69 (OP_OFF): Call intel_operand_size if suffix_always. Remove
70 ATTRIBUTE_UNUSED from parameters.
71 (OP_OFF64): Likewise.
72 (OP_ESreg): Call intel_operand_size.
73 (OP_DSreg): Likewise.
74 (OP_DIR): Use colon rather than semicolon as separator of far
75 jump/call operands.
76
fd25c5a9
CF		 772005-08-25 Chao-ying Fu <fu@mips.com>
78
79 * mips-opc.c (WR_a, RD_a, MOD_a, DSP_VOLA, D32): New define.
80 (mips_builtin_opcodes): Add DSP instructions.
81 * mips-dis.c (mips_arch_choices): Enable INSN_DSP for mips32, mips32r2,
82 mips64, mips64r2.
83 (print_insn_args): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, :, ', @
84 operand formats.
85
dd8b7c22
DU		 862005-08-23 David Ung <davidu@mips.com>
87
88 * mips16-opc.c (mips16_opcodes): Add the MIPS16e jalrc/jrc
89 instructions to the table.
90
c17ae8a2
AM		 912005-08-18 Alan Modra <amodra@bigpond.net.au>
92
848cf006 93 * a29k-dis.c: Delete.
c17ae8a2
AM		 94 * Makefile.am: Remove a29k support.
95 * configure.in: Likewise.
96 * disassemble.c: Likewise.
97 * Makefile.in: Regenerate.
98 * configure: Regenerate.
99 * po/POTFILES.in: Regenerate.
100
36ae0db3
DJ		 1012005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
102
103 * ppc-dis.c (powerpc_dialect): Handle e300.
104 (print_ppc_disassembler_options): Likewise.
105 * ppc-opc.c (PPCE300): Define.
106 (powerpc_opcodes): Mark icbt as available for the e300.
107
63a3357b
DA		 1082005-08-13 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
109
110 * hppa-dis.c (print_insn_hppa): Don't print '%' before register names.
111 Use "rp" instead of "%r2" in "b,l" insns.
112
ad101263
MS		 1132005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
114
115 * s390-dis.c (print_insn_s390): Print unsigned operands with %u.
116 * s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109.
117 (main): Likewise.
118 * s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates
119 and 4 bit optional masks.
120 (INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD,
121 INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats.
122 (MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD,
123 MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise.
124 (s390_opformats): Likewise.
125 * s390-opc.txt: Add new instructions for cpu type z9-109.
126
f1fa1093
DA		 1272005-08-05 John David Anglin <dave.anglin@nrc-crnc.gc.ca>
128
129 * hppa-dis.c (print_insn_hppa): Prefix 21-bit values with "L%".
130
e9f89963
PB		 1312005-07-29 Paul Brook <paul@codesourcery.com>
132
133 * arm-dis.c: Fix disassebly of thumb2 writeback addressing modes.
134
92e90b6e
PB		 1352005-07-29 Paul Brook <paul@codesourcery.com>
136
137 * arm-dis.c (thumb32_opc): Fix addressing mode for tbh.
138 (print_insn_thumb32): Fix decoding of thumb2 'I' operands.
139
fd54057a
DD		 1402005-07-25 DJ Delorie <dj@redhat.com>
141
142 * m32c-asm.c Regenerate.
143 * m32c-dis.c Regenerate.
144
760c0f6a
DD		 1452005-07-20 DJ Delorie <dj@redhat.com>
146
147 * disassemble.c (disassemble_init_for_target): M32C ISAs are
148 enums, so convert them to bit masks, which attributes are.
149
85da3a56
NC		 1502005-07-18 Nick Clifton <nickc@redhat.com>
151
152 * configure.in: Restore alpha ordering to list of arches.
153 * configure: Regenerate.
154 * disassemble.c: Restore alpha ordering to list of arches.
155
1562005-07-18 Nick Clifton <nickc@redhat.com>
157
158 * m32c-asm.c: Regenerate.
159 * m32c-desc.c: Regenerate.
160 * m32c-desc.h: Regenerate.
161 * m32c-dis.c: Regenerate.
162 * m32c-ibld.h: Regenerate.
163 * m32c-opc.c: Regenerate.
164 * m32c-opc.h: Regenerate.
165
22cbf2e7
L		 1662005-07-18 H.J. Lu <hongjiu.lu@intel.com>
167
168 * i386-dis.c (PNI_Fixup): Update comment.
169 (VMX_Fixup): Properly handle the suffix check.
170
0aea0460
DA		 1712005-07-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
172
173 * hppa-dis.c (print_insn_hppa): Add space after 'w' in wide-mode
174 mfctl disassembly.
175
0f82ff91
AM		 1762005-07-16 Alan Modra <amodra@bigpond.net.au>
177
178 * Makefile.am: Run "make dep-am".
179 (stamp-m32c): Fix cpu dependencies.
180 * Makefile.in: Regenerate.
181 * ip2k-dis.c: Regenerate.
182
90700ea2
L		 1832007-07-15 H.J. Lu <hongjiu.lu@intel.com>
184
185 * i386-dis.c (OP_VMX): New. Handle Intel VMX Instructions.
186 (VMX_Fixup): New. Fix up Intel VMX Instructions.
187 (Em): New.
188 (Gm): New.
189 (VM): New.
190 (dis386_twobyte): Updated entries 0x78 and 0x79.
191 (twobyte_has_modrm): Likewise.
192 (grps): Use OP_VMX in the "sgdtIQ" entry. Updated GRP9.
193 (OP_G): Handle m_mode.
194
49f58d10
JB		 1952005-07-14 Jim Blandy <jimb@redhat.com>
196
197 Add support for the Renesas M32C and M16C.
198 * m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New.
199 * m32c-desc.h, m32c-opc.h: New.
200 * Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h.
201 (CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c,
202 m32c-opc.c.
203 (ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo,
204 m32c-ibld.lo, m32c-opc.lo.
205 (CLEANFILES): List stamp-m32c.
206 (M32C_DEPS): List stamp-m32c, if CGEN_MAINT.
207 (CGEN_CPUS): Add m32c.
208 (m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c)
209 (m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS.
210 (m32c_opc_h): New variable.
211 (stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo)
212 (m32c-opc.lo): New rules.
213 * Makefile.in: Regenerated.
214 * configure.in: Add case for bfd_m32c_arch.
215 * configure: Regenerated.
216 * disassemble.c (ARCH_m32c): New.
217 [ARCH_m32c]: #include "m32c-desc.h".
218 (disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c.
219 (disassemble_init_for_target) [ARCH_m32c]: Same.
220
221 * cgen-ops.h, cgen-types.h: New files.
222 * Makefile.am (HFILES): List them.
223 * Makefile.in: Regenerated.
224
0fd3a477
JW		 2252005-07-07 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
226
227 * arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c,
228 d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c,
229 ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c,
230 m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c,
231 ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c,
232 v850-dis.c: Fix format bugs.
233 * ia64-gen.c (fail, warn): Add format attribute.
234 * or32-opc.c (debug): Likewise.
235
22f8fcbd
NC		 2362005-07-07 Khem Raj <kraj@mvista.com>
237
238 * arm-dis.c (opcode32 arm_opcodes): Fix ARM VFP fadds instruction
239 disassembly pattern.
240
d125c27b
AM		 2412005-07-06 Alan Modra <amodra@bigpond.net.au>
242
243 * Makefile.am (stamp-m32r): Fix path to cpu files.
244 (stamp-m32r, stamp-iq2000): Likewise.
245 * Makefile.in: Regenerate.
246 * m32r-asm.c: Regenerate.
247 * po/POTFILES.in: Remove arm-opc.h. Add ms1-asm.c, ms1-desc.c,
248 ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h.
249
3ec2b351
NC		 2502005-07-05 Nick Clifton <nickc@redhat.com>
251
252 * iq2000-asm.c: Regenerate.
253 * ms1-asm.c: Regenerate.
254
30123838
JB		 2552005-07-05 Jan Beulich <jbeulich@novell.com>
256
257 * i386-dis.c (SVME_Fixup): New.
258 (grps): Use it for the lidt entry.
259 (PNI_Fixup): Call OP_M rather than OP_E.
260 (INVLPG_Fixup): Likewise.
261
b0eec63e
L		 2622005-07-04 H.J. Lu <hongjiu.lu@intel.com>
263
264 * tic30-dis.c (cnvt_tmsfloat_ieee): Use HUGE_VALF if defined.
265
47b0e7ad
NC		 2662005-07-01 Nick Clifton <nickc@redhat.com>
267
268 * a29k-dis.c: Update to ISO C90 style function declarations and
269 fix formatting.
270 * alpha-opc.c: Likewise.
271 * arc-dis.c: Likewise.
272 * arc-opc.c: Likewise.
273 * avr-dis.c: Likewise.
274 * cgen-asm.in: Likewise.
275 * cgen-dis.in: Likewise.
276 * cgen-ibld.in: Likewise.
277 * cgen-opc.c: Likewise.
278 * cris-dis.c: Likewise.
279 * d10v-dis.c: Likewise.
280 * d30v-dis.c: Likewise.
281 * d30v-opc.c: Likewise.
282 * dis-buf.c: Likewise.
283 * dlx-dis.c: Likewise.
284 * h8300-dis.c: Likewise.
285 * h8500-dis.c: Likewise.
286 * hppa-dis.c: Likewise.
287 * i370-dis.c: Likewise.
288 * i370-opc.c: Likewise.
289 * m10200-dis.c: Likewise.
290 * m10300-dis.c: Likewise.
291 * m68k-dis.c: Likewise.
292 * m88k-dis.c: Likewise.
293 * mips-dis.c: Likewise.
294 * mmix-dis.c: Likewise.
295 * msp430-dis.c: Likewise.
296 * ns32k-dis.c: Likewise.
297 * or32-dis.c: Likewise.
298 * or32-opc.c: Likewise.
299 * pdp11-dis.c: Likewise.
300 * pj-dis.c: Likewise.
301 * s390-dis.c: Likewise.
302 * sh-dis.c: Likewise.
303 * sh64-dis.c: Likewise.
304 * sparc-dis.c: Likewise.
305 * sparc-opc.c: Likewise.
306 * sysdep.h: Likewise.
307 * tic30-dis.c: Likewise.
308 * tic4x-dis.c: Likewise.
309 * tic80-dis.c: Likewise.
310 * v850-dis.c: Likewise.
311 * v850-opc.c: Likewise.
312 * vax-dis.c: Likewise.
313 * w65-dis.c: Likewise.
314 * z8kgen.c: Likewise.
315
316 * fr30-*: Regenerate.
317 * frv-*: Regenerate.
318 * ip2k-*: Regenerate.
319 * iq2000-*: Regenerate.
320 * m32r-*: Regenerate.
321 * ms1-*: Regenerate.
322 * openrisc-*: Regenerate.
323 * xstormy16-*: Regenerate.
324
cc16ba8c
BE		 3252005-06-23 Ben Elliston <bje@gnu.org>
326
327 * m68k-dis.c: Use ISC C90.
328 * m68k-opc.c: Formatting fixes.
329
4b185e97
DU		 3302005-06-16 David Ung <davidu@mips.com>
331
332 * mips16-opc.c (mips16_opcodes): Add the following MIPS16e
333 instructions to the table; seb/seh/sew/zeb/zeh/zew.
334
ac188222
DB		 3352005-06-15 Dave Brolley <brolley@redhat.com>
336
337 Contribute Morpho ms1 on behalf of Red Hat
338 * ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c,
339 ms1-opc.h: New files, Morpho ms1 target.
340
341 2004-05-14 Stan Cox <scox@redhat.com>
342
343 * disassemble.c (ARCH_ms1): Define.
344 (disassembler): Handle bfd_arch_ms1
345
346 2004-05-13 Michael Snyder <msnyder@redhat.com>
347
348 * Makefile.am, Makefile.in: Add ms1 target.
349 * configure.in: Ditto.
350
6b5d3a4d
ZW		 3512005-06-08 Zack Weinberg <zack@codesourcery.com>
352
353 * arm-opc.h: Delete; fold contents into ...
354 * arm-dis.c: ... here. Move includes of internal COFF headers
355 next to includes of internal ELF headers.
356 (streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
357 (struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
358 (struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
359 (arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
360 (iwmmxt_wwnames, iwmmxt_wwssnames):
361 Make const.
362 (regnames): Remove iWMMXt coprocessor register sets.
363 (iwmmxt_regnames, iwmmxt_cregnames): New statics.
364 (get_arm_regnames): Adjust fourth argument to match above changes.
365 (set_iwmmxt_regnames): Delete.
366 (print_insn_arm): Constify 'c'. Use ISO syntax for function
367 pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
368 and iwmmxt_cregnames, not set_iwmmxt_regnames.
369 (print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
370 ISO syntax for function pointer calls.
371
4a5329c6
ZW		 3722005-06-07 Zack Weinberg <zack@codesourcery.com>
373
374 * arm-dis.c: Split up the comments describing the format codes, so
375 that the ARM and 16-bit Thumb opcode tables each have comments
376 preceding them that describe all the codes, and only the codes,
377 valid in those tables. (32-bit Thumb table is already like this.)
378 Reorder the lists in all three comments to match the order in
379 which the codes are implemented.
380 Remove all forward declarations of static functions. Convert all
381 function definitions to ISO C format.
382 (print_insn_arm, print_insn_thumb16, print_insn_thumb32):
383 Return nothing.
384 (print_insn_thumb16): Remove unused case 'I'.
385 (print_insn): Update for changed calling convention of subroutines.
386
3d456fa1
JB		 3872005-05-25 Jan Beulich <jbeulich@novell.com>
388
389 * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
390 hex (but retain it being displayed as signed). Remove redundant
391 checks. Add handling of displacements for 16-bit addressing in Intel
392 mode.
393
2888cb7a
JB		 3942005-05-25 Jan Beulich <jbeulich@novell.com>
395
396 * i386-dis.c (prefix_name): Remove pointless mode_64bit check.
397 (OP_E): Remove redundant REX_EXTZ handling. Remove pointless
398 masking of 'rm' in 16-bit memory address handling.
399
1ed8e1e4
AM		 4002005-05-19 Anton Blanchard <anton@samba.org>
401
402 * ppc-dis.c (powerpc_dialect): Handle "-Mpower5".
403 (print_ppc_disassembler_options): Document it.
404 * ppc-opc.c (SVC_LEV): Define.
405 (LEV): Allow optional operand.
406 (POWER5): Define.
407 (powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
408 "hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
409
49cc2e69
KC		 4102005-05-19 Kelley Cook <kcook@gcc.gnu.org>
411
412 * Makefile.in: Regenerate.
413
c19d1205
ZW		 4142005-05-17 Zack Weinberg <zack@codesourcery.com>
415
416 * arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
417 instructions. Adjust disassembly of some opcodes to match
418 unified syntax.
419 (thumb32_opcodes): New table.
420 (print_insn_thumb): Rename print_insn_thumb16; don't handle
421 two-halfword branches here.
422 (print_insn_thumb32): New function.
423 (print_insn): Choose among print_insn_arm, print_insn_thumb16,
424 and print_insn_thumb32. Be consistent about order of
425 halfwords when printing 32-bit instructions.
426
003519a7
L		 4272005-05-07 H.J. Lu <hongjiu.lu@intel.com>
428
429 PR 843
430 * i386-dis.c (branch_v_mode): New.
431 (indirEv): Use branch_v_mode instead of v_mode.
432 (OP_E): Handle branch_v_mode.
433
920a34a7
L		 4342005-05-07 H.J. Lu <hongjiu.lu@intel.com>
435
436 * d10v-dis.c (dis_2_short): Support 64bit host.
437
5de773c1
NC		 4382005-05-07 Nick Clifton <nickc@redhat.com>
439
440 * po/nl.po: Updated translation.
441
f4321104
NC		 4422005-05-07 Nick Clifton <nickc@redhat.com>
443
444 * Update the address and phone number of the FSF organization in
445 the GPL notices in the following files:
446 a29k-dis.c, aclocal.m4, alpha-dis.c, alpha-opc.c, arc-dis.c,
447 arc-dis.h, arc-ext.c, arc-ext.h, arc-opc.c, arm-dis.c, arm-opc.h,
448 avr-dis.c, cgen-asm.c, cgen-asm.in, cgen-dis.c, cgen-dis.in,
449 cgen-ibld.in, cgen-opc.c, cgen.sh, cris-dis.c, cris-opc.c,
450 crx-dis.c, crx-opc.c, d10v-dis.c, d10v-opc.c, d30v-dis.c,
451 d30v-opc.c, dis-buf.c, dis-init.c, disassemble.c, dlx-dis.c,
452 fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c,
453 fr30-opc.c, fr30-opc.h, frv-asm.c, frv-desc.c, frv-desc.h,
454 frv-dis.c, frv-ibld.c, frv-opc.c, frv-opc.h, h8300-dis.c,
455 h8500-dis.c, h8500-opc.h, hppa-dis.c, i370-dis.c, i370-opc.c,
456 i386-dis.c, i860-dis.c, i960-dis.c, ia64-asmtab.h, ia64-dis.c,
457 ia64-gen.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c,
458 ia64-opc-f.c, ia64-opc-i.c, ia64-opc-m.c, ia64-opc-x.c,
459 ia64-opc.c, ia64-opc.h, ip2k-asm.c, ip2k-desc.c, ip2k-desc.h,
460 ip2k-dis.c, ip2k-ibld.c, ip2k-opc.c, ip2k-opc.h, iq2000-asm.c,
461 iq2000-desc.c, iq2000-desc.h, iq2000-dis.c, iq2000-ibld.c,
462 iq2000-opc.c, iq2000-opc.h, m10200-dis.c, m10200-opc.c,
463 m10300-dis.c, m10300-opc.c, m32r-asm.c, m32r-desc.c, m32r-desc.h,
464 m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c,
465 m68hc11-dis.c, m68hc11-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c,
466 maxq-dis.c, mcore-dis.c, mcore-opc.h, mips-dis.c, mips-opc.c,
467 mips16-opc.c, mmix-dis.c, mmix-opc.c, msp430-dis.c, ns32k-dis.c,
468 openrisc-asm.c, openrisc-desc.c, openrisc-desc.h, openrisc-dis.c,
469 openrisc-ibld.c, openrisc-opc.c, openrisc-opc.h, opintl.h,
470 or32-dis.c, or32-opc.c, pdp11-dis.c, pdp11-opc.c, pj-dis.c,
471 pj-opc.c, ppc-dis.c, ppc-opc.c, s390-dis.c, s390-mkopc.c,
472 s390-opc.c, sh-dis.c, sh-opc.h, sh64-dis.c, sh64-opc.c,
473 sh64-opc.h, sparc-dis.c, sparc-opc.c, sysdep.h, tic30-dis.c,
474 tic4x-dis.c, tic54x-dis.c, tic54x-opc.c, tic80-dis.c, tic80-opc.c,
475 v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, w65-opc.h,
476 xstormy16-asm.c, xstormy16-desc.c, xstormy16-desc.h,
477 xstormy16-dis.c, xstormy16-ibld.c, xstormy16-opc.c,
478 xstormy16-opc.h, xtensa-dis.c, z8k-dis.c, z8kgen.c
479
10b076a2
JW		 4802005-05-05 James E Wilson <wilson@specifixinc.com>
481
482 * ia64-opc.c: Include sysdep.h before libiberty.h.
483
022716b6
NC		 4842005-05-05 Nick Clifton <nickc@redhat.com>
485
486 * configure.in (ALL_LINGUAS): Add vi.
487 * configure: Regenerate.
488 * po/vi.po: New.
489
db5152b4
JG		 4902005-04-26 Jerome Guitton <guitton@gnat.com>
491
492 * configure.in: Fix the check for basename declaration.
493 * configure: Regenerate.
494
eed0d89a
AM		 4952005-04-19 Alan Modra <amodra@bigpond.net.au>
496
497 * ppc-opc.c (RTO): Define.
498 (powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
499 entries to suit PPC440.
500
791fe849
MK		 5012005-04-18 Mark Kettenis <kettenis@gnu.org>
502
503 * i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
504 Add xcrypt-ctr.
505
ffe58f7c
NC		 5062005-04-14 Nick Clifton <nickc@redhat.com>
507
508 * po/fi.po: New translation: Finnish.
509 * configure.in (ALL_LINGUAS): Add fi.
510 * configure: Regenerate.
511
9e9b66a9
AM		 5122005-04-14 Alan Modra <amodra@bigpond.net.au>
513
514 * Makefile.am (NO_WERROR): Define.
515 * configure.in: Invoke AM_BINUTILS_WARNINGS.
516 * Makefile.in: Regenerate.
517 * aclocal.m4: Regenerate.
518 * configure: Regenerate.
519
9494d739
NC		 5202005-04-04 Nick Clifton <nickc@redhat.com>
521
522 * fr30-asm.c: Regenerate.
523 * frv-asm.c: Regenerate.
524 * iq2000-asm.c: Regenerate.
525 * m32r-asm.c: Regenerate.
526 * openrisc-asm.c: Regenerate.
527
6128c599
JB		 5282005-04-01 Jan Beulich <jbeulich@novell.com>
529
530 * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
531 visible operands in Intel mode. The first operand of monitor is
532 %rax in 64-bit mode.
533
373ff435
JB		 5342005-04-01 Jan Beulich <jbeulich@novell.com>
535
536 * i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
537 easier future additions.
538
4bd60896
JG		 5392005-03-31 Jerome Guitton <guitton@gnat.com>
540
541 * configure.in: Check for basename.
542 * configure: Regenerate.
543 * config.in: Ditto.
544
4cc91dba
L		 5452005-03-29 H.J. Lu <hongjiu.lu@intel.com>
546
547 * i386-dis.c (SEG_Fixup): New.
548 (Sv): New.
549 (dis386): Use "Sv" for 0x8c and 0x8e.
550
ec72cfe5
NC		 5512005-03-21 Jan-Benedict Glaw <jbglaw@lug-owl.de>
552 Nick Clifton <nickc@redhat.com>
c19d1205 553
ec72cfe5
NC		 554 * vax-dis.c: (entry_addr): New varible: An array of user supplied
555 function entry mask addresses.
556 (entry_addr_occupied_slots): New variable: The number of occupied
c19d1205 557 elements in entry_addr.
ec72cfe5
NC		 558 (entry_addr_total_slots): New variable: The total number of
559 elements in entry_addr.
560 (parse_disassembler_options): New function. Fills in the entry_addr
561 array.
562 (free_entry_array): New function. Release the memory used by the
563 entry addr array. Suppressed because there is no way to call it.
564 (is_function_entry): Check if a given address is a function's
565 start address by looking at supplied entry mask addresses and
566 symbol information, if available.
567 (print_insn_vax): Use parse_disassembler_options and is_function_entry.
568
85064c79
L		 5692005-03-23 H.J. Lu <hongjiu.lu@intel.com>
570
571 * cris-dis.c (print_with_operands): Use ~31L for long instead
572 of ~31.
573
de7141c7
L		 5742005-03-20 H.J. Lu <hongjiu.lu@intel.com>
575
576 * mmix-opc.c (O): Revert the last change.
577 (Z): Likewise.
578
e493ab45
L		 5792005-03-19 H.J. Lu <hongjiu.lu@intel.com>
580
581 * mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
582 (Z): Likewise.
583
d8d7c459
HPN		 5842005-03-19 Hans-Peter Nilsson <hp@bitrange.com>
585
586 * mmix-opc.c (O, Z): Force expression as unsigned long.
587
ebdb0383
NC		 5882005-03-18 Nick Clifton <nickc@redhat.com>
589
590 * ip2k-asm.c: Regenerate.
591 * op/opcodes.pot: Regenerate.
592
1ad12f97
NC		 5932005-03-16 Nick Clifton <nickc@redhat.com>
594 Ben Elliston <bje@au.ibm.com>
595
569acd2c 596 * configure.in (werror): New switch: Add -Werror to the
1ad12f97 597 compiler command line. Enabled by default. Disable via
569acd2c 598 --disable-werror.
1ad12f97
NC		 599 * configure: Regenerate.
600
4eb30afc
AM		 6012005-03-16 Alan Modra <amodra@bigpond.net.au>
602
603 * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when
604 BOOKE.
605
ea8409f7
AM		 6062005-03-15 Alan Modra <amodra@bigpond.net.au>
607
729ae8d2
AM		 608 * po/es.po: Commit new Spanish translation.
609
ea8409f7
AM		 610 * po/fr.po: Commit new French translation.
611
4f495e61
NC		 6122005-03-14 Jan-Benedict Glaw <jbglaw@lug-owl.de>
613
614 * vax-dis.c: Fix spelling error
615 (print_insn_vax): Use ".word 0x0012 # Entry mask: r1 r2 >" instead
616 of just "Entry mask: < r1 ... >"
617
0a003adc
ZW		 6182005-03-12 Zack Weinberg <zack@codesourcery.com>
619
620 * arm-dis.c (arm_opcodes): Document %E and %V.
621 Add entries for v6T2 ARM instructions:
622 bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
623 (print_insn_arm): Add support for %E and %V.
885fc257 624 (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield.
0a003adc 625
da99ee72
AM		 6262005-03-10 Jeff Baker <jbaker@qnx.com>
627 Alan Modra <amodra@bigpond.net.au>
628
629 * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
630 (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
631 (SPRG_MASK): Delete.
632 (XSPRG_MASK): Mask off extra bits now part of sprg field.
0a003adc 633 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
da99ee72
AM		 634 mfsprg4..7 after msprg and consolidate.
635
220abb21
AM		 6362005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
637
638 * vax-dis.c (entry_mask_bit): New array.
639 (print_insn_vax): Decode function entry mask.
640
0e06657a
AH		 6412005-03-07 Aldy Hernandez <aldyh@redhat.com>
642
643 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
644
06647dfd
AM		 6452005-03-05 Alan Modra <amodra@bigpond.net.au>
646
647 * po/opcodes.pot: Regenerate.
648
82b829a7
RR		 6492005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
650
220abb21 651 * arc-dis.c (a4_decoding_class): New enum.
06647dfd
AM		 652 (dsmOneArcInst): Use the enum values for the decoding class.
653 Remove redundant case in the switch for decodingClass value 11.
82b829a7 654
c4a530c5
JB		 6552005-03-02 Jan Beulich <jbeulich@novell.com>
656
657 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
658 accesses.
659 (OP_C): Consider lock prefix in non-64-bit modes.
660
47d8304e
AM		 6612005-02-24 Alan Modra <amodra@bigpond.net.au>
662
663 * cris-dis.c (format_hex): Remove ineffective warning fix.
664 * crx-dis.c (make_instruction): Warning fix.
665 * frv-asm.c: Regenerate.
666
ec36c4a4
NC		 6672005-02-23 Nick Clifton <nickc@redhat.com>
668
33b71eeb
NC		 669 * cgen-dis.in: Use bfd_byte for buffers that are passed to
670 read_memory.
06647dfd 671
33b71eeb 672 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
06647dfd 673
ec36c4a4
NC		 674 * crx-dis.c (make_instruction): Move argument structure into inner
675 scope and ensure that all of its fields are initialised before
676 they are used.
677
33b71eeb
NC		 678 * fr30-asm.c: Regenerate.
679 * fr30-dis.c: Regenerate.
680 * frv-asm.c: Regenerate.
681 * frv-dis.c: Regenerate.
682 * ip2k-asm.c: Regenerate.
683 * ip2k-dis.c: Regenerate.
684 * iq2000-asm.c: Regenerate.
685 * iq2000-dis.c: Regenerate.
686 * m32r-asm.c: Regenerate.
687 * m32r-dis.c: Regenerate.
688 * openrisc-asm.c: Regenerate.
689 * openrisc-dis.c: Regenerate.
690 * xstormy16-asm.c: Regenerate.
691 * xstormy16-dis.c: Regenerate.
692
53c9ebc5
AM		 6932005-02-22 Alan Modra <amodra@bigpond.net.au>
694
695 * arc-ext.c: Warning fixes.
696 * arc-ext.h: Likewise.
697 * cgen-opc.c: Likewise.
698 * ia64-gen.c: Likewise.
699 * maxq-dis.c: Likewise.
700 * ns32k-dis.c: Likewise.
701 * w65-dis.c: Likewise.
702 * ia64-asmtab.c: Regenerate.
703
610ad19b
AM		 7042005-02-22 Alan Modra <amodra@bigpond.net.au>
705
706 * fr30-desc.c: Regenerate.
707 * fr30-desc.h: Regenerate.
708 * fr30-opc.c: Regenerate.
709 * fr30-opc.h: Regenerate.
710 * frv-desc.c: Regenerate.
711 * frv-desc.h: Regenerate.
712 * frv-opc.c: Regenerate.
713 * frv-opc.h: Regenerate.
714 * ip2k-desc.c: Regenerate.
715 * ip2k-desc.h: Regenerate.
716 * ip2k-opc.c: Regenerate.
717 * ip2k-opc.h: Regenerate.
718 * iq2000-desc.c: Regenerate.
719 * iq2000-desc.h: Regenerate.
720 * iq2000-opc.c: Regenerate.
721 * iq2000-opc.h: Regenerate.
722 * m32r-desc.c: Regenerate.
723 * m32r-desc.h: Regenerate.
724 * m32r-opc.c: Regenerate.
725 * m32r-opc.h: Regenerate.
726 * m32r-opinst.c: Regenerate.
727 * openrisc-desc.c: Regenerate.
728 * openrisc-desc.h: Regenerate.
729 * openrisc-opc.c: Regenerate.
730 * openrisc-opc.h: Regenerate.
731 * xstormy16-desc.c: Regenerate.
732 * xstormy16-desc.h: Regenerate.
733 * xstormy16-opc.c: Regenerate.
734 * xstormy16-opc.h: Regenerate.
735
db9db6f2
AM		 7362005-02-21 Alan Modra <amodra@bigpond.net.au>
737
738 * Makefile.am: Run "make dep-am"
739 * Makefile.in: Regenerate.
740
bf143b25
NC		 7412005-02-15 Nick Clifton <nickc@redhat.com>
742
743 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
744 compile time warnings.
745 (print_keyword): Likewise.
746 (default_print_insn): Likewise.
747
748 * fr30-desc.c: Regenerated.
749 * fr30-desc.h: Regenerated.
750 * fr30-dis.c: Regenerated.
751 * fr30-opc.c: Regenerated.
752 * fr30-opc.h: Regenerated.
753 * frv-desc.c: Regenerated.
754 * frv-dis.c: Regenerated.
755 * frv-opc.c: Regenerated.
756 * ip2k-asm.c: Regenerated.
757 * ip2k-desc.c: Regenerated.
758 * ip2k-desc.h: Regenerated.
759 * ip2k-dis.c: Regenerated.
760 * ip2k-opc.c: Regenerated.
761 * ip2k-opc.h: Regenerated.
762 * iq2000-desc.c: Regenerated.
763 * iq2000-dis.c: Regenerated.
764 * iq2000-opc.c: Regenerated.
765 * m32r-asm.c: Regenerated.
766 * m32r-desc.c: Regenerated.
767 * m32r-desc.h: Regenerated.
768 * m32r-dis.c: Regenerated.
769 * m32r-opc.c: Regenerated.
770 * m32r-opc.h: Regenerated.
771 * m32r-opinst.c: Regenerated.
772 * openrisc-desc.c: Regenerated.
773 * openrisc-desc.h: Regenerated.
774 * openrisc-dis.c: Regenerated.
775 * openrisc-opc.c: Regenerated.
776 * openrisc-opc.h: Regenerated.
777 * xstormy16-desc.c: Regenerated.
778 * xstormy16-desc.h: Regenerated.
779 * xstormy16-dis.c: Regenerated.
780 * xstormy16-opc.c: Regenerated.
781 * xstormy16-opc.h: Regenerated.
782
d6098898
L		 7832005-02-14 H.J. Lu <hongjiu.lu@intel.com>
784
785 * dis-buf.c (perror_memory): Use sprintf_vma to print out
786 address.
787
5a84f3e0
NC		 7882005-02-11 Nick Clifton <nickc@redhat.com>
789
bc18c937
NC		 790 * iq2000-asm.c: Regenerate.
791
5a84f3e0
NC		 792 * frv-dis.c: Regenerate.
793
0a40490e
JB		 7942005-02-07 Jim Blandy <jimb@redhat.com>
795
796 * Makefile.am (CGEN): Load guile.scm before calling the main
797 application script.
798 * Makefile.in: Regenerated.
799 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
800 Simply pass the cgen-opc.scm path to ${cgen} as its first
801 argument; ${cgen} itself now contains the '-s', or whatever is
802 appropriate for the Scheme being used.
803
c46f8c51
AC		 8042005-01-31 Andrew Cagney <cagney@gnu.org>
805
806 * configure: Regenerate to track ../gettext.m4.
807
60b9a617
JB		 8082005-01-31 Jan Beulich <jbeulich@novell.com>
809
810 * ia64-gen.c (NELEMS): Define.
811 (shrink): Generate alias with missing second predicate register when
812 opcode has two outputs and these are both predicates.
813 * ia64-opc-i.c (FULL17): Define.
814 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
815 here to generate output template.
816 (TBITCM, TNATCM): Undefine after use.
817 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
818 first input. Add ld16 aliases without ar.csd as second output. Add
819 st16 aliases without ar.csd as second input. Add cmpxchg aliases
820 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
821 ar.ccv as third/fourth inputs. Consolidate through...
822 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
823 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
824 * ia64-asmtab.c: Regenerate.
825
a53bf506
AC		 8262005-01-27 Andrew Cagney <cagney@gnu.org>
827
828 * configure: Regenerate to track ../gettext.m4 change.
829
90219bd0
AO		 8302005-01-25 Alexandre Oliva <aoliva@redhat.com>
831
832 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
833 * frv-asm.c: Rebuilt.
834 * frv-desc.c: Rebuilt.
835 * frv-desc.h: Rebuilt.
836 * frv-dis.c: Rebuilt.
837 * frv-ibld.c: Rebuilt.
838 * frv-opc.c: Rebuilt.
839 * frv-opc.h: Rebuilt.
840
45181ed1
AC		 8412005-01-24 Andrew Cagney <cagney@gnu.org>
842
843 * configure: Regenerate, ../gettext.m4 was updated.
844
9e836e3d
FF		 8452005-01-21 Fred Fish <fnf@specifixinc.com>
846
847 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
848 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
849 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
850 * mips-dis.c: Ditto.
851
5e8cb021
AM		 8522005-01-20 Alan Modra <amodra@bigpond.net.au>
853
854 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
855
986e18a5
FF		 8562005-01-19 Fred Fish <fnf@specifixinc.com>
857
858 * mips-dis.c (no_aliases): New disassembly option flag.
859 (set_default_mips_dis_options): Init no_aliases to zero.
860 (parse_mips_dis_option): Handle no-aliases option.
861 (print_insn_mips): Ignore table entries that are aliases
862 if no_aliases is set.
863 (print_insn_mips16): Ditto.
864 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
865 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
866 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
867 * mips16-opc.c (mips16_opcodes): Ditto.
868
e38bc3b5
NC		 8692005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
870
871 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
872 (inheritance diagram): Add missing edge.
873 (arch_sh1_up): Rename arch_sh_up to match external name to make life
874 easier for the testsuite.
875 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
876 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 877 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 878 arch_sh2a_or_sh4_up child.
879 (sh_table): Do renaming as above.
880 Correct comment for ldc.l for gas testsuite to read.
881 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
882 Correct comments for movy.w and movy.l for gas testsuite to read.
883 Correct comments for fmov.d and fmov.s for gas testsuite to read.
884
9df48ba9
L		 8852005-01-12 H.J. Lu <hongjiu.lu@intel.com>
886
887 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
888
2033b4b9
L		 8892005-01-12 H.J. Lu <hongjiu.lu@intel.com>
890
891 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
892
0bcb06d2
AS		 8932005-01-10 Andreas Schwab <schwab@suse.de>
894
895 * disassemble.c (disassemble_init_for_target) <case
896 bfd_arch_ia64>: Set skip_zeroes to 16.
897 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
898
47add74d
TL		 8992004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
900
901 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
902
246f4c05
SS		 9032004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
904
905 * avr-dis.c: Prettyprint. Added printing of symbol names in all
906 memory references. Convert avr_operand() to C90 formatting.
907
0e1200e5
TL		 9082004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
909
910 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
911
89a649f7
TL		 9122004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
913
914 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
915 (no_op_insn): Initialize array with instructions that have no
916 operands.
917 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
918
6255809c
RE		 9192004-11-29 Richard Earnshaw <rearnsha@arm.com>
920
921 * arm-dis.c: Correct top-level comment.
922
2fbad815
RE		 9232004-11-27 Richard Earnshaw <rearnsha@arm.com>
924
925 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
926 architecuture defining the insn.
927 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 928 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
929 field.
2fbad815
RE		 930 Also include opcode/arm.h.
931 * Makefile.am (arm-dis.lo): Update dependency list.
932 * Makefile.in: Regenerate.
933
d81acc42
NC		 9342004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
935
936 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
937 reflect the change to the short immediate syntax.
938
ca4f2377
AM		 9392004-11-19 Alan Modra <amodra@bigpond.net.au>
940
5da8bf1b
AM		 941 * or32-opc.c (debug): Warning fix.
942 * po/POTFILES.in: Regenerate.
943
ca4f2377
AM		 944 * maxq-dis.c: Formatting.
945 (print_insn): Warning fix.
946
b7693d02
DJ		 9472004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
948
949 * arm-dis.c (WORD_ADDRESS): Define.
950 (print_insn): Use it. Correct big-endian end-of-section handling.
951
300dac7e
NC		 9522004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
953 Vineet Sharma <vineets@noida.hcltech.com>
954
955 * maxq-dis.c: New file.
956 * disassemble.c (ARCH_maxq): Define.
610ad19b 957 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 958 instructions..
959 * configure.in: Add case for bfd_maxq_arch.
960 * configure: Regenerate.
961 * Makefile.am: Add support for maxq-dis.c
962 * Makefile.in: Regenerate.
963 * aclocal.m4: Regenerate.
964
42048ee7
TL		 9652004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
966
967 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
968 mode.
969 * crx-dis.c: Likewise.
970
bd21e58e
HPN		 9712004-11-04 Hans-Peter Nilsson <hp@axis.com>
972
973 Generally, handle CRISv32.
974 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
975 (struct cris_disasm_data): New type.
976 (format_reg, format_hex, cris_constraint, print_flags)
977 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
978 callers changed.
979 (format_sup_reg, print_insn_crisv32_with_register_prefix)
980 (print_insn_crisv32_without_register_prefix)
981 (print_insn_crisv10_v32_with_register_prefix)
982 (print_insn_crisv10_v32_without_register_prefix)
983 (cris_parse_disassembler_options): New functions.
984 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
985 parameter. All callers changed.
986 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
987 failure.
988 (cris_constraint) <case 'Y', 'U'>: New cases.
989 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
990 for constraint 'n'.
991 (print_with_operands) <case 'Y'>: New case.
992 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
993 <case 'N', 'Y', 'Q'>: New cases.
994 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
995 (print_insn_cris_with_register_prefix)
996 (print_insn_cris_without_register_prefix): Call
997 cris_parse_disassembler_options.
998 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
999 for CRISv32 and the size of immediate operands. New v32-only
1000 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
1001 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
1002 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
1003 Change brp to be v3..v10.
1004 (cris_support_regs): New vector.
1005 (cris_opcodes): Update head comment. New format characters '[',
1006 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
1007 Add new opcodes for v32 and adjust existing opcodes to accommodate
1008 differences to earlier variants.
1009 (cris_cond15s): New vector.
1010
9306ca4a
JB		 10112004-11-04 Jan Beulich <jbeulich@novell.com>
1012
1013 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
1014 (indirEb): Remove.
1015 (Mp): Use f_mode rather than none at all.
1016 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
1017 replaces what previously was x_mode; x_mode now means 128-bit SSE
1018 operands.
1019 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
1020 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
1021 pinsrw's second operand is Edqw.
1022 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
1023 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
1024 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
1025 mode when an operand size override is present or always suffixing.
1026 More instructions will need to be added to this group.
1027 (putop): Handle new macro chars 'C' (short/long suffix selector),
1028 'I' (Intel mode override for following macro char), and 'J' (for
1029 adding the 'l' prefix to far branches in AT&T mode). When an
1030 alternative was specified in the template, honor macro character when
1031 specified for Intel mode.
1032 (OP_E): Handle new *_mode values. Correct pointer specifications for
1033 memory operands. Consolidate output of index register.
1034 (OP_G): Handle new *_mode values.
1035 (OP_I): Handle const_1_mode.
1036 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
1037 respective opcode prefix bits have been consumed.
1038 (OP_EM, OP_EX): Provide some default handling for generating pointer
1039 specifications.
1040
f39c96a9
TL		 10412004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
1042
1043 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
1044 COP_INST macro.
1045
812337be
TL		 10462004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1047
1048 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
1049 (getregliststring): Support HI/LO and user registers.
610ad19b 1050 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 1051 rearrangement done in CRX opcode header file.
1052 (crx_regtab): Likewise.
1053 (crx_optab): Likewise.
610ad19b 1054 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 1055 formats.
1056 support new Co-Processor instruction 'cpi'.
1057
4030fa5a
NC		 10582004-10-27 Nick Clifton <nickc@redhat.com>
1059
1060 * opcodes/iq2000-asm.c: Regenerate.
1061 * opcodes/iq2000-desc.c: Regenerate.
1062 * opcodes/iq2000-desc.h: Regenerate.
1063 * opcodes/iq2000-dis.c: Regenerate.
1064 * opcodes/iq2000-ibld.c: Regenerate.
1065 * opcodes/iq2000-opc.c: Regenerate.
1066 * opcodes/iq2000-opc.h: Regenerate.
1067
fc3d45e8
TL		 10682004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1069
1070 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
1071 us4, us5 (respectively).
1072 Remove unsupported 'popa' instruction.
1073 Reverse operands order in store co-processor instructions.
1074
3c55da70
AM		 10752004-10-15 Alan Modra <amodra@bigpond.net.au>
1076
1077 * Makefile.am: Run "make dep-am"
1078 * Makefile.in: Regenerate.
1079
7fa3d080
BW		 10802004-10-12 Bob Wilson <bob.wilson@acm.org>
1081
1082 * xtensa-dis.c: Use ISO C90 formatting.
1083
e612bb4d
AM		 10842004-10-09 Alan Modra <amodra@bigpond.net.au>
1085
1086 * ppc-opc.c: Revert 2004-09-09 change.
1087
43cd72b9
BW		 10882004-10-07 Bob Wilson <bob.wilson@acm.org>
1089
1090 * xtensa-dis.c (state_names): Delete.
1091 (fetch_data): Use xtensa_isa_maxlength.
1092 (print_xtensa_operand): Replace operand parameter with opcode/operand
1093 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
1094 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
1095 instruction bundles. Use xmalloc instead of malloc.
1096
bbac1f2a
NC		 10972004-10-07 David Gibson <david@gibson.dropbear.id.au>
1098
1099 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
1100 initializers.
1101
48c9f030
NC		 11022004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1103
1104 * crx-opc.c (crx_instruction): Support Co-processor insns.
1105 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
1106 (getregliststring): Change function to use the above enum.
1107 (print_arg): Handle CO-Processor insns.
1108 (crx_cinvs): Add 'b' option to invalidate the branch-target
1109 cache.
1110
12c64a4e
AH		 11112004-10-06 Aldy Hernandez <aldyh@redhat.com>
1112
1113 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
1114 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
1115 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
1116 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
1117 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
1118
14127cc4
NC		 11192004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
1120
1121 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
1122 rather than add it.
1123
0dd132b6
NC		 11242004-09-30 Paul Brook <paul@codesourcery.com>
1125
1126 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
1127 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
1128
3f85e526
L		 11292004-09-17 H.J. Lu <hongjiu.lu@intel.com>
1130
1131 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
1132 (CONFIG_STATUS_DEPENDENCIES): New.
1133 (Makefile): Removed.
1134 (config.status): Likewise.
1135 * Makefile.in: Regenerated.
1136
8ae85421
AM		 11372004-09-17 Alan Modra <amodra@bigpond.net.au>
1138
1139 * Makefile.am: Run "make dep-am".
1140 * Makefile.in: Regenerate.
1141 * aclocal.m4: Regenerate.
1142 * configure: Regenerate.
1143 * po/POTFILES.in: Regenerate.
1144 * po/opcodes.pot: Regenerate.
1145
24443139
AS		 11462004-09-11 Andreas Schwab <schwab@suse.de>
1147
1148 * configure: Rebuild.
1149
2a309db0
AM		 11502004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1151
1152 * ppc-opc.c (L): Make this field not optional.
1153
42851540
NC		 11542004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
1155
1156 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
1157 Fix parameter to 'm[t|f]csr' insns.
1158
979273e3
NN		 11592004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
1160
1161 * configure.in: Autoupdate to autoconf 2.59.
1162 * aclocal.m4: Rebuild with aclocal 1.4p6.
1163 * configure: Rebuild with autoconf 2.59.
1164 * Makefile.in: Rebuild with automake 1.4p6 (picking up
1165 bfd changes for autoconf 2.59 on the way).
1166 * config.in: Rebuild with autoheader 2.59.
1167
ac28a1cb
RS		 11682004-08-27 Richard Sandiford <rsandifo@redhat.com>
1169
1170 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
1171
30d1c836
ML		 11722004-07-30 Michal Ludvig <mludvig@suse.cz>
1173
1174 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
1175 (GRPPADLCK2): New define.
1176 (twobyte_has_modrm): True for 0xA6.
1177 (grps): GRPPADLCK2 for opcode 0xA6.
1178
0b0ac059
AO		 11792004-07-29 Alexandre Oliva <aoliva@redhat.com>
1180
1181 Introduce SH2a support.
1182 * sh-opc.h (arch_sh2a_base): Renumber.
1183 (arch_sh2a_nofpu_base): Remove.
1184 (arch_sh_base_mask): Adjust.
1185 (arch_opann_mask): New.
1186 (arch_sh2a, arch_sh2a_nofpu): Adjust.
1187 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
1188 (sh_table): Adjust whitespace.
1189 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
1190 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
1191 instruction list throughout.
1192 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
1193 of arch_sh2a in instruction list throughout.
1194 (arch_sh2e_up): Accomodate above changes.
1195 (arch_sh2_up): Ditto.
1196 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
1197 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
1198 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
1199 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
1200 * sh-opc.h (arch_sh2a_nofpu): New.
1201 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
1202 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
1203 instruction.
1204 2004-01-20 DJ Delorie <dj@redhat.com>
1205 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
1206 2003-12-29 DJ Delorie <dj@redhat.com>
1207 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
1208 sh_opcode_info, sh_table): Add sh2a support.
1209 (arch_op32): New, to tag 32-bit opcodes.
1210 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
1211 2003-12-02 Michael Snyder <msnyder@redhat.com>
1212 * sh-opc.h (arch_sh2a): Add.
1213 * sh-dis.c (arch_sh2a): Handle.
1214 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
1215
670ec21d
NC		 12162004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
1217
1218 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
1219
ed049af3
NC		 12202004-07-22 Nick Clifton <nickc@redhat.com>
1221
1222 PR/280
1223 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
1224 insns - this is done by objdump itself.
1225 * h8500-dis.c (print_insn_h8500): Likewise.
1226
20f0a1fc
NC		 12272004-07-21 Jan Beulich <jbeulich@novell.com>
1228
1229 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
1230 regardless of address size prefix in effect.
1231 (ptr_reg): Size or address registers does not depend on rex64, but
1232 on the presence of an address size override.
1233 (OP_MMX): Use rex.x only for xmm registers.
1234 (OP_EM): Use rex.z only for xmm registers.
1235
6f14957b
MR		 12362004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
1237
1238 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
1239 move/branch operations to the bottom so that VR5400 multimedia
1240 instructions take precedence in disassembly.
1241
1586d91e
MR		 12422004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
1243
1244 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
1245 ISA-specific "break" encoding.
1246
982de27a
NC		 12472004-07-13 Elvis Chiang <elvisfb@gmail.com>
1248
1249 * arm-opc.h: Fix typo in comment.
1250
4300ab10
AS		 12512004-07-11 Andreas Schwab <schwab@suse.de>
1252
1253 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
1254
8577e690
AS		 12552004-07-09 Andreas Schwab <schwab@suse.de>
1256
1257 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
1258
1fe1f39c
NC		 12592004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1260
1261 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
1262 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
1263 (crx-dis.lo): New target.
1264 (crx-opc.lo): Likewise.
1265 * Makefile.in: Regenerate.
1266 * configure.in: Handle bfd_crx_arch.
1267 * configure: Regenerate.
1268 * crx-dis.c: New file.
1269 * crx-opc.c: New file.
1270 * disassemble.c (ARCH_crx): Define.
1271 (disassembler): Handle ARCH_crx.
1272
7a33b495
JW		 12732004-06-29 James E Wilson <wilson@specifixinc.com>
1274
1275 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
1276 * ia64-asmtab.c: Regnerate.
1277
98e69875
AM		 12782004-06-28 Alan Modra <amodra@bigpond.net.au>
1279
1280 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
1281 (extract_fxm): Don't test dialect.
1282 (XFXFXM_MASK): Include the power4 bit.
1283 (XFXM): Add p4 param.
1284 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
1285
a53b85e2
AO		 12862004-06-27 Alexandre Oliva <aoliva@redhat.com>
1287
1288 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
1289 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
1290
d0618d1c
AM		 12912004-06-26 Alan Modra <amodra@bigpond.net.au>
1292
1293 * ppc-opc.c (BH, XLBH_MASK): Define.
1294 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
1295
1d9f512f
AM		 12962004-06-24 Alan Modra <amodra@bigpond.net.au>
1297
1298 * i386-dis.c (x_mode): Comment.
1299 (two_source_ops): File scope.
1300 (float_mem): Correct fisttpll and fistpll.
1301 (float_mem_mode): New table.
1302 (dofloat): Use it.
1303 (OP_E): Correct intel mode PTR output.
1304 (ptr_reg): Use open_char and close_char.
1305 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
1306 operands. Set two_source_ops.
1307
52886d70
AM		 13082004-06-15 Alan Modra <amodra@bigpond.net.au>
1309
1310 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
1311 instead of _raw_size.
1312
bad9ceea
JJ		 13132004-06-08 Jakub Jelinek <jakub@redhat.com>
1314
1315 * ia64-gen.c (in_iclass): Handle more postinc st
1316 and ld variants.
1317 * ia64-asmtab.c: Rebuilt.
1318
0451f5df
MS		 13192004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
1320
1321 * s390-opc.txt: Correct architecture mask for some opcodes.
1322 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
1323 in the esa mode as well.
1324
f6f9408f
JR		 13252004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
1326
1327 * sh-dis.c (target_arch): Make unsigned.
1328 (print_insn_sh): Replace (most of) switch with a call to
1329 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
1330 * sh-opc.h: Redefine architecture flags values.
1331 Add sh3-nommu architecture.
1332 Reorganise <arch>_up macros so they make more visual sense.
1333 (SH_MERGE_ARCH_SET): Define new macro.
1334 (SH_VALID_BASE_ARCH_SET): Likewise.
1335 (SH_VALID_MMU_ARCH_SET): Likewise.
1336 (SH_VALID_CO_ARCH_SET): Likewise.
1337 (SH_VALID_ARCH_SET): Likewise.
1338 (SH_MERGE_ARCH_SET_VALID): Likewise.
1339 (SH_ARCH_SET_HAS_FPU): Likewise.
1340 (SH_ARCH_SET_HAS_DSP): Likewise.
1341 (SH_ARCH_UNKNOWN_ARCH): Likewise.
1342 (sh_get_arch_from_bfd_mach): Add prototype.
1343 (sh_get_arch_up_from_bfd_mach): Likewise.
1344 (sh_get_bfd_mach_from_arch_set): Likewise.
1345 (sh_merge_bfd_arc): Likewise.
1346
be8c092b
NC		 13472004-05-24 Peter Barada <peter@the-baradas.com>
1348
1349 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 1350 into new match_insn_m68k function. Loop over canidate
1351 matches and select first that completely matches.
be8c092b
NC		 1352 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
1353 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 1354 to verify addressing for MAC/EMAC.
be8c092b
NC		 1355 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
1356 reigster halves since 'fpu' and 'spl' look misleading.
1357 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
1358 * m68k-opc.c: Rearragne mac/emac cases to use longest for
1359 first, tighten up match masks.
1360 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
1361 'size' from special case code in print_insn_m68k to
1362 determine decode size of insns.
1363
a30e9cc4
AM		 13642004-05-19 Alan Modra <amodra@bigpond.net.au>
1365
1366 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
1367 well as when -mpower4.
1368
9598fbe5
NC		 13692004-05-13 Nick Clifton <nickc@redhat.com>
1370
1371 * po/fr.po: Updated French translation.
1372
6b6e92f4
NC		 13732004-05-05 Peter Barada <peter@the-baradas.com>
1374
1375 * m68k-dis.c(print_insn_m68k): Add new chips, use core
1376 variants in arch_mask. Only set m68881/68851 for 68k chips.
1377 * m68k-op.c: Switch from ColdFire chips to core variants.
1378
a404d431
AM		 13792004-05-05 Alan Modra <amodra@bigpond.net.au>
1380
a30e9cc4 1381 PR 147.
a404d431
AM		 1382 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
1383
f3806e43
BE		 13842004-04-29 Ben Elliston <bje@au.ibm.com>
1385
520ceea4
BE		 1386 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
1387 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 1388
1f1799d5
KK		 13892004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
1390
1391 * sh-dis.c (print_insn_sh): Print the value in constant pool
1392 as a symbol if it looks like a symbol.
1393
fd99574b
NC		 13942004-04-22 Peter Barada <peter@the-baradas.com>
1395
1396 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
1397 appropriate ColdFire architectures.
1398 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
1399 mask addressing.
1400 Add EMAC instructions, fix MAC instructions. Remove
1401 macmw/macml/msacmw/msacml instructions since mask addressing now
1402 supported.
1403
b4781d44
JJ		 14042004-04-20 Jakub Jelinek <jakub@redhat.com>
1405
1406 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
1407 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
1408 suffix. Use fmov*x macros, create all 3 fpsize variants in one
1409 macro. Adjust all users.
1410
91809fda 14112004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 1412
91809fda
NC		 1413 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
1414 separately.
1415
f4453dfa
NC		 14162004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
1417
1418 * m32r-asm.c: Regenerate.
1419
9b0de91a
SS		 14202004-03-29 Stan Shebs <shebs@apple.com>
1421
1422 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
1423 used.
1424
e20c0b3d
AM		 14252004-03-19 Alan Modra <amodra@bigpond.net.au>
1426
1427 * aclocal.m4: Regenerate.
1428 * config.in: Regenerate.
1429 * configure: Regenerate.
1430 * po/POTFILES.in: Regenerate.
1431 * po/opcodes.pot: Regenerate.
1432
fdd12ef3
AM		 14332004-03-16 Alan Modra <amodra@bigpond.net.au>
1434
1435 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
1436 PPC_OPERANDS_GPR_0.
1437 * ppc-opc.c (RA0): Define.
1438 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
1439 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 1440 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 1441
2dc111b3 14422004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 1443
1444 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 1445
7bfeee7b
AM		 14462004-03-15 Alan Modra <amodra@bigpond.net.au>
1447
1448 * sparc-dis.c (print_insn_sparc): Update getword prototype.
1449
7ffdda93
ML		 14502004-03-12 Michal Ludvig <mludvig@suse.cz>
1451
1452 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 1453 (grps): Delete GRPPLOCK entry.
7ffdda93 1454
cc0ec051
AM		 14552004-03-12 Alan Modra <amodra@bigpond.net.au>
1456
1457 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
1458 (M, Mp): Use OP_M.
1459 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
1460 (GRPPADLCK): Define.
1461 (dis386): Use NOP_Fixup on "nop".
1462 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
1463 (twobyte_has_modrm): Set for 0xa7.
1464 (padlock_table): Delete. Move to..
1465 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
1466 and clflush.
1467 (print_insn): Revert PADLOCK_SPECIAL code.
1468 (OP_E): Delete sfence, lfence, mfence checks.
1469
4fd61dcb
JJ		 14702004-03-12 Jakub Jelinek <jakub@redhat.com>
1471
1472 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
1473 (INVLPG_Fixup): New function.
1474 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
1475
0f10071e
ML		 14762004-03-12 Michal Ludvig <mludvig@suse.cz>
1477
1478 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
1479 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
1480 (padlock_table): New struct with PadLock instructions.
1481 (print_insn): Handle PADLOCK_SPECIAL.
1482
c02908d2
AM		 14832004-03-12 Alan Modra <amodra@bigpond.net.au>
1484
1485 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
1486 (OP_E): Twiddle clflush to sfence here.
1487
d5bb7600
NC		 14882004-03-08 Nick Clifton <nickc@redhat.com>
1489
1490 * po/de.po: Updated German translation.
1491
ae51a426
JR		 14922003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
1493
1494 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
1495 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
1496 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
1497 accordingly.
1498
676a64f4
RS		 14992004-03-01 Richard Sandiford <rsandifo@redhat.com>
1500
1501 * frv-asm.c: Regenerate.
1502 * frv-desc.c: Regenerate.
1503 * frv-desc.h: Regenerate.
1504 * frv-dis.c: Regenerate.
1505 * frv-ibld.c: Regenerate.
1506 * frv-opc.c: Regenerate.
1507 * frv-opc.h: Regenerate.
1508
c7a48b9a
RS		 15092004-03-01 Richard Sandiford <rsandifo@redhat.com>
1510
1511 * frv-desc.c, frv-opc.c: Regenerate.
1512
8ae0baa2
RS		 15132004-03-01 Richard Sandiford <rsandifo@redhat.com>
1514
1515 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
1516
ce11586c
JR		 15172004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1518
1519 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
1520 Also correct mistake in the comment.
1521
6a5709a5
JR		 15222004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1523
1524 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
1525 ensure that double registers have even numbers.
1526 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
1527 that reserved instruction 0xfffd does not decode the same
1528 as 0xfdfd (ftrv).
1529 * sh-opc.h: Add REG_N_D nibble type and use it whereever
1530 REG_N refers to a double register.
1531 Add REG_N_B01 nibble type and use it instead of REG_NM
1532 in ftrv.
1533 Adjust the bit patterns in a few comments.
1534
e5d2b64f 15352004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1536
1537 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 1538
1f04b05f
AH		 15392004-02-20 Aldy Hernandez <aldyh@redhat.com>
1540
1541 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
1542
2f3b8700
AH		 15432004-02-20 Aldy Hernandez <aldyh@redhat.com>
1544
1545 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
1546
f0b26da6 15472004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1548
1549 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
1550 mtivor32, mtivor33, mtivor34.
f0b26da6 1551
23d59c56 15522004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1553
1554 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 1555
34920d91
NC		 15562004-02-10 Petko Manolov <petkan@nucleusys.com>
1557
1558 * arm-opc.h Maverick accumulator register opcode fixes.
1559
44d86481
BE		 15602004-02-13 Ben Elliston <bje@wasabisystems.com>
1561
1562 * m32r-dis.c: Regenerate.
1563
17707c23
MS		 15642004-01-27 Michael Snyder <msnyder@redhat.com>
1565
1566 * sh-opc.h (sh_table): "fsrra", not "fssra".
1567
fe3a9bc4
NC		 15682004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
1569
1570 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
1571 contraints.
1572
ff24f124
JJ		 15732004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
1574
1575 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
1576
a02a862a
AM		 15772004-01-19 Alan Modra <amodra@bigpond.net.au>
1578
1579 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
1580 1. Don't print scale factor on AT&T mode when index missing.
1581
d164ea7f
AO		 15822004-01-16 Alexandre Oliva <aoliva@redhat.com>
1583
1584 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
1585 when loaded into XR registers.
1586
cb10e79a
RS		 15872004-01-14 Richard Sandiford <rsandifo@redhat.com>
1588
1589 * frv-desc.h: Regenerate.
1590 * frv-desc.c: Regenerate.
1591 * frv-opc.c: Regenerate.
1592
f532f3fa
MS		 15932004-01-13 Michael Snyder <msnyder@redhat.com>
1594
1595 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
1596
e45d0630
PB		 15972004-01-09 Paul Brook <paul@codesourcery.com>
1598
1599 * arm-opc.h (arm_opcodes): Move generic mcrr after known
1600 specific opcodes.
1601
3ba7a1aa
DJ		 16022004-01-07 Daniel Jacobowitz <drow@mvista.com>
1603
1604 * Makefile.am (libopcodes_la_DEPENDENCIES)
1605 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
1606 comment about the problem.
1607 * Makefile.in: Regenerate.
1608
ba2d3f07
AO		 16092004-01-06 Alexandre Oliva <aoliva@redhat.com>
1610
1611 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
1612 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
1613 cut&paste errors in shifting/truncating numerical operands.
1614 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1615 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
1616 (parse_uslo16): Likewise.
1617 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1618 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1619 (parse_s12): Likewise.
1620 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1621 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
1622 (parse_uslo16): Likewise.
1623 (parse_uhi16): Parse gothi and gotfuncdeschi.
1624 (parse_d12): Parse got12 and gotfuncdesc12.
1625 (parse_s12): Likewise.
1626
3ab48931
NC		 16272004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
1628
1629 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
1630 instruction which looks similar to an 'rla' instruction.
a0bd404e 1631
c9e214e5 1632For older changes see ChangeLog-0203
252b5132
RH		 1633\f
1634Local Variables:
2f6d2f85
NC		 1635mode: change-log
1636left-margin: 8
1637fill-column: 74
252b5132
RH		 1638version-control: never
1639End:
GDB Binutils - Deliverables
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