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simplify tic54x_set_default_include ()
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
ce440d63
GM		 12016-06-23 Graham Markall <graham.markall@embecosm.com>
2
3 * arc-opc.c: Correct description of availability of NPS400
4 features.
5
6fd3a02d
PB		 62016-06-22 Peter Bergner <bergner@vnet.ibm.com>
7
8 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
9 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
10 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
11 xor3>: New mnemonics.
12 <setb>: Change to a VX form instruction.
13 (insert_sh6): Add support for rldixor.
14 (extract_sh6): Likewise.
15
6b477896
TS		 162016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
17
18 * arc-ext.h: Wrap in extern C.
19
bdd582db
GM		 202016-06-21 Graham Markall <graham.markall@embecosm.com>
21
22 * arc-dis.c (arc_insn_length): Add comment on instruction length.
23 Use same method for determining instruction length on ARC700 and
24 NPS-400.
25 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
26 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
27 with the NPS400 subclass.
28 * arc-opc.c: Likewise.
29
96074adc
JM		 302016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
31
32 * sparc-opc.c (rdasr): New macro.
33 (wrasr): Likewise.
34 (rdpr): Likewise.
35 (wrpr): Likewise.
36 (rdhpr): Likewise.
37 (wrhpr): Likewise.
38 (sparc_opcodes): Use the macros above to fix and expand the
39 definition of read/write instructions from/to
40 asr/privileged/hyperprivileged instructions.
41 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
42 %hva_mask_nz. Prefer softint_set and softint_clear over
43 set_softint and clear_softint.
44 (print_insn_sparc): Support %ver in Rd.
45
7a10c22f
JM		 462016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
47
48 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
49 architecture according to the hardware capabilities they require.
50
4f26fb3a
JM		 512016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
52
53 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
54 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
55 bfd_mach_sparc_v9{c,d,e,v,m}.
56 * sparc-opc.c (MASK_V9C): Define.
57 (MASK_V9D): Likewise.
58 (MASK_V9E): Likewise.
59 (MASK_V9V): Likewise.
60 (MASK_V9M): Likewise.
61 (v6): Add MASK_V9{C,D,E,V,M}.
62 (v6notlet): Likewise.
63 (v7): Likewise.
64 (v8): Likewise.
65 (v9): Likewise.
66 (v9andleon): Likewise.
67 (v9a): Likewise.
68 (v9b): Likewise.
69 (v9c): Define.
70 (v9d): Likewise.
71 (v9e): Likewise.
72 (v9v): Likewise.
73 (v9m): Likewise.
74 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
75
3ee6e4fb
NC		 762016-06-15 Nick Clifton <nickc@redhat.com>
77
78 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
79 constants to match expected behaviour.
80 (nds32_parse_opcode): Likewise. Also for whitespace.
81
02f3be19
AB		 822016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
83
84 * arc-opc.c (extract_rhv1): Extract value from insn.
85
6f9f37ed 862016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 87
88 * arc-nps400-tbl.h: Add ldbit instruction.
89 * arc-opc.c: Add flag classes required for ldbit.
90
6f9f37ed 912016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 92
93 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
94 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
95 support the above instructions.
96
6f9f37ed 972016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 98
99 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
100 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
101 csma, cbba, zncv, and hofs.
102 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
103 support the above instructions.
104
1052016-06-06 Graham Markall <graham.markall@embecosm.com>
106
107 * arc-nps400-tbl.h: Add andab and orab instructions.
108
1092016-06-06 Graham Markall <graham.markall@embecosm.com>
110
111 * arc-nps400-tbl.h: Add addl-like instructions.
112
1132016-06-06 Graham Markall <graham.markall@embecosm.com>
114
115 * arc-nps400-tbl.h: Add mxb and imxb instructions.
116
1172016-06-06 Graham Markall <graham.markall@embecosm.com>
118
119 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
120 instructions.
121
b2cc3f6f
AK		 1222016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
123
124 * s390-dis.c (option_use_insn_len_bits_p): New file scope
125 variable.
126 (init_disasm): Handle new command line option "insnlength".
127 (print_s390_disassembler_options): Mention new option in help
128 output.
129 (print_insn_s390): Use the encoded insn length when dumping
130 unknown instructions.
131
1857fe72
DC		 1322016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
133
134 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
135 to the address and set as symbol address for LDS/ STS immediate operands.
136
14b57c7c
AM		 1372016-06-07 Alan Modra <amodra@gmail.com>
138
139 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
140 cpu for "vle" to e500.
141 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
142 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
143 (PPCNONE): Delete, substitute throughout.
144 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
145 except for major opcode 4 and 31.
146 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
147
4d1464f2
MW		 1482016-06-07 Matthew Wahab <matthew.wahab@arm.com>
149
150 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
151 ARM_EXT_RAS in relevant entries.
152
026122a6
PB		 1532016-06-03 Peter Bergner <bergner@vnet.ibm.com>
154
155 PR binutils/20196
156 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
157 opcodes for E6500.
158
07f5af7d
L		 1592016-06-03 H.J. Lu <hongjiu.lu@intel.com>
160
161 PR binutis/18386
162 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
163 (indir_v_mode): New.
164 Add comments for '&'.
165 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
166 (putop): Handle '&'.
167 (intel_operand_size): Handle indir_v_mode.
168 (OP_E_register): Likewise.
169 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
170 64-bit indirect call/jmp for AMD64.
171 * i386-tbl.h: Regenerated
172
4eb6f892
AB		 1732016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
174
175 * arc-dis.c (struct arc_operand_iterator): New structure.
176 (find_format_from_table): All the old content from find_format,
177 with some minor adjustments, and parameter renaming.
178 (find_format_long_instructions): New function.
179 (find_format): Rewritten.
180 (arc_insn_length): Add LSB parameter.
181 (extract_operand_value): New function.
182 (operand_iterator_next): New function.
183 (print_insn_arc): Use new functions to find opcode, and iterator
184 over operands.
185 * arc-opc.c (insert_nps_3bit_dst_short): New function.
186 (extract_nps_3bit_dst_short): New function.
187 (insert_nps_3bit_src2_short): New function.
188 (extract_nps_3bit_src2_short): New function.
189 (insert_nps_bitop1_size): New function.
190 (extract_nps_bitop1_size): New function.
191 (insert_nps_bitop2_size): New function.
192 (extract_nps_bitop2_size): New function.
193 (insert_nps_bitop_mod4_msb): New function.
194 (extract_nps_bitop_mod4_msb): New function.
195 (insert_nps_bitop_mod4_lsb): New function.
196 (extract_nps_bitop_mod4_lsb): New function.
197 (insert_nps_bitop_dst_pos3_pos4): New function.
198 (extract_nps_bitop_dst_pos3_pos4): New function.
199 (insert_nps_bitop_ins_ext): New function.
200 (extract_nps_bitop_ins_ext): New function.
201 (arc_operands): Add new operands.
202 (arc_long_opcodes): New global array.
203 (arc_num_long_opcodes): New global.
204 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
205
1fe0971e
TS		 2062016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
207
208 * nds32-asm.h: Add extern "C".
209 * sh-opc.h: Likewise.
210
315f180f
GM		 2112016-06-01 Graham Markall <graham.markall@embecosm.com>
212
213 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
214 0,b,limm to the rflt instruction.
215
a2b5fccc
TS		 2162016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
217
218 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
219 constant.
220
0cbd0046
L		 2212016-05-29 H.J. Lu <hongjiu.lu@intel.com>
222
223 PR gas/20145
224 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
225 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
226 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
227 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
228 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
229 * i386-init.h: Regenerated.
230
1848e567
L		 2312016-05-27 H.J. Lu <hongjiu.lu@intel.com>
232
233 PR gas/20145
234 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
235 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
236 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
237 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
238 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
239 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
240 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
241 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
242 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
243 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
244 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
245 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
246 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
247 CpuRegMask for AVX512.
248 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
249 and CpuRegMask.
250 (set_bitfield_from_cpu_flag_init): New function.
251 (set_bitfield): Remove const on f. Call
252 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
253 * i386-opc.h (CpuRegMMX): New.
254 (CpuRegXMM): Likewise.
255 (CpuRegYMM): Likewise.
256 (CpuRegZMM): Likewise.
257 (CpuRegMask): Likewise.
258 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
259 and cpuregmask.
260 * i386-init.h: Regenerated.
261 * i386-tbl.h: Likewise.
262
e92bae62
L		 2632016-05-27 H.J. Lu <hongjiu.lu@intel.com>
264
265 PR gas/20154
266 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
267 (opcode_modifiers): Add AMD64 and Intel64.
268 (main): Properly verify CpuMax.
269 * i386-opc.h (CpuAMD64): Removed.
270 (CpuIntel64): Likewise.
271 (CpuMax): Set to CpuNo64.
272 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
273 (AMD64): New.
274 (Intel64): Likewise.
275 (i386_opcode_modifier): Add amd64 and intel64.
276 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
277 on call and jmp.
278 * i386-init.h: Regenerated.
279 * i386-tbl.h: Likewise.
280
e89c5eaa
L		 2812016-05-27 H.J. Lu <hongjiu.lu@intel.com>
282
283 PR gas/20154
284 * i386-gen.c (main): Fail if CpuMax is incorrect.
285 * i386-opc.h (CpuMax): Set to CpuIntel64.
286 * i386-tbl.h: Regenerated.
287
77d66e7b
NC		 2882016-05-27 Nick Clifton <nickc@redhat.com>
289
290 PR target/20150
291 * msp430-dis.c (msp430dis_read_two_bytes): New function.
292 (msp430dis_opcode_unsigned): New function.
293 (msp430dis_opcode_signed): New function.
294 (msp430_singleoperand): Use the new opcode reading functions.
295 Only disassenmble bytes if they were successfully read.
296 (msp430_doubleoperand): Likewise.
297 (msp430_branchinstr): Likewise.
298 (msp430x_callx_instr): Likewise.
299 (print_insn_msp430): Check that it is safe to read bytes before
300 attempting disassembly. Use the new opcode reading functions.
301
19dfcc89
PB		 3022016-05-26 Peter Bergner <bergner@vnet.ibm.com>
303
304 * ppc-opc.c (CY): New define. Document it.
305 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
306
f3ad7637
L		 3072016-05-25 H.J. Lu <hongjiu.lu@intel.com>
308
309 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
310 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
311 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
312 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
313 CPU_ANY_AVX_FLAGS.
314 * i386-init.h: Regenerated.
315
f1360d58
L		 3162016-05-25 H.J. Lu <hongjiu.lu@intel.com>
317
318 PR gas/20141
319 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
320 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
321 * i386-init.h: Regenerated.
322
293f5f65
L		 3232016-05-25 H.J. Lu <hongjiu.lu@intel.com>
324
325 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
326 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
327 * i386-init.h: Regenerated.
328
d9eca1df
CZ		 3292016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
330
331 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
332 information.
333 (print_insn_arc): Set insn_type information.
334 * arc-opc.c (C_CC): Add F_CLASS_COND.
335 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
336 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
337 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
338 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
339 (brne, brne_s, jeq_s, jne_s): Likewise.
340
87789e08
CZ		 3412016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
342
343 * arc-tbl.h (neg): New instruction variant.
344
c810e0b8
CZ		 3452016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
346
347 * arc-dis.c (find_format, find_format, get_auxreg)
348 (print_insn_arc): Changed.
349 * arc-ext.h (INSERT_XOP): Likewise.
350
3d207518
TS		 3512016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
352
353 * tic54x-dis.c (sprint_mmr): Adjust.
354 * tic54x-opc.c: Likewise.
355
514e58b7
AM		 3562016-05-19 Alan Modra <amodra@gmail.com>
357
358 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
359
e43de63c
AM		 3602016-05-19 Alan Modra <amodra@gmail.com>
361
362 * ppc-opc.c: Formatting.
363 (NSISIGNOPT): Define.
364 (powerpc_opcodes <subis>): Use NSISIGNOPT.
365
1401d2fe
MR		 3662016-05-18 Maciej W. Rozycki <macro@imgtec.com>
367
368 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
369 replacing references to `micromips_ase' throughout.
370 (_print_insn_mips): Don't use file-level microMIPS annotation to
371 determine the disassembly mode with the symbol table.
372
1178da44
PB		 3732016-05-13 Peter Bergner <bergner@vnet.ibm.com>
374
375 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
376
8f4f9071
MF		 3772016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
378
379 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
380 mips64r6.
381 * mips-opc.c (D34): New macro.
382 (mips_builtin_opcodes): Define bposge32c for DSPr3.
383
8bc52696
AF		 3842016-05-10 Alexander Fomin <alexander.fomin@intel.com>
385
386 * i386-dis.c (prefix_table): Add RDPID instruction.
387 * i386-gen.c (cpu_flag_init): Add RDPID flag.
388 (cpu_flags): Add RDPID bitfield.
389 * i386-opc.h (enum): Add RDPID element.
390 (i386_cpu_flags): Add RDPID field.
391 * i386-opc.tbl: Add RDPID instruction.
392 * i386-init.h: Regenerate.
393 * i386-tbl.h: Regenerate.
394
39d911fc
TP		 3952016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
396
397 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
398 branch type of a symbol.
399 (print_insn): Likewise.
400
16a1fa25
TP		 4012016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
402
403 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
404 Mainline Security Extensions instructions.
405 (thumb_opcodes): Add entries for narrow ARMv8-M Security
406 Extensions instructions.
407 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
408 instructions.
409 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
410 special registers.
411
d751b79e
JM		 4122016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
413
414 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
415
945e0f82
CZ		 4162016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
417
418 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
419 (arcExtMap_genOpcode): Likewise.
420 * arc-opc.c (arg_32bit_rc): Define new variable.
421 (arg_32bit_u6): Likewise.
422 (arg_32bit_limm): Likewise.
423
20f55f38
SN		 4242016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
425
426 * aarch64-gen.c (VERIFIER): Define.
427 * aarch64-opc.c (VERIFIER): Define.
428 (verify_ldpsw): Use static linkage.
429 * aarch64-opc.h (verify_ldpsw): Remove.
430 * aarch64-tbl.h: Use VERIFIER for verifiers.
431
4bd13cde
NC		 4322016-04-28 Nick Clifton <nickc@redhat.com>
433
434 PR target/19722
435 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
436 * aarch64-opc.c (verify_ldpsw): New function.
437 * aarch64-opc.h (verify_ldpsw): New prototype.
438 * aarch64-tbl.h: Add initialiser for verifier field.
439 (LDPSW): Set verifier to verify_ldpsw.
440
c0f92bf9
L		 4412016-04-23 H.J. Lu <hongjiu.lu@intel.com>
442
443 PR binutils/19983
444 PR binutils/19984
445 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
446 smaller than address size.
447
e6c7cdec
TS		 4482016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
449
450 * alpha-dis.c: Regenerate.
451 * crx-dis.c: Likewise.
452 * disassemble.c: Likewise.
453 * epiphany-opc.c: Likewise.
454 * fr30-opc.c: Likewise.
455 * frv-opc.c: Likewise.
456 * ip2k-opc.c: Likewise.
457 * iq2000-opc.c: Likewise.
458 * lm32-opc.c: Likewise.
459 * lm32-opinst.c: Likewise.
460 * m32c-opc.c: Likewise.
461 * m32r-opc.c: Likewise.
462 * m32r-opinst.c: Likewise.
463 * mep-opc.c: Likewise.
464 * mt-opc.c: Likewise.
465 * or1k-opc.c: Likewise.
466 * or1k-opinst.c: Likewise.
467 * tic80-opc.c: Likewise.
468 * xc16x-opc.c: Likewise.
469 * xstormy16-opc.c: Likewise.
470
537aefaf
AB		 4712016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
472
473 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
474 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
475 calcsd, and calcxd instructions.
476 * arc-opc.c (insert_nps_bitop_size): Delete.
477 (extract_nps_bitop_size): Delete.
478 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
479 (extract_nps_qcmp_m3): Define.
480 (extract_nps_qcmp_m2): Define.
481 (extract_nps_qcmp_m1): Define.
482 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
483 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
484 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
485 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
486 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
487 NPS_QCMP_M3.
488
c8f785f2
AB		 4892016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
490
491 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
492
6fd8e7c2
L		 4932016-04-15 H.J. Lu <hongjiu.lu@intel.com>
494
495 * Makefile.in: Regenerated with automake 1.11.6.
496 * aclocal.m4: Likewise.
497
4b0c052e
AB		 4982016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
499
500 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
501 instructions.
502 * arc-opc.c (insert_nps_cmem_uimm16): New function.
503 (extract_nps_cmem_uimm16): New function.
504 (arc_operands): Add NPS_XLDST_UIMM16 operand.
505
cb040366
AB		 5062016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
507
508 * arc-dis.c (arc_insn_length): New function.
509 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
510 (find_format): Change insnLen parameter to unsigned.
511
accc0180
NC		 5122016-04-13 Nick Clifton <nickc@redhat.com>
513
514 PR target/19937
515 * v850-opc.c (v850_opcodes): Correct masks for long versions of
516 the LD.B and LD.BU instructions.
517
f36e33da
CZ		 5182016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
519
520 * arc-dis.c (find_format): Check for extension flags.
521 (print_flags): New function.
522 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
523 .extAuxRegister.
524 * arc-ext.c (arcExtMap_coreRegName): Use
525 LAST_EXTENSION_CORE_REGISTER.
526 (arcExtMap_coreReadWrite): Likewise.
527 (dump_ARC_extmap): Update printing.
528 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
529 (arc_aux_regs): Add cpu field.
530 * arc-regs.h: Add cpu field, lower case name aux registers.
531
1c2e355e
CZ		 5322016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
533
534 * arc-tbl.h: Add rtsc, sleep with no arguments.
535
b99747ae
CZ		 5362016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
537
538 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
539 Initialize.
540 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
541 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
542 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
543 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
544 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
545 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
546 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
547 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
548 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
549 (arc_opcode arc_opcodes): Null terminate the array.
550 (arc_num_opcodes): Remove.
551 * arc-ext.h (INSERT_XOP): Define.
552 (extInstruction_t): Likewise.
553 (arcExtMap_instName): Delete.
554 (arcExtMap_insn): New function.
555 (arcExtMap_genOpcode): Likewise.
556 * arc-ext.c (ExtInstruction): Remove.
557 (create_map): Zero initialize instruction fields.
558 (arcExtMap_instName): Remove.
559 (arcExtMap_insn): New function.
560 (dump_ARC_extmap): More info while debuging.
561 (arcExtMap_genOpcode): New function.
562 * arc-dis.c (find_format): New function.
563 (print_insn_arc): Use find_format.
564 (arc_get_disassembler): Enable dump_ARC_extmap only when
565 debugging.
566
92708cec
MR		 5672016-04-11 Maciej W. Rozycki <macro@imgtec.com>
568
569 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
570 instruction bits out.
571
a42a4f84
AB		 5722016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
573
574 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
575 * arc-opc.c (arc_flag_operands): Add new flags.
576 (arc_flag_classes): Add new classes.
577
1328504b
AB		 5782016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
579
580 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
581
820f03ff
AB		 5822016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
583
584 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
585 encode1, rflt, crc16, and crc32 instructions.
586 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
587 (arc_flag_classes): Add C_NPS_R.
588 (insert_nps_bitop_size_2b): New function.
589 (extract_nps_bitop_size_2b): Likewise.
590 (insert_nps_bitop_uimm8): Likewise.
591 (extract_nps_bitop_uimm8): Likewise.
592 (arc_operands): Add new operand entries.
593
8ddf6b2a
CZ		 5942016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
595
b99747ae
CZ		 596 * arc-regs.h: Add a new subclass field. Add double assist
597 accumulator register values.
598 * arc-tbl.h: Use DPA subclass to mark the double assist
599 instructions. Use DPX/SPX subclas to mark the FPX instructions.
600 * arc-opc.c (RSP): Define instead of SP.
601 (arc_aux_regs): Add the subclass field.
8ddf6b2a 602
589a7d88
JW		 6032016-04-05 Jiong Wang <jiong.wang@arm.com>
604
605 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
606
0a191de9 6072016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 608
609 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
610 NPS_R_SRC1.
611
0a106562
AB		 6122016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
613
614 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
615 issues. No functional changes.
616
bd05ac5f
CZ		 6172016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
618
b99747ae
CZ		 619 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
620 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
621 (RTT): Remove duplicate.
622 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
623 (PCT_CONFIG*): Remove.
624 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 625
9885948f
CZ		 6262016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
627
b99747ae 628 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 629
f2dd8838
CZ		 6302016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
631
b99747ae
CZ		 632 * arc-tbl.h (invld07): Remove.
633 * arc-ext-tbl.h: New file.
634 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
635 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 636
0d2f91fe
JK		 6372016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
638
639 Fix -Wstack-usage warnings.
640 * aarch64-dis.c (print_operands): Substitute size.
641 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
642
a6b71f42
JM		 6432016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
644
645 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
646 to get a proper diagnostic when an invalid ASR register is used.
647
9780e045
NC		 6482016-03-22 Nick Clifton <nickc@redhat.com>
649
650 * configure: Regenerate.
651
e23e8ebe
AB		 6522016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
653
654 * arc-nps400-tbl.h: New file.
655 * arc-opc.c: Add top level comment.
656 (insert_nps_3bit_dst): New function.
657 (extract_nps_3bit_dst): New function.
658 (insert_nps_3bit_src2): New function.
659 (extract_nps_3bit_src2): New function.
660 (insert_nps_bitop_size): New function.
661 (extract_nps_bitop_size): New function.
662 (arc_flag_operands): Add nps400 entries.
663 (arc_flag_classes): Add nps400 entries.
664 (arc_operands): Add nps400 entries.
665 (arc_opcodes): Add nps400 include.
666
1ae8ab47
AB		 6672016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
668
669 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
670 the new class enum values.
671
8699fc3e
AB		 6722016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
673
674 * arc-dis.c (print_insn_arc): Handle nps400.
675
24740d83
AB		 6762016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
677
678 * arc-opc.c (BASE): Delete.
679
8678914f
NC		 6802016-03-18 Nick Clifton <nickc@redhat.com>
681
682 PR target/19721
683 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
684 of MOV insn that aliases an ORR insn.
685
cc933301
JW		 6862016-03-16 Jiong Wang <jiong.wang@arm.com>
687
688 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
689
f86f5863
TS		 6902016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
691
692 * mcore-opc.h: Add const qualifiers.
693 * microblaze-opc.h (struct op_code_struct): Likewise.
694 * sh-opc.h: Likewise.
695 * tic4x-dis.c (tic4x_print_indirect): Likewise.
696 (tic4x_print_op): Likewise.
697
62de1c63
AM		 6982016-03-02 Alan Modra <amodra@gmail.com>
699
d11698cd 700 * or1k-desc.h: Regenerate.
62de1c63 701 * fr30-ibld.c: Regenerate.
c697cf0b 702 * rl78-decode.c: Regenerate.
62de1c63 703
020efce5
NC		 7042016-03-01 Nick Clifton <nickc@redhat.com>
705
706 PR target/19747
707 * rl78-dis.c (print_insn_rl78_common): Fix typo.
708
b0c11777
RL		 7092016-02-24 Renlin Li <renlin.li@arm.com>
710
711 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
712 (print_insn_coprocessor): Support fp16 instructions.
713
3e309328
RL		 7142016-02-24 Renlin Li <renlin.li@arm.com>
715
716 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
717 vminnm, vrint(mpna).
718
8afc7bea
RL		 7192016-02-24 Renlin Li <renlin.li@arm.com>
720
721 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
722 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
723
4fd7268a
L		 7242016-02-15 H.J. Lu <hongjiu.lu@intel.com>
725
726 * i386-dis.c (print_insn): Parenthesize expression to prevent
727 truncated addresses.
728 (OP_J): Likewise.
729
4670103e
CZ		 7302016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
731 Janek van Oirschot <jvanoirs@synopsys.com>
732
b99747ae
CZ		 733 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
734 variable.
4670103e 735
c1d9289f
NC		 7362016-02-04 Nick Clifton <nickc@redhat.com>
737
738 PR target/19561
739 * msp430-dis.c (print_insn_msp430): Add a special case for
740 decoding an RRC instruction with the ZC bit set in the extension
741 word.
742
a143b004
AB		 7432016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
744
745 * cgen-ibld.in (insert_normal): Rework calculation of shift.
746 * epiphany-ibld.c: Regenerate.
747 * fr30-ibld.c: Regenerate.
748 * frv-ibld.c: Regenerate.
749 * ip2k-ibld.c: Regenerate.
750 * iq2000-ibld.c: Regenerate.
751 * lm32-ibld.c: Regenerate.
752 * m32c-ibld.c: Regenerate.
753 * m32r-ibld.c: Regenerate.
754 * mep-ibld.c: Regenerate.
755 * mt-ibld.c: Regenerate.
756 * or1k-ibld.c: Regenerate.
757 * xc16x-ibld.c: Regenerate.
758 * xstormy16-ibld.c: Regenerate.
759
b89807c6
AB		 7602016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
761
762 * epiphany-dis.c: Regenerated from latest cpu files.
763
d8c823c8
MM		 7642016-02-01 Michael McConville <mmcco@mykolab.com>
765
766 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
767 test bit.
768
5bc5ae88
RL		 7692016-01-25 Renlin Li <renlin.li@arm.com>
770
771 * arm-dis.c (mapping_symbol_for_insn): New function.
772 (find_ifthen_state): Call mapping_symbol_for_insn().
773
0bff6e2d
MW		 7742016-01-20 Matthew Wahab <matthew.wahab@arm.com>
775
776 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
777 of MSR UAO immediate operand.
778
100b4f2e
MR		 7792016-01-18 Maciej W. Rozycki <macro@imgtec.com>
780
781 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
782 instruction support.
783
5c14705f
AM		 7842016-01-17 Alan Modra <amodra@gmail.com>
785
786 * configure: Regenerate.
787
4d82fe66
NC		 7882016-01-14 Nick Clifton <nickc@redhat.com>
789
790 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
791 instructions that can support stack pointer operations.
792 * rl78-decode.c: Regenerate.
793 * rl78-dis.c: Fix display of stack pointer in MOVW based
794 instructions.
795
651657fa
MW		 7962016-01-14 Matthew Wahab <matthew.wahab@arm.com>
797
798 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
799 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
800 erxtatus_el1 and erxaddr_el1.
801
105bde57
MW		 8022016-01-12 Matthew Wahab <matthew.wahab@arm.com>
803
804 * arm-dis.c (arm_opcodes): Add "esb".
805 (thumb_opcodes): Likewise.
806
afa8d405
PB		 8072016-01-11 Peter Bergner <bergner@vnet.ibm.com>
808
809 * ppc-opc.c <xscmpnedp>: Delete.
810 <xvcmpnedp>: Likewise.
811 <xvcmpnedp.>: Likewise.
812 <xvcmpnesp>: Likewise.
813 <xvcmpnesp.>: Likewise.
814
83c3256e
AS		 8152016-01-08 Andreas Schwab <schwab@linux-m68k.org>
816
817 PR gas/13050
818 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
819 addition to ISA_A.
820
6f2750fe
AM		 8212016-01-01 Alan Modra <amodra@gmail.com>
822
823 Update year range in copyright notice of all files.
824
3499769a
AM		 825For older changes see ChangeLog-2015
826\f
827Copyright (C) 2016 Free Software Foundation, Inc.
828
829Copying and distribution of this file, with or without modification,
830are permitted in any medium without royalty provided the copyright
831notice and this notice are preserved.
832
833Local Variables:
834mode: change-log
835left-margin: 8
836fill-column: 74
837version-control: never
838End:
GDB Binutils - Deliverables
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