[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>

	* po/Make-in (top_builddir): Define.

2006-06-05  Alan Modra  <amodra@bigpond.net.au>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.
	* config.in: Regenerate.

2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>

	* Makefile.am (INCLUDES): Use @INCINTL@.
	* acinclude.m4: Include new gettext macros.
	* configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
	Remove local code for po/Makefile.
	* Makefile.in, aclocal.m4, configure: Regenerated.

2006-05-30  Nick Clifton  <nickc@redhat.com>

	* po/es.po: Updated Spanish translation.

2006-05-25  Richard Sandiford  <richard@codesourcery.com>

	* m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
	and fmovem entries.  Put register list entries before immediate
	mask entries.  Use "l" rather than "L" in the fmovem entries.
	* m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
	out from INFO.
	(m68k_scan_mask): New function, split out from...
	(print_insn_m68k): ...here.  If no architecture has been set,
	first try printing an m680x0 instruction, then try a Coldfire one.

2006-05-24  Nick Clifton  <nickc@redhat.com>

	* po/ga.po: Updated Irish translation.

2006-05-22  Nick Clifton  <nickc@redhat.com>

	* crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.

2006-05-22  Nick Clifton  <nickc@redhat.com>

	* po/nl.po: Updated translation.

2006-05-18  Alan Modra  <amodra@bigpond.net.au>

	* avr-dis.c: Formatting fix.

2006-05-14  Thiemo Seufer  <ths@mips.com>

	* mips16-opc.c (I1, I32, I64): New shortcut defines.
	(mips16_opcodes): Change membership of instructions to their
	lowest baseline ISA.

2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (grps): Update sgdt/sidt for 64bit.

2006-05-05  Julian Brown  <julian@codesourcery.com>

	* arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
	vldm/vstm.

2006-05-05  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>

	* mips-opc.c: Add macro for cache instruction.

2006-05-04  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
	    David Ung  <davidu@mips.com>

	* mips-dis.c (mips_arch_choices): Add smartmips instruction
	decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
	2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
	MIPS64R2.
	* mips-opc.c: fix random typos in comments.
	(INSN_SMARTMIPS): New defines.
	(mips_builtin_opcodes): Add paired single support for MIPS32R2.
	Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
	flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
	FP_S and FP_D flags to denote single and double register
	accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
	Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
	for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
	variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
	release 2 ISAs.
	* mips16-opc.c (mips16_opcodes): Add sdbbp instruction.

2006-05-03  Thiemo Seufer  <ths@mips.com>

	* mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.

2006-05-02  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
            David Ung  <davidu@mips.com>

	* mips-dis.c (print_insn_args): Force mips16 to odd addresses.
	(print_mips16_insn_arg): Force mips16 to odd addresses.

2006-04-30  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>

	* mips-opc.c (mips_builtin_opcodes): Add udi instructions
	"udi0" to "udi15".
	* mips-dis.c (print_insn_args): Adds udi argument handling.

2006-04-28  James E Wilson  <wilson@specifix.com>

	* m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
	error message.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>
	    Nigel Stephens  <nigel@mips.com>

	* mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
	names.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
            David Ung  <davidu@mips.com>

	* mips-dis.c (print_insn_args): Add mips_opcode argument.
	(print_insn_mips):  Adjust print_insn_args call.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>

	* mips-dis.c (print_insn_args): Print $fcc only for FP
	instructions, use $cc elsewise.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>

	* opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
	Map MIPS16 registers to O32 names.
	(print_mips16_insn_arg): Use mips16_reg_names.

2006-04-26  Julian Brown  <julian@codesourcery.com>

	* arm-dis.c (print_insn_neon): Disassemble floating-point constant
	VMOV.

2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>

	* opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
	%<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
	Add unified load/store instruction names.
	(neon_opcode_table): New.
	(arm_opcodes): Expand meaning of %<bitfield>['`?].
	(arm_decode_bitfield): New.
	(print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
	Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
	(print_insn_neon): New.
	(print_insn_arm): Adjust print_insn_coprocessor call. Call
	print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
	(print_insn_thumb32): Likewise.

2006-04-19  Alan Modra  <amodra@bigpond.net.au>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.

2006-04-19  Alan Modra  <amodra@bigpond.net.au>

	* avr-dis.c (avr_operand): Warning fix.

	* configure: Regenerate.

2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>

	* po/POTFILES.in: Regenerated.

2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>

	PR binutils/2454
	* avr-dis.c (avr_operand): Arrange for a comment to appear before
	the symolic form of an address, so that the output of objdump -d
	can be reassembled.

2006-04-10  DJ Delorie  <dj@redhat.com>

	* m32c-asm.c: Regenerate.

2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>

	* Makefile.am: Add install-html target.
	* Makefile.in: Regenerate.

2006-04-06  Nick Clifton  <nickc@redhat.com>

	* po/vi/po: Updated Vietnamese translation.

2006-03-31  Paul Koning  <ni1d@arrl.net>

	* pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.

2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>

	* bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
	logic to identify halfword shifts.

2006-03-16  Paul Brook  <paul@codesourcery.com>

	* arm-dis.c (arm_opcodes): Rename swi to svc.
	(thumb_opcodes): Ditto.

2006-03-13  DJ Delorie  <dj@redhat.com>

	* m32c-asm.c: Regenerate.
	* m32c-desc.c: Likewise.
	* m32c-desc.h: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-ibld.c: Likewise.
	* m32c-opc.c: Likewise.
	* m32c-opc.h: Likewise.

2006-03-10  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate with mul.l, mulu.l.
	* m32c-opc.c: Likewise.
	* m32c-opc.h: Likewise.


2006-03-09  Nick Clifton  <nickc@redhat.com>

	* po/sv.po: Updated Swedish translation.

2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/2428
	* i386-dis.c (REP_Fixup): New function.
	(AL): Remove duplicate.
	(Xbr): New.
	(Xvr): Likewise.
	(Ybr): Likewise.
	(Yvr): Likewise.
	(indirDXr): Likewise.
	(ALr): Likewise.
	(eAXr): Likewise.
	(dis386): Updated entries of ins, outs, movs, lods and stos.

2006-03-05  Nick Clifton  <nickc@redhat.com>

	* cgen-ibld.in (insert_normal): Cope with attempts to insert a
	signed 32-bit value into an unsigned 32-bit field when the host is
	a 64-bit machine.
	* fr30-ibld.c: Regenerate.
	* frv-ibld.c: Regenerate.
	* ip2k-ibld.c: Regenerate.
	* iq2000-asm.c: Regenerate.
	* iq2000-ibld.c: Regenerate.
	* m32c-ibld.c: Regenerate.
	* m32r-ibld.c: Regenerate.
	* openrisc-ibld.c: Regenerate.
	* xc16x-ibld.c: Regenerate.
	* xstormy16-ibld.c: Regenerate.

2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)

	* xc16x-asm.c: Regenerate.
	* xc16x-dis.c: Regenerate.

2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>

	* po/Make-in: Add html target.

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
	Intel Merom New Instructions.
	(THREE_BYTE_0): Likewise.
	(THREE_BYTE_1): Likewise.
	(three_byte_table): Likewise.
	(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
	THREE_BYTE_1 for entry 0x3a.
	(twobyte_has_modrm): Updated.
	(twobyte_uses_SSE_prefix): Likewise.
	(print_insn): Handle 3-byte opcodes used by Intel Merom New
	Instructions.

2006-02-24  David S. Miller  <davem@sunset.davemloft.net>

	* sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
	(v9_hpriv_reg_names): New table.
	(print_insn_sparc): Allow values up to 16 for '?' and '!'.
	New cases '$' and '%' for read/write hyperprivileged register.
	* sparc-opc.c (sparc_opcodes): Add new entries for UA2005
	window handling and rdhpr/wrhpr instructions.
	
2006-02-24  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate with linker relaxation attributes.
	* m32c-desc.h: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-opc.c: Likewise.

2006-02-24  Paul Brook  <paul@codesourcery.com>

	* arm-dis.c (arm_opcodes): Add V7 instructions.
	(thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
	(print_arm_address): New function.
	(print_insn_arm): Use it.  Add 'P' and 'U' cases.
	(psr_name): New function.
	(print_insn_thumb32): Add 'U', 'C' and 'D' cases.

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-opc-i.c (bXc): New.
	(mXc): Likewise.
	(OpX2TaTbYaXcC): Likewise.
	(TF). Likewise.
	(TFCM). Likewise.
	(ia64_opcodes_i): Add instructions for tf.

	* ia64-opc.h (IMMU5b): New.

	* ia64-asmtab.c: Regenerated.

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-gen.c: Update copyright years.
	* ia64-opc-b.c: Likewise.

2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-gen.c (lookup_regindex): Handle ".vm".
	(print_dependency_table): Handle '\"'.

	* ia64-ic.tbl: Updated from SDM 2.2.
	* ia64-raw.tbl: Likewise.
	* ia64-waw.tbl: Likewise.
	* ia64-asmtab.c: Regenerated.

	* ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.

2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
            Anil Paranjape   <anilp1@kpitcummins.com>
            Shilin Shakti    <shilins@kpitcummins.com>

	* xc16x-desc.h: New file
	* xc16x-desc.c: New file
	* xc16x-opc.h: New file	
	* xc16x-opc.c: New file
	* xc16x-ibld.c: New file
	* xc16x-asm.c: New file
	* xc16x-dis.c: New file
	* Makefile.am: Entries for xc16x 
	* Makefile.in: Regenerate 
	* cofigure.in: Add xc16x target information.
	* configure: Regenerate.
	* disassemble.c: Add xc16x target information.

2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (dis386_twobyte): Use "movZ" for debug register
	moves.

2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c ('Z'): Add a new macro.
	(dis386_twobyte): Use "movZ" for control register moves.

2006-02-10  Nick Clifton  <nickc@redhat.com>

	* iq2000-asm.c: Regenerate.

2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>

	* m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.

2006-01-26  David Ung  <davidu@mips.com>

	* mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
	ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
	floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
	nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
	rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.

2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>

	* z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
	ld_d_r, pref_xd_cb): Use signed char to hold data to be
	disassembled.	
	* z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
	buffer overflows when disassembling instructions like
	ld (ix+123),0x23
	* z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
	operand, if the offset is negative.

2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>

	* z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
	unsigned char to hold data to be disassembled.

2006-01-17  Andreas Schwab  <schwab@suse.de>

	PR binutils/1486
	* disassemble.c (disassemble_init_for_target): Set
	disassembler_needs_relocs for bfd_arch_arm.

2006-01-16  Paul Brook  <paul@codesourcery.com>

	* m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
	f?add?, and f?sub? instructions.

2006-01-16  Nick Clifton  <nickc@redhat.com>

	* po/zh_CN.po: New Chinese (simplified) translation.
	* configure.in (ALL_LINGUAS): Add "zh_CH".
	* configure: Regenerate.

2006-01-05  Paul Brook  <paul@codesourcery.com>

	* m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.

2006-01-06  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate.
	* m32c-opc.c: Regenerate.
	* m32c-opc.h: Regenerate.

2006-01-03  DJ Delorie  <dj@redhat.com>

	* cgen-ibld.in (extract_normal): Avoid memory range errors.
	* m32c-ibld.c: Regenerated.

For older changes see ChangeLog-2005
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
4cfe2c59 DJ	1	2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
	2
	3	* po/Make-in (top_builddir): Define.
	4
7ff1a5b5 AM	5	2006-06-05 Alan Modra <amodra@bigpond.net.au>
	6
	7	* Makefile.am: Run "make dep-am".
	8	* Makefile.in: Regenerate.
	9	* config.in: Regenerate.
	10
20e95c23 DJ	11	2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
	12
	13	* Makefile.am (INCLUDES): Use @INCINTL@.
	14	* acinclude.m4: Include new gettext macros.
	15	* configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
	16	Remove local code for po/Makefile.
	17	* Makefile.in, aclocal.m4, configure: Regenerated.
	18
eebf07fb NC	19	2006-05-30 Nick Clifton <nickc@redhat.com>
	20
	21	* po/es.po: Updated Spanish translation.
	22
a596001e RS	23	2006-05-25 Richard Sandiford <richard@codesourcery.com>
	24
	25	* m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
	26	and fmovem entries. Put register list entries before immediate
	27	mask entries. Use "l" rather than "L" in the fmovem entries.
	28	* m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
	29	out from INFO.
	30	(m68k_scan_mask): New function, split out from...
	31	(print_insn_m68k): ...here. If no architecture has been set,
	32	first try printing an m680x0 instruction, then try a Coldfire one.
	33
4a4d496a NC	34	2006-05-24 Nick Clifton <nickc@redhat.com>
	35
	36	* po/ga.po: Updated Irish translation.
	37
a854efa3 NC	38	2006-05-22 Nick Clifton <nickc@redhat.com>
	39
	40	* crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
	41
0bd79061 NC	42	2006-05-22 Nick Clifton <nickc@redhat.com>
	43
	44	* po/nl.po: Updated translation.
	45
00988f49 AM	46	2006-05-18 Alan Modra <amodra@bigpond.net.au>
	47
	48	* avr-dis.c: Formatting fix.
	49
9b3f89ee TS	50	2006-05-14 Thiemo Seufer <ths@mips.com>
	51
	52	* mips16-opc.c (I1, I32, I64): New shortcut defines.
	53	(mips16_opcodes): Change membership of instructions to their
	54	lowest baseline ISA.
	55
cb6d3433 L	56	2006-05-09 H.J. Lu <hongjiu.lu@intel.com>
	57
	58	* i386-dis.c (grps): Update sgdt/sidt for 64bit.
	59
1f3c39b9 JB	60	2006-05-05 Julian Brown <julian@codesourcery.com>
	61
	62	* arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
	63	vldm/vstm.
	64
d43b4baf TS	65	2006-05-05 Thiemo Seufer <ths@mips.com>
	66	David Ung <davidu@mips.com>
	67
	68	* mips-opc.c: Add macro for cache instruction.
	69
39a7806d TS	70	2006-05-04 Thiemo Seufer <ths@mips.com>
	71	Nigel Stephens <nigel@mips.com>
	72	David Ung <davidu@mips.com>
	73
	74	* mips-dis.c (mips_arch_choices): Add smartmips instruction
	75	decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
	76	2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
	77	MIPS64R2.
	78	* mips-opc.c: fix random typos in comments.
	79	(INSN_SMARTMIPS): New defines.
	80	(mips_builtin_opcodes): Add paired single support for MIPS32R2.
	81	Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
	82	flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
	83	FP_S and FP_D flags to denote single and double register
	84	accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
	85	Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
	86	for MIPS32R2. Add SmartMIPS instructions. Add two-argument
	87	variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
	88	release 2 ISAs.
	89	* mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
	90
104b4fab TS	91	2006-05-03 Thiemo Seufer <ths@mips.com>
	92
	93	* mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
	94
022fac6d TS	95	2006-05-02 Thiemo Seufer <ths@mips.com>
	96	Nigel Stephens <nigel@mips.com>
	97	David Ung <davidu@mips.com>
	98
	99	* mips-dis.c (print_insn_args): Force mips16 to odd addresses.
	100	(print_mips16_insn_arg): Force mips16 to odd addresses.
	101
9bcd4f99 TS	102	2006-04-30 Thiemo Seufer <ths@mips.com>
	103	David Ung <davidu@mips.com>
	104
	105	* mips-opc.c (mips_builtin_opcodes): Add udi instructions
	106	"udi0" to "udi15".
	107	* mips-dis.c (print_insn_args): Adds udi argument handling.
	108
f095b97b JW	109	2006-04-28 James E Wilson <wilson@specifix.com>
	110
	111	* m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
	112	error message.
	113
59c455b3 TS	114	2006-04-28 Thiemo Seufer <ths@mips.com>
59c455b3 TS	115	David Ung <davidu@mips.com>
bdb09db1	116	Nigel Stephens <nigel@mips.com>
59c455b3 TS	117
	118	* mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
	119	names.
	120
cc0ca239	121	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	122	Nigel Stephens <nigel@mips.com>
cc0ca239 TS	123	David Ung <davidu@mips.com>
	124
	125	* mips-dis.c (print_insn_args): Add mips_opcode argument.
	126	(print_insn_mips): Adjust print_insn_args call.
	127
0d09bfe6	128	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	129	Nigel Stephens <nigel@mips.com>
0d09bfe6 TS	130
	131	* mips-dis.c (print_insn_args): Print $fcc only for FP
	132	instructions, use $cc elsewise.
	133
654c225a	134	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	135	Nigel Stephens <nigel@mips.com>
654c225a TS	136
	137	* opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
	138	Map MIPS16 registers to O32 names.
	139	(print_mips16_insn_arg): Use mips16_reg_names.
	140
0dbde4cf JB	141	2006-04-26 Julian Brown <julian@codesourcery.com>
	142
	143	* arm-dis.c (print_insn_neon): Disassemble floating-point constant
	144	VMOV.
	145
16980d0b JB	146	2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
	147	Julian Brown <julian@codesourcery.com>
	148
	149	* opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
	150	%<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
	151	Add unified load/store instruction names.
	152	(neon_opcode_table): New.
	153	(arm_opcodes): Expand meaning of %<bitfield>['`?].
	154	(arm_decode_bitfield): New.
	155	(print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
	156	Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
	157	(print_insn_neon): New.
	158	(print_insn_arm): Adjust print_insn_coprocessor call. Call
	159	print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
	160	(print_insn_thumb32): Likewise.
	161
ec3fcc56 AM	162	2006-04-19 Alan Modra <amodra@bigpond.net.au>
	163
	164	* Makefile.am: Run "make dep-am".
	165	* Makefile.in: Regenerate.
	166
241a6c40 AM	167	2006-04-19 Alan Modra <amodra@bigpond.net.au>
241a6c40 AM	168
7c6646cd AM	169	* avr-dis.c (avr_operand): Warning fix.
7c6646cd AM	170
241a6c40 AM	171	* configure: Regenerate.
241a6c40 AM	172
e7403566 DJ	173	2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
	174
	175	* po/POTFILES.in: Regenerated.
	176
52f16a0e NC	177	2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
	178
	179	PR binutils/2454
	180	* avr-dis.c (avr_operand): Arrange for a comment to appear before
	181	the symolic form of an address, so that the output of objdump -d
	182	can be reassembled.
	183
e78efa90 DD	184	2006-04-10 DJ Delorie <dj@redhat.com>
	185
	186	* m32c-asm.c: Regenerate.
	187
108a6f8e CD	188	2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
	189
	190	* Makefile.am: Add install-html target.
	191	* Makefile.in: Regenerate.
	192
a135cb2c NC	193	2006-04-06 Nick Clifton <nickc@redhat.com>
	194
	195	* po/vi/po: Updated Vietnamese translation.
	196
47426b41 AM	197	2006-03-31 Paul Koning <ni1d@arrl.net>
	198
	199	* pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
	200
331f1cbe BS	201	2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
	202
	203	* bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
	204	logic to identify halfword shifts.
	205
c16d2bf0 PB	206	2006-03-16 Paul Brook <paul@codesourcery.com>
	207
	208	* arm-dis.c (arm_opcodes): Rename swi to svc.
	209	(thumb_opcodes): Ditto.
	210
5348b81e DD	211	2006-03-13 DJ Delorie <dj@redhat.com>
5348b81e DD	212
5398310a DD	213	* m32c-asm.c: Regenerate.
	214	* m32c-desc.c: Likewise.
	215	* m32c-desc.h: Likewise.
	216	* m32c-dis.c: Likewise.
	217	* m32c-ibld.c: Likewise.
5348b81e DD	218	* m32c-opc.c: Likewise.
	219	* m32c-opc.h: Likewise.
	220
253d272c DD	221	2006-03-10 DJ Delorie <dj@redhat.com>
	222
	223	* m32c-desc.c: Regenerate with mul.l, mulu.l.
	224	* m32c-opc.c: Likewise.
	225	* m32c-opc.h: Likewise.
	226
	227
f530741d NC	228	2006-03-09 Nick Clifton <nickc@redhat.com>
	229
	230	* po/sv.po: Updated Swedish translation.
	231
35c52694 L	232	2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
	233
	234	PR binutils/2428
	235	* i386-dis.c (REP_Fixup): New function.
	236	(AL): Remove duplicate.
	237	(Xbr): New.
	238	(Xvr): Likewise.
	239	(Ybr): Likewise.
	240	(Yvr): Likewise.
	241	(indirDXr): Likewise.
	242	(ALr): Likewise.
	243	(eAXr): Likewise.
	244	(dis386): Updated entries of ins, outs, movs, lods and stos.
	245
ed963e2d NC	246	2006-03-05 Nick Clifton <nickc@redhat.com>
	247
	248	* cgen-ibld.in (insert_normal): Cope with attempts to insert a
	249	signed 32-bit value into an unsigned 32-bit field when the host is
	250	a 64-bit machine.
	251	* fr30-ibld.c: Regenerate.
	252	* frv-ibld.c: Regenerate.
	253	* ip2k-ibld.c: Regenerate.
	254	* iq2000-asm.c: Regenerate.
	255	* iq2000-ibld.c: Regenerate.
	256	* m32c-ibld.c: Regenerate.
	257	* m32r-ibld.c: Regenerate.
	258	* openrisc-ibld.c: Regenerate.
	259	* xc16x-ibld.c: Regenerate.
	260	* xstormy16-ibld.c: Regenerate.
	261
c7d41dc5 NC	262	2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
	263
	264	* xc16x-asm.c: Regenerate.
	265	* xc16x-dis.c: Regenerate.
c7d41dc5	266
f7d9e5c3 CD	267	2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
	268
	269	* po/Make-in: Add html target.
	270
331d2d0d L	271	2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
	272
	273	* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
	274	Intel Merom New Instructions.
	275	(THREE_BYTE_0): Likewise.
	276	(THREE_BYTE_1): Likewise.
	277	(three_byte_table): Likewise.
	278	(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
	279	THREE_BYTE_1 for entry 0x3a.
	280	(twobyte_has_modrm): Updated.
	281	(twobyte_uses_SSE_prefix): Likewise.
	282	(print_insn): Handle 3-byte opcodes used by Intel Merom New
	283	Instructions.
	284
ff3f9d5b DM	285	2006-02-24 David S. Miller <davem@sunset.davemloft.net>
	286
	287	* sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
	288	(v9_hpriv_reg_names): New table.
	289	(print_insn_sparc): Allow values up to 16 for '?' and '!'.
	290	New cases '$' and '%' for read/write hyperprivileged register.
	291	* sparc-opc.c (sparc_opcodes): Add new entries for UA2005
	292	window handling and rdhpr/wrhpr instructions.
	293
6772dd07 DD	294	2006-02-24 DJ Delorie <dj@redhat.com>
	295
	296	* m32c-desc.c: Regenerate with linker relaxation attributes.
	297	* m32c-desc.h: Likewise.
	298	* m32c-dis.c: Likewise.
	299	* m32c-opc.c: Likewise.
	300
62b3e311 PB	301	2006-02-24 Paul Brook <paul@codesourcery.com>
	302
	303	* arm-dis.c (arm_opcodes): Add V7 instructions.
	304	(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
	305	(print_arm_address): New function.
	306	(print_insn_arm): Use it. Add 'P' and 'U' cases.
	307	(psr_name): New function.
	308	(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
	309
59cf82fe L	310	2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
	311
	312	* ia64-opc-i.c (bXc): New.
	313	(mXc): Likewise.
	314	(OpX2TaTbYaXcC): Likewise.
	315	(TF). Likewise.
	316	(TFCM). Likewise.
	317	(ia64_opcodes_i): Add instructions for tf.
	318
	319	* ia64-opc.h (IMMU5b): New.
	320
	321	* ia64-asmtab.c: Regenerated.
	322
19a7219f L	323	2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
	324
	325	* ia64-gen.c: Update copyright years.
	326	* ia64-opc-b.c: Likewise.
	327
7f3dfb9c L	328	2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
	329
	330	* ia64-gen.c (lookup_regindex): Handle ".vm".
	331	(print_dependency_table): Handle '\"'.
	332
	333	* ia64-ic.tbl: Updated from SDM 2.2.
	334	* ia64-raw.tbl: Likewise.
	335	* ia64-waw.tbl: Likewise.
	336	* ia64-asmtab.c: Regenerated.
	337
	338	* ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
	339
d70c5fc7 NC	340	2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
	341	Anil Paranjape <anilp1@kpitcummins.com>
	342	Shilin Shakti <shilins@kpitcummins.com>
	343
	344	* xc16x-desc.h: New file
	345	* xc16x-desc.c: New file
	346	* xc16x-opc.h: New file
	347	* xc16x-opc.c: New file
	348	* xc16x-ibld.c: New file
	349	* xc16x-asm.c: New file
	350	* xc16x-dis.c: New file
	351	* Makefile.am: Entries for xc16x
	352	* Makefile.in: Regenerate
	353	* cofigure.in: Add xc16x target information.
	354	* configure: Regenerate.
	355	* disassemble.c: Add xc16x target information.
	356
a1cfb73e L	357	2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
	358
	359	* i386-dis.c (dis386_twobyte): Use "movZ" for debug register
	360	moves.
	361
6dd5059a L	362	2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
	363
	364	* i386-dis.c ('Z'): Add a new macro.
	365	(dis386_twobyte): Use "movZ" for control register moves.
	366
8536c657 NC	367	2006-02-10 Nick Clifton <nickc@redhat.com>
	368
	369	* iq2000-asm.c: Regenerate.
	370
266abb8f NS	371	2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
	372
	373	* m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
	374
f1a64f49 DU	375	2006-01-26 David Ung <davidu@mips.com>
	376
	377	* mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
	378	ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
	379	floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
	380	nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
	381	rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
	382
9e919b5f AM	383	2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
	384
	385	* z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
	386	ld_d_r, pref_xd_cb): Use signed char to hold data to be
	387	disassembled.
	388	* z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
	389	buffer overflows when disassembling instructions like
	390	ld (ix+123),0x23
	391	* z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
	392	operand, if the offset is negative.
	393
c9021189 AM	394	2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
	395
	396	* z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
	397	unsigned char to hold data to be disassembled.
	398
d99b6465 AS	399	2006-01-17 Andreas Schwab <schwab@suse.de>
	400
	401	PR binutils/1486
	402	* disassemble.c (disassemble_init_for_target): Set
	403	disassembler_needs_relocs for bfd_arch_arm.
	404
c2fe9327 PB	405	2006-01-16 Paul Brook <paul@codesourcery.com>
c2fe9327 PB	406
e88d958a	407	* m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
c2fe9327 PB	408	f?add?, and f?sub? instructions.
c2fe9327 PB	409
32fba81d NC	410	2006-01-16 Nick Clifton <nickc@redhat.com>
	411
	412	* po/zh_CN.po: New Chinese (simplified) translation.
	413	* configure.in (ALL_LINGUAS): Add "zh_CH".
	414	* configure: Regenerate.
	415
1b3a26b5 PB	416	2006-01-05 Paul Brook <paul@codesourcery.com>
	417
	418	* m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
	419
db313fa6 DD	420	2006-01-06 DJ Delorie <dj@redhat.com>
	421
	422	* m32c-desc.c: Regenerate.
	423	* m32c-opc.c: Regenerate.
	424	* m32c-opc.h: Regenerate.
	425
54d46aca DD	426	2006-01-03 DJ Delorie <dj@redhat.com>
	427
	428	* cgen-ibld.in (extract_normal): Avoid memory range errors.
	429	* m32c-ibld.c: Regenerated.
	430
e88d958a	431	For older changes see ChangeLog-2005
252b5132 RH	432	\f
252b5132 RH	433	Local Variables:
2f6d2f85 NC	434	mode: change-log
	435	left-margin: 8
	436	fill-column: 74
252b5132 RH	437	version-control: never
252b5132 RH	438	End: