projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i386: Reformat OP_E_memory
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
5074ad8a
L		 12018-09-14 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-dis.c (OP_E_memory): Reformat.
4
556059dd
JB		 52018-09-14 Jan Beulich <jbeulich@suse.com>
6
7 * i386-opc.tbl (crc32): Fold byte and word forms.
8 * i386-tbl.h: Re-generate.
9
41d1ab6a
L		 102018-09-13 H.J. Lu <hongjiu.lu@intel.com>
11
12 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
13 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
14 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
15 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
16 * i386-tbl.h: Regenerated.
17
57f6375e
JB		 182018-09-13 Jan Beulich <jbeulich@suse.com>
19
20 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
21 meaningless.
22 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
23 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
24 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
25 * i386-tbl.h: Re-generate.
26
2589a7e5
JB		 272018-09-13 Jan Beulich <jbeulich@suse.com>
28
29 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
30 AVX512_4VNNIW insns.
31 * i386-tbl.h: Re-generate.
32
a760eb41
JB		 332018-09-13 Jan Beulich <jbeulich@suse.com>
34
35 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
36 meaningless.
37 * i386-tbl.h: Re-generate.
38
e9042658
JB		 392018-09-13 Jan Beulich <jbeulich@suse.com>
40
41 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
42 meaningless.
43 * i386-tbl.h: Re-generate.
44
9caa306f
JB		 452018-09-13 Jan Beulich <jbeulich@suse.com>
46
47 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
48 meaningless.
49 * i386-tbl.h: Re-generate.
50
fb6ce599
JB		 512018-09-13 Jan Beulich <jbeulich@suse.com>
52
53 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
54 meaningless.
55 * i386-tbl.h: Re-generate.
56
6a8da886
JB		 572018-09-13 Jan Beulich <jbeulich@suse.com>
58
59 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
60 meaningless.
61 * i386-tbl.h: Re-generate.
62
c7f27919
JB		 632018-09-13 Jan Beulich <jbeulich@suse.com>
64
65 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
66 * i386-tbl.h: Re-generate.
67
0f407ee9
JB		 682018-09-13 Jan Beulich <jbeulich@suse.com>
69
70 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
71 * i386-tbl.h: Re-generate.
72
2fbbbee5
JB		 732018-09-13 Jan Beulich <jbeulich@suse.com>
74
75 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
76 meaningless.
77 * i386-tbl.h: Re-generate.
78
2b02b9a2
JB		 792018-09-13 Jan Beulich <jbeulich@suse.com>
80
81 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
82 meaningless.
83 * i386-tbl.h: Re-generate.
84
963c68aa
JB		 852018-09-13 Jan Beulich <jbeulich@suse.com>
86
87 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
88 * i386-tbl.h: Re-generate.
89
64e025c3
JB		 902018-09-13 Jan Beulich <jbeulich@suse.com>
91
92 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
93 * i386-tbl.h: Re-generate.
94
47603f88
JB		 952018-09-13 Jan Beulich <jbeulich@suse.com>
96
97 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
98 * i386-tbl.h: Re-generate.
99
0001cfd0
JB		 1002018-09-13 Jan Beulich <jbeulich@suse.com>
101
102 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
103 meaningless.
104 * i386-tbl.h: Re-generate.
105
be4b452e
JB		 1062018-09-13 Jan Beulich <jbeulich@suse.com>
107
108 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
109 meaningless.
110 * i386-tbl.h: Re-generate.
111
d09a1394
JB		 1122018-09-13 Jan Beulich <jbeulich@suse.com>
113
114 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
115 meaningless.
116 * i386-tbl.h: Re-generate.
117
07599e13
JB		 1182018-09-13 Jan Beulich <jbeulich@suse.com>
119
120 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
121 * i386-tbl.h: Re-generate.
122
1ee3e487
JB		 1232018-09-13 Jan Beulich <jbeulich@suse.com>
124
125 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
126 * i386-tbl.h: Re-generate.
127
a5f580e5
JB		 1282018-09-13 Jan Beulich <jbeulich@suse.com>
129
130 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
131 * i386-tbl.h: Re-generate.
132
49d5d12d
JB		 1332018-09-13 Jan Beulich <jbeulich@suse.com>
134
135 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
136 (vpbroadcastw, rdpid): Drop NoRex64.
137 * i386-tbl.h: Re-generate.
138
f5eb1d70
JB		 1392018-09-13 Jan Beulich <jbeulich@suse.com>
140
141 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
142 store templates, adding D.
143 * i386-tbl.h: Re-generate.
144
dbbc8b7e
JB		 1452018-09-13 Jan Beulich <jbeulich@suse.com>
146
147 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
148 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
149 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
150 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
151 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
152 Fold load and store templates where possible, adding D. Drop
153 IgnoreSize where it was pointlessly present. Drop redundant
154 *word.
155 * i386-tbl.h: Re-generate.
156
d276ec69
JB		 1572018-09-13 Jan Beulich <jbeulich@suse.com>
158
159 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
160 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
161 (intel_operand_size): Handle v_bndmk_mode.
162 (OP_E_memory): Likewise. Produce (bad) when also riprel.
163
9da4dfd6
JD		 1642018-09-08 John Darrington <john@darrington.wattle.id.au>
165
166 * disassemble.c (ARCH_s12z): Define if ARCH_all.
167
be192bc2
JW		 1682018-08-31 Kito Cheng <kito@andestech.com>
169
170 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
171 compressed floating point instructions.
172
43135d3b
JW		 1732018-08-30 Kito Cheng <kito@andestech.com>
174
175 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
176 riscv_opcode.xlen_requirement.
177 * riscv-opc.c (riscv_opcodes): Update for struct change.
178
df28970f
MA		 1792018-08-29 Martin Aberg <maberg@gaisler.com>
180
181 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
182 psr (PWRPSR) instruction.
183
9108bc33
CX		 1842018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
185
186 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
187
bd782c07
CX		 1882018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
189
190 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
191
ac8cb70f
CX		 1922018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
193
194 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
195 loongson3a as an alias of gs464 for compatibility.
196 * mips-opc.c (mips_opcodes): Change Comments.
197
a693765e
CX		 1982018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
199
200 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
201 option.
202 (print_mips_disassembler_options): Document -M loongson-ext.
203 * mips-opc.c (LEXT2): New macro.
204 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
205
bdc6c06e
CX		 2062018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
207
208 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
209 descriptors.
210 (parse_mips_ase_option): Handle -M loongson-ext option.
211 (print_mips_disassembler_options): Document -M loongson-ext.
212 * mips-opc.c (IL3A): Delete.
213 * mips-opc.c (LEXT): New macro.
214 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
215 instructions.
216
716c08de
CX		 2172018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
218
219 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
220 descriptors.
221 (parse_mips_ase_option): Handle -M loongson-cam option.
222 (print_mips_disassembler_options): Document -M loongson-cam.
223 * mips-opc.c (LCAM): New macro.
224 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
225 instructions.
226
9cf7e568
AM		 2272018-08-21 Alan Modra <amodra@gmail.com>
228
229 * ppc-dis.c (operand_value_powerpc): Init "invalid".
230 (skip_optional_operands): Count optional operands, and update
231 ppc_optional_operand_value call.
232 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
233 (extract_vlensi): Likewise.
234 (extract_fxm): Return default value for missing optional operand.
235 (extract_ls, extract_raq, extract_tbr): Likewise.
236 (insert_sxl, extract_sxl): New functions.
237 (insert_esync, extract_esync): Remove Power9 handling and simplify.
238 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
239 flag and extra entry.
240 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
241 extract_sxl.
242
d203b41a 2432018-08-20 Alan Modra <amodra@gmail.com>
f4107842 244
d203b41a 245 * sh-opc.h (MASK): Simplify.
f4107842 246
08a8fe2f 2472018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 248
d203b41a
AM		 249 * s12z-dis.c (bm_decode): Deal with cases where the mode is
250 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 251 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 252
08a8fe2f 2532018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 254
255 * s12z.h: Delete.
7ba3ba91 256
1bc60e56
L		 2572018-08-14 H.J. Lu <hongjiu.lu@intel.com>
258
259 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
260 address with the addr32 prefix and without base nor index
261 registers.
262
d871f3f4
L		 2632018-08-11 H.J. Lu <hongjiu.lu@intel.com>
264
265 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
266 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
267 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
268 (cpu_flags): Add CpuCMOV and CpuFXSR.
269 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
270 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
271 * i386-init.h: Regenerated.
272 * i386-tbl.h: Likewise.
273
b6523c37 2742018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
275
276 * arc-regs.h: Update auxiliary registers.
277
e968fc9b
JB		 2782018-08-06 Jan Beulich <jbeulich@suse.com>
279
280 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
281 (RegIP, RegIZ): Define.
282 * i386-reg.tbl: Adjust comments.
283 (rip): Use Qword instead of BaseIndex. Use RegIP.
284 (eip): Use Dword instead of BaseIndex. Use RegIP.
285 (riz): Add Qword. Use RegIZ.
286 (eiz): Add Dword. Use RegIZ.
287 * i386-tbl.h: Re-generate.
288
dbf8be89
JB		 2892018-08-03 Jan Beulich <jbeulich@suse.com>
290
291 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
292 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
293 vpmovzxdq, vpmovzxwd): Remove NoRex64.
294 * i386-tbl.h: Re-generate.
295
c48dadc9
JB		 2962018-08-03 Jan Beulich <jbeulich@suse.com>
297
298 * i386-gen.c (operand_types): Remove Mem field.
299 * i386-opc.h (union i386_operand_type): Remove mem field.
300 * i386-init.h, i386-tbl.h: Re-generate.
301
cb86a42a
AM		 3022018-08-01 Alan Modra <amodra@gmail.com>
303
304 * po/POTFILES.in: Regenerate.
305
07cc0450
NC		 3062018-07-31 Nick Clifton <nickc@redhat.com>
307
308 * po/sv.po: Updated Swedish translation.
309
1424ad86
JB		 3102018-07-31 Jan Beulich <jbeulich@suse.com>
311
312 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
313 * i386-init.h, i386-tbl.h: Re-generate.
314
ae2387fe
JB		 3152018-07-31 Jan Beulich <jbeulich@suse.com>
316
317 * i386-opc.h (ZEROING_MASKING) Rename to ...
318 (DYNAMIC_MASKING): ... this. Adjust comment.
319 * i386-opc.tbl (MaskingMorZ): Define.
320 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
321 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
322 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
323 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
324 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
325 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
326 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
327 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
328 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
329
6ff00b5e
JB		 3302018-07-31 Jan Beulich <jbeulich@suse.com>
331
332 * i386-opc.tbl: Use element rather than vector size for AVX512*
333 scatter/gather insns.
334 * i386-tbl.h: Re-generate.
335
e951d5ca
JB		 3362018-07-31 Jan Beulich <jbeulich@suse.com>
337
338 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
339 (cpu_flags): Drop CpuVREX.
340 * i386-opc.h (CpuVREX): Delete.
341 (union i386_cpu_flags): Remove cpuvrex.
342 * i386-init.h, i386-tbl.h: Re-generate.
343
eb41b248
JW		 3442018-07-30 Jim Wilson <jimw@sifive.com>
345
346 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
347 fields.
348 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
349
b8891f8d
AJ		 3502018-07-30 Andrew Jenner <andrew@codesourcery.com>
351
352 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
353 * Makefile.in: Regenerated.
354 * configure.ac: Add C-SKY.
355 * configure: Regenerated.
356 * csky-dis.c: New file.
357 * csky-opc.h: New file.
358 * disassemble.c (ARCH_csky): Define.
359 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
360 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
361
16065af1
AM		 3622018-07-27 Alan Modra <amodra@gmail.com>
363
364 * ppc-opc.c (insert_sprbat): Correct function parameter and
365 return type.
366 (extract_sprbat): Likewise, variable too.
367
fa758a70
AC		 3682018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
369 Alan Modra <amodra@gmail.com>
370
371 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
372 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
373 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
374 support disjointed BAT.
375 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
376 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
377 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
378
4a1b91ea
L		 3792018-07-25 H.J. Lu <hongjiu.lu@intel.com>
380 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
381
382 * i386-gen.c (adjust_broadcast_modifier): New function.
383 (process_i386_opcode_modifier): Add an argument for operands.
384 Adjust the Broadcast value based on operands.
385 (output_i386_opcode): Pass operand_types to
386 process_i386_opcode_modifier.
387 (process_i386_opcodes): Pass NULL as operands to
388 process_i386_opcode_modifier.
389 * i386-opc.h (BYTE_BROADCAST): New.
390 (WORD_BROADCAST): Likewise.
391 (DWORD_BROADCAST): Likewise.
392 (QWORD_BROADCAST): Likewise.
393 (i386_opcode_modifier): Expand broadcast to 3 bits.
394 * i386-tbl.h: Regenerated.
395
67ce483b
AM		 3962018-07-24 Alan Modra <amodra@gmail.com>
397
398 PR 23430
399 * or1k-desc.h: Regenerate.
400
4174bfff
JB		 4012018-07-24 Jan Beulich <jbeulich@suse.com>
402
403 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
404 vcvtusi2ss, and vcvtusi2sd.
405 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
406 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
407 * i386-tbl.h: Re-generate.
408
04e65276
CZ		 4092018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
410
411 * arc-opc.c (extract_w6): Fix extending the sign.
412
47e6f81c
CZ		 4132018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
414
415 * arc-tbl.h (vewt): Allow it for ARC EM family.
416
bb71536f
AM		 4172018-07-23 Alan Modra <amodra@gmail.com>
418
419 PR 23419
420 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
421 opcode variants for mtspr/mfspr encodings.
422
8095d2f7
CX		 4232018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
424 Maciej W. Rozycki <macro@mips.com>
425
426 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
427 loongson3a descriptors.
428 (parse_mips_ase_option): Handle -M loongson-mmi option.
429 (print_mips_disassembler_options): Document -M loongson-mmi.
430 * mips-opc.c (LMMI): New macro.
431 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
432 instructions.
433
5f32791e
JB		 4342018-07-19 Jan Beulich <jbeulich@suse.com>
435
436 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
437 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
438 IgnoreSize and [XYZ]MMword where applicable.
439 * i386-tbl.h: Re-generate.
440
625cbd7a
JB		 4412018-07-19 Jan Beulich <jbeulich@suse.com>
442
443 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
444 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
445 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
446 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
447 * i386-tbl.h: Re-generate.
448
86b15c32
JB		 4492018-07-19 Jan Beulich <jbeulich@suse.com>
450
451 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
452 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
453 VPCLMULQDQ templates into their respective AVX512VL counterparts
454 where possible, using Disp8ShiftVL and CheckRegSize instead of
455 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
456 * i386-tbl.h: Re-generate.
457
cf769ed5
JB		 4582018-07-19 Jan Beulich <jbeulich@suse.com>
459
460 * i386-opc.tbl: Fold AVX512DQ templates into their respective
461 AVX512VL counterparts where possible, using Disp8ShiftVL and
462 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
463 IgnoreSize) as appropriate.
464 * i386-tbl.h: Re-generate.
465
8282b7ad
JB		 4662018-07-19 Jan Beulich <jbeulich@suse.com>
467
468 * i386-opc.tbl: Fold AVX512BW templates into their respective
469 AVX512VL counterparts where possible, using Disp8ShiftVL and
470 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
471 IgnoreSize) as appropriate.
472 * i386-tbl.h: Re-generate.
473
755908cc
JB		 4742018-07-19 Jan Beulich <jbeulich@suse.com>
475
476 * i386-opc.tbl: Fold AVX512CD templates into their respective
477 AVX512VL counterparts where possible, using Disp8ShiftVL and
478 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
479 IgnoreSize) as appropriate.
480 * i386-tbl.h: Re-generate.
481
7091c612
JB		 4822018-07-19 Jan Beulich <jbeulich@suse.com>
483
484 * i386-opc.h (DISP8_SHIFT_VL): New.
485 * i386-opc.tbl (Disp8ShiftVL): Define.
486 (various): Fold AVX512VL templates into their respective
487 AVX512F counterparts where possible, using Disp8ShiftVL and
488 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
489 IgnoreSize) as appropriate.
490 * i386-tbl.h: Re-generate.
491
c30be56e
JB		 4922018-07-19 Jan Beulich <jbeulich@suse.com>
493
494 * Makefile.am: Change dependencies and rule for
495 $(srcdir)/i386-init.h.
496 * Makefile.in: Re-generate.
497 * i386-gen.c (process_i386_opcodes): New local variable
498 "marker". Drop opening of input file. Recognize marker and line
499 number directives.
500 * i386-opc.tbl (OPCODE_I386_H): Define.
501 (i386-opc.h): Include it.
502 (None): Undefine.
503
11a322db
L		 5042018-07-18 H.J. Lu <hongjiu.lu@intel.com>
505
506 PR gas/23418
507 * i386-opc.h (Byte): Update comments.
508 (Word): Likewise.
509 (Dword): Likewise.
510 (Fword): Likewise.
511 (Qword): Likewise.
512 (Tbyte): Likewise.
513 (Xmmword): Likewise.
514 (Ymmword): Likewise.
515 (Zmmword): Likewise.
516 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
517 vcvttps2uqq.
518 * i386-tbl.h: Regenerated.
519
cde3679e
NC		 5202018-07-12 Sudakshina Das <sudi.das@arm.com>
521
522 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
523 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
524 * aarch64-asm-2.c: Regenerate.
525 * aarch64-dis-2.c: Regenerate.
526 * aarch64-opc-2.c: Regenerate.
527
45a28947
TC		 5282018-07-12 Tamar Christina <tamar.christina@arm.com>
529
530 PR binutils/23192
531 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
532 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
533 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
534 sqdmulh, sqrdmulh): Use Em16.
535
c597cc3d
SD		 5362018-07-11 Sudakshina Das <sudi.das@arm.com>
537
538 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
539 csdb together with them.
540 (thumb32_opcodes): Likewise.
541
a79eaed6
JB		 5422018-07-11 Jan Beulich <jbeulich@suse.com>
543
544 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
545 requiring 32-bit registers as operands 2 and 3. Improve
546 comments.
547 (mwait, mwaitx): Fold templates. Improve comments.
548 OPERAND_TYPE_INOUTPORTREG.
549 * i386-tbl.h: Re-generate.
550
2fb5be8d
JB		 5512018-07-11 Jan Beulich <jbeulich@suse.com>
552
553 * i386-gen.c (operand_type_init): Remove
554 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
555 OPERAND_TYPE_INOUTPORTREG.
556 * i386-init.h: Re-generate.
557
7f5cad30
JB		 5582018-07-11 Jan Beulich <jbeulich@suse.com>
559
560 * i386-opc.tbl (wrssd, wrussd): Add Dword.
561 (wrssq, wrussq): Add Qword.
562 * i386-tbl.h: Re-generate.
563
f0a85b07
JB		 5642018-07-11 Jan Beulich <jbeulich@suse.com>
565
566 * i386-opc.h: Rename OTMax to OTNum.
567 (OTNumOfUints): Adjust calculation.
568 (OTUnused): Directly alias to OTNum.
569
9dcb0ba4
MR		 5702018-07-09 Maciej W. Rozycki <macro@mips.com>
571
572 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
573 `reg_xys'.
574 (lea_reg_xys): Likewise.
575 (print_insn_loop_primitive): Rename `reg' local variable to
576 `reg_dxy'.
577
f311ba7e
TC		 5782018-07-06 Tamar Christina <tamar.christina@arm.com>
579
580 PR binutils/23242
581 * aarch64-tbl.h (ldarh): Fix disassembly mask.
582
cba05feb
TC		 5832018-07-06 Tamar Christina <tamar.christina@arm.com>
584
585 PR binutils/23369
586 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
587 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
588
471b9d15
MR		 5892018-07-02 Maciej W. Rozycki <macro@mips.com>
590
591 PR tdep/8282
592 * mips-dis.c (mips_option_arg_t): New enumeration.
593 (mips_options): New variable.
594 (disassembler_options_mips): New function.
595 (print_mips_disassembler_options): Reimplement in terms of
596 `disassembler_options_mips'.
597 * arm-dis.c (disassembler_options_arm): Adapt to using the
598 `disasm_options_and_args_t' structure.
599 * ppc-dis.c (disassembler_options_powerpc): Likewise.
600 * s390-dis.c (disassembler_options_s390): Likewise.
601
c0c468d5
TP		 6022018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
603
604 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
605 expected result.
606 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
607 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
608 * testsuite/ld-arm/tls-longplt.d: Likewise.
609
369c9167
TC		 6102018-06-29 Tamar Christina <tamar.christina@arm.com>
611
612 PR binutils/23192
613 * aarch64-asm-2.c: Regenerate.
614 * aarch64-dis-2.c: Likewise.
615 * aarch64-opc-2.c: Likewise.
616 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
617 * aarch64-opc.c (operand_general_constraint_met_p,
618 aarch64_print_operand): Likewise.
619 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
620 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
621 fmlal2, fmlsl2.
622 (AARCH64_OPERANDS): Add Em2.
623
30aa1306
NC		 6242018-06-26 Nick Clifton <nickc@redhat.com>
625
626 * po/uk.po: Updated Ukranian translation.
627 * po/de.po: Updated German translation.
628 * po/pt_BR.po: Updated Brazilian Portuguese translation.
629
eca4b721
NC		 6302018-06-26 Nick Clifton <nickc@redhat.com>
631
632 * nfp-dis.c: Fix spelling mistake.
633
71300e2c
NC		 6342018-06-24 Nick Clifton <nickc@redhat.com>
635
636 * configure: Regenerate.
637 * po/opcodes.pot: Regenerate.
638
719d8288
NC		 6392018-06-24 Nick Clifton <nickc@redhat.com>
640
641 2.31 branch created.
642
514cd3a0
TC		 6432018-06-19 Tamar Christina <tamar.christina@arm.com>
644
645 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
646 * aarch64-asm-2.c: Regenerate.
647 * aarch64-dis-2.c: Likewise.
648
385e4d0f
MR		 6492018-06-21 Maciej W. Rozycki <macro@mips.com>
650
651 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
652 `-M ginv' option description.
653
160d1b3d
SH		 6542018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
655
656 PR gas/23305
657 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
658 la and lla.
659
d0ac1c44
SM		 6602018-06-19 Simon Marchi <simon.marchi@ericsson.com>
661
662 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
663 * configure.ac: Remove AC_PREREQ.
664 * Makefile.in: Re-generate.
665 * aclocal.m4: Re-generate.
666 * configure: Re-generate.
667
6f20c942
FS		 6682018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
669
670 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
671 mips64r6 descriptors.
672 (parse_mips_ase_option): Handle -Mginv option.
673 (print_mips_disassembler_options): Document -Mginv.
674 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
675 (GINV): New macro.
676 (mips_opcodes): Define ginvi and ginvt.
677
730c3174
SE		 6782018-06-13 Scott Egerton <scott.egerton@imgtec.com>
679 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
680
681 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
682 * mips-opc.c (CRC, CRC64): New macros.
683 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
684 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
685 crc32cd for CRC64.
686
cb366992
EB		 6872018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
688
689 PR 20319
690 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
691 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
692
ce72cd46
AM		 6932018-06-06 Alan Modra <amodra@gmail.com>
694
695 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
696 setjmp. Move init for some other vars later too.
697
4b8e28c7
MF		 6982018-06-04 Max Filippov <jcmvbkbc@gmail.com>
699
700 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
701 (dis_private): Add new fields for property section tracking.
702 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
703 (xtensa_instruction_fits): New functions.
704 (fetch_data): Bump minimal fetch size to 4.
705 (print_insn_xtensa): Make struct dis_private static.
706 Load and prepare property table on section change.
707 Don't disassemble literals. Don't disassemble instructions that
708 cross property table boundaries.
709
55e99962
L		 7102018-06-01 H.J. Lu <hongjiu.lu@intel.com>
711
712 * configure: Regenerated.
713
733bd0ab
JB		 7142018-06-01 Jan Beulich <jbeulich@suse.com>
715
716 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
717 * i386-tbl.h: Re-generate.
718
dfd27d41
JB		 7192018-06-01 Jan Beulich <jbeulich@suse.com>
720
721 * i386-opc.tbl (sldt, str): Add NoRex64.
722 * i386-tbl.h: Re-generate.
723
64795710
JB		 7242018-06-01 Jan Beulich <jbeulich@suse.com>
725
726 * i386-opc.tbl (invpcid): Add Oword.
727 * i386-tbl.h: Re-generate.
728
030157d8
AM		 7292018-06-01 Alan Modra <amodra@gmail.com>
730
731 * sysdep.h (_bfd_error_handler): Don't declare.
732 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
733 * rl78-decode.opc: Likewise.
734 * msp430-decode.c: Regenerate.
735 * rl78-decode.c: Regenerate.
736
a9660a6f
AP		 7372018-05-30 Amit Pawar <Amit.Pawar@amd.com>
738
739 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
740 * i386-init.h : Regenerated.
741
277eb7f6
AM		 7422018-05-25 Alan Modra <amodra@gmail.com>
743
744 * Makefile.in: Regenerate.
745 * po/POTFILES.in: Regenerate.
746
98553ad3
PB		 7472018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
748
749 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
750 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
751 (insert_bab, extract_bab, insert_btab, extract_btab,
752 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
753 (BAT, BBA VBA RBS XB6S): Delete macros.
754 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
755 (BB, BD, RBX, XC6): Update for new macros.
756 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
757 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
758 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
759 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
760
7b4ae824
JD		 7612018-05-18 John Darrington <john@darrington.wattle.id.au>
762
763 * Makefile.am: Add support for s12z architecture.
764 * configure.ac: Likewise.
765 * disassemble.c: Likewise.
766 * disassemble.h: Likewise.
767 * Makefile.in: Regenerate.
768 * configure: Regenerate.
769 * s12z-dis.c: New file.
770 * s12z.h: New file.
771
29e0f0a1
AM		 7722018-05-18 Alan Modra <amodra@gmail.com>
773
774 * nfp-dis.c: Don't #include libbfd.h.
775 (init_nfp3200_priv): Use bfd_get_section_contents.
776 (nit_nfp6000_mecsr_sec): Likewise.
777
809276d2
NC		 7782018-05-17 Nick Clifton <nickc@redhat.com>
779
780 * po/zh_CN.po: Updated simplified Chinese translation.
781
ff329288
TC		 7822018-05-16 Tamar Christina <tamar.christina@arm.com>
783
784 PR binutils/23109
785 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
786 * aarch64-dis-2.c: Regenerate.
787
f9830ec1
TC		 7882018-05-15 Tamar Christina <tamar.christina@arm.com>
789
790 PR binutils/21446
791 * aarch64-asm.c (opintl.h): Include.
792 (aarch64_ins_sysreg): Enforce read/write constraints.
793 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
794 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
795 (F_REG_READ, F_REG_WRITE): New.
796 * aarch64-opc.c (aarch64_print_operand): Generate notes for
797 AARCH64_OPND_SYSREG.
798 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
799 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
800 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
801 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
802 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
803 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
804 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
805 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
806 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
807 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
808 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
809 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
810 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
811 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
812 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
813 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
814 msr (F_SYS_WRITE), mrs (F_SYS_READ).
815
7d02540a
TC		 8162018-05-15 Tamar Christina <tamar.christina@arm.com>
817
818 PR binutils/21446
819 * aarch64-dis.c (no_notes: New.
820 (parse_aarch64_dis_option): Support notes.
821 (aarch64_decode_insn, print_operands): Likewise.
822 (print_aarch64_disassembler_options): Document notes.
823 * aarch64-opc.c (aarch64_print_operand): Support notes.
824
561a72d4
TC		 8252018-05-15 Tamar Christina <tamar.christina@arm.com>
826
827 PR binutils/21446
828 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
829 and take error struct.
830 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
831 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
832 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
833 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
834 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
835 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
836 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
837 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
838 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
839 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
840 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
841 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
842 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
843 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
844 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
845 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
846 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
847 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
848 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
849 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
850 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
851 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
852 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
853 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
854 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
855 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
856 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
857 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
858 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
859 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
860 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
861 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
862 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
863 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
864 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
865 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
866 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
867 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
868 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
869 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
870 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
871 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
872 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
873 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
874 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
875 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
876 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
877 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
878 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
879 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
880 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
881 (determine_disassembling_preference, aarch64_decode_insn,
882 print_insn_aarch64_word, print_insn_data): Take errors struct.
883 (print_insn_aarch64): Use errors.
884 * aarch64-asm-2.c: Regenerate.
885 * aarch64-dis-2.c: Regenerate.
886 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
887 boolean in aarch64_insert_operan.
888 (print_operand_extractor): Likewise.
889 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
890
1678bd35
FT		 8912018-05-15 Francois H. Theron <francois.theron@netronome.com>
892
893 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
894
06cfb1c8
L		 8952018-05-09 H.J. Lu <hongjiu.lu@intel.com>
896
897 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
898
84f9f8c3
AM		 8992018-05-09 Sebastian Rasmussen <sebras@gmail.com>
900
901 * cr16-opc.c (cr16_instruction): Comment typo fix.
902 * hppa-dis.c (print_insn_hppa): Likewise.
903
e6f372ba
JW		 9042018-05-08 Jim Wilson <jimw@sifive.com>
905
906 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
907 (match_c_slli64, match_srxi_as_c_srxi): New.
908 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
909 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
910 <c.slli, c.srli, c.srai>: Use match_s_slli.
911 <c.slli64, c.srli64, c.srai64>: New.
912
f413a913
AM		 9132018-05-08 Alan Modra <amodra@gmail.com>
914
915 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
916 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
917 partition opcode space for index lookup.
918
a87a6478
PB		 9192018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
920
921 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
922 <insn_length>: ...with this. Update usage.
923 Remove duplicate call to *info->memory_error_func.
924
c0a30a9f
L		 9252018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
926 H.J. Lu <hongjiu.lu@intel.com>
927
928 * i386-dis.c (Gva): New.
929 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
930 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
931 (prefix_table): New instructions (see prefix above).
932 (mod_table): New instructions (see prefix above).
933 (OP_G): Handle va_mode.
934 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
935 CPU_MOVDIR64B_FLAGS.
936 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
937 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
938 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
939 * i386-opc.tbl: Add movidir{i,64b}.
940 * i386-init.h: Regenerated.
941 * i386-tbl.h: Likewise.
942
75c0a438
L		 9432018-05-07 H.J. Lu <hongjiu.lu@intel.com>
944
945 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
946 AddrPrefixOpReg.
947 * i386-opc.h (AddrPrefixOp0): Renamed to ...
948 (AddrPrefixOpReg): This.
949 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
950 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
951
2ceb7719
PB		 9522018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
953
954 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
955 (vle_num_opcodes): Likewise.
956 (spe2_num_opcodes): Likewise.
957 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
958 initialization loop.
959 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
960 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
961 only once.
962
b3ac5c6c
TC		 9632018-05-01 Tamar Christina <tamar.christina@arm.com>
964
965 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
966
fe944acf
FT		 9672018-04-30 Francois H. Theron <francois.theron@netronome.com>
968
969 Makefile.am: Added nfp-dis.c.
970 configure.ac: Added bfd_nfp_arch.
971 disassemble.h: Added print_insn_nfp prototype.
972 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
973 nfp-dis.c: New, for NFP support.
974 po/POTFILES.in: Added nfp-dis.c to the list.
975 Makefile.in: Regenerate.
976 configure: Regenerate.
977
e2195274
JB		 9782018-04-26 Jan Beulich <jbeulich@suse.com>
979
980 * i386-opc.tbl: Fold various non-memory operand AVX512VL
981 templates into their base ones.
982 * i386-tlb.h: Re-generate.
983
59ef5df4
JB		 9842018-04-26 Jan Beulich <jbeulich@suse.com>
985
986 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
987 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
988 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
989 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
990 * i386-init.h: Re-generate.
991
6e041cf4
JB		 9922018-04-26 Jan Beulich <jbeulich@suse.com>
993
994 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
995 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
996 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
997 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
998 comment.
999 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1000 and CpuRegMask.
1001 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1002 CpuRegMask: Delete.
1003 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1004 cpuregzmm, and cpuregmask.
1005 * i386-init.h: Re-generate.
1006 * i386-tbl.h: Re-generate.
1007
0e0eea78
JB		 10082018-04-26 Jan Beulich <jbeulich@suse.com>
1009
1010 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1011 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1012 * i386-init.h: Re-generate.
1013
2f1bada2
JB		 10142018-04-26 Jan Beulich <jbeulich@suse.com>
1015
1016 * i386-gen.c (VexImmExt): Delete.
1017 * i386-opc.h (VexImmExt, veximmext): Delete.
1018 * i386-opc.tbl: Drop all VexImmExt uses.
1019 * i386-tlb.h: Re-generate.
1020
bacd1457
JB		 10212018-04-25 Jan Beulich <jbeulich@suse.com>
1022
1023 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1024 register-only forms.
1025 * i386-tlb.h: Re-generate.
1026
10bba94b
TC		 10272018-04-25 Tamar Christina <tamar.christina@arm.com>
1028
1029 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1030
c48935d7
IT		 10312018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1032
1033 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1034 PREFIX_0F1C.
1035 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1036 (cpu_flags): Add CpuCLDEMOTE.
1037 * i386-init.h: Regenerate.
1038 * i386-opc.h (enum): Add CpuCLDEMOTE,
1039 (i386_cpu_flags): Add cpucldemote.
1040 * i386-opc.tbl: Add cldemote.
1041 * i386-tbl.h: Regenerate.
1042
211dc24b
AM		 10432018-04-16 Alan Modra <amodra@gmail.com>
1044
1045 * Makefile.am: Remove sh5 and sh64 support.
1046 * configure.ac: Likewise.
1047 * disassemble.c: Likewise.
1048 * disassemble.h: Likewise.
1049 * sh-dis.c: Likewise.
1050 * sh64-dis.c: Delete.
1051 * sh64-opc.c: Delete.
1052 * sh64-opc.h: Delete.
1053 * Makefile.in: Regenerate.
1054 * configure: Regenerate.
1055 * po/POTFILES.in: Regenerate.
1056
a9a4b302
AM		 10572018-04-16 Alan Modra <amodra@gmail.com>
1058
1059 * Makefile.am: Remove w65 support.
1060 * configure.ac: Likewise.
1061 * disassemble.c: Likewise.
1062 * disassemble.h: Likewise.
1063 * w65-dis.c: Delete.
1064 * w65-opc.h: Delete.
1065 * Makefile.in: Regenerate.
1066 * configure: Regenerate.
1067 * po/POTFILES.in: Regenerate.
1068
04cb01fd
AM		 10692018-04-16 Alan Modra <amodra@gmail.com>
1070
1071 * configure.ac: Remove we32k support.
1072 * configure: Regenerate.
1073
c2bf1eec
AM		 10742018-04-16 Alan Modra <amodra@gmail.com>
1075
1076 * Makefile.am: Remove m88k support.
1077 * configure.ac: Likewise.
1078 * disassemble.c: Likewise.
1079 * disassemble.h: Likewise.
1080 * m88k-dis.c: Delete.
1081 * Makefile.in: Regenerate.
1082 * configure: Regenerate.
1083 * po/POTFILES.in: Regenerate.
1084
6793974d
AM		 10852018-04-16 Alan Modra <amodra@gmail.com>
1086
1087 * Makefile.am: Remove i370 support.
1088 * configure.ac: Likewise.
1089 * disassemble.c: Likewise.
1090 * disassemble.h: Likewise.
1091 * i370-dis.c: Delete.
1092 * i370-opc.c: Delete.
1093 * Makefile.in: Regenerate.
1094 * configure: Regenerate.
1095 * po/POTFILES.in: Regenerate.
1096
e82aa794
AM		 10972018-04-16 Alan Modra <amodra@gmail.com>
1098
1099 * Makefile.am: Remove h8500 support.
1100 * configure.ac: Likewise.
1101 * disassemble.c: Likewise.
1102 * disassemble.h: Likewise.
1103 * h8500-dis.c: Delete.
1104 * h8500-opc.h: Delete.
1105 * Makefile.in: Regenerate.
1106 * configure: Regenerate.
1107 * po/POTFILES.in: Regenerate.
1108
fceadf09
AM		 11092018-04-16 Alan Modra <amodra@gmail.com>
1110
1111 * configure.ac: Remove tahoe support.
1112 * configure: Regenerate.
1113
ae1d3843
L		 11142018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1115
1116 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1117 umwait.
1118 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1119 64-bit mode.
1120 * i386-tbl.h: Regenerated.
1121
de89d0a3
IT		 11222018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1123
1124 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1125 PREFIX_MOD_1_0FAE_REG_6.
1126 (va_mode): New.
1127 (OP_E_register): Use va_mode.
1128 * i386-dis-evex.h (prefix_table):
1129 New instructions (see prefixes above).
1130 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1131 (cpu_flags): Likewise.
1132 * i386-opc.h (enum): Likewise.
1133 (i386_cpu_flags): Likewise.
1134 * i386-opc.tbl: Add umonitor, umwait, tpause.
1135 * i386-init.h: Regenerate.
1136 * i386-tbl.h: Likewise.
1137
a8eb42a8
AM		 11382018-04-11 Alan Modra <amodra@gmail.com>
1139
1140 * opcodes/i860-dis.c: Delete.
1141 * opcodes/i960-dis.c: Delete.
1142 * Makefile.am: Remove i860 and i960 support.
1143 * configure.ac: Likewise.
1144 * disassemble.c: Likewise.
1145 * disassemble.h: Likewise.
1146 * Makefile.in: Regenerate.
1147 * configure: Regenerate.
1148 * po/POTFILES.in: Regenerate.
1149
caf0678c
L		 11502018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1151
1152 PR binutils/23025
1153 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1154 to 0.
1155 (print_insn): Clear vex instead of vex.evex.
1156
4fb0d2b9
NC		 11572018-04-04 Nick Clifton <nickc@redhat.com>
1158
1159 * po/es.po: Updated Spanish translation.
1160
c39e5b26
JB		 11612018-03-28 Jan Beulich <jbeulich@suse.com>
1162
1163 * i386-gen.c (opcode_modifiers): Delete VecESize.
1164 * i386-opc.h (VecESize): Delete.
1165 (struct i386_opcode_modifier): Delete vecesize.
1166 * i386-opc.tbl: Drop VecESize.
1167 * i386-tlb.h: Re-generate.
1168
8e6e0792
JB		 11692018-03-28 Jan Beulich <jbeulich@suse.com>
1170
1171 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1172 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1173 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1174 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1175 * i386-tlb.h: Re-generate.
1176
9f123b91
JB		 11772018-03-28 Jan Beulich <jbeulich@suse.com>
1178
1179 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1180 Fold AVX512 forms
1181 * i386-tlb.h: Re-generate.
1182
9646c87b
JB		 11832018-03-28 Jan Beulich <jbeulich@suse.com>
1184
1185 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1186 (vex_len_table): Drop Y for vcvt*2si.
1187 (putop): Replace plain 'Y' handling by abort().
1188
c8d59609
NC		 11892018-03-28 Nick Clifton <nickc@redhat.com>
1190
1191 PR 22988
1192 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1193 instructions with only a base address register.
1194 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1195 handle AARHC64_OPND_SVE_ADDR_R.
1196 (aarch64_print_operand): Likewise.
1197 * aarch64-asm-2.c: Regenerate.
1198 * aarch64_dis-2.c: Regenerate.
1199 * aarch64-opc-2.c: Regenerate.
1200
b8c169f3
JB		 12012018-03-22 Jan Beulich <jbeulich@suse.com>
1202
1203 * i386-opc.tbl: Drop VecESize from register only insn forms and
1204 memory forms not allowing broadcast.
1205 * i386-tlb.h: Re-generate.
1206
96bc132a
JB		 12072018-03-22 Jan Beulich <jbeulich@suse.com>
1208
1209 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1210 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1211 sha256*): Drop Disp<N>.
1212
9f79e886
JB		 12132018-03-22 Jan Beulich <jbeulich@suse.com>
1214
1215 * i386-dis.c (EbndS, bnd_swap_mode): New.
1216 (prefix_table): Use EbndS.
1217 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1218 * i386-opc.tbl (bndmov): Move misplaced Load.
1219 * i386-tlb.h: Re-generate.
1220
d6793fa1
JB		 12212018-03-22 Jan Beulich <jbeulich@suse.com>
1222
1223 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1224 templates allowing memory operands and folded ones for register
1225 only flavors.
1226 * i386-tlb.h: Re-generate.
1227
f7768225
JB		 12282018-03-22 Jan Beulich <jbeulich@suse.com>
1229
1230 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1231 256-bit templates. Drop redundant leftover Disp<N>.
1232 * i386-tlb.h: Re-generate.
1233
0e35537d
JW		 12342018-03-14 Kito Cheng <kito.cheng@gmail.com>
1235
1236 * riscv-opc.c (riscv_insn_types): New.
1237
b4a3689a
NC		 12382018-03-13 Nick Clifton <nickc@redhat.com>
1239
1240 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1241
d3d50934
L		 12422018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1243
1244 * i386-opc.tbl: Add Optimize to clr.
1245 * i386-tbl.h: Regenerated.
1246
bd5dea88
L		 12472018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1248
1249 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1250 * i386-opc.h (OldGcc): Removed.
1251 (i386_opcode_modifier): Remove oldgcc.
1252 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1253 instructions for old (<= 2.8.1) versions of gcc.
1254 * i386-tbl.h: Regenerated.
1255
e771e7c9
JB		 12562018-03-08 Jan Beulich <jbeulich@suse.com>
1257
1258 * i386-opc.h (EVEXDYN): New.
1259 * i386-opc.tbl: Fold various AVX512VL templates.
1260 * i386-tlb.h: Re-generate.
1261
ed438a93
JB		 12622018-03-08 Jan Beulich <jbeulich@suse.com>
1263
1264 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1265 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1266 vpexpandd, vpexpandq): Fold AFX512VF templates.
1267 * i386-tlb.h: Re-generate.
1268
454172a9
JB		 12692018-03-08 Jan Beulich <jbeulich@suse.com>
1270
1271 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1272 Fold 128- and 256-bit VEX-encoded templates.
1273 * i386-tlb.h: Re-generate.
1274
36824150
JB		 12752018-03-08 Jan Beulich <jbeulich@suse.com>
1276
1277 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1278 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1279 vpexpandd, vpexpandq): Fold AVX512F templates.
1280 * i386-tlb.h: Re-generate.
1281
e7f5c0a9
JB		 12822018-03-08 Jan Beulich <jbeulich@suse.com>
1283
1284 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1285 64-bit templates. Drop Disp<N>.
1286 * i386-tlb.h: Re-generate.
1287
25a4277f
JB		 12882018-03-08 Jan Beulich <jbeulich@suse.com>
1289
1290 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1291 and 256-bit templates.
1292 * i386-tlb.h: Re-generate.
1293
d2224064
JB		 12942018-03-08 Jan Beulich <jbeulich@suse.com>
1295
1296 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1297 * i386-tlb.h: Re-generate.
1298
1b193f0b
JB		 12992018-03-08 Jan Beulich <jbeulich@suse.com>
1300
1301 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1302 Drop NoAVX.
1303 * i386-tlb.h: Re-generate.
1304
f2f6a710
JB		 13052018-03-08 Jan Beulich <jbeulich@suse.com>
1306
1307 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1308 * i386-tlb.h: Re-generate.
1309
38e314eb
JB		 13102018-03-08 Jan Beulich <jbeulich@suse.com>
1311
1312 * i386-gen.c (opcode_modifiers): Delete FloatD.
1313 * i386-opc.h (FloatD): Delete.
1314 (struct i386_opcode_modifier): Delete floatd.
1315 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1316 FloatD by D.
1317 * i386-tlb.h: Re-generate.
1318
d53e6b98
JB		 13192018-03-08 Jan Beulich <jbeulich@suse.com>
1320
1321 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1322
2907c2f5
JB		 13232018-03-08 Jan Beulich <jbeulich@suse.com>
1324
1325 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1326 * i386-tlb.h: Re-generate.
1327
73053c1f
JB		 13282018-03-08 Jan Beulich <jbeulich@suse.com>
1329
1330 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1331 forms.
1332 * i386-tlb.h: Re-generate.
1333
52fe4420
AM		 13342018-03-07 Alan Modra <amodra@gmail.com>
1335
1336 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1337 bfd_arch_rs6000.
1338 * disassemble.h (print_insn_rs6000): Delete.
1339 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1340 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1341 (print_insn_rs6000): Delete.
1342
a6743a54
AM		 13432018-03-03 Alan Modra <amodra@gmail.com>
1344
1345 * sysdep.h (opcodes_error_handler): Define.
1346 (_bfd_error_handler): Declare.
1347 * Makefile.am: Remove stray #.
1348 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1349 EDIT" comment.
1350 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1351 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1352 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1353 opcodes_error_handler to print errors. Standardize error messages.
1354 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1355 and include opintl.h.
1356 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1357 * i386-gen.c: Standardize error messages.
1358 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1359 * Makefile.in: Regenerate.
1360 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1361 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1362 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1363 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1364 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1365 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1366 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1367 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1368 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1369 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1370 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1371 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1372 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1373
8305403a
L		 13742018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1375
1376 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1377 vpsub[bwdq] instructions.
1378 * i386-tbl.h: Regenerated.
1379
e184813f
AM		 13802018-03-01 Alan Modra <amodra@gmail.com>
1381
1382 * configure.ac (ALL_LINGUAS): Sort.
1383 * configure: Regenerate.
1384
5b616bef
TP		 13852018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1386
1387 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1388 macro by assignements.
1389
b6f8c7c4
L		 13902018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1391
1392 PR gas/22871
1393 * i386-gen.c (opcode_modifiers): Add Optimize.
1394 * i386-opc.h (Optimize): New enum.
1395 (i386_opcode_modifier): Add optimize.
1396 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1397 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1398 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1399 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1400 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1401 vpxord and vpxorq.
1402 * i386-tbl.h: Regenerated.
1403
e95b887f
AM		 14042018-02-26 Alan Modra <amodra@gmail.com>
1405
1406 * crx-dis.c (getregliststring): Allocate a large enough buffer
1407 to silence false positive gcc8 warning.
1408
0bccfb29
JW		 14092018-02-22 Shea Levy <shea@shealevy.com>
1410
1411 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1412
6b6b6807
L		 14132018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1414
1415 * i386-opc.tbl: Add {rex},
1416 * i386-tbl.h: Regenerated.
1417
75f31665
MR		 14182018-02-20 Maciej W. Rozycki <macro@mips.com>
1419
1420 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1421 (mips16_opcodes): Replace `M' with `m' for "restore".
1422
e207bc53
TP		 14232018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1424
1425 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1426
87993319
MR		 14272018-02-13 Maciej W. Rozycki <macro@mips.com>
1428
1429 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1430 variable to `function_index'.
1431
68d20676
NC		 14322018-02-13 Nick Clifton <nickc@redhat.com>
1433
1434 PR 22823
1435 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1436 about truncation of printing.
1437
d2159fdc
HW		 14382018-02-12 Henry Wong <henry@stuffedcow.net>
1439
1440 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1441
f174ef9f
NC		 14422018-02-05 Nick Clifton <nickc@redhat.com>
1443
1444 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1445
be3a8dca
IT		 14462018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1447
1448 * i386-dis.c (enum): Add pconfig.
1449 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1450 (cpu_flags): Add CpuPCONFIG.
1451 * i386-opc.h (enum): Add CpuPCONFIG.
1452 (i386_cpu_flags): Add cpupconfig.
1453 * i386-opc.tbl: Add PCONFIG instruction.
1454 * i386-init.h: Regenerate.
1455 * i386-tbl.h: Likewise.
1456
3233d7d0
IT		 14572018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1458
1459 * i386-dis.c (enum): Add PREFIX_0F09.
1460 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1461 (cpu_flags): Add CpuWBNOINVD.
1462 * i386-opc.h (enum): Add CpuWBNOINVD.
1463 (i386_cpu_flags): Add cpuwbnoinvd.
1464 * i386-opc.tbl: Add WBNOINVD instruction.
1465 * i386-init.h: Regenerate.
1466 * i386-tbl.h: Likewise.
1467
e925c834
JW		 14682018-01-17 Jim Wilson <jimw@sifive.com>
1469
1470 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1471
d777820b
IT		 14722018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1473
1474 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1475 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1476 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1477 (cpu_flags): Add CpuIBT, CpuSHSTK.
1478 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1479 (i386_cpu_flags): Add cpuibt, cpushstk.
1480 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1481 * i386-init.h: Regenerate.
1482 * i386-tbl.h: Likewise.
1483
f6efed01
NC		 14842018-01-16 Nick Clifton <nickc@redhat.com>
1485
1486 * po/pt_BR.po: Updated Brazilian Portugese translation.
1487 * po/de.po: Updated German translation.
1488
2721d702
JW		 14892018-01-15 Jim Wilson <jimw@sifive.com>
1490
1491 * riscv-opc.c (match_c_nop): New.
1492 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1493
616dcb87
NC		 14942018-01-15 Nick Clifton <nickc@redhat.com>
1495
1496 * po/uk.po: Updated Ukranian translation.
1497
3957a496
NC		 14982018-01-13 Nick Clifton <nickc@redhat.com>
1499
1500 * po/opcodes.pot: Regenerated.
1501
769c7ea5
NC		 15022018-01-13 Nick Clifton <nickc@redhat.com>
1503
1504 * configure: Regenerate.
1505
faf766e3
NC		 15062018-01-13 Nick Clifton <nickc@redhat.com>
1507
1508 2.30 branch created.
1509
888a89da
IT		 15102018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1511
1512 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1513 * i386-tbl.h: Regenerate.
1514
cbda583a
JB		 15152018-01-10 Jan Beulich <jbeulich@suse.com>
1516
1517 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1518 * i386-tbl.h: Re-generate.
1519
c9e92278
JB		 15202018-01-10 Jan Beulich <jbeulich@suse.com>
1521
1522 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1523 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1524 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1525 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1526 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1527 Disp8MemShift of AVX512VL forms.
1528 * i386-tbl.h: Re-generate.
1529
35fd2b2b
JW		 15302018-01-09 Jim Wilson <jimw@sifive.com>
1531
1532 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1533 then the hi_addr value is zero.
1534
91d8b670
JG		 15352018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1536
1537 * arm-dis.c (arm_opcodes): Add csdb.
1538 (thumb32_opcodes): Add csdb.
1539
be2e7d95
JG		 15402018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1541
1542 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1543 * aarch64-asm-2.c: Regenerate.
1544 * aarch64-dis-2.c: Regenerate.
1545 * aarch64-opc-2.c: Regenerate.
1546
704a705d
L		 15472018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1548
1549 PR gas/22681
1550 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1551 Remove AVX512 vmovd with 64-bit operands.
1552 * i386-tbl.h: Regenerated.
1553
35eeb78f
JW		 15542018-01-05 Jim Wilson <jimw@sifive.com>
1555
1556 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1557 jalr.
1558
219d1afa
AM		 15592018-01-03 Alan Modra <amodra@gmail.com>
1560
1561 Update year range in copyright notice of all files.
1562
1508bbf5
JB		 15632018-01-02 Jan Beulich <jbeulich@suse.com>
1564
1565 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1566 and OPERAND_TYPE_REGZMM entries.
1567
1e563868 1568For older changes see ChangeLog-2017
3499769a 1569\f
1e563868 1570Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1571
1572Copying and distribution of this file, with or without modification,
1573are permitted in any medium without royalty provided the copyright
1574notice and this notice are preserved.
1575
1576Local Variables:
1577mode: change-log
1578left-margin: 8
1579fill-column: 74
1580version-control: never
1581End:
GDB Binutils - Deliverables
This page took 0.212439 seconds and 4 git commands to generate.