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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
192c2bfb
JD		 12018-10-22 John Darrington <john@darrington.wattle.id.au>
2
3 * s12z-dis.c (decode_possible_symbol): Add fallback case.
4 (rel_15_7): Likewise.
5
0b347048
TC		 62018-10-19 Tamar Christina <tamar.christina@arm.com>
7
8 * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
9 (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
10 (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
11
66e6f0b7
MM		 122018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
13
14 * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
15 corresponding to AARCH64_OPND_QLF_S_4B qualifier.
16
673fe0f0
JB		 172018-10-10 Jan Beulich <jbeulich@suse.com>
18
19 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
20 Size64. Add Size.
21 * i386-opc.h (Size16, Size32, Size64): Delete.
22 (Size): New.
23 (SIZE16, SIZE32, SIZE64): Define.
24 (struct i386_opcode_modifier): Drop size16, size32, and size64.
25 Add size.
26 * i386-opc.tbl (Size16, Size32, Size64): Define.
27 * i386-tbl.h: Re-generate.
28
104fefee
SD		 292018-10-09 Sudakshina Das <sudi.das@arm.com>
30
31 * aarch64-opc.c (operand_general_constraint_met_p): Add
32 SSBS in the check for one-bit immediate.
33 (aarch64_sys_regs): New entry for SSBS.
34 (aarch64_sys_reg_supported_p): New check for above.
35 (aarch64_pstatefields): New entry for SSBS.
36 (aarch64_pstatefield_supported_p): New check for above.
37
a97330e7
SD		 382018-10-09 Sudakshina Das <sudi.das@arm.com>
39
40 * aarch64-opc.c (aarch64_sys_regs): New entries for
41 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
42 (aarch64_sys_reg_supported_p): New checks for above.
43
ff605452
SD		 442018-10-09 Sudakshina Das <sudi.das@arm.com>
45
46 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
47 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
48 with the hint immediate.
49 * aarch64-opc.c (aarch64_hint_options): New entries for
50 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
51 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
52 while checking for HINT_OPD_F_NOPRINT flag.
53 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
54 extract value.
55 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
56 (aarch64_opcode_table): Add entry for BTI.
57 (AARCH64_OPERANDS): Add new description for BTI targets.
58 * aarch64-asm-2.c: Regenerate.
59 * aarch64-dis-2.c: Regenerate.
60 * aarch64-opc-2.c: Regenerate.
61
af4bcb4c
SD		 622018-10-09 Sudakshina Das <sudi.das@arm.com>
63
64 * aarch64-opc.c (aarch64_sys_regs): New entries for
65 rndr and rndrrs.
66 (aarch64_sys_reg_supported_p): New check for above.
67
3fd229a4
SD		 682018-10-09 Sudakshina Das <sudi.das@arm.com>
69
70 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
71 (aarch64_sys_ins_reg_supported_p): New check for above.
72
2ac435d4
SD		 732018-10-09 Sudakshina Das <sudi.das@arm.com>
74
75 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
76 AARCH64_OPND_SYSREG_SR.
77 * aarch64-opc.c (aarch64_print_operand): Likewise.
78 (aarch64_sys_regs_sr): Define table.
79 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
80 AARCH64_FEATURE_PREDRES.
81 * aarch64-tbl.h (aarch64_feature_predres): New.
82 (PREDRES, PREDRES_INSN): New.
83 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
84 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
85 * aarch64-asm-2.c: Regenerate.
86 * aarch64-dis-2.c: Regenerate.
87 * aarch64-opc-2.c: Regenerate.
88
68dfbb92
SD		 892018-10-09 Sudakshina Das <sudi.das@arm.com>
90
91 * aarch64-tbl.h (aarch64_feature_sb): New.
92 (SB, SB_INSN): New.
93 (aarch64_opcode_table): Add entry for sb.
94 * aarch64-asm-2.c: Regenerate.
95 * aarch64-dis-2.c: Regenerate.
96 * aarch64-opc-2.c: Regenerate.
97
13c60ad7
SD		 982018-10-09 Sudakshina Das <sudi.das@arm.com>
99
100 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
101 (aarch64_feature_frintts): New.
102 (FLAGMANIP, FRINTTS): New.
103 (aarch64_opcode_table): Add entries for xaflag, axflag
104 and frint[32,64][x,z] instructions.
105 * aarch64-asm-2.c: Regenerate.
106 * aarch64-dis-2.c: Regenerate.
107 * aarch64-opc-2.c: Regenerate.
108
70d56181
SD		 1092018-10-09 Sudakshina Das <sudi.das@arm.com>
110
111 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
112 (ARMV8_5, V8_5_INSN): New.
113
780f601c
TC		 1142018-10-08 Tamar Christina <tamar.christina@arm.com>
115
116 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
117
a4e78aa5
L		 1182018-10-05 H.J. Lu <hongjiu.lu@intel.com>
119
120 * i386-dis.c (rm_table): Add enclv.
121 * i386-opc.tbl: Add enclv.
122 * i386-tbl.h: Regenerated.
123
7fadb25d
SD		 1242018-10-05 Sudakshina Das <sudi.das@arm.com>
125
126 * arm-dis.c (arm_opcodes): Add sb.
127 (thumb32_opcodes): Likewise.
128
07f5f4c6
RH		 1292018-10-05 Richard Henderson <rth@twiddle.net>
130 Stafford Horne <shorne@gmail.com>
131
132 * or1k-desc.c: Regenerate.
133 * or1k-desc.h: Regenerate.
134 * or1k-opc.c: Regenerate.
135 * or1k-opc.h: Regenerate.
136 * or1k-opinst.c: Regenerate.
137
c8e98e36
SH		 1382018-10-05 Richard Henderson <rth@twiddle.net>
139
140 * or1k-asm.c: Regenerated.
141 * or1k-desc.c: Regenerated.
142 * or1k-desc.h: Regenerated.
143 * or1k-dis.c: Regenerated.
144 * or1k-ibld.c: Regenerated.
145 * or1k-opc.c: Regenerated.
146 * or1k-opc.h: Regenerated.
147 * or1k-opinst.c: Regenerated.
148
1c4f3780
RH		 1492018-10-05 Richard Henderson <rth@twiddle.net>
150
151 * or1k-asm.c: Regenerate.
152
bde90be2
TC		 1532018-10-03 Tamar Christina <tamar.christina@arm.com>
154
155 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
156 * aarch64-dis.c (print_operands): Refactor to take notes.
157 (print_verifier_notes): New.
158 (print_aarch64_insn): Apply constraint verifier.
159 (print_insn_aarch64_word): Update call to print_aarch64_insn.
160 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
161
a68f4cd2
TC		 1622018-10-03 Tamar Christina <tamar.christina@arm.com>
163
164 * aarch64-opc.c (init_insn_block): New.
165 (verify_constraints, aarch64_is_destructive_by_operands): New.
166 * aarch64-opc.h (verify_constraints): New.
167
755b748f
TC		 1682018-10-03 Tamar Christina <tamar.christina@arm.com>
169
170 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
171 * aarch64-opc.c (verify_ldpsw): Update arguments.
172
1d482394
TC		 1732018-10-03 Tamar Christina <tamar.christina@arm.com>
174
175 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
176 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
177
7e84b55d
TC		 1782018-10-03 Tamar Christina <tamar.christina@arm.com>
179
180 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
181 * aarch64-dis.c (insn_sequence): New.
182
eae424ae
TC		 1832018-10-03 Tamar Christina <tamar.christina@arm.com>
184
185 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
186 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
187 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
188 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
189 constraints.
190 (_SVE_INSNC): New.
191 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
192 constraints.
193 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
194 F_SCAN flags.
195 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
196 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
197 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
198 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
199 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
200 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
201 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
202
64a336ac
PD		 2032018-10-02 Palmer Dabbelt <palmer@sifive.com>
204
205 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
206
6031ac35
SL		 2072018-09-23 Sandra Loosemore <sandra@codesourcery.com>
208
209 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
210 are used when extracting signed fields and converting them to
211 potentially 64-bit types.
212
f24ff6e9
SM		 2132018-09-21 Simon Marchi <simon.marchi@ericsson.com>
214
215 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
216 * Makefile.in: Re-generate.
217 * aclocal.m4: Re-generate.
218 * configure: Re-generate.
219 * configure.ac: Remove check for -Wno-missing-field-initializers.
220 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
221 (csky_v2_opcodes): Likewise.
222
53b6d6f5
MR		 2232018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
224
225 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
226
fbaf61ad
NC		 2272018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
228
229 * nds32-asm.c (operand_fields): Remove the unused fields.
230 (nds32_opcodes): Remove the unused instructions.
231 * nds32-dis.c (nds32_ex9_info): Removed.
232 (nds32_parse_opcode): Updated.
233 (print_insn_nds32): Likewise.
234 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
235 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
236 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
237 build_opcode_hash_table): New functions.
238 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
239 nds32_opcode_table): New.
240 (hw_ktabs): Declare it to a pointer rather than an array.
241 (build_hash_table): Removed.
242 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
243 SYN_ROPT and upadte HW_GPR and HW_INT.
244 * nds32-dis.c (keywords): Remove const.
245 (match_field): New function.
246 (nds32_parse_opcode): Updated.
247 * disassemble.c (disassemble_init_for_target):
248 Add disassemble_init_nds32.
249 * nds32-dis.c (eum map_type): New.
250 (nds32_private_data): Likewise.
251 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
252 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
253 (print_insn_nds32): Updated.
254 * nds32-asm.c (parse_aext_reg): Add new parameter.
255 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
256 are allowed to use.
257 All callers changed.
258 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
259 (operand_fields): Add new fields.
260 (nds32_opcodes): Add new instructions.
261 (keyword_aridxi_mx): New keyword.
262 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
263 and NASM_ATTR_ZOL.
264 (ALU2_1, ALU2_2, ALU2_3): New macros.
265 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
266
4e2b1898
JW		 2672018-09-17 Kito Cheng <kito@andestech.com>
268
269 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
270
04e2a182
L		 2712018-09-17 H.J. Lu <hongjiu.lu@intel.com>
272
273 PR gas/23670
274 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
275 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
276 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
277 (EVEX_LEN_0F7E_P_1): Likewise.
278 (EVEX_LEN_0F7E_P_2): Likewise.
279 (EVEX_LEN_0FD6_P_2): Likewise.
280 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
281 (EVEX_LEN_TABLE): Likewise.
282 (EVEX_LEN_0F6E_P_2): New enum.
283 (EVEX_LEN_0F7E_P_1): Likewise.
284 (EVEX_LEN_0F7E_P_2): Likewise.
285 (EVEX_LEN_0FD6_P_2): Likewise.
286 (evex_len_table): New.
287 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
288 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
289 * i386-tbl.h: Regenerated.
290
d5f787c2
L		 2912018-09-17 H.J. Lu <hongjiu.lu@intel.com>
292
293 PR gas/23665
294 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
295 VEX_LEN_0F7E_P_2 entries.
296 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
297 * i386-tbl.h: Regenerated.
298
ec6f095a
L		 2992018-09-17 H.J. Lu <hongjiu.lu@intel.com>
300
301 * i386-dis.c (VZERO_Fixup): Removed.
302 (VZERO): Likewise.
303 (VEX_LEN_0F10_P_1): Likewise.
304 (VEX_LEN_0F10_P_3): Likewise.
305 (VEX_LEN_0F11_P_1): Likewise.
306 (VEX_LEN_0F11_P_3): Likewise.
307 (VEX_LEN_0F2E_P_0): Likewise.
308 (VEX_LEN_0F2E_P_2): Likewise.
309 (VEX_LEN_0F2F_P_0): Likewise.
310 (VEX_LEN_0F2F_P_2): Likewise.
311 (VEX_LEN_0F51_P_1): Likewise.
312 (VEX_LEN_0F51_P_3): Likewise.
313 (VEX_LEN_0F52_P_1): Likewise.
314 (VEX_LEN_0F53_P_1): Likewise.
315 (VEX_LEN_0F58_P_1): Likewise.
316 (VEX_LEN_0F58_P_3): Likewise.
317 (VEX_LEN_0F59_P_1): Likewise.
318 (VEX_LEN_0F59_P_3): Likewise.
319 (VEX_LEN_0F5A_P_1): Likewise.
320 (VEX_LEN_0F5A_P_3): Likewise.
321 (VEX_LEN_0F5C_P_1): Likewise.
322 (VEX_LEN_0F5C_P_3): Likewise.
323 (VEX_LEN_0F5D_P_1): Likewise.
324 (VEX_LEN_0F5D_P_3): Likewise.
325 (VEX_LEN_0F5E_P_1): Likewise.
326 (VEX_LEN_0F5E_P_3): Likewise.
327 (VEX_LEN_0F5F_P_1): Likewise.
328 (VEX_LEN_0F5F_P_3): Likewise.
329 (VEX_LEN_0FC2_P_1): Likewise.
330 (VEX_LEN_0FC2_P_3): Likewise.
331 (VEX_LEN_0F3A0A_P_2): Likewise.
332 (VEX_LEN_0F3A0B_P_2): Likewise.
333 (VEX_W_0F10_P_0): Likewise.
334 (VEX_W_0F10_P_1): Likewise.
335 (VEX_W_0F10_P_2): Likewise.
336 (VEX_W_0F10_P_3): Likewise.
337 (VEX_W_0F11_P_0): Likewise.
338 (VEX_W_0F11_P_1): Likewise.
339 (VEX_W_0F11_P_2): Likewise.
340 (VEX_W_0F11_P_3): Likewise.
341 (VEX_W_0F12_P_0_M_0): Likewise.
342 (VEX_W_0F12_P_0_M_1): Likewise.
343 (VEX_W_0F12_P_1): Likewise.
344 (VEX_W_0F12_P_2): Likewise.
345 (VEX_W_0F12_P_3): Likewise.
346 (VEX_W_0F13_M_0): Likewise.
347 (VEX_W_0F14): Likewise.
348 (VEX_W_0F15): Likewise.
349 (VEX_W_0F16_P_0_M_0): Likewise.
350 (VEX_W_0F16_P_0_M_1): Likewise.
351 (VEX_W_0F16_P_1): Likewise.
352 (VEX_W_0F16_P_2): Likewise.
353 (VEX_W_0F17_M_0): Likewise.
354 (VEX_W_0F28): Likewise.
355 (VEX_W_0F29): Likewise.
356 (VEX_W_0F2B_M_0): Likewise.
357 (VEX_W_0F2E_P_0): Likewise.
358 (VEX_W_0F2E_P_2): Likewise.
359 (VEX_W_0F2F_P_0): Likewise.
360 (VEX_W_0F2F_P_2): Likewise.
361 (VEX_W_0F50_M_0): Likewise.
362 (VEX_W_0F51_P_0): Likewise.
363 (VEX_W_0F51_P_1): Likewise.
364 (VEX_W_0F51_P_2): Likewise.
365 (VEX_W_0F51_P_3): Likewise.
366 (VEX_W_0F52_P_0): Likewise.
367 (VEX_W_0F52_P_1): Likewise.
368 (VEX_W_0F53_P_0): Likewise.
369 (VEX_W_0F53_P_1): Likewise.
370 (VEX_W_0F58_P_0): Likewise.
371 (VEX_W_0F58_P_1): Likewise.
372 (VEX_W_0F58_P_2): Likewise.
373 (VEX_W_0F58_P_3): Likewise.
374 (VEX_W_0F59_P_0): Likewise.
375 (VEX_W_0F59_P_1): Likewise.
376 (VEX_W_0F59_P_2): Likewise.
377 (VEX_W_0F59_P_3): Likewise.
378 (VEX_W_0F5A_P_0): Likewise.
379 (VEX_W_0F5A_P_1): Likewise.
380 (VEX_W_0F5A_P_3): Likewise.
381 (VEX_W_0F5B_P_0): Likewise.
382 (VEX_W_0F5B_P_1): Likewise.
383 (VEX_W_0F5B_P_2): Likewise.
384 (VEX_W_0F5C_P_0): Likewise.
385 (VEX_W_0F5C_P_1): Likewise.
386 (VEX_W_0F5C_P_2): Likewise.
387 (VEX_W_0F5C_P_3): Likewise.
388 (VEX_W_0F5D_P_0): Likewise.
389 (VEX_W_0F5D_P_1): Likewise.
390 (VEX_W_0F5D_P_2): Likewise.
391 (VEX_W_0F5D_P_3): Likewise.
392 (VEX_W_0F5E_P_0): Likewise.
393 (VEX_W_0F5E_P_1): Likewise.
394 (VEX_W_0F5E_P_2): Likewise.
395 (VEX_W_0F5E_P_3): Likewise.
396 (VEX_W_0F5F_P_0): Likewise.
397 (VEX_W_0F5F_P_1): Likewise.
398 (VEX_W_0F5F_P_2): Likewise.
399 (VEX_W_0F5F_P_3): Likewise.
400 (VEX_W_0F60_P_2): Likewise.
401 (VEX_W_0F61_P_2): Likewise.
402 (VEX_W_0F62_P_2): Likewise.
403 (VEX_W_0F63_P_2): Likewise.
404 (VEX_W_0F64_P_2): Likewise.
405 (VEX_W_0F65_P_2): Likewise.
406 (VEX_W_0F66_P_2): Likewise.
407 (VEX_W_0F67_P_2): Likewise.
408 (VEX_W_0F68_P_2): Likewise.
409 (VEX_W_0F69_P_2): Likewise.
410 (VEX_W_0F6A_P_2): Likewise.
411 (VEX_W_0F6B_P_2): Likewise.
412 (VEX_W_0F6C_P_2): Likewise.
413 (VEX_W_0F6D_P_2): Likewise.
414 (VEX_W_0F6F_P_1): Likewise.
415 (VEX_W_0F6F_P_2): Likewise.
416 (VEX_W_0F70_P_1): Likewise.
417 (VEX_W_0F70_P_2): Likewise.
418 (VEX_W_0F70_P_3): Likewise.
419 (VEX_W_0F71_R_2_P_2): Likewise.
420 (VEX_W_0F71_R_4_P_2): Likewise.
421 (VEX_W_0F71_R_6_P_2): Likewise.
422 (VEX_W_0F72_R_2_P_2): Likewise.
423 (VEX_W_0F72_R_4_P_2): Likewise.
424 (VEX_W_0F72_R_6_P_2): Likewise.
425 (VEX_W_0F73_R_2_P_2): Likewise.
426 (VEX_W_0F73_R_3_P_2): Likewise.
427 (VEX_W_0F73_R_6_P_2): Likewise.
428 (VEX_W_0F73_R_7_P_2): Likewise.
429 (VEX_W_0F74_P_2): Likewise.
430 (VEX_W_0F75_P_2): Likewise.
431 (VEX_W_0F76_P_2): Likewise.
432 (VEX_W_0F77_P_0): Likewise.
433 (VEX_W_0F7C_P_2): Likewise.
434 (VEX_W_0F7C_P_3): Likewise.
435 (VEX_W_0F7D_P_2): Likewise.
436 (VEX_W_0F7D_P_3): Likewise.
437 (VEX_W_0F7E_P_1): Likewise.
438 (VEX_W_0F7F_P_1): Likewise.
439 (VEX_W_0F7F_P_2): Likewise.
440 (VEX_W_0FAE_R_2_M_0): Likewise.
441 (VEX_W_0FAE_R_3_M_0): Likewise.
442 (VEX_W_0FC2_P_0): Likewise.
443 (VEX_W_0FC2_P_1): Likewise.
444 (VEX_W_0FC2_P_2): Likewise.
445 (VEX_W_0FC2_P_3): Likewise.
446 (VEX_W_0FD0_P_2): Likewise.
447 (VEX_W_0FD0_P_3): Likewise.
448 (VEX_W_0FD1_P_2): Likewise.
449 (VEX_W_0FD2_P_2): Likewise.
450 (VEX_W_0FD3_P_2): Likewise.
451 (VEX_W_0FD4_P_2): Likewise.
452 (VEX_W_0FD5_P_2): Likewise.
453 (VEX_W_0FD6_P_2): Likewise.
454 (VEX_W_0FD7_P_2_M_1): Likewise.
455 (VEX_W_0FD8_P_2): Likewise.
456 (VEX_W_0FD9_P_2): Likewise.
457 (VEX_W_0FDA_P_2): Likewise.
458 (VEX_W_0FDB_P_2): Likewise.
459 (VEX_W_0FDC_P_2): Likewise.
460 (VEX_W_0FDD_P_2): Likewise.
461 (VEX_W_0FDE_P_2): Likewise.
462 (VEX_W_0FDF_P_2): Likewise.
463 (VEX_W_0FE0_P_2): Likewise.
464 (VEX_W_0FE1_P_2): Likewise.
465 (VEX_W_0FE2_P_2): Likewise.
466 (VEX_W_0FE3_P_2): Likewise.
467 (VEX_W_0FE4_P_2): Likewise.
468 (VEX_W_0FE5_P_2): Likewise.
469 (VEX_W_0FE6_P_1): Likewise.
470 (VEX_W_0FE6_P_2): Likewise.
471 (VEX_W_0FE6_P_3): Likewise.
472 (VEX_W_0FE7_P_2_M_0): Likewise.
473 (VEX_W_0FE8_P_2): Likewise.
474 (VEX_W_0FE9_P_2): Likewise.
475 (VEX_W_0FEA_P_2): Likewise.
476 (VEX_W_0FEB_P_2): Likewise.
477 (VEX_W_0FEC_P_2): Likewise.
478 (VEX_W_0FED_P_2): Likewise.
479 (VEX_W_0FEE_P_2): Likewise.
480 (VEX_W_0FEF_P_2): Likewise.
481 (VEX_W_0FF0_P_3_M_0): Likewise.
482 (VEX_W_0FF1_P_2): Likewise.
483 (VEX_W_0FF2_P_2): Likewise.
484 (VEX_W_0FF3_P_2): Likewise.
485 (VEX_W_0FF4_P_2): Likewise.
486 (VEX_W_0FF5_P_2): Likewise.
487 (VEX_W_0FF6_P_2): Likewise.
488 (VEX_W_0FF7_P_2): Likewise.
489 (VEX_W_0FF8_P_2): Likewise.
490 (VEX_W_0FF9_P_2): Likewise.
491 (VEX_W_0FFA_P_2): Likewise.
492 (VEX_W_0FFB_P_2): Likewise.
493 (VEX_W_0FFC_P_2): Likewise.
494 (VEX_W_0FFD_P_2): Likewise.
495 (VEX_W_0FFE_P_2): Likewise.
496 (VEX_W_0F3800_P_2): Likewise.
497 (VEX_W_0F3801_P_2): Likewise.
498 (VEX_W_0F3802_P_2): Likewise.
499 (VEX_W_0F3803_P_2): Likewise.
500 (VEX_W_0F3804_P_2): Likewise.
501 (VEX_W_0F3805_P_2): Likewise.
502 (VEX_W_0F3806_P_2): Likewise.
503 (VEX_W_0F3807_P_2): Likewise.
504 (VEX_W_0F3808_P_2): Likewise.
505 (VEX_W_0F3809_P_2): Likewise.
506 (VEX_W_0F380A_P_2): Likewise.
507 (VEX_W_0F380B_P_2): Likewise.
508 (VEX_W_0F3817_P_2): Likewise.
509 (VEX_W_0F381C_P_2): Likewise.
510 (VEX_W_0F381D_P_2): Likewise.
511 (VEX_W_0F381E_P_2): Likewise.
512 (VEX_W_0F3820_P_2): Likewise.
513 (VEX_W_0F3821_P_2): Likewise.
514 (VEX_W_0F3822_P_2): Likewise.
515 (VEX_W_0F3823_P_2): Likewise.
516 (VEX_W_0F3824_P_2): Likewise.
517 (VEX_W_0F3825_P_2): Likewise.
518 (VEX_W_0F3828_P_2): Likewise.
519 (VEX_W_0F3829_P_2): Likewise.
520 (VEX_W_0F382A_P_2_M_0): Likewise.
521 (VEX_W_0F382B_P_2): Likewise.
522 (VEX_W_0F3830_P_2): Likewise.
523 (VEX_W_0F3831_P_2): Likewise.
524 (VEX_W_0F3832_P_2): Likewise.
525 (VEX_W_0F3833_P_2): Likewise.
526 (VEX_W_0F3834_P_2): Likewise.
527 (VEX_W_0F3835_P_2): Likewise.
528 (VEX_W_0F3837_P_2): Likewise.
529 (VEX_W_0F3838_P_2): Likewise.
530 (VEX_W_0F3839_P_2): Likewise.
531 (VEX_W_0F383A_P_2): Likewise.
532 (VEX_W_0F383B_P_2): Likewise.
533 (VEX_W_0F383C_P_2): Likewise.
534 (VEX_W_0F383D_P_2): Likewise.
535 (VEX_W_0F383E_P_2): Likewise.
536 (VEX_W_0F383F_P_2): Likewise.
537 (VEX_W_0F3840_P_2): Likewise.
538 (VEX_W_0F3841_P_2): Likewise.
539 (VEX_W_0F38DB_P_2): Likewise.
540 (VEX_W_0F3A08_P_2): Likewise.
541 (VEX_W_0F3A09_P_2): Likewise.
542 (VEX_W_0F3A0A_P_2): Likewise.
543 (VEX_W_0F3A0B_P_2): Likewise.
544 (VEX_W_0F3A0C_P_2): Likewise.
545 (VEX_W_0F3A0D_P_2): Likewise.
546 (VEX_W_0F3A0E_P_2): Likewise.
547 (VEX_W_0F3A0F_P_2): Likewise.
548 (VEX_W_0F3A21_P_2): Likewise.
549 (VEX_W_0F3A40_P_2): Likewise.
550 (VEX_W_0F3A41_P_2): Likewise.
551 (VEX_W_0F3A42_P_2): Likewise.
552 (VEX_W_0F3A62_P_2): Likewise.
553 (VEX_W_0F3A63_P_2): Likewise.
554 (VEX_W_0F3ADF_P_2): Likewise.
555 (VEX_LEN_0F77_P_0): New.
556 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
557 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
558 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
559 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
560 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
561 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
562 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
563 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
564 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
565 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
566 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
567 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
568 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
569 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
570 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
571 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
572 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
573 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
574 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
575 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
576 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
577 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
578 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
579 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
580 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
581 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
582 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
583 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
584 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
585 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
586 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
587 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
588 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
589 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
590 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
591 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
592 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
593 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
594 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
595 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
596 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
597 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
598 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
599 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
600 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
601 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
602 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
603 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
604 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
605 (vex_table): Update VEX 0F28 and 0F29 entries.
606 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
607 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
608 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
609 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
610 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
611 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
612 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
613 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
614 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
615 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
616 VEX_LEN_0F3A0B_P_2 entries.
617 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
618 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
619 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
620 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
621 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
622 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
623 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
624 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
625 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
626 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
627 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
628 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
629 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
630 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
631 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
632 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
633 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
634 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
635 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
636 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
637 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
638 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
639 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
640 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
641 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
642 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
643 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
644 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
645 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
646 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
647 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
648 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
649 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
650 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
651 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
652 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
653 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
654 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
655 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
656 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
657 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
658 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
659 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
660 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
661 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
662 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
663 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
664 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
665 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
666 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
667 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
668 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
669 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
670 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
671 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
672 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
673 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
674 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
675 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
676 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
677 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
678 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
679 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
680 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
681 VEX_W_0F3ADF_P_2 entries.
682 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
683 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
684 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
685
6fa52824
L		 6862018-09-17 H.J. Lu <hongjiu.lu@intel.com>
687
688 * i386-opc.tbl (VexWIG): New.
689 Replace VexW=3 with VexWIG.
690
db4cc665
L		 6912018-09-15 H.J. Lu <hongjiu.lu@intel.com>
692
693 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
694 * i386-tbl.h: Regenerated.
695
3c374143
L		 6962018-09-15 H.J. Lu <hongjiu.lu@intel.com>
697
698 PR gas/23665
699 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
700 VEX_LEN_0FD6_P_2 entries.
701 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
702 * i386-tbl.h: Regenerated.
703
6865c043
L		 7042018-09-14 H.J. Lu <hongjiu.lu@intel.com>
705
706 PR gas/23642
707 * i386-opc.h (VEXWIG): New.
708 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
709 * i386-tbl.h: Regenerated.
710
70df6fc9
L		 7112018-09-14 H.J. Lu <hongjiu.lu@intel.com>
712
713 PR binutils/23655
714 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
715 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
716 * i386-dis.c (EXxEVexR64): New.
717 (evex_rounding_64_mode): Likewise.
718 (OP_Rounding): Handle evex_rounding_64_mode.
719
d20dee9e
L		 7202018-09-14 H.J. Lu <hongjiu.lu@intel.com>
721
722 PR binutils/23655
723 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
724 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
725 * i386-dis.c (Edqa): New.
726 (dqa_mode): Likewise.
727 (intel_operand_size): Handle dqa_mode as m_mode.
728 (OP_E_register): Handle dqa_mode as dq_mode.
729 (OP_E_memory): Set shift for dqa_mode based on address_mode.
730
5074ad8a
L		 7312018-09-14 H.J. Lu <hongjiu.lu@intel.com>
732
733 * i386-dis.c (OP_E_memory): Reformat.
734
556059dd
JB		 7352018-09-14 Jan Beulich <jbeulich@suse.com>
736
737 * i386-opc.tbl (crc32): Fold byte and word forms.
738 * i386-tbl.h: Re-generate.
739
41d1ab6a
L		 7402018-09-13 H.J. Lu <hongjiu.lu@intel.com>
741
742 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
743 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
744 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
745 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
746 * i386-tbl.h: Regenerated.
747
57f6375e
JB		 7482018-09-13 Jan Beulich <jbeulich@suse.com>
749
750 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
751 meaningless.
752 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
753 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
754 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
755 * i386-tbl.h: Re-generate.
756
2589a7e5
JB		 7572018-09-13 Jan Beulich <jbeulich@suse.com>
758
759 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
760 AVX512_4VNNIW insns.
761 * i386-tbl.h: Re-generate.
762
a760eb41
JB		 7632018-09-13 Jan Beulich <jbeulich@suse.com>
764
765 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
766 meaningless.
767 * i386-tbl.h: Re-generate.
768
e9042658
JB		 7692018-09-13 Jan Beulich <jbeulich@suse.com>
770
771 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
772 meaningless.
773 * i386-tbl.h: Re-generate.
774
9caa306f
JB		 7752018-09-13 Jan Beulich <jbeulich@suse.com>
776
777 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
778 meaningless.
779 * i386-tbl.h: Re-generate.
780
fb6ce599
JB		 7812018-09-13 Jan Beulich <jbeulich@suse.com>
782
783 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
784 meaningless.
785 * i386-tbl.h: Re-generate.
786
6a8da886
JB		 7872018-09-13 Jan Beulich <jbeulich@suse.com>
788
789 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
790 meaningless.
791 * i386-tbl.h: Re-generate.
792
c7f27919
JB		 7932018-09-13 Jan Beulich <jbeulich@suse.com>
794
795 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
796 * i386-tbl.h: Re-generate.
797
0f407ee9
JB		 7982018-09-13 Jan Beulich <jbeulich@suse.com>
799
800 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
801 * i386-tbl.h: Re-generate.
802
2fbbbee5
JB		 8032018-09-13 Jan Beulich <jbeulich@suse.com>
804
805 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
806 meaningless.
807 * i386-tbl.h: Re-generate.
808
2b02b9a2
JB		 8092018-09-13 Jan Beulich <jbeulich@suse.com>
810
811 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
812 meaningless.
813 * i386-tbl.h: Re-generate.
814
963c68aa
JB		 8152018-09-13 Jan Beulich <jbeulich@suse.com>
816
817 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
818 * i386-tbl.h: Re-generate.
819
64e025c3
JB		 8202018-09-13 Jan Beulich <jbeulich@suse.com>
821
822 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
823 * i386-tbl.h: Re-generate.
824
47603f88
JB		 8252018-09-13 Jan Beulich <jbeulich@suse.com>
826
827 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
828 * i386-tbl.h: Re-generate.
829
0001cfd0
JB		 8302018-09-13 Jan Beulich <jbeulich@suse.com>
831
832 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
833 meaningless.
834 * i386-tbl.h: Re-generate.
835
be4b452e
JB		 8362018-09-13 Jan Beulich <jbeulich@suse.com>
837
838 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
839 meaningless.
840 * i386-tbl.h: Re-generate.
841
d09a1394
JB		 8422018-09-13 Jan Beulich <jbeulich@suse.com>
843
844 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
845 meaningless.
846 * i386-tbl.h: Re-generate.
847
07599e13
JB		 8482018-09-13 Jan Beulich <jbeulich@suse.com>
849
850 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
851 * i386-tbl.h: Re-generate.
852
1ee3e487
JB		 8532018-09-13 Jan Beulich <jbeulich@suse.com>
854
855 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
856 * i386-tbl.h: Re-generate.
857
a5f580e5
JB		 8582018-09-13 Jan Beulich <jbeulich@suse.com>
859
860 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
861 * i386-tbl.h: Re-generate.
862
49d5d12d
JB		 8632018-09-13 Jan Beulich <jbeulich@suse.com>
864
865 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
866 (vpbroadcastw, rdpid): Drop NoRex64.
867 * i386-tbl.h: Re-generate.
868
f5eb1d70
JB		 8692018-09-13 Jan Beulich <jbeulich@suse.com>
870
871 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
872 store templates, adding D.
873 * i386-tbl.h: Re-generate.
874
dbbc8b7e
JB		 8752018-09-13 Jan Beulich <jbeulich@suse.com>
876
877 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
878 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
879 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
880 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
881 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
882 Fold load and store templates where possible, adding D. Drop
883 IgnoreSize where it was pointlessly present. Drop redundant
884 *word.
885 * i386-tbl.h: Re-generate.
886
d276ec69
JB		 8872018-09-13 Jan Beulich <jbeulich@suse.com>
888
889 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
890 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
891 (intel_operand_size): Handle v_bndmk_mode.
892 (OP_E_memory): Likewise. Produce (bad) when also riprel.
893
9da4dfd6
JD		 8942018-09-08 John Darrington <john@darrington.wattle.id.au>
895
896 * disassemble.c (ARCH_s12z): Define if ARCH_all.
897
be192bc2
JW		 8982018-08-31 Kito Cheng <kito@andestech.com>
899
900 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
901 compressed floating point instructions.
902
43135d3b
JW		 9032018-08-30 Kito Cheng <kito@andestech.com>
904
905 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
906 riscv_opcode.xlen_requirement.
907 * riscv-opc.c (riscv_opcodes): Update for struct change.
908
df28970f
MA		 9092018-08-29 Martin Aberg <maberg@gaisler.com>
910
911 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
912 psr (PWRPSR) instruction.
913
9108bc33
CX		 9142018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
915
916 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
917
bd782c07
CX		 9182018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
919
920 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
921
ac8cb70f
CX		 9222018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
923
924 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
925 loongson3a as an alias of gs464 for compatibility.
926 * mips-opc.c (mips_opcodes): Change Comments.
927
a693765e
CX		 9282018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
929
930 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
931 option.
932 (print_mips_disassembler_options): Document -M loongson-ext.
933 * mips-opc.c (LEXT2): New macro.
934 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
935
bdc6c06e
CX		 9362018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
937
938 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
939 descriptors.
940 (parse_mips_ase_option): Handle -M loongson-ext option.
941 (print_mips_disassembler_options): Document -M loongson-ext.
942 * mips-opc.c (IL3A): Delete.
943 * mips-opc.c (LEXT): New macro.
944 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
945 instructions.
946
716c08de
CX		 9472018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
948
949 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
950 descriptors.
951 (parse_mips_ase_option): Handle -M loongson-cam option.
952 (print_mips_disassembler_options): Document -M loongson-cam.
953 * mips-opc.c (LCAM): New macro.
954 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
955 instructions.
956
9cf7e568
AM		 9572018-08-21 Alan Modra <amodra@gmail.com>
958
959 * ppc-dis.c (operand_value_powerpc): Init "invalid".
960 (skip_optional_operands): Count optional operands, and update
961 ppc_optional_operand_value call.
962 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
963 (extract_vlensi): Likewise.
964 (extract_fxm): Return default value for missing optional operand.
965 (extract_ls, extract_raq, extract_tbr): Likewise.
966 (insert_sxl, extract_sxl): New functions.
967 (insert_esync, extract_esync): Remove Power9 handling and simplify.
968 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
969 flag and extra entry.
970 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
971 extract_sxl.
972
d203b41a 9732018-08-20 Alan Modra <amodra@gmail.com>
f4107842 974
d203b41a 975 * sh-opc.h (MASK): Simplify.
f4107842 976
08a8fe2f 9772018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 978
d203b41a
AM		 979 * s12z-dis.c (bm_decode): Deal with cases where the mode is
980 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 981 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 982
08a8fe2f 9832018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 984
985 * s12z.h: Delete.
7ba3ba91 986
1bc60e56
L		 9872018-08-14 H.J. Lu <hongjiu.lu@intel.com>
988
989 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
990 address with the addr32 prefix and without base nor index
991 registers.
992
d871f3f4
L		 9932018-08-11 H.J. Lu <hongjiu.lu@intel.com>
994
995 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
996 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
997 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
998 (cpu_flags): Add CpuCMOV and CpuFXSR.
999 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1000 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
1001 * i386-init.h: Regenerated.
1002 * i386-tbl.h: Likewise.
1003
b6523c37 10042018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
1005
1006 * arc-regs.h: Update auxiliary registers.
1007
e968fc9b
JB		 10082018-08-06 Jan Beulich <jbeulich@suse.com>
1009
1010 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1011 (RegIP, RegIZ): Define.
1012 * i386-reg.tbl: Adjust comments.
1013 (rip): Use Qword instead of BaseIndex. Use RegIP.
1014 (eip): Use Dword instead of BaseIndex. Use RegIP.
1015 (riz): Add Qword. Use RegIZ.
1016 (eiz): Add Dword. Use RegIZ.
1017 * i386-tbl.h: Re-generate.
1018
dbf8be89
JB		 10192018-08-03 Jan Beulich <jbeulich@suse.com>
1020
1021 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1022 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1023 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1024 * i386-tbl.h: Re-generate.
1025
c48dadc9
JB		 10262018-08-03 Jan Beulich <jbeulich@suse.com>
1027
1028 * i386-gen.c (operand_types): Remove Mem field.
1029 * i386-opc.h (union i386_operand_type): Remove mem field.
1030 * i386-init.h, i386-tbl.h: Re-generate.
1031
cb86a42a
AM		 10322018-08-01 Alan Modra <amodra@gmail.com>
1033
1034 * po/POTFILES.in: Regenerate.
1035
07cc0450
NC		 10362018-07-31 Nick Clifton <nickc@redhat.com>
1037
1038 * po/sv.po: Updated Swedish translation.
1039
1424ad86
JB		 10402018-07-31 Jan Beulich <jbeulich@suse.com>
1041
1042 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1043 * i386-init.h, i386-tbl.h: Re-generate.
1044
ae2387fe
JB		 10452018-07-31 Jan Beulich <jbeulich@suse.com>
1046
1047 * i386-opc.h (ZEROING_MASKING) Rename to ...
1048 (DYNAMIC_MASKING): ... this. Adjust comment.
1049 * i386-opc.tbl (MaskingMorZ): Define.
1050 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1051 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1052 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1053 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1054 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1055 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1056 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1057 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1058 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1059
6ff00b5e
JB		 10602018-07-31 Jan Beulich <jbeulich@suse.com>
1061
1062 * i386-opc.tbl: Use element rather than vector size for AVX512*
1063 scatter/gather insns.
1064 * i386-tbl.h: Re-generate.
1065
e951d5ca
JB		 10662018-07-31 Jan Beulich <jbeulich@suse.com>
1067
1068 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1069 (cpu_flags): Drop CpuVREX.
1070 * i386-opc.h (CpuVREX): Delete.
1071 (union i386_cpu_flags): Remove cpuvrex.
1072 * i386-init.h, i386-tbl.h: Re-generate.
1073
eb41b248
JW		 10742018-07-30 Jim Wilson <jimw@sifive.com>
1075
1076 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1077 fields.
1078 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1079
b8891f8d
AJ		 10802018-07-30 Andrew Jenner <andrew@codesourcery.com>
1081
1082 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1083 * Makefile.in: Regenerated.
1084 * configure.ac: Add C-SKY.
1085 * configure: Regenerated.
1086 * csky-dis.c: New file.
1087 * csky-opc.h: New file.
1088 * disassemble.c (ARCH_csky): Define.
1089 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1090 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1091
16065af1
AM		 10922018-07-27 Alan Modra <amodra@gmail.com>
1093
1094 * ppc-opc.c (insert_sprbat): Correct function parameter and
1095 return type.
1096 (extract_sprbat): Likewise, variable too.
1097
fa758a70
AC		 10982018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1099 Alan Modra <amodra@gmail.com>
1100
1101 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1102 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1103 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1104 support disjointed BAT.
1105 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1106 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1107 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1108
4a1b91ea
L		 11092018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1110 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1111
1112 * i386-gen.c (adjust_broadcast_modifier): New function.
1113 (process_i386_opcode_modifier): Add an argument for operands.
1114 Adjust the Broadcast value based on operands.
1115 (output_i386_opcode): Pass operand_types to
1116 process_i386_opcode_modifier.
1117 (process_i386_opcodes): Pass NULL as operands to
1118 process_i386_opcode_modifier.
1119 * i386-opc.h (BYTE_BROADCAST): New.
1120 (WORD_BROADCAST): Likewise.
1121 (DWORD_BROADCAST): Likewise.
1122 (QWORD_BROADCAST): Likewise.
1123 (i386_opcode_modifier): Expand broadcast to 3 bits.
1124 * i386-tbl.h: Regenerated.
1125
67ce483b
AM		 11262018-07-24 Alan Modra <amodra@gmail.com>
1127
1128 PR 23430
1129 * or1k-desc.h: Regenerate.
1130
4174bfff
JB		 11312018-07-24 Jan Beulich <jbeulich@suse.com>
1132
1133 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1134 vcvtusi2ss, and vcvtusi2sd.
1135 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1136 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1137 * i386-tbl.h: Re-generate.
1138
04e65276
CZ		 11392018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1140
1141 * arc-opc.c (extract_w6): Fix extending the sign.
1142
47e6f81c
CZ		 11432018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1144
1145 * arc-tbl.h (vewt): Allow it for ARC EM family.
1146
bb71536f
AM		 11472018-07-23 Alan Modra <amodra@gmail.com>
1148
1149 PR 23419
1150 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1151 opcode variants for mtspr/mfspr encodings.
1152
8095d2f7
CX		 11532018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1154 Maciej W. Rozycki <macro@mips.com>
1155
1156 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1157 loongson3a descriptors.
1158 (parse_mips_ase_option): Handle -M loongson-mmi option.
1159 (print_mips_disassembler_options): Document -M loongson-mmi.
1160 * mips-opc.c (LMMI): New macro.
1161 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1162 instructions.
1163
5f32791e
JB		 11642018-07-19 Jan Beulich <jbeulich@suse.com>
1165
1166 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1167 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1168 IgnoreSize and [XYZ]MMword where applicable.
1169 * i386-tbl.h: Re-generate.
1170
625cbd7a
JB		 11712018-07-19 Jan Beulich <jbeulich@suse.com>
1172
1173 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1174 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1175 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1176 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1177 * i386-tbl.h: Re-generate.
1178
86b15c32
JB		 11792018-07-19 Jan Beulich <jbeulich@suse.com>
1180
1181 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1182 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1183 VPCLMULQDQ templates into their respective AVX512VL counterparts
1184 where possible, using Disp8ShiftVL and CheckRegSize instead of
1185 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1186 * i386-tbl.h: Re-generate.
1187
cf769ed5
JB		 11882018-07-19 Jan Beulich <jbeulich@suse.com>
1189
1190 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1191 AVX512VL counterparts where possible, using Disp8ShiftVL and
1192 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1193 IgnoreSize) as appropriate.
1194 * i386-tbl.h: Re-generate.
1195
8282b7ad
JB		 11962018-07-19 Jan Beulich <jbeulich@suse.com>
1197
1198 * i386-opc.tbl: Fold AVX512BW templates into their respective
1199 AVX512VL counterparts where possible, using Disp8ShiftVL and
1200 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1201 IgnoreSize) as appropriate.
1202 * i386-tbl.h: Re-generate.
1203
755908cc
JB		 12042018-07-19 Jan Beulich <jbeulich@suse.com>
1205
1206 * i386-opc.tbl: Fold AVX512CD templates into their respective
1207 AVX512VL counterparts where possible, using Disp8ShiftVL and
1208 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1209 IgnoreSize) as appropriate.
1210 * i386-tbl.h: Re-generate.
1211
7091c612
JB		 12122018-07-19 Jan Beulich <jbeulich@suse.com>
1213
1214 * i386-opc.h (DISP8_SHIFT_VL): New.
1215 * i386-opc.tbl (Disp8ShiftVL): Define.
1216 (various): Fold AVX512VL templates into their respective
1217 AVX512F counterparts where possible, using Disp8ShiftVL and
1218 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1219 IgnoreSize) as appropriate.
1220 * i386-tbl.h: Re-generate.
1221
c30be56e
JB		 12222018-07-19 Jan Beulich <jbeulich@suse.com>
1223
1224 * Makefile.am: Change dependencies and rule for
1225 $(srcdir)/i386-init.h.
1226 * Makefile.in: Re-generate.
1227 * i386-gen.c (process_i386_opcodes): New local variable
1228 "marker". Drop opening of input file. Recognize marker and line
1229 number directives.
1230 * i386-opc.tbl (OPCODE_I386_H): Define.
1231 (i386-opc.h): Include it.
1232 (None): Undefine.
1233
11a322db
L		 12342018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1235
1236 PR gas/23418
1237 * i386-opc.h (Byte): Update comments.
1238 (Word): Likewise.
1239 (Dword): Likewise.
1240 (Fword): Likewise.
1241 (Qword): Likewise.
1242 (Tbyte): Likewise.
1243 (Xmmword): Likewise.
1244 (Ymmword): Likewise.
1245 (Zmmword): Likewise.
1246 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1247 vcvttps2uqq.
1248 * i386-tbl.h: Regenerated.
1249
cde3679e
NC		 12502018-07-12 Sudakshina Das <sudi.das@arm.com>
1251
1252 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1253 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1254 * aarch64-asm-2.c: Regenerate.
1255 * aarch64-dis-2.c: Regenerate.
1256 * aarch64-opc-2.c: Regenerate.
1257
45a28947
TC		 12582018-07-12 Tamar Christina <tamar.christina@arm.com>
1259
1260 PR binutils/23192
1261 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1262 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1263 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1264 sqdmulh, sqrdmulh): Use Em16.
1265
c597cc3d
SD		 12662018-07-11 Sudakshina Das <sudi.das@arm.com>
1267
1268 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1269 csdb together with them.
1270 (thumb32_opcodes): Likewise.
1271
a79eaed6
JB		 12722018-07-11 Jan Beulich <jbeulich@suse.com>
1273
1274 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1275 requiring 32-bit registers as operands 2 and 3. Improve
1276 comments.
1277 (mwait, mwaitx): Fold templates. Improve comments.
1278 OPERAND_TYPE_INOUTPORTREG.
1279 * i386-tbl.h: Re-generate.
1280
2fb5be8d
JB		 12812018-07-11 Jan Beulich <jbeulich@suse.com>
1282
1283 * i386-gen.c (operand_type_init): Remove
1284 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1285 OPERAND_TYPE_INOUTPORTREG.
1286 * i386-init.h: Re-generate.
1287
7f5cad30
JB		 12882018-07-11 Jan Beulich <jbeulich@suse.com>
1289
1290 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1291 (wrssq, wrussq): Add Qword.
1292 * i386-tbl.h: Re-generate.
1293
f0a85b07
JB		 12942018-07-11 Jan Beulich <jbeulich@suse.com>
1295
1296 * i386-opc.h: Rename OTMax to OTNum.
1297 (OTNumOfUints): Adjust calculation.
1298 (OTUnused): Directly alias to OTNum.
1299
9dcb0ba4
MR		 13002018-07-09 Maciej W. Rozycki <macro@mips.com>
1301
1302 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1303 `reg_xys'.
1304 (lea_reg_xys): Likewise.
1305 (print_insn_loop_primitive): Rename `reg' local variable to
1306 `reg_dxy'.
1307
f311ba7e
TC		 13082018-07-06 Tamar Christina <tamar.christina@arm.com>
1309
1310 PR binutils/23242
1311 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1312
cba05feb
TC		 13132018-07-06 Tamar Christina <tamar.christina@arm.com>
1314
1315 PR binutils/23369
1316 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1317 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1318
471b9d15
MR		 13192018-07-02 Maciej W. Rozycki <macro@mips.com>
1320
1321 PR tdep/8282
1322 * mips-dis.c (mips_option_arg_t): New enumeration.
1323 (mips_options): New variable.
1324 (disassembler_options_mips): New function.
1325 (print_mips_disassembler_options): Reimplement in terms of
1326 `disassembler_options_mips'.
1327 * arm-dis.c (disassembler_options_arm): Adapt to using the
1328 `disasm_options_and_args_t' structure.
1329 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1330 * s390-dis.c (disassembler_options_s390): Likewise.
1331
c0c468d5
TP		 13322018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1333
1334 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1335 expected result.
1336 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1337 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1338 * testsuite/ld-arm/tls-longplt.d: Likewise.
1339
369c9167
TC		 13402018-06-29 Tamar Christina <tamar.christina@arm.com>
1341
1342 PR binutils/23192
1343 * aarch64-asm-2.c: Regenerate.
1344 * aarch64-dis-2.c: Likewise.
1345 * aarch64-opc-2.c: Likewise.
1346 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1347 * aarch64-opc.c (operand_general_constraint_met_p,
1348 aarch64_print_operand): Likewise.
1349 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1350 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1351 fmlal2, fmlsl2.
1352 (AARCH64_OPERANDS): Add Em2.
1353
30aa1306
NC		 13542018-06-26 Nick Clifton <nickc@redhat.com>
1355
1356 * po/uk.po: Updated Ukranian translation.
1357 * po/de.po: Updated German translation.
1358 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1359
eca4b721
NC		 13602018-06-26 Nick Clifton <nickc@redhat.com>
1361
1362 * nfp-dis.c: Fix spelling mistake.
1363
71300e2c
NC		 13642018-06-24 Nick Clifton <nickc@redhat.com>
1365
1366 * configure: Regenerate.
1367 * po/opcodes.pot: Regenerate.
1368
719d8288
NC		 13692018-06-24 Nick Clifton <nickc@redhat.com>
1370
1371 2.31 branch created.
1372
514cd3a0
TC		 13732018-06-19 Tamar Christina <tamar.christina@arm.com>
1374
1375 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1376 * aarch64-asm-2.c: Regenerate.
1377 * aarch64-dis-2.c: Likewise.
1378
385e4d0f
MR		 13792018-06-21 Maciej W. Rozycki <macro@mips.com>
1380
1381 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1382 `-M ginv' option description.
1383
160d1b3d
SH		 13842018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1385
1386 PR gas/23305
1387 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1388 la and lla.
1389
d0ac1c44
SM		 13902018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1391
1392 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1393 * configure.ac: Remove AC_PREREQ.
1394 * Makefile.in: Re-generate.
1395 * aclocal.m4: Re-generate.
1396 * configure: Re-generate.
1397
6f20c942
FS		 13982018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1399
1400 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1401 mips64r6 descriptors.
1402 (parse_mips_ase_option): Handle -Mginv option.
1403 (print_mips_disassembler_options): Document -Mginv.
1404 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1405 (GINV): New macro.
1406 (mips_opcodes): Define ginvi and ginvt.
1407
730c3174
SE		 14082018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1409 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1410
1411 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1412 * mips-opc.c (CRC, CRC64): New macros.
1413 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1414 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1415 crc32cd for CRC64.
1416
cb366992
EB		 14172018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1418
1419 PR 20319
1420 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1421 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1422
ce72cd46
AM		 14232018-06-06 Alan Modra <amodra@gmail.com>
1424
1425 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1426 setjmp. Move init for some other vars later too.
1427
4b8e28c7
MF		 14282018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1429
1430 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1431 (dis_private): Add new fields for property section tracking.
1432 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1433 (xtensa_instruction_fits): New functions.
1434 (fetch_data): Bump minimal fetch size to 4.
1435 (print_insn_xtensa): Make struct dis_private static.
1436 Load and prepare property table on section change.
1437 Don't disassemble literals. Don't disassemble instructions that
1438 cross property table boundaries.
1439
55e99962
L		 14402018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1441
1442 * configure: Regenerated.
1443
733bd0ab
JB		 14442018-06-01 Jan Beulich <jbeulich@suse.com>
1445
1446 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1447 * i386-tbl.h: Re-generate.
1448
dfd27d41
JB		 14492018-06-01 Jan Beulich <jbeulich@suse.com>
1450
1451 * i386-opc.tbl (sldt, str): Add NoRex64.
1452 * i386-tbl.h: Re-generate.
1453
64795710
JB		 14542018-06-01 Jan Beulich <jbeulich@suse.com>
1455
1456 * i386-opc.tbl (invpcid): Add Oword.
1457 * i386-tbl.h: Re-generate.
1458
030157d8
AM		 14592018-06-01 Alan Modra <amodra@gmail.com>
1460
1461 * sysdep.h (_bfd_error_handler): Don't declare.
1462 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1463 * rl78-decode.opc: Likewise.
1464 * msp430-decode.c: Regenerate.
1465 * rl78-decode.c: Regenerate.
1466
a9660a6f
AP		 14672018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1468
1469 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1470 * i386-init.h : Regenerated.
1471
277eb7f6
AM		 14722018-05-25 Alan Modra <amodra@gmail.com>
1473
1474 * Makefile.in: Regenerate.
1475 * po/POTFILES.in: Regenerate.
1476
98553ad3
PB		 14772018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1478
1479 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1480 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1481 (insert_bab, extract_bab, insert_btab, extract_btab,
1482 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1483 (BAT, BBA VBA RBS XB6S): Delete macros.
1484 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1485 (BB, BD, RBX, XC6): Update for new macros.
1486 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1487 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1488 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1489 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1490
7b4ae824
JD		 14912018-05-18 John Darrington <john@darrington.wattle.id.au>
1492
1493 * Makefile.am: Add support for s12z architecture.
1494 * configure.ac: Likewise.
1495 * disassemble.c: Likewise.
1496 * disassemble.h: Likewise.
1497 * Makefile.in: Regenerate.
1498 * configure: Regenerate.
1499 * s12z-dis.c: New file.
1500 * s12z.h: New file.
1501
29e0f0a1
AM		 15022018-05-18 Alan Modra <amodra@gmail.com>
1503
1504 * nfp-dis.c: Don't #include libbfd.h.
1505 (init_nfp3200_priv): Use bfd_get_section_contents.
1506 (nit_nfp6000_mecsr_sec): Likewise.
1507
809276d2
NC		 15082018-05-17 Nick Clifton <nickc@redhat.com>
1509
1510 * po/zh_CN.po: Updated simplified Chinese translation.
1511
ff329288
TC		 15122018-05-16 Tamar Christina <tamar.christina@arm.com>
1513
1514 PR binutils/23109
1515 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1516 * aarch64-dis-2.c: Regenerate.
1517
f9830ec1
TC		 15182018-05-15 Tamar Christina <tamar.christina@arm.com>
1519
1520 PR binutils/21446
1521 * aarch64-asm.c (opintl.h): Include.
1522 (aarch64_ins_sysreg): Enforce read/write constraints.
1523 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1524 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1525 (F_REG_READ, F_REG_WRITE): New.
1526 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1527 AARCH64_OPND_SYSREG.
1528 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1529 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1530 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1531 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1532 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1533 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1534 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1535 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1536 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1537 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1538 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1539 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1540 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1541 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1542 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1543 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1544 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1545
7d02540a
TC		 15462018-05-15 Tamar Christina <tamar.christina@arm.com>
1547
1548 PR binutils/21446
1549 * aarch64-dis.c (no_notes: New.
1550 (parse_aarch64_dis_option): Support notes.
1551 (aarch64_decode_insn, print_operands): Likewise.
1552 (print_aarch64_disassembler_options): Document notes.
1553 * aarch64-opc.c (aarch64_print_operand): Support notes.
1554
561a72d4
TC		 15552018-05-15 Tamar Christina <tamar.christina@arm.com>
1556
1557 PR binutils/21446
1558 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1559 and take error struct.
1560 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1561 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1562 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1563 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1564 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1565 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1566 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1567 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1568 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1569 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1570 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1571 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1572 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1573 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1574 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1575 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1576 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1577 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1578 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1579 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1580 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1581 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1582 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1583 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1584 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1585 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1586 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1587 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1588 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1589 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1590 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1591 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1592 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1593 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1594 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1595 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1596 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1597 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1598 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1599 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1600 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1601 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1602 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1603 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1604 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1605 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1606 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1607 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1608 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1609 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1610 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1611 (determine_disassembling_preference, aarch64_decode_insn,
1612 print_insn_aarch64_word, print_insn_data): Take errors struct.
1613 (print_insn_aarch64): Use errors.
1614 * aarch64-asm-2.c: Regenerate.
1615 * aarch64-dis-2.c: Regenerate.
1616 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1617 boolean in aarch64_insert_operan.
1618 (print_operand_extractor): Likewise.
1619 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1620
1678bd35
FT		 16212018-05-15 Francois H. Theron <francois.theron@netronome.com>
1622
1623 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1624
06cfb1c8
L		 16252018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1626
1627 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1628
84f9f8c3
AM		 16292018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1630
1631 * cr16-opc.c (cr16_instruction): Comment typo fix.
1632 * hppa-dis.c (print_insn_hppa): Likewise.
1633
e6f372ba
JW		 16342018-05-08 Jim Wilson <jimw@sifive.com>
1635
1636 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1637 (match_c_slli64, match_srxi_as_c_srxi): New.
1638 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1639 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1640 <c.slli, c.srli, c.srai>: Use match_s_slli.
1641 <c.slli64, c.srli64, c.srai64>: New.
1642
f413a913
AM		 16432018-05-08 Alan Modra <amodra@gmail.com>
1644
1645 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1646 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1647 partition opcode space for index lookup.
1648
a87a6478
PB		 16492018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1650
1651 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1652 <insn_length>: ...with this. Update usage.
1653 Remove duplicate call to *info->memory_error_func.
1654
c0a30a9f
L		 16552018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1656 H.J. Lu <hongjiu.lu@intel.com>
1657
1658 * i386-dis.c (Gva): New.
1659 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1660 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1661 (prefix_table): New instructions (see prefix above).
1662 (mod_table): New instructions (see prefix above).
1663 (OP_G): Handle va_mode.
1664 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1665 CPU_MOVDIR64B_FLAGS.
1666 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1667 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1668 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1669 * i386-opc.tbl: Add movidir{i,64b}.
1670 * i386-init.h: Regenerated.
1671 * i386-tbl.h: Likewise.
1672
75c0a438
L		 16732018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1674
1675 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1676 AddrPrefixOpReg.
1677 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1678 (AddrPrefixOpReg): This.
1679 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1680 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1681
2ceb7719
PB		 16822018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1683
1684 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1685 (vle_num_opcodes): Likewise.
1686 (spe2_num_opcodes): Likewise.
1687 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1688 initialization loop.
1689 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1690 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1691 only once.
1692
b3ac5c6c
TC		 16932018-05-01 Tamar Christina <tamar.christina@arm.com>
1694
1695 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1696
fe944acf
FT		 16972018-04-30 Francois H. Theron <francois.theron@netronome.com>
1698
1699 Makefile.am: Added nfp-dis.c.
1700 configure.ac: Added bfd_nfp_arch.
1701 disassemble.h: Added print_insn_nfp prototype.
1702 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1703 nfp-dis.c: New, for NFP support.
1704 po/POTFILES.in: Added nfp-dis.c to the list.
1705 Makefile.in: Regenerate.
1706 configure: Regenerate.
1707
e2195274
JB		 17082018-04-26 Jan Beulich <jbeulich@suse.com>
1709
1710 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1711 templates into their base ones.
1712 * i386-tlb.h: Re-generate.
1713
59ef5df4
JB		 17142018-04-26 Jan Beulich <jbeulich@suse.com>
1715
1716 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1717 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1718 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1719 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1720 * i386-init.h: Re-generate.
1721
6e041cf4
JB		 17222018-04-26 Jan Beulich <jbeulich@suse.com>
1723
1724 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1725 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1726 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1727 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1728 comment.
1729 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1730 and CpuRegMask.
1731 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1732 CpuRegMask: Delete.
1733 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1734 cpuregzmm, and cpuregmask.
1735 * i386-init.h: Re-generate.
1736 * i386-tbl.h: Re-generate.
1737
0e0eea78
JB		 17382018-04-26 Jan Beulich <jbeulich@suse.com>
1739
1740 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1741 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1742 * i386-init.h: Re-generate.
1743
2f1bada2
JB		 17442018-04-26 Jan Beulich <jbeulich@suse.com>
1745
1746 * i386-gen.c (VexImmExt): Delete.
1747 * i386-opc.h (VexImmExt, veximmext): Delete.
1748 * i386-opc.tbl: Drop all VexImmExt uses.
1749 * i386-tlb.h: Re-generate.
1750
bacd1457
JB		 17512018-04-25 Jan Beulich <jbeulich@suse.com>
1752
1753 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1754 register-only forms.
1755 * i386-tlb.h: Re-generate.
1756
10bba94b
TC		 17572018-04-25 Tamar Christina <tamar.christina@arm.com>
1758
1759 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1760
c48935d7
IT		 17612018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1762
1763 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1764 PREFIX_0F1C.
1765 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1766 (cpu_flags): Add CpuCLDEMOTE.
1767 * i386-init.h: Regenerate.
1768 * i386-opc.h (enum): Add CpuCLDEMOTE,
1769 (i386_cpu_flags): Add cpucldemote.
1770 * i386-opc.tbl: Add cldemote.
1771 * i386-tbl.h: Regenerate.
1772
211dc24b
AM		 17732018-04-16 Alan Modra <amodra@gmail.com>
1774
1775 * Makefile.am: Remove sh5 and sh64 support.
1776 * configure.ac: Likewise.
1777 * disassemble.c: Likewise.
1778 * disassemble.h: Likewise.
1779 * sh-dis.c: Likewise.
1780 * sh64-dis.c: Delete.
1781 * sh64-opc.c: Delete.
1782 * sh64-opc.h: Delete.
1783 * Makefile.in: Regenerate.
1784 * configure: Regenerate.
1785 * po/POTFILES.in: Regenerate.
1786
a9a4b302
AM		 17872018-04-16 Alan Modra <amodra@gmail.com>
1788
1789 * Makefile.am: Remove w65 support.
1790 * configure.ac: Likewise.
1791 * disassemble.c: Likewise.
1792 * disassemble.h: Likewise.
1793 * w65-dis.c: Delete.
1794 * w65-opc.h: Delete.
1795 * Makefile.in: Regenerate.
1796 * configure: Regenerate.
1797 * po/POTFILES.in: Regenerate.
1798
04cb01fd
AM		 17992018-04-16 Alan Modra <amodra@gmail.com>
1800
1801 * configure.ac: Remove we32k support.
1802 * configure: Regenerate.
1803
c2bf1eec
AM		 18042018-04-16 Alan Modra <amodra@gmail.com>
1805
1806 * Makefile.am: Remove m88k support.
1807 * configure.ac: Likewise.
1808 * disassemble.c: Likewise.
1809 * disassemble.h: Likewise.
1810 * m88k-dis.c: Delete.
1811 * Makefile.in: Regenerate.
1812 * configure: Regenerate.
1813 * po/POTFILES.in: Regenerate.
1814
6793974d
AM		 18152018-04-16 Alan Modra <amodra@gmail.com>
1816
1817 * Makefile.am: Remove i370 support.
1818 * configure.ac: Likewise.
1819 * disassemble.c: Likewise.
1820 * disassemble.h: Likewise.
1821 * i370-dis.c: Delete.
1822 * i370-opc.c: Delete.
1823 * Makefile.in: Regenerate.
1824 * configure: Regenerate.
1825 * po/POTFILES.in: Regenerate.
1826
e82aa794
AM		 18272018-04-16 Alan Modra <amodra@gmail.com>
1828
1829 * Makefile.am: Remove h8500 support.
1830 * configure.ac: Likewise.
1831 * disassemble.c: Likewise.
1832 * disassemble.h: Likewise.
1833 * h8500-dis.c: Delete.
1834 * h8500-opc.h: Delete.
1835 * Makefile.in: Regenerate.
1836 * configure: Regenerate.
1837 * po/POTFILES.in: Regenerate.
1838
fceadf09
AM		 18392018-04-16 Alan Modra <amodra@gmail.com>
1840
1841 * configure.ac: Remove tahoe support.
1842 * configure: Regenerate.
1843
ae1d3843
L		 18442018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1845
1846 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1847 umwait.
1848 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1849 64-bit mode.
1850 * i386-tbl.h: Regenerated.
1851
de89d0a3
IT		 18522018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1853
1854 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1855 PREFIX_MOD_1_0FAE_REG_6.
1856 (va_mode): New.
1857 (OP_E_register): Use va_mode.
1858 * i386-dis-evex.h (prefix_table):
1859 New instructions (see prefixes above).
1860 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1861 (cpu_flags): Likewise.
1862 * i386-opc.h (enum): Likewise.
1863 (i386_cpu_flags): Likewise.
1864 * i386-opc.tbl: Add umonitor, umwait, tpause.
1865 * i386-init.h: Regenerate.
1866 * i386-tbl.h: Likewise.
1867
a8eb42a8
AM		 18682018-04-11 Alan Modra <amodra@gmail.com>
1869
1870 * opcodes/i860-dis.c: Delete.
1871 * opcodes/i960-dis.c: Delete.
1872 * Makefile.am: Remove i860 and i960 support.
1873 * configure.ac: Likewise.
1874 * disassemble.c: Likewise.
1875 * disassemble.h: Likewise.
1876 * Makefile.in: Regenerate.
1877 * configure: Regenerate.
1878 * po/POTFILES.in: Regenerate.
1879
caf0678c
L		 18802018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1881
1882 PR binutils/23025
1883 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1884 to 0.
1885 (print_insn): Clear vex instead of vex.evex.
1886
4fb0d2b9
NC		 18872018-04-04 Nick Clifton <nickc@redhat.com>
1888
1889 * po/es.po: Updated Spanish translation.
1890
c39e5b26
JB		 18912018-03-28 Jan Beulich <jbeulich@suse.com>
1892
1893 * i386-gen.c (opcode_modifiers): Delete VecESize.
1894 * i386-opc.h (VecESize): Delete.
1895 (struct i386_opcode_modifier): Delete vecesize.
1896 * i386-opc.tbl: Drop VecESize.
1897 * i386-tlb.h: Re-generate.
1898
8e6e0792
JB		 18992018-03-28 Jan Beulich <jbeulich@suse.com>
1900
1901 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1902 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1903 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1904 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1905 * i386-tlb.h: Re-generate.
1906
9f123b91
JB		 19072018-03-28 Jan Beulich <jbeulich@suse.com>
1908
1909 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1910 Fold AVX512 forms
1911 * i386-tlb.h: Re-generate.
1912
9646c87b
JB		 19132018-03-28 Jan Beulich <jbeulich@suse.com>
1914
1915 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1916 (vex_len_table): Drop Y for vcvt*2si.
1917 (putop): Replace plain 'Y' handling by abort().
1918
c8d59609
NC		 19192018-03-28 Nick Clifton <nickc@redhat.com>
1920
1921 PR 22988
1922 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1923 instructions with only a base address register.
1924 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1925 handle AARHC64_OPND_SVE_ADDR_R.
1926 (aarch64_print_operand): Likewise.
1927 * aarch64-asm-2.c: Regenerate.
1928 * aarch64_dis-2.c: Regenerate.
1929 * aarch64-opc-2.c: Regenerate.
1930
b8c169f3
JB		 19312018-03-22 Jan Beulich <jbeulich@suse.com>
1932
1933 * i386-opc.tbl: Drop VecESize from register only insn forms and
1934 memory forms not allowing broadcast.
1935 * i386-tlb.h: Re-generate.
1936
96bc132a
JB		 19372018-03-22 Jan Beulich <jbeulich@suse.com>
1938
1939 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1940 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1941 sha256*): Drop Disp<N>.
1942
9f79e886
JB		 19432018-03-22 Jan Beulich <jbeulich@suse.com>
1944
1945 * i386-dis.c (EbndS, bnd_swap_mode): New.
1946 (prefix_table): Use EbndS.
1947 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1948 * i386-opc.tbl (bndmov): Move misplaced Load.
1949 * i386-tlb.h: Re-generate.
1950
d6793fa1
JB		 19512018-03-22 Jan Beulich <jbeulich@suse.com>
1952
1953 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1954 templates allowing memory operands and folded ones for register
1955 only flavors.
1956 * i386-tlb.h: Re-generate.
1957
f7768225
JB		 19582018-03-22 Jan Beulich <jbeulich@suse.com>
1959
1960 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1961 256-bit templates. Drop redundant leftover Disp<N>.
1962 * i386-tlb.h: Re-generate.
1963
0e35537d
JW		 19642018-03-14 Kito Cheng <kito.cheng@gmail.com>
1965
1966 * riscv-opc.c (riscv_insn_types): New.
1967
b4a3689a
NC		 19682018-03-13 Nick Clifton <nickc@redhat.com>
1969
1970 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1971
d3d50934
L		 19722018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1973
1974 * i386-opc.tbl: Add Optimize to clr.
1975 * i386-tbl.h: Regenerated.
1976
bd5dea88
L		 19772018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1978
1979 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1980 * i386-opc.h (OldGcc): Removed.
1981 (i386_opcode_modifier): Remove oldgcc.
1982 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1983 instructions for old (<= 2.8.1) versions of gcc.
1984 * i386-tbl.h: Regenerated.
1985
e771e7c9
JB		 19862018-03-08 Jan Beulich <jbeulich@suse.com>
1987
1988 * i386-opc.h (EVEXDYN): New.
1989 * i386-opc.tbl: Fold various AVX512VL templates.
1990 * i386-tlb.h: Re-generate.
1991
ed438a93
JB		 19922018-03-08 Jan Beulich <jbeulich@suse.com>
1993
1994 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1995 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1996 vpexpandd, vpexpandq): Fold AFX512VF templates.
1997 * i386-tlb.h: Re-generate.
1998
454172a9
JB		 19992018-03-08 Jan Beulich <jbeulich@suse.com>
2000
2001 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2002 Fold 128- and 256-bit VEX-encoded templates.
2003 * i386-tlb.h: Re-generate.
2004
36824150
JB		 20052018-03-08 Jan Beulich <jbeulich@suse.com>
2006
2007 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2008 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2009 vpexpandd, vpexpandq): Fold AVX512F templates.
2010 * i386-tlb.h: Re-generate.
2011
e7f5c0a9
JB		 20122018-03-08 Jan Beulich <jbeulich@suse.com>
2013
2014 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2015 64-bit templates. Drop Disp<N>.
2016 * i386-tlb.h: Re-generate.
2017
25a4277f
JB		 20182018-03-08 Jan Beulich <jbeulich@suse.com>
2019
2020 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2021 and 256-bit templates.
2022 * i386-tlb.h: Re-generate.
2023
d2224064
JB		 20242018-03-08 Jan Beulich <jbeulich@suse.com>
2025
2026 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2027 * i386-tlb.h: Re-generate.
2028
1b193f0b
JB		 20292018-03-08 Jan Beulich <jbeulich@suse.com>
2030
2031 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2032 Drop NoAVX.
2033 * i386-tlb.h: Re-generate.
2034
f2f6a710
JB		 20352018-03-08 Jan Beulich <jbeulich@suse.com>
2036
2037 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2038 * i386-tlb.h: Re-generate.
2039
38e314eb
JB		 20402018-03-08 Jan Beulich <jbeulich@suse.com>
2041
2042 * i386-gen.c (opcode_modifiers): Delete FloatD.
2043 * i386-opc.h (FloatD): Delete.
2044 (struct i386_opcode_modifier): Delete floatd.
2045 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2046 FloatD by D.
2047 * i386-tlb.h: Re-generate.
2048
d53e6b98
JB		 20492018-03-08 Jan Beulich <jbeulich@suse.com>
2050
2051 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2052
2907c2f5
JB		 20532018-03-08 Jan Beulich <jbeulich@suse.com>
2054
2055 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2056 * i386-tlb.h: Re-generate.
2057
73053c1f
JB		 20582018-03-08 Jan Beulich <jbeulich@suse.com>
2059
2060 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2061 forms.
2062 * i386-tlb.h: Re-generate.
2063
52fe4420
AM		 20642018-03-07 Alan Modra <amodra@gmail.com>
2065
2066 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2067 bfd_arch_rs6000.
2068 * disassemble.h (print_insn_rs6000): Delete.
2069 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2070 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2071 (print_insn_rs6000): Delete.
2072
a6743a54
AM		 20732018-03-03 Alan Modra <amodra@gmail.com>
2074
2075 * sysdep.h (opcodes_error_handler): Define.
2076 (_bfd_error_handler): Declare.
2077 * Makefile.am: Remove stray #.
2078 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2079 EDIT" comment.
2080 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2081 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2082 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2083 opcodes_error_handler to print errors. Standardize error messages.
2084 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2085 and include opintl.h.
2086 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2087 * i386-gen.c: Standardize error messages.
2088 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2089 * Makefile.in: Regenerate.
2090 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2091 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2092 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2093 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2094 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2095 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2096 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2097 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2098 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2099 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2100 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2101 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2102 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2103
8305403a
L		 21042018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2105
2106 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2107 vpsub[bwdq] instructions.
2108 * i386-tbl.h: Regenerated.
2109
e184813f
AM		 21102018-03-01 Alan Modra <amodra@gmail.com>
2111
2112 * configure.ac (ALL_LINGUAS): Sort.
2113 * configure: Regenerate.
2114
5b616bef
TP		 21152018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2116
2117 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2118 macro by assignements.
2119
b6f8c7c4
L		 21202018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2121
2122 PR gas/22871
2123 * i386-gen.c (opcode_modifiers): Add Optimize.
2124 * i386-opc.h (Optimize): New enum.
2125 (i386_opcode_modifier): Add optimize.
2126 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2127 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2128 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2129 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2130 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2131 vpxord and vpxorq.
2132 * i386-tbl.h: Regenerated.
2133
e95b887f
AM		 21342018-02-26 Alan Modra <amodra@gmail.com>
2135
2136 * crx-dis.c (getregliststring): Allocate a large enough buffer
2137 to silence false positive gcc8 warning.
2138
0bccfb29
JW		 21392018-02-22 Shea Levy <shea@shealevy.com>
2140
2141 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2142
6b6b6807
L		 21432018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2144
2145 * i386-opc.tbl: Add {rex},
2146 * i386-tbl.h: Regenerated.
2147
75f31665
MR		 21482018-02-20 Maciej W. Rozycki <macro@mips.com>
2149
2150 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2151 (mips16_opcodes): Replace `M' with `m' for "restore".
2152
e207bc53
TP		 21532018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2154
2155 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2156
87993319
MR		 21572018-02-13 Maciej W. Rozycki <macro@mips.com>
2158
2159 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2160 variable to `function_index'.
2161
68d20676
NC		 21622018-02-13 Nick Clifton <nickc@redhat.com>
2163
2164 PR 22823
2165 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2166 about truncation of printing.
2167
d2159fdc
HW		 21682018-02-12 Henry Wong <henry@stuffedcow.net>
2169
2170 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2171
f174ef9f
NC		 21722018-02-05 Nick Clifton <nickc@redhat.com>
2173
2174 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2175
be3a8dca
IT		 21762018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2177
2178 * i386-dis.c (enum): Add pconfig.
2179 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2180 (cpu_flags): Add CpuPCONFIG.
2181 * i386-opc.h (enum): Add CpuPCONFIG.
2182 (i386_cpu_flags): Add cpupconfig.
2183 * i386-opc.tbl: Add PCONFIG instruction.
2184 * i386-init.h: Regenerate.
2185 * i386-tbl.h: Likewise.
2186
3233d7d0
IT		 21872018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2188
2189 * i386-dis.c (enum): Add PREFIX_0F09.
2190 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2191 (cpu_flags): Add CpuWBNOINVD.
2192 * i386-opc.h (enum): Add CpuWBNOINVD.
2193 (i386_cpu_flags): Add cpuwbnoinvd.
2194 * i386-opc.tbl: Add WBNOINVD instruction.
2195 * i386-init.h: Regenerate.
2196 * i386-tbl.h: Likewise.
2197
e925c834
JW		 21982018-01-17 Jim Wilson <jimw@sifive.com>
2199
2200 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2201
d777820b
IT		 22022018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2203
2204 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2205 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2206 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2207 (cpu_flags): Add CpuIBT, CpuSHSTK.
2208 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2209 (i386_cpu_flags): Add cpuibt, cpushstk.
2210 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2211 * i386-init.h: Regenerate.
2212 * i386-tbl.h: Likewise.
2213
f6efed01
NC		 22142018-01-16 Nick Clifton <nickc@redhat.com>
2215
2216 * po/pt_BR.po: Updated Brazilian Portugese translation.
2217 * po/de.po: Updated German translation.
2218
2721d702
JW		 22192018-01-15 Jim Wilson <jimw@sifive.com>
2220
2221 * riscv-opc.c (match_c_nop): New.
2222 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2223
616dcb87
NC		 22242018-01-15 Nick Clifton <nickc@redhat.com>
2225
2226 * po/uk.po: Updated Ukranian translation.
2227
3957a496
NC		 22282018-01-13 Nick Clifton <nickc@redhat.com>
2229
2230 * po/opcodes.pot: Regenerated.
2231
769c7ea5
NC		 22322018-01-13 Nick Clifton <nickc@redhat.com>
2233
2234 * configure: Regenerate.
2235
faf766e3
NC		 22362018-01-13 Nick Clifton <nickc@redhat.com>
2237
2238 2.30 branch created.
2239
888a89da
IT		 22402018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2241
2242 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2243 * i386-tbl.h: Regenerate.
2244
cbda583a
JB		 22452018-01-10 Jan Beulich <jbeulich@suse.com>
2246
2247 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2248 * i386-tbl.h: Re-generate.
2249
c9e92278
JB		 22502018-01-10 Jan Beulich <jbeulich@suse.com>
2251
2252 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2253 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2254 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2255 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2256 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2257 Disp8MemShift of AVX512VL forms.
2258 * i386-tbl.h: Re-generate.
2259
35fd2b2b
JW		 22602018-01-09 Jim Wilson <jimw@sifive.com>
2261
2262 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2263 then the hi_addr value is zero.
2264
91d8b670
JG		 22652018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2266
2267 * arm-dis.c (arm_opcodes): Add csdb.
2268 (thumb32_opcodes): Add csdb.
2269
be2e7d95
JG		 22702018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2271
2272 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2273 * aarch64-asm-2.c: Regenerate.
2274 * aarch64-dis-2.c: Regenerate.
2275 * aarch64-opc-2.c: Regenerate.
2276
704a705d
L		 22772018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2278
2279 PR gas/22681
2280 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2281 Remove AVX512 vmovd with 64-bit operands.
2282 * i386-tbl.h: Regenerated.
2283
35eeb78f
JW		 22842018-01-05 Jim Wilson <jimw@sifive.com>
2285
2286 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2287 jalr.
2288
219d1afa
AM		 22892018-01-03 Alan Modra <amodra@gmail.com>
2290
2291 Update year range in copyright notice of all files.
2292
1508bbf5
JB		 22932018-01-02 Jan Beulich <jbeulich@suse.com>
2294
2295 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2296 and OPERAND_TYPE_REGZMM entries.
2297
1e563868 2298For older changes see ChangeLog-2017
3499769a 2299\f
1e563868 2300Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 2301
2302Copying and distribution of this file, with or without modification,
2303are permitted in any medium without royalty provided the copyright
2304notice and this notice are preserved.
2305
2306Local Variables:
2307mode: change-log
2308left-margin: 8
2309fill-column: 74
2310version-control: never
2311End:
GDB Binutils - Deliverables
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