projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Automatic date update in version.in
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
4e9ac44a
L		 12017-09-09 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-dis.c (last_active_prefix): Removed.
4 (ckprefix): Don't set last_active_prefix.
5 (NOTRACK_Fixup): Don't check last_active_prefix.
6
b55f3386
NC		 72017-08-31 Nick Clifton <nickc@redhat.com>
8
9 * po/fr.po: Updated French translation.
10
59e8523b
JB		 112017-08-31 James Bowman <james.bowman@ftdichip.com>
12
13 * ft32-dis.c (print_insn_ft32): Correct display of non-address
14 fields.
15
74081948
AF		 162017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
17 Edmar Wienskoski <edmar.wienskoski@nxp.com>
18
19 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
20 PPC_OPCODE_EFS2 flag to "e200z4" entry.
21 New entries efs2 and spe2.
22 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
23 (SPE2_OPCD_SEGS): New macro.
24 (spe2_opcd_indices): New.
25 (disassemble_init_powerpc): Handle SPE2 opcodes.
26 (lookup_spe2): New function.
27 (print_insn_powerpc): call lookup_spe2.
28 * ppc-opc.c (insert_evuimm1_ex0): New function.
29 (extract_evuimm1_ex0): Likewise.
30 (insert_evuimm_lt8): Likewise.
31 (extract_evuimm_lt8): Likewise.
32 (insert_off_spe2): Likewise.
33 (extract_off_spe2): Likewise.
34 (insert_Ddd): Likewise.
35 (extract_Ddd): Likewise.
36 (DD): New operand.
37 (EVUIMM_LT8): Likewise.
38 (EVUIMM_LT16): Adjust.
39 (MMMM): New operand.
40 (EVUIMM_1): Likewise.
41 (EVUIMM_1_EX0): Likewise.
42 (EVUIMM_2): Adjust.
43 (NNN): New operand.
44 (VX_OFF_SPE2): Likewise.
45 (BBB): Likewise.
46 (DDD): Likewise.
47 (VX_MASK_DDD): New mask.
48 (HH): New operand.
49 (VX_RA_CONST): New macro.
50 (VX_RA_CONST_MASK): Likewise.
51 (VX_RB_CONST): Likewise.
52 (VX_RB_CONST_MASK): Likewise.
53 (VX_OFF_SPE2_MASK): Likewise.
54 (VX_SPE_CRFD): Likewise.
55 (VX_SPE_CRFD_MASK VX): Likewise.
56 (VX_SPE2_CLR): Likewise.
57 (VX_SPE2_CLR_MASK): Likewise.
58 (VX_SPE2_SPLATB): Likewise.
59 (VX_SPE2_SPLATB_MASK): Likewise.
60 (VX_SPE2_OCTET): Likewise.
61 (VX_SPE2_OCTET_MASK): Likewise.
62 (VX_SPE2_DDHH): Likewise.
63 (VX_SPE2_DDHH_MASK): Likewise.
64 (VX_SPE2_HH): Likewise.
65 (VX_SPE2_HH_MASK): Likewise.
66 (VX_SPE2_EVMAR): Likewise.
67 (VX_SPE2_EVMAR_MASK): Likewise.
68 (PPCSPE2): Likewise.
69 (PPCEFS2): Likewise.
70 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
71 (powerpc_macros): Map old SPE instructions have new names
72 with the same opcodes. Add SPE2 instructions which just are
73 mapped to SPE2.
74 (spe2_opcodes): Add SPE2 opcodes.
75
b80c7270
AM		 762017-08-23 Alan Modra <amodra@gmail.com>
77
78 * ppc-opc.c: Formatting and comment fixes. Move insert and
79 extract functions earlier, deleting forward declarations.
80 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
81 RA_MASK.
82
67d888f5
PD		 832017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
84
85 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
86
e3c2f928
AF		 872017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
88 Edmar Wienskoski <edmar.wienskoski@nxp.com>
89
90 * ppc-opc.c (insert_evuimm2_ex0): New function.
91 (extract_evuimm2_ex0): Likewise.
92 (insert_evuimm4_ex0): Likewise.
93 (extract_evuimm4_ex0): Likewise.
94 (insert_evuimm8_ex0): Likewise.
95 (extract_evuimm8_ex0): Likewise.
96 (insert_evuimm_lt16): Likewise.
97 (extract_evuimm_lt16): Likewise.
98 (insert_rD_rS_even): Likewise.
99 (extract_rD_rS_even): Likewise.
100 (insert_off_lsp): Likewise.
101 (extract_off_lsp): Likewise.
102 (RD_EVEN): New operand.
103 (RS_EVEN): Likewise.
104 (RSQ): Adjust.
105 (EVUIMM_LT16): New operand.
106 (HTM_SI): Adjust.
107 (EVUIMM_2_EX0): New operand.
108 (EVUIMM_4): Adjust.
109 (EVUIMM_4_EX0): New operand.
110 (EVUIMM_8): Adjust.
111 (EVUIMM_8_EX0): New operand.
112 (WS): Adjust.
113 (VX_OFF): New operand.
114 (VX_LSP): New macro.
115 (VX_LSP_MASK): Likewise.
116 (VX_LSP_OFF_MASK): Likewise.
117 (PPC_OPCODE_LSP): Likewise.
118 (vle_opcodes): Add LSP opcodes.
119 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
120
cc4a945a
JW		 1212017-08-09 Jiong Wang <jiong.wang@arm.com>
122
123 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
124 register operands in CRC instructions.
125 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
126 comments.
127
b28b8b5e
L		 1282017-08-07 H.J. Lu <hongjiu.lu@intel.com>
129
130 * disassemble.c (disassembler): Mark big and mach with
131 ATTRIBUTE_UNUSED.
132
e347efc3
MR		 1332017-08-07 Maciej W. Rozycki <macro@imgtec.com>
134
135 * disassemble.c (disassembler): Remove arch/mach/endian
136 assertions.
137
7cbc739c
NC		 1382017-07-25 Nick Clifton <nickc@redhat.com>
139
140 PR 21739
141 * arc-opc.c (insert_rhv2): Use lower case first letter in error
142 message.
143 (insert_r0): Likewise.
144 (insert_r1): Likewise.
145 (insert_r2): Likewise.
146 (insert_r3): Likewise.
147 (insert_sp): Likewise.
148 (insert_gp): Likewise.
149 (insert_pcl): Likewise.
150 (insert_blink): Likewise.
151 (insert_ilink1): Likewise.
152 (insert_ilink2): Likewise.
153 (insert_ras): Likewise.
154 (insert_rbs): Likewise.
155 (insert_rcs): Likewise.
156 (insert_simm3s): Likewise.
157 (insert_rrange): Likewise.
158 (insert_r13el): Likewise.
159 (insert_fpel): Likewise.
160 (insert_blinkel): Likewise.
161 (insert_pclel): Likewise.
162 (insert_nps_bitop_size_2b): Likewise.
163 (insert_nps_imm_offset): Likewise.
164 (insert_nps_imm_entry): Likewise.
165 (insert_nps_size_16bit): Likewise.
166 (insert_nps_##NAME##_pos): Likewise.
167 (insert_nps_##NAME): Likewise.
168 (insert_nps_bitop_ins_ext): Likewise.
169 (insert_nps_##NAME): Likewise.
170 (insert_nps_min_hofs): Likewise.
171 (insert_nps_##NAME): Likewise.
172 (insert_nps_rbdouble_64): Likewise.
173 (insert_nps_misc_imm_offset): Likewise.
174 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
175 option description.
176
7684e580
JW		 1772017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
178 Jiong Wang <jiong.wang@arm.com>
179
180 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
181 correct the print.
182 * aarch64-dis-2.c: Regenerated.
183
47826cdb
AK		 1842017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
185
186 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
187 table.
188
2d2dbad0
NC		 1892017-07-20 Nick Clifton <nickc@redhat.com>
190
191 * po/de.po: Updated German translation.
192
70b448ba 1932017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
194
195 * arc-regs.h (sec_stat): New aux register.
196 (aux_kernel_sp): Likewise.
197 (aux_sec_u_sp): Likewise.
198 (aux_sec_k_sp): Likewise.
199 (sec_vecbase_build): Likewise.
200 (nsc_table_top): Likewise.
201 (nsc_table_base): Likewise.
202 (ersec_stat): Likewise.
203 (aux_sec_except): Likewise.
204
7179e0e6
CZ		 2052017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
206
207 * arc-opc.c (extract_uimm12_20): New function.
208 (UIMM12_20): New operand.
209 (SIMM3_5_S): Adjust.
210 * arc-tbl.h (sjli): Add new instruction.
211
684d5a10
JEM		 2122017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
213 John Eric Martin <John.Martin@emmicro-us.com>
214
215 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
216 (UIMM3_23): Adjust accordingly.
217 * arc-regs.h: Add/correct jli_base register.
218 * arc-tbl.h (jli_s): Likewise.
219
de194d85
YC		 2202017-07-18 Nick Clifton <nickc@redhat.com>
221
222 PR 21775
223 * aarch64-opc.c: Fix spelling typos.
224 * i386-dis.c: Likewise.
225
0f6329bd
RB		 2262017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
227
228 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
229 max_addr_offset and octets variables to size_t.
230
429d795d
AM		 2312017-07-12 Alan Modra <amodra@gmail.com>
232
233 * po/da.po: Update from translationproject.org/latest/opcodes/.
234 * po/de.po: Likewise.
235 * po/es.po: Likewise.
236 * po/fi.po: Likewise.
237 * po/fr.po: Likewise.
238 * po/id.po: Likewise.
239 * po/it.po: Likewise.
240 * po/nl.po: Likewise.
241 * po/pt_BR.po: Likewise.
242 * po/ro.po: Likewise.
243 * po/sv.po: Likewise.
244 * po/tr.po: Likewise.
245 * po/uk.po: Likewise.
246 * po/vi.po: Likewise.
247 * po/zh_CN.po: Likewise.
248
4162bb66
AM		 2492017-07-11 Yao Qi <yao.qi@linaro.org>
250 Alan Modra <amodra@gmail.com>
251
252 * cgen.sh: Mark generated files read-only.
253 * epiphany-asm.c: Regenerate.
254 * epiphany-desc.c: Regenerate.
255 * epiphany-desc.h: Regenerate.
256 * epiphany-dis.c: Regenerate.
257 * epiphany-ibld.c: Regenerate.
258 * epiphany-opc.c: Regenerate.
259 * epiphany-opc.h: Regenerate.
260 * fr30-asm.c: Regenerate.
261 * fr30-desc.c: Regenerate.
262 * fr30-desc.h: Regenerate.
263 * fr30-dis.c: Regenerate.
264 * fr30-ibld.c: Regenerate.
265 * fr30-opc.c: Regenerate.
266 * fr30-opc.h: Regenerate.
267 * frv-asm.c: Regenerate.
268 * frv-desc.c: Regenerate.
269 * frv-desc.h: Regenerate.
270 * frv-dis.c: Regenerate.
271 * frv-ibld.c: Regenerate.
272 * frv-opc.c: Regenerate.
273 * frv-opc.h: Regenerate.
274 * ip2k-asm.c: Regenerate.
275 * ip2k-desc.c: Regenerate.
276 * ip2k-desc.h: Regenerate.
277 * ip2k-dis.c: Regenerate.
278 * ip2k-ibld.c: Regenerate.
279 * ip2k-opc.c: Regenerate.
280 * ip2k-opc.h: Regenerate.
281 * iq2000-asm.c: Regenerate.
282 * iq2000-desc.c: Regenerate.
283 * iq2000-desc.h: Regenerate.
284 * iq2000-dis.c: Regenerate.
285 * iq2000-ibld.c: Regenerate.
286 * iq2000-opc.c: Regenerate.
287 * iq2000-opc.h: Regenerate.
288 * lm32-asm.c: Regenerate.
289 * lm32-desc.c: Regenerate.
290 * lm32-desc.h: Regenerate.
291 * lm32-dis.c: Regenerate.
292 * lm32-ibld.c: Regenerate.
293 * lm32-opc.c: Regenerate.
294 * lm32-opc.h: Regenerate.
295 * lm32-opinst.c: Regenerate.
296 * m32c-asm.c: Regenerate.
297 * m32c-desc.c: Regenerate.
298 * m32c-desc.h: Regenerate.
299 * m32c-dis.c: Regenerate.
300 * m32c-ibld.c: Regenerate.
301 * m32c-opc.c: Regenerate.
302 * m32c-opc.h: Regenerate.
303 * m32r-asm.c: Regenerate.
304 * m32r-desc.c: Regenerate.
305 * m32r-desc.h: Regenerate.
306 * m32r-dis.c: Regenerate.
307 * m32r-ibld.c: Regenerate.
308 * m32r-opc.c: Regenerate.
309 * m32r-opc.h: Regenerate.
310 * m32r-opinst.c: Regenerate.
311 * mep-asm.c: Regenerate.
312 * mep-desc.c: Regenerate.
313 * mep-desc.h: Regenerate.
314 * mep-dis.c: Regenerate.
315 * mep-ibld.c: Regenerate.
316 * mep-opc.c: Regenerate.
317 * mep-opc.h: Regenerate.
318 * mt-asm.c: Regenerate.
319 * mt-desc.c: Regenerate.
320 * mt-desc.h: Regenerate.
321 * mt-dis.c: Regenerate.
322 * mt-ibld.c: Regenerate.
323 * mt-opc.c: Regenerate.
324 * mt-opc.h: Regenerate.
325 * or1k-asm.c: Regenerate.
326 * or1k-desc.c: Regenerate.
327 * or1k-desc.h: Regenerate.
328 * or1k-dis.c: Regenerate.
329 * or1k-ibld.c: Regenerate.
330 * or1k-opc.c: Regenerate.
331 * or1k-opc.h: Regenerate.
332 * or1k-opinst.c: Regenerate.
333 * xc16x-asm.c: Regenerate.
334 * xc16x-desc.c: Regenerate.
335 * xc16x-desc.h: Regenerate.
336 * xc16x-dis.c: Regenerate.
337 * xc16x-ibld.c: Regenerate.
338 * xc16x-opc.c: Regenerate.
339 * xc16x-opc.h: Regenerate.
340 * xstormy16-asm.c: Regenerate.
341 * xstormy16-desc.c: Regenerate.
342 * xstormy16-desc.h: Regenerate.
343 * xstormy16-dis.c: Regenerate.
344 * xstormy16-ibld.c: Regenerate.
345 * xstormy16-opc.c: Regenerate.
346 * xstormy16-opc.h: Regenerate.
347
7639175c
AM		 3482017-07-07 Alan Modra <amodra@gmail.com>
349
350 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
351 * m32c-dis.c: Regenerate.
352 * mep-dis.c: Regenerate.
353
e4bdd679
BP		 3542017-07-05 Borislav Petkov <bp@suse.de>
355
356 * i386-dis.c: Enable ModRM.reg /6 aliases.
357
60c96dbf
RR		 3582017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
359
360 * opcodes/arm-dis.c: Support MVFR2 in disassembly
361 with vmrs and vmsr.
362
0d702cfe
TG		 3632017-07-04 Tristan Gingold <gingold@adacore.com>
364
365 * configure: Regenerate.
366
15e6ed8c
TG		 3672017-07-03 Tristan Gingold <gingold@adacore.com>
368
369 * po/opcodes.pot: Regenerate.
370
b1d3c886
MR		 3712017-06-30 Maciej W. Rozycki <macro@imgtec.com>
372
373 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
374 entries to the MSA ASE instruction block.
375
909b4e3d
MR		 3762017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
377 Maciej W. Rozycki <macro@imgtec.com>
378
379 * micromips-opc.c (XPA, XPAVZ): New macros.
380 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
381 "mthgc0".
382
f5b2fd52
MR		 3832017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
384 Maciej W. Rozycki <macro@imgtec.com>
385
386 * micromips-opc.c (I36): New macro.
387 (micromips_opcodes): Add "eretnc".
388
9785fc2a
MR		 3892017-06-30 Maciej W. Rozycki <macro@imgtec.com>
390 Andrew Bennett <andrew.bennett@imgtec.com>
391
392 * mips-dis.c (mips_calculate_combination_ases): Handle the
393 ASE_XPA_VIRT flag.
394 (parse_mips_ase_option): New function.
395 (parse_mips_dis_option): Factor out ASE option handling to the
396 new function. Call `mips_calculate_combination_ases'.
397 * mips-opc.c (XPAVZ): New macro.
398 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
399 "mfhgc0", "mthc0" and "mthgc0".
400
60804c53
MR		 4012017-06-29 Maciej W. Rozycki <macro@imgtec.com>
402
403 * mips-dis.c (mips_calculate_combination_ases): New function.
404 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
405 calculation to the new function.
406 (set_default_mips_dis_options): Call the new function.
407
2e74f9dd
AK		 4082017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
409
410 * arc-dis.c (parse_disassembler_options): Use
411 FOR_EACH_DISASSEMBLER_OPTION.
412
e1e94c49
AK		 4132017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
414
415 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
416 disassembler option strings.
417 (parse_cpu_option): Likewise.
418
65a55fbb
TC		 4192017-06-28 Tamar Christina <tamar.christina@arm.com>
420
421 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
422 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
423 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
424 (aarch64_feature_dotprod, DOT_INSN): New.
425 (udot, sdot): New.
426 * aarch64-dis-2.c: Regenerated.
427
c604a79a
JW		 4282017-06-28 Jiong Wang <jiong.wang@arm.com>
429
430 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
431
38bf472a
MR		 4322017-06-28 Maciej W. Rozycki <macro@imgtec.com>
433 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 434 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 435
436 * mips-formats.h (INT_BIAS): New macro.
437 (INT_ADJ): Redefine in INT_BIAS terms.
438 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
439 (mips_print_save_restore): New function.
440 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
441 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
442 call.
443 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
444 (print_mips16_insn_arg): Call `mips_print_save_restore' for
445 OP_SAVE_RESTORE_LIST handling, factored out from here.
446 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
447 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
448 (mips_builtin_opcodes): Add "restore" and "save" entries.
449 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
450 (IAMR2): New macro.
451 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
452
9bdfdbf9
AW		 4532017-06-23 Andrew Waterman <andrew@sifive.com>
454
455 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
456 alias; do not mark SLTI instruction as an alias.
457
2234eee6
L		 4582017-06-21 H.J. Lu <hongjiu.lu@intel.com>
459
460 * i386-dis.c (RM_0FAE_REG_5): Removed.
461 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
462 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
463 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
464 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
465 PREFIX_MOD_3_0F01_REG_5_RM_0.
466 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
467 PREFIX_MOD_3_0FAE_REG_5.
468 (mod_table): Update MOD_0FAE_REG_5.
469 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
470 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
471 * i386-tbl.h: Regenerated.
472
c2f76402
L		 4732017-06-21 H.J. Lu <hongjiu.lu@intel.com>
474
475 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
476 * i386-opc.tbl: Likewise.
477 * i386-tbl.h: Regenerated.
478
9fef80d6
L		 4792017-06-21 H.J. Lu <hongjiu.lu@intel.com>
480
481 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
482 and "jmp{&|}".
483 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
484 prefix.
485
0f6d864d
NC		 4862017-06-19 Nick Clifton <nickc@redhat.com>
487
488 PR binutils/21614
489 * score-dis.c (score_opcodes): Add sentinel.
490
e197589b
AM		 4912017-06-16 Alan Modra <amodra@gmail.com>
492
493 * rx-decode.c: Regenerate.
494
0d96e4df
L		 4952017-06-15 H.J. Lu <hongjiu.lu@intel.com>
496
497 PR binutils/21594
498 * i386-dis.c (OP_E_register): Check valid bnd register.
499 (OP_G): Likewise.
500
cd3ea7c6
NC		 5012017-06-15 Nick Clifton <nickc@redhat.com>
502
503 PR binutils/21595
504 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
505 range value.
506
63323b5b
NC		 5072017-06-15 Nick Clifton <nickc@redhat.com>
508
509 PR binutils/21588
510 * rl78-decode.opc (OP_BUF_LEN): Define.
511 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
512 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
513 array.
514 * rl78-decode.c: Regenerate.
515
08c7881b
NC		 5162017-06-15 Nick Clifton <nickc@redhat.com>
517
518 PR binutils/21586
519 * bfin-dis.c (gregs): Clip index to prevent overflow.
520 (regs): Likewise.
521 (regs_lo): Likewise.
522 (regs_hi): Likewise.
523
e64519d1
NC		 5242017-06-14 Nick Clifton <nickc@redhat.com>
525
526 PR binutils/21576
527 * score7-dis.c (score_opcodes): Add sentinel.
528
6394c606
YQ		 5292017-06-14 Yao Qi <yao.qi@linaro.org>
530
531 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
532 * arm-dis.c: Likewise.
533 * ia64-dis.c: Likewise.
534 * mips-dis.c: Likewise.
535 * spu-dis.c: Likewise.
536 * disassemble.h (print_insn_aarch64): New declaration, moved from
537 include/dis-asm.h.
538 (print_insn_big_arm, print_insn_big_mips): Likewise.
539 (print_insn_i386, print_insn_ia64): Likewise.
540 (print_insn_little_arm, print_insn_little_mips): Likewise.
541
db5fa770
NC		 5422017-06-14 Nick Clifton <nickc@redhat.com>
543
544 PR binutils/21587
545 * rx-decode.opc: Include libiberty.h
546 (GET_SCALE): New macro - validates access to SCALE array.
547 (GET_PSCALE): New macro - validates access to PSCALE array.
548 (DIs, SIs, S2Is, rx_disp): Use new macros.
549 * rx-decode.c: Regenerate.
550
05c966f3
AV		 5512017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
552
553 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
554
10045478
AK		 5552017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
556
557 * arc-dis.c (enforced_isa_mask): Declare.
558 (cpu_types): Likewise.
559 (parse_cpu_option): New function.
560 (parse_disassembler_options): Use it.
561 (print_insn_arc): Use enforced_isa_mask.
562 (print_arc_disassembler_options): Document new options.
563
88c1242d
YQ		 5642017-05-24 Yao Qi <yao.qi@linaro.org>
565
566 * alpha-dis.c: Include disassemble.h, don't include
567 dis-asm.h.
568 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
569 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
570 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
571 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
572 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
573 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
574 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
575 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
576 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
577 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
578 * moxie-dis.c, msp430-dis.c, mt-dis.c:
579 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
580 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
581 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
582 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
583 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
584 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
585 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
586 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
587 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
588 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
589 * z80-dis.c, z8k-dis.c: Likewise.
590 * disassemble.h: New file.
591
ab20fa4a
YQ		 5922017-05-24 Yao Qi <yao.qi@linaro.org>
593
594 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
595 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
596
003ca0fd
YQ		 5972017-05-24 Yao Qi <yao.qi@linaro.org>
598
599 * disassemble.c (disassembler): Add arguments a, big and mach.
600 Use them.
601
04ef582a
L		 6022017-05-22 H.J. Lu <hongjiu.lu@intel.com>
603
604 * i386-dis.c (NOTRACK_Fixup): New.
605 (NOTRACK): Likewise.
606 (NOTRACK_PREFIX): Likewise.
607 (last_active_prefix): Likewise.
608 (reg_table): Use NOTRACK on indirect call and jmp.
609 (ckprefix): Set last_active_prefix.
610 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
611 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
612 * i386-opc.h (NoTrackPrefixOk): New.
613 (i386_opcode_modifier): Add notrackprefixok.
614 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
615 Add notrack.
616 * i386-tbl.h: Regenerated.
617
64517994
JM		 6182017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
619
620 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
621 (X_IMM2): Define.
622 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
623 bfd_mach_sparc_v9m8.
624 (print_insn_sparc): Handle new operand types.
625 * sparc-opc.c (MASK_M8): Define.
626 (v6): Add MASK_M8.
627 (v6notlet): Likewise.
628 (v7): Likewise.
629 (v8): Likewise.
630 (v9): Likewise.
631 (v9a): Likewise.
632 (v9b): Likewise.
633 (v9c): Likewise.
634 (v9d): Likewise.
635 (v9e): Likewise.
636 (v9v): Likewise.
637 (v9m): Likewise.
638 (v9andleon): Likewise.
639 (m8): Define.
640 (HWS_VM8): Define.
641 (HWS2_VM8): Likewise.
642 (sparc_opcode_archs): Add entry for "m8".
643 (sparc_opcodes): Add OSA2017 and M8 instructions
644 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
645 fpx{ll,ra,rl}64x,
646 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
647 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
648 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
649 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
650 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
651 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
652 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
653 ASI_CORE_SELECT_COMMIT_NHT.
654
535b785f
AM		 6552017-05-18 Alan Modra <amodra@gmail.com>
656
657 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
658 * aarch64-dis.c: Likewise.
659 * aarch64-gen.c: Likewise.
660 * aarch64-opc.c: Likewise.
661
25499ac7
MR		 6622017-05-15 Maciej W. Rozycki <macro@imgtec.com>
663 Matthew Fortune <matthew.fortune@imgtec.com>
664
665 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
666 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
667 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
668 (print_insn_arg) <OP_REG28>: Add handler.
669 (validate_insn_args) <OP_REG28>: Handle.
670 (print_mips16_insn_arg): Handle MIPS16 instructions that require
671 32-bit encoding and 9-bit immediates.
672 (print_insn_mips16): Handle MIPS16 instructions that require
673 32-bit encoding and MFC0/MTC0 operand decoding.
674 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
675 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
676 (RD_C0, WR_C0, E2, E2MT): New macros.
677 (mips16_opcodes): Add entries for MIPS16e2 instructions:
678 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
679 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
680 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
681 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
682 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
683 instructions, "swl", "swr", "sync" and its "sync_acquire",
684 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
685 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
686 regular/extended entries for original MIPS16 ISA revision
687 instructions whose extended forms are subdecoded in the MIPS16e2
688 ISA revision: "li", "sll" and "srl".
689
fdfb4752
MR		 6902017-05-15 Maciej W. Rozycki <macro@imgtec.com>
691
692 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
693 reference in CP0 move operand decoding.
694
a4f89915
MR		 6952017-05-12 Maciej W. Rozycki <macro@imgtec.com>
696
697 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
698 type to hexadecimal.
699 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
700
99e2d67a
MR		 7012017-05-11 Maciej W. Rozycki <macro@imgtec.com>
702
703 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
704 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
705 "sync_rmb" and "sync_wmb" as aliases.
706 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
707 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
708
53a346d8
CZ		 7092017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
710
711 * arc-dis.c (parse_option): Update quarkse_em option..
712 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
713 QUARKSE1.
714 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
715
f91d48de
KC		 7162017-05-03 Kito Cheng <kito.cheng@gmail.com>
717
718 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
719
43e379d7
MC		 7202017-05-01 Michael Clark <michaeljclark@mac.com>
721
722 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
723 register.
724
a4ddc54e
MR		 7252017-05-02 Maciej W. Rozycki <macro@imgtec.com>
726
727 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
728 and branches and not synthetic data instructions.
729
fe50e98c
BE		 7302017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
731
732 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
733
126124cc
CZ		 7342017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
735
736 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
737 * arc-opc.c (insert_r13el): New function.
738 (R13_EL): Define.
739 * arc-tbl.h: Add new enter/leave variants.
740
be6a24d8
CZ		 7412017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
742
743 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
744
0348fd79
MR		 7452017-04-25 Maciej W. Rozycki <macro@imgtec.com>
746
747 * mips-dis.c (print_mips_disassembler_options): Add
748 `no-aliases'.
749
6e3d1f07
MR		 7502017-04-25 Maciej W. Rozycki <macro@imgtec.com>
751
752 * mips16-opc.c (AL): New macro.
753 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
754 of "ld" and "lw" as aliases.
755
957f6b39
TC		 7562017-04-24 Tamar Christina <tamar.christina@arm.com>
757
758 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
759 arguments.
760
a8cc8a54
AM		 7612017-04-22 Alexander Fedotov <alfedotov@gmail.com>
762 Alan Modra <amodra@gmail.com>
763
764 * ppc-opc.c (ELEV): Define.
765 (vle_opcodes): Add se_rfgi and e_sc.
766 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
767 for E200Z4.
768
3ab87b68
JM		 7692017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
770
771 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
772
792f174f
NC		 7732017-04-21 Nick Clifton <nickc@redhat.com>
774
775 PR binutils/21380
776 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
777 LD3R and LD4R.
778
42742084
AM		 7792017-04-13 Alan Modra <amodra@gmail.com>
780
781 * epiphany-desc.c: Regenerate.
782 * fr30-desc.c: Regenerate.
783 * frv-desc.c: Regenerate.
784 * ip2k-desc.c: Regenerate.
785 * iq2000-desc.c: Regenerate.
786 * lm32-desc.c: Regenerate.
787 * m32c-desc.c: Regenerate.
788 * m32r-desc.c: Regenerate.
789 * mep-desc.c: Regenerate.
790 * mt-desc.c: Regenerate.
791 * or1k-desc.c: Regenerate.
792 * xc16x-desc.c: Regenerate.
793 * xstormy16-desc.c: Regenerate.
794
9a85b496
AM		 7952017-04-11 Alan Modra <amodra@gmail.com>
796
ef85eab0 797 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 798 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
799 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 800 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
801 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 802 (PPCVSX2): Define as PPC_OPCODE_POWER8.
803 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 804 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 805 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 806
62adc510
AM		 8072017-04-10 Alan Modra <amodra@gmail.com>
808
809 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
810 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
811 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
812 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
813
aa808707
PC		 8142017-04-09 Pip Cet <pipcet@gmail.com>
815
816 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
817 appropriate floating-point precision directly.
818
ac8f0f72
AM		 8192017-04-07 Alan Modra <amodra@gmail.com>
820
821 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
822 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
823 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
824 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
825 vector instructions with E6500 not PPCVEC2.
826
62ecb94c
PC		 8272017-04-06 Pip Cet <pipcet@gmail.com>
828
829 * Makefile.am: Add wasm32-dis.c.
830 * configure.ac: Add wasm32-dis.c to wasm32 target.
831 * disassemble.c: Add wasm32 disassembler code.
832 * wasm32-dis.c: New file.
833 * Makefile.in: Regenerate.
834 * configure: Regenerate.
835 * po/POTFILES.in: Regenerate.
836 * po/opcodes.pot: Regenerate.
837
f995bbe8
PA		 8382017-04-05 Pedro Alves <palves@redhat.com>
839
840 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
841 * arm-dis.c (parse_arm_disassembler_options): Constify.
842 * ppc-dis.c (powerpc_init_dialect): Constify local.
843 * vax-dis.c (parse_disassembler_options): Constify.
844
b5292032
PD		 8452017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
846
847 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
848 RISCV_GP_SYMBOL.
849
f96bd6c2
PC		 8502017-03-30 Pip Cet <pipcet@gmail.com>
851
852 * configure.ac: Add (empty) bfd_wasm32_arch target.
853 * configure: Regenerate
854 * po/opcodes.pot: Regenerate.
855
f7c514a3
JM		 8562017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
857
858 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
859 OSA2015.
860 * opcodes/sparc-opc.c (asi_table): New ASIs.
861
52be03fd
AM		 8622017-03-29 Alan Modra <amodra@gmail.com>
863
864 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
865 "raw" option.
866 (lookup_powerpc): Don't special case -1 dialect. Handle
867 PPC_OPCODE_RAW.
868 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
869 lookup_powerpc call, pass it on second.
870
9b753937
AM		 8712017-03-27 Alan Modra <amodra@gmail.com>
872
873 PR 21303
874 * ppc-dis.c (struct ppc_mopt): Comment.
875 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
876
c0c31e91
RZ		 8772017-03-27 Rinat Zelig <rinat@mellanox.com>
878
879 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
880 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
881 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
882 (insert_nps_misc_imm_offset): New function.
883 (extract_nps_misc imm_offset): New function.
884 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
885 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
886
2253c8f0
AK		 8872017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
888
889 * s390-mkopc.c (main): Remove vx2 check.
890 * s390-opc.txt: Remove vx2 instruction flags.
891
645d3342
RZ		 8922017-03-21 Rinat Zelig <rinat@mellanox.com>
893
894 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
895 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
896 (insert_nps_imm_offset): New function.
897 (extract_nps_imm_offset): New function.
898 (insert_nps_imm_entry): New function.
899 (extract_nps_imm_entry): New function.
900
4b94dd2d
AM		 9012017-03-17 Alan Modra <amodra@gmail.com>
902
903 PR 21248
904 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
905 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
906 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
907
b416fe87
KC		 9082017-03-14 Kito Cheng <kito.cheng@gmail.com>
909
910 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
911 <c.andi>: Likewise.
912 <c.addiw> Likewise.
913
03b039a5
KC		 9142017-03-14 Kito Cheng <kito.cheng@gmail.com>
915
916 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
917
2c232b83
AW		 9182017-03-13 Andrew Waterman <andrew@sifive.com>
919
920 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
921 <srl> Likewise.
922 <srai> Likewise.
923 <sra> Likewise.
924
86fa6981
L		 9252017-03-09 H.J. Lu <hongjiu.lu@intel.com>
926
927 * i386-gen.c (opcode_modifiers): Replace S with Load.
928 * i386-opc.h (S): Removed.
929 (Load): New.
930 (i386_opcode_modifier): Replace s with load.
931 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
932 and {evex}. Replace S with Load.
933 * i386-tbl.h: Regenerated.
934
c1fe188b
L		 9352017-03-09 H.J. Lu <hongjiu.lu@intel.com>
936
937 * i386-opc.tbl: Use CpuCET on rdsspq.
938 * i386-tbl.h: Regenerated.
939
4b8b687e
PB		 9402017-03-08 Peter Bergner <bergner@vnet.ibm.com>
941
942 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
943 <vsx>: Do not use PPC_OPCODE_VSX3;
944
1437d063
PB		 9452017-03-08 Peter Bergner <bergner@vnet.ibm.com>
946
947 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
948
603555e5
L		 9492017-03-06 H.J. Lu <hongjiu.lu@intel.com>
950
951 * i386-dis.c (REG_0F1E_MOD_3): New enum.
952 (MOD_0F1E_PREFIX_1): Likewise.
953 (MOD_0F38F5_PREFIX_2): Likewise.
954 (MOD_0F38F6_PREFIX_0): Likewise.
955 (RM_0F1E_MOD_3_REG_7): Likewise.
956 (PREFIX_MOD_0_0F01_REG_5): Likewise.
957 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
958 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
959 (PREFIX_0F1E): Likewise.
960 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
961 (PREFIX_0F38F5): Likewise.
962 (dis386_twobyte): Use PREFIX_0F1E.
963 (reg_table): Add REG_0F1E_MOD_3.
964 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
965 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
966 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
967 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
968 (three_byte_table): Use PREFIX_0F38F5.
969 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
970 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
971 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
972 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
973 PREFIX_MOD_3_0F01_REG_5_RM_2.
974 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
975 (cpu_flags): Add CpuCET.
976 * i386-opc.h (CpuCET): New enum.
977 (CpuUnused): Commented out.
978 (i386_cpu_flags): Add cpucet.
979 * i386-opc.tbl: Add Intel CET instructions.
980 * i386-init.h: Regenerated.
981 * i386-tbl.h: Likewise.
982
73f07bff
AM		 9832017-03-06 Alan Modra <amodra@gmail.com>
984
985 PR 21124
986 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
987 (extract_raq, extract_ras, extract_rbx): New functions.
988 (powerpc_operands): Use opposite corresponding insert function.
989 (Q_MASK): Define.
990 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
991 register restriction.
992
65b48a81
PB		 9932017-02-28 Peter Bergner <bergner@vnet.ibm.com>
994
995 * disassemble.c Include "safe-ctype.h".
996 (disassemble_init_for_target): Handle s390 init.
997 (remove_whitespace_and_extra_commas): New function.
998 (disassembler_options_cmp): Likewise.
999 * arm-dis.c: Include "libiberty.h".
1000 (NUM_ELEM): Delete.
1001 (regnames): Use long disassembler style names.
1002 Add force-thumb and no-force-thumb options.
1003 (NUM_ARM_REGNAMES): Rename from this...
1004 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1005 (get_arm_regname_num_options): Delete.
1006 (set_arm_regname_option): Likewise.
1007 (get_arm_regnames): Likewise.
1008 (parse_disassembler_options): Likewise.
1009 (parse_arm_disassembler_option): Rename from this...
1010 (parse_arm_disassembler_options): ...to this. Make static.
1011 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1012 (print_insn): Use parse_arm_disassembler_options.
1013 (disassembler_options_arm): New function.
1014 (print_arm_disassembler_options): Handle updated regnames.
1015 * ppc-dis.c: Include "libiberty.h".
1016 (ppc_opts): Add "32" and "64" entries.
1017 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1018 (powerpc_init_dialect): Add break to switch statement.
1019 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1020 (disassembler_options_powerpc): New function.
1021 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1022 Remove printing of "32" and "64".
1023 * s390-dis.c: Include "libiberty.h".
1024 (init_flag): Remove unneeded variable.
1025 (struct s390_options_t): New structure type.
1026 (options): New structure.
1027 (init_disasm): Rename from this...
1028 (disassemble_init_s390): ...to this. Add initializations for
1029 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1030 (print_insn_s390): Delete call to init_disasm.
1031 (disassembler_options_s390): New function.
1032 (print_s390_disassembler_options): Print using information from
1033 struct 'options'.
1034 * po/opcodes.pot: Regenerate.
1035
15c7c1d8
JB		 10362017-02-28 Jan Beulich <jbeulich@suse.com>
1037
1038 * i386-dis.c (PCMPESTR_Fixup): New.
1039 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1040 (prefix_table): Use PCMPESTR_Fixup.
1041 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1042 PCMPESTR_Fixup.
1043 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1044 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1045 Split 64-bit and non-64-bit variants.
1046 * opcodes/i386-tbl.h: Re-generate.
1047
582e12bf
RS		 10482017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1049
1050 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1051 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1052 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1053 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1054 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1055 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1056 (OP_SVE_V_HSD): New macros.
1057 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1058 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1059 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1060 (aarch64_opcode_table): Add new SVE instructions.
1061 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1062 for rotation operands. Add new SVE operands.
1063 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1064 (ins_sve_quad_index): Likewise.
1065 (ins_imm_rotate): Split into...
1066 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1067 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1068 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1069 functions.
1070 (aarch64_ins_sve_addr_ri_s4): New function.
1071 (aarch64_ins_sve_quad_index): Likewise.
1072 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1073 * aarch64-asm-2.c: Regenerate.
1074 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1075 (ext_sve_quad_index): Likewise.
1076 (ext_imm_rotate): Split into...
1077 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1078 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1079 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1080 functions.
1081 (aarch64_ext_sve_addr_ri_s4): New function.
1082 (aarch64_ext_sve_quad_index): Likewise.
1083 (aarch64_ext_sve_index): Allow quad indices.
1084 (do_misc_decoding): Likewise.
1085 * aarch64-dis-2.c: Regenerate.
1086 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1087 aarch64_field_kinds.
1088 (OPD_F_OD_MASK): Widen by one bit.
1089 (OPD_F_NO_ZR): Bump accordingly.
1090 (get_operand_field_width): New function.
1091 * aarch64-opc.c (fields): Add new SVE fields.
1092 (operand_general_constraint_met_p): Handle new SVE operands.
1093 (aarch64_print_operand): Likewise.
1094 * aarch64-opc-2.c: Regenerate.
1095
f482d304
RS		 10962017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1097
1098 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1099 (aarch64_feature_compnum): ...this.
1100 (SIMD_V8_3): Replace with...
1101 (COMPNUM): ...this.
1102 (CNUM_INSN): New macro.
1103 (aarch64_opcode_table): Use it for the complex number instructions.
1104
7db2c588
JB		 11052017-02-24 Jan Beulich <jbeulich@suse.com>
1106
1107 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1108
1e9d41d4
SL		 11092017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1110
1111 Add support for associating SPARC ASIs with an architecture level.
1112 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1113 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1114 decoding of SPARC ASIs.
1115
53c4d625
JB		 11162017-02-23 Jan Beulich <jbeulich@suse.com>
1117
1118 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1119 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1120
11648de5
JB		 11212017-02-21 Jan Beulich <jbeulich@suse.com>
1122
1123 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1124 1 (instead of to itself). Correct typo.
1125
f98d33be
AW		 11262017-02-14 Andrew Waterman <andrew@sifive.com>
1127
1128 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1129 pseudoinstructions.
1130
773fb663
RS		 11312017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1132
1133 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1134 (aarch64_sys_reg_supported_p): Handle them.
1135
cc07cda6
CZ		 11362017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1137
1138 * arc-opc.c (UIMM6_20R): Define.
1139 (SIMM12_20): Use above.
1140 (SIMM12_20R): Define.
1141 (SIMM3_5_S): Use above.
1142 (UIMM7_A32_11R_S): Define.
1143 (UIMM7_9_S): Use above.
1144 (UIMM3_13R_S): Define.
1145 (SIMM11_A32_7_S): Use above.
1146 (SIMM9_8R): Define.
1147 (UIMM10_A32_8_S): Use above.
1148 (UIMM8_8R_S): Define.
1149 (W6): Use above.
1150 (arc_relax_opcodes): Use all above defines.
1151
66a5a740
VG		 11522017-02-15 Vineet Gupta <vgupta@synopsys.com>
1153
1154 * arc-regs.h: Distinguish some of the registers different on
1155 ARC700 and HS38 cpus.
1156
7e0de605
AM		 11572017-02-14 Alan Modra <amodra@gmail.com>
1158
1159 PR 21118
1160 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1161 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1162
54064fdb
AM		 11632017-02-11 Stafford Horne <shorne@gmail.com>
1164 Alan Modra <amodra@gmail.com>
1165
1166 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1167 Use insn_bytes_value and insn_int_value directly instead. Don't
1168 free allocated memory until function exit.
1169
dce75bf9
NP		 11702017-02-10 Nicholas Piggin <npiggin@gmail.com>
1171
1172 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1173
1b7e3d2f
NC		 11742017-02-03 Nick Clifton <nickc@redhat.com>
1175
1176 PR 21096
1177 * aarch64-opc.c (print_register_list): Ensure that the register
1178 list index will fir into the tb buffer.
1179 (print_register_offset_address): Likewise.
1180 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1181
8ec5cf65
AD		 11822017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1183
1184 PR 21056
1185 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1186 instructions when the previous fetch packet ends with a 32-bit
1187 instruction.
1188
a1aa5e81
DD		 11892017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1190
1191 * pru-opc.c: Remove vague reference to a future GDB port.
1192
add3afb2
NC		 11932017-01-20 Nick Clifton <nickc@redhat.com>
1194
1195 * po/ga.po: Updated Irish translation.
1196
c13a63b0
SN		 11972017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1198
1199 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1200
9608051a
YQ		 12012017-01-13 Yao Qi <yao.qi@linaro.org>
1202
1203 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1204 if FETCH_DATA returns 0.
1205 (m68k_scan_mask): Likewise.
1206 (print_insn_m68k): Update code to handle -1 return value.
1207
f622ea96
YQ		 12082017-01-13 Yao Qi <yao.qi@linaro.org>
1209
1210 * m68k-dis.c (enum print_insn_arg_error): New.
1211 (NEXTBYTE): Replace -3 with
1212 PRINT_INSN_ARG_MEMORY_ERROR.
1213 (NEXTULONG): Likewise.
1214 (NEXTSINGLE): Likewise.
1215 (NEXTDOUBLE): Likewise.
1216 (NEXTDOUBLE): Likewise.
1217 (NEXTPACKED): Likewise.
1218 (FETCH_ARG): Likewise.
1219 (FETCH_DATA): Update comments.
1220 (print_insn_arg): Update comments. Replace magic numbers with
1221 enum.
1222 (match_insn_m68k): Likewise.
1223
620214f7
IT		 12242017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1225
1226 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1227 * i386-dis-evex.h (evex_table): Updated.
1228 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1229 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1230 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1231 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1232 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1233 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1234 * i386-init.h: Regenerate.
1235 * i386-tbl.h: Ditto.
1236
d95014a2
YQ		 12372017-01-12 Yao Qi <yao.qi@linaro.org>
1238
1239 * msp430-dis.c (msp430_singleoperand): Return -1 if
1240 msp430dis_opcode_signed returns false.
1241 (msp430_doubleoperand): Likewise.
1242 (msp430_branchinstr): Return -1 if
1243 msp430dis_opcode_unsigned returns false.
1244 (msp430x_calla_instr): Likewise.
1245 (print_insn_msp430): Likewise.
1246
0ae60c3e
NC		 12472017-01-05 Nick Clifton <nickc@redhat.com>
1248
1249 PR 20946
1250 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1251 could not be matched.
1252 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1253 NULL.
1254
d74d4880
SN		 12552017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1256
1257 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1258 (aarch64_opcode_table): Use RCPC_INSN.
1259
cc917fd9
KC		 12602017-01-03 Kito Cheng <kito.cheng@gmail.com>
1261
1262 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1263 extension.
1264 * riscv-opcodes/all-opcodes: Likewise.
1265
b52d3cfc
DP		 12662017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1267
1268 * riscv-dis.c (print_insn_args): Add fall through comment.
1269
f90c58d5
NC		 12702017-01-03 Nick Clifton <nickc@redhat.com>
1271
1272 * po/sr.po: New Serbian translation.
1273 * configure.ac (ALL_LINGUAS): Add sr.
1274 * configure: Regenerate.
1275
f47b0d4a
AM		 12762017-01-02 Alan Modra <amodra@gmail.com>
1277
1278 * epiphany-desc.h: Regenerate.
1279 * epiphany-opc.h: Regenerate.
1280 * fr30-desc.h: Regenerate.
1281 * fr30-opc.h: Regenerate.
1282 * frv-desc.h: Regenerate.
1283 * frv-opc.h: Regenerate.
1284 * ip2k-desc.h: Regenerate.
1285 * ip2k-opc.h: Regenerate.
1286 * iq2000-desc.h: Regenerate.
1287 * iq2000-opc.h: Regenerate.
1288 * lm32-desc.h: Regenerate.
1289 * lm32-opc.h: Regenerate.
1290 * m32c-desc.h: Regenerate.
1291 * m32c-opc.h: Regenerate.
1292 * m32r-desc.h: Regenerate.
1293 * m32r-opc.h: Regenerate.
1294 * mep-desc.h: Regenerate.
1295 * mep-opc.h: Regenerate.
1296 * mt-desc.h: Regenerate.
1297 * mt-opc.h: Regenerate.
1298 * or1k-desc.h: Regenerate.
1299 * or1k-opc.h: Regenerate.
1300 * xc16x-desc.h: Regenerate.
1301 * xc16x-opc.h: Regenerate.
1302 * xstormy16-desc.h: Regenerate.
1303 * xstormy16-opc.h: Regenerate.
1304
2571583a
AM		 13052017-01-02 Alan Modra <amodra@gmail.com>
1306
1307 Update year range in copyright notice of all files.
1308
5c1ad6b5 1309For older changes see ChangeLog-2016
3499769a 1310\f
5c1ad6b5 1311Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1312
1313Copying and distribution of this file, with or without modification,
1314are permitted in any medium without royalty provided the copyright
1315notice and this notice are preserved.
1316
1317Local Variables:
1318mode: change-log
1319left-margin: 8
1320fill-column: 74
1321version-control: never
1322End:
GDB Binutils - Deliverables
This page took 0.153765 seconds and 4 git commands to generate.