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2012-11-09 Yao Qi <yao@codesourcery.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
6febeb74
AM		 12012-11-08 Alan Modra <amodra@gmail.com>
2
3 * po/POTFILES.in: Regenerate.
4
d17dce55
AM		 52012-11-05 Alan Modra <amodra@gmail.com>
6
7 * configure.in: Apply 2012-09-10 change to config.in here.
8
aac129d7
AK		 92012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
10
11 * s390-mkopc.c: Accept empty lines in s390-opc.txt.
d17dce55
AM		 12 * s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2
13 and RRF_RMRR.
aac129d7
AK		 14 * s390-opc.txt: Add new instructions. New instruction type for lptea.
15
747a4ac1
CG		 162012-10-26 Christian Groessler <chris@groessler.org>
17
18 * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb,
19 trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb). Remove
20 non-existing opcode trtrb.
21 * z8k-opc.h: Regenerate.
22
62082a42
AM		 232012-10-26 Alan Modra <amodra@gmail.com>
24
25 * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.
26
6c067bbb
RM		 272012-10-24 Roland McGrath <mcgrathr@google.com>
28
29 * i386-dis.c (ckprefix): When bailing out for fwait with prefixes,
30 set rex_used to rex.
31
ab4437c3
PB		 322012-10-22 Peter Bergner <bergner@vnet.ibm.com>
33
34 * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.
35
9a176a4a
TT		 362012-10-18 Tom Tromey <tromey@redhat.com>
37
38 * tic54x-dis.c (print_instruction): Don't use K&R style.
39 (print_parallel_instruction, sprint_dual_address)
40 (sprint_indirect_address, sprint_direct_address, sprint_mmr)
41 (sprint_cc2, sprint_condition): Likewise.
42
4ad3b7ef
KT		 432012-10-18 Kai Tietz <ktietz@redhat.com>
44
45 * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize
46 value with a default.
47 (do_special_encoding): Likewise.
48 (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
49 variables with default.
50 * arc-dis.c (write_comments_): Don't use strncat due
51 size of state->commentBuffer pointer isn't predictable.
52
b7a54b55
YZ		 532012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
54
55 * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
56 rmr_el3; remove daifset and daifclr.
57
9b61754a
YZ		 582012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
59
60 * aarch64-opc.c (operand_general_constraint_met_p): Change to check
61 the alignment of addr.offset.imm instead of that of shifter.amount for
62 operand type AARCH64_OPND_ADDR_UIMM12.
63
f8ece37f
RE		 642012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
65
66 * arm-dis.c: Use preferred form of vrint instruction variants
67 for disassembly.
68
5e5c50d3
NE		 692012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
70
71 * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
72 * i386-init.h: Regenerated.
73
c7a5aa9c
PB		 742012-10-05 Peter Bergner <bergner@vnet.ibm.com>
75
76 * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
77 * ppc-opc.c (VBA): New define.
78 (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
79 mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.
80
04ee5257
NC		 812012-10-04 Nick Clifton <nickc@redhat.com>
82
83 * v850-dis.c (disassemble): Place square parentheses around second
84 register operand of clr1, not1, set1 and tst1 instructions.
85
cfc72779
AK		 862012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
87
88 * s390-mkopc.c: Support new option zEC12.
89 * s390-opc.c: Add new instruction formats.
90 * s390-opc.txt: Add new instructions for zEC12.
91
1415a2a7
AG		 922012-09-27 Anthony Green <green@moxielogic.com>
93
94 * moxie-dis.c (print_insn_moxie): Print 'bad' instructions.
95 * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD.
96
160a30bb
L		 972012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
98
04ee5257
NC		 99 * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
100 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
160a30bb
L		 101 and CPU_BTVER2_FLAGS.
102 * i386-init.h: Regenerated.
103
60aa667e
L		 1042012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
105
106 * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
107 CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
108 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
109 CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
110 (cpu_flags): Add CpuCX16.
111 * i386-opc.h (CpuCX16): New.
112 (i386_cpu_flags): Add cpucx16.
113 * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
114 * i386-tbl.h: Regenerate.
115 * i386-init.h: Likewise.
116
4b8c8c02
RE		 1172012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
118
60aa667e 119 * arm-dis.c: Changed ldra and strl-form mnemonics
4b8c8c02
RE		 120 to lda and stl-form.
121
83ea18d0
MR		 1222012-09-18 Chao-ying Fu <fu@mips.com>
123
124 * micromips-opc.c (micromips_opcodes): Correct the encoding of
125 the "swxc1" instruction.
126
062f38fa
RE		 1272012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
128
129 * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
130 the parameter 'inst'.
131 (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
132 (convert_mov_to_movewide): Change to assert (0) when
133 aarch64_wide_constant_p returns FALSE.
134
b132a67d
DE		 1352012-09-14 David Edelsohn <dje.gcc@gmail.com>
136
137 * configure: Regenerate.
138
1f9b75dd
AG		 1392012-09-14 Anthony Green <green@moxielogic.com>
140
141 * moxie-dis.c (print_insn_moxie): Branch targets are relative to
142 the address after the branch instruction.
143
e202fa84
AG		 1442012-09-13 Anthony Green <green@moxielogic.com>
145
146 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
147
00716ab1
AM		 1482012-09-10 Matthias Klose <doko@ubuntu.com>
149
150 * config.in: Disable sanity check for kfreebsd.
151
6d2920c8
L		 1522012-09-10 H.J. Lu <hongjiu.lu@intel.com>
153
154 * configure: Regenerated.
155
b3e14eda
L		 1562012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
157
158 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
159 * ia64-gen.c: Promote completer index type to longlong.
160 (irf_operand): Add new register recognition.
161 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
162 (lookup_specifier): Add new resource recognition.
163 (insert_bit_table_ent): Relax abort condition according to the
164 changed completer index type.
165 (print_dis_table): Fix printf format for completer index.
166 * ia64-ic.tbl: Add a new instruction class.
167 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
168 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
169 * ia64-opc.h: Define short names for new operand types.
170 * ia64-raw.tbl: Add new RAW resource for DAHR register.
171 * ia64-waw.tbl: Add new WAW resource for DAHR register.
172 * ia64-asmtab.c: Regenerate.
173
382c72e9
PB		 1742012-08-29 Peter Bergner <bergner@vnet.ibm.com>
175
176 * ppc-opc.c (VXASHB_MASK): New define.
177 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
178
fb048c26
PB		 1792012-08-28 Peter Bergner <bergner@vnet.ibm.com>
180
181 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
182 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
183 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
184 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
185 vupklsh>: Use VXVA_MASK.
186 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
187 <mfvscr>: Use VXVAVB_MASK.
188 <mtvscr>: Use VXVDVA_MASK.
189 <vspltb>: Use VXUIMM4_MASK.
190 <vsplth>: Use VXUIMM3_MASK.
191 <vspltw>: Use VXUIMM2_MASK.
192
3c9017d2
MGD		 1932012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
194
195 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
196
48adcd8e
MGD		 1972012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
198
199 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
200
4f51b4bd
MGD		 2012012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
202
203 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
204
91ff7894
MGD		 2052012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
206
207 * arm-dis.c (neon_opcodes): Add support for AES instructions.
208
c70a8987
MGD		 2092012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
210
211 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
212 conversions.
213
30bdf752
MGD		 2142012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
215
216 * arm-dis.c (coprocessor_opcodes): Add VRINT.
217 (neon_opcodes): Likewise.
218
7e8e6784
MGD		 2192012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
220
221 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
222 variants.
223 (neon_opcodes): Likewise.
224
73924fbc
MGD		 2252012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
226
227 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
228 (neon_opcodes): Likewise.
229
33399f07
MGD		 2302012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
231
232 * arm-dis.c (coprocessor_opcodes): Add VSEL.
233 (print_insn_coprocessor): Add new %<>c bitfield format
234 specifier.
235
9eb6c0f1
MGD		 2362012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
237
238 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
239 (thumb32_opcodes): Likewise.
240 (print_arm_insn): Add support for %<>T formatter.
241
8884b720
MGD		 2422012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
243
244 * arm-dis.c (arm_opcodes): Add HLT.
245 (thumb_opcodes): Likewise.
246
b79f7053
MGD		 2472012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
248
249 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
250
53c4b28b
MGD		 2512012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
252
253 * arm-dis.c (arm_opcodes): Add SEVL.
254 (thumb_opcodes): Likewise.
255 (thumb32_opcodes): Likewise.
256
e797f7e0
MGD		 2572012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
258
259 * arm-dis.c (data_barrier_option): New function.
260 (print_insn_arm): Use data_barrier_option.
261 (print_insn_thumb32): Use data_barrier_option.
262
e2efe87d
MGD		 2632012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
264
265 * arm-dis.c (COND_UNCOND): New constant.
266 (print_insn_coprocessor): Add support for %u format specifier.
267 (print_insn_neon): Likewise.
268
2c63854f
DM		 2692012-08-21 David S. Miller <davem@davemloft.net>
270
271 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
272 F3F4 macro.
273
e67ed0e8
AM		 2742012-08-20 Edmar Wienskoski <edmar@freescale.com>
275
276 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
277 vabsduh, vabsduw, mviwsplt.
278
7b458c12
L		 2792012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
280
281 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
282 CPU_BTVER2_FLAGS.
283
e67ed0e8 284 * i386-opc.h: Update CpuPRFCHW comment.
7b458c12
L		 285
286 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
287 * i386-init.h: Regenerated.
288 * i386-tbl.h: Likewise.
289
eb80cb87
NC		 2902012-08-17 Nick Clifton <nickc@redhat.com>
291
292 * po/uk.po: New Ukranian translation.
293 * configure.in (ALL_LINGUAS): Add uk.
294 * configure: Regenerate.
295
8baf7b78
PB		 2962012-08-16 Peter Bergner <bergner@vnet.ibm.com>
297
298 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
299 RBX for the third operand.
300 <"lswi">: Use RAX for second and NBI for the third operand.
301
3d557b4c
DD		 3022012-08-15 DJ Delorie <dj@redhat.com>
303
304 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
305 operands, so that data addresses can be corrected when not
306 ES-overridden.
307 * rl78-decode.c: Regenerate.
308 * rl78-dis.c (print_insn_rl78): Make order of modifiers
309 irrelevent. When the 'e' specifier is used on an operand and no
310 ES prefix is provided, adjust address to make it absolute.
311
588925d0
PB		 3122012-08-15 Peter Bergner <bergner@vnet.ibm.com>
313
314 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
315
9f6a6cc0
PB		 3162012-08-15 Peter Bergner <bergner@vnet.ibm.com>
317
318 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
319
fc8c4fd1
MR		 3202012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
321
322 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
323 macros, use local variables for info struct member accesses,
324 update the type of the variable used to hold the instruction
325 word.
326 (print_insn_mips, print_mips16_insn_arg): Likewise.
327 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
328 local variables for info struct member accesses.
329 (print_insn_micromips): Add GET_OP_S local macro.
330 (_print_insn_mips): Update the type of the variable used to hold
331 the instruction word.
332
a06ea964 3332012-08-13 Ian Bolton <ian.bolton@arm.com>
e67ed0e8
AM		 334 Laurent Desnogues <laurent.desnogues@arm.com>
335 Jim MacArthur <jim.macarthur@arm.com>
336 Marcus Shawcroft <marcus.shawcroft@arm.com>
337 Nigel Stephens <nigel.stephens@arm.com>
338 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
339 Richard Earnshaw <rearnsha@arm.com>
340 Sofiane Naci <sofiane.naci@arm.com>
341 Tejas Belagod <tejas.belagod@arm.com>
342 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 343
344 * Makefile.am: Add AArch64.
345 * Makefile.in: Regenerate.
346 * aarch64-asm.c: New file.
347 * aarch64-asm.h: New file.
348 * aarch64-dis.c: New file.
349 * aarch64-dis.h: New file.
350 * aarch64-gen.c: New file.
351 * aarch64-opc.c: New file.
352 * aarch64-opc.h: New file.
353 * aarch64-tbl.h: New file.
354 * configure.in: Add AArch64.
355 * configure: Regenerate.
356 * disassemble.c: Add AArch64.
357 * aarch64-asm-2.c: New file (automatically generated).
358 * aarch64-dis-2.c: New file (automatically generated).
359 * aarch64-opc-2.c: New file (automatically generated).
360 * po/POTFILES.in: Regenerate.
361
35d0a169
MR		 3622012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
363
364 * micromips-opc.c (micromips_opcodes): Update comment.
365 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
366 instructions for IOCT as appropriate.
367 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
368 opcode_is_member.
369 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
370 the result of a check for the -Wno-missing-field-initializers
371 GCC option.
372 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
373 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
374 compilation.
375 (mips16-opc.lo): Likewise.
376 (micromips-opc.lo): Likewise.
377 * aclocal.m4: Regenerate.
378 * configure: Regenerate.
379 * Makefile.in: Regenerate.
380
5c5acbbd
L		 3812012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
382
383 PR gas/14423
384 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
385 * i386-init.h: Regenerated.
386
3c892704
NC		 3872012-08-09 Nick Clifton <nickc@redhat.com>
388
389 * po/vi.po: Updated Vietnamese translation.
390
d7189fa5
RM		 3912012-08-07 Roland McGrath <mcgrathr@google.com>
392
393 * i386-dis.c (reg_table): Fill out REG_0F0D table with
394 AMD-reserved cases as "prefetch".
395 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
396 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
397 (reg_table): Use those under REG_0F18.
398 (mod_table): Add those cases as "nop/reserved".
399
4c692bc7
JB		 4002012-08-07 Jan Beulich <jbeulich@suse.com>
401
402 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
403
de882298
RM		 4042012-08-06 Roland McGrath <mcgrathr@google.com>
405
406 * i386-dis.c (print_insn): Print spaces between multiple excess
407 prefixes. Return actual number of excess prefixes consumed,
408 not always one.
409
410 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
411
7bb15c6f
RM		 4122012-08-06 Roland McGrath <mcgrathr@google.com>
413 Victor Khimenko <khim@google.com>
414 H.J. Lu <hongjiu.lu@intel.com>
415
416 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
417 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
418 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
419 (OP_E_register): Likewise.
420 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
421
3843081d
JBG		 4222012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
423
424 * configure.in: Formatting.
425 * configure: Regenerate.
426
48891606
AM		 4272012-08-01 Alan Modra <amodra@gmail.com>
428
429 * h8300-dis.c: Fix printf arg warnings.
430 * i960-dis.c: Likewise.
431 * mips-dis.c: Likewise.
432 * pdp11-dis.c: Likewise.
433 * sh-dis.c: Likewise.
434 * v850-dis.c: Likewise.
435 * configure.in: Formatting.
436 * configure: Regenerate.
437 * rl78-decode.c: Regenerate.
438 * po/POTFILES.in: Regenerate.
439
03f66e8a 4402012-07-31 Chao-Ying Fu <fu@mips.com>
e67ed0e8
AM		 441 Catherine Moore <clm@codesourcery.com>
442 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 443
444 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
445 (DSP_VOLA): Likewise.
446 (D32, D33): Likewise.
447 (micromips_opcodes): Add DSP ASE instructions.
48891606 448 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
03f66e8a
MR		 449 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
450
94948e64
JB		 4512012-07-31 Jan Beulich <jbeulich@suse.com>
452
453 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
454 instruction group. Mark as requiring AVX2.
455 * i386-tbl.h: Re-generate.
456
a6dc81d2
NC		 4572012-07-30 Nick Clifton <nickc@redhat.com>
458
459 * po/opcodes.pot: Updated template.
460 * po/es.po: Updated Spanish translation.
461 * po/fi.po: Updated Finnish translation.
462
c4dd807e
MF		 4632012-07-27 Mike Frysinger <vapier@gentoo.org>
464
465 * configure.in (BFD_VERSION): Run bfd/configure --version and
466 parse the output of that.
467 * configure: Regenerate.
468
03edbe3b
JL		 4692012-07-25 James Lemke <jwlemke@codesourcery.com>
470
471 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
472
63d08c68
NC		 4732012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
474 Dr David Alan Gilbert <dave@treblig.org>
d908c8af
NC		 475
476 PR binutils/13135
477 * arm-dis.c: Add necessary casts for printing integer values.
478 Use %s when printing string values.
479 * hppa-dis.c: Likewise.
480 * m68k-dis.c: Likewise.
481 * microblaze-dis.c: Likewise.
482 * mips-dis.c: Likewise.
483 * sparc-dis.c: Likewise.
484
ff688e1f
L		 4852012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
486
487 PR binutils/14355
488 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
489 (VEX_LEN_0FXOP_08_CD): Likewise.
490 (VEX_LEN_0FXOP_08_CE): Likewise.
491 (VEX_LEN_0FXOP_08_CF): Likewise.
492 (VEX_LEN_0FXOP_08_EC): Likewise.
493 (VEX_LEN_0FXOP_08_ED): Likewise.
494 (VEX_LEN_0FXOP_08_EE): Likewise.
495 (VEX_LEN_0FXOP_08_EF): Likewise.
496 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
497 vpcomub, vpcomuw, vpcomud, vpcomuq.
498 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
499 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
500 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
501 VEX_LEN_0FXOP_08_EF.
502
e2e1fcde
L		 5032012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
504
505 * i386-dis.c (PREFIX_0F38F6): New.
506 (prefix_table): Add adcx, adox instructions.
507 (three_byte_table): Use PREFIX_0F38F6.
508 (mod_table): Add rdseed instruction.
509 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
510 (cpu_flags): Likewise.
511 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
512 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
513 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
514 prefetchw.
515 * i386-tbl.h: Regenerate.
516 * i386-init.h: Likewise.
517
8b99bf0b
TS		 5182012-07-05 Thomas Schwinge <thomas@codesourcery.com>
519
f4263ca2 520 * mips-dis.c: Remove gratuitous newline.
8b99bf0b 521
416cf80a
SK		 5222012-07-05 Sean Keys <skeys@ipdatasys.com>
523
524 * xgate-dis.c: Removed an IF statement that will
e67ed0e8
AM		 525 always be false due to overlapping operand masks.
526 * xgate-opc.c: Corrected 'com' opcode entry and
527 fixed spacing.
416cf80a 528
9fa0f14a
RM		 5292012-07-02 Roland McGrath <mcgrathr@google.com>
530
531 * i386-opc.tbl: Add RepPrefixOk to nop.
532 * i386-tbl.h: Regenerate.
533
4c6a93d3
NC		 5342012-06-28 Nick Clifton <nickc@redhat.com>
535
536 * po/vi.po: Updated Vietnamese translation.
537
29c048b6
RM		 5382012-06-22 Roland McGrath <mcgrathr@google.com>
539
fe13e45b
RM		 540 * i386-opc.tbl: Add RepPrefixOk to ret.
541 * i386-tbl.h: Regenerate.
542
29c048b6
RM		 543 * i386-opc.h (RepPrefixOk): New enum constant.
544 (i386_opcode_modifier): New bitfield 'repprefixok'.
545 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
546 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
547 instructions that have IsString.
548 * i386-tbl.h: Regenerate.
549
c7a8dbf9
AS		 5502012-06-11 Andreas Schwab <schwab@linux-m68k.org>
551
552 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
553 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
554 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
555 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
556 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
557 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
558 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
559 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
560 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
561
94caa966
AM		 5622012-05-19 Alan Modra <amodra@gmail.com>
563
564 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
565 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
566
5eb3690e
AM		 5672012-05-18 Alan Modra <amodra@gmail.com>
568
71fe7bab
AM		 569 * ia64-opc.c: Remove #include "ansidecl.h".
570 * z8kgen.c: Include sysdep.h first.
571
5eb3690e
AM		 572 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
573 * bfin-dis.c: Likewise.
574 * i860-dis.c: Likewise.
575 * ia64-dis.c: Likewise.
576 * ia64-gen.c: Likewise.
577 * m68hc11-dis.c: Likewise.
578 * mmix-dis.c: Likewise.
579 * msp430-dis.c: Likewise.
580 * or32-dis.c: Likewise.
581 * rl78-dis.c: Likewise.
582 * rx-dis.c: Likewise.
583 * tic4x-dis.c: Likewise.
584 * tilegx-opc.c: Likewise.
585 * tilepro-opc.c: Likewise.
586 * rx-decode.c: Regenerate.
587
a4ebc835
AM		 5882012-05-17 James Lemke <jwlemke@codesourcery.com>
589
590 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
591
98c76446
AM		 5922012-05-17 James Lemke <jwlemke@codesourcery.com>
593
594 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
595
df7b86aa
NC		 5962012-05-17 Daniel Richard G. <skunk@iskunk.org>
597 Nick Clifton <nickc@redhat.com>
598
599 PR 14072
600 * configure.in: Add check that sysdep.h has been included before
601 any system header files.
602 * configure: Regenerate.
603 * config.in: Regenerate.
604 * sysdep.h: Generate an error if included before config.h.
605 * alpha-opc.c: Include sysdep.h before any other header file.
606 * alpha-dis.c: Likewise.
607 * avr-dis.c: Likewise.
608 * cgen-opc.c: Likewise.
609 * cr16-dis.c: Likewise.
610 * cris-dis.c: Likewise.
611 * crx-dis.c: Likewise.
612 * d10v-dis.c: Likewise.
613 * d10v-opc.c: Likewise.
614 * d30v-dis.c: Likewise.
615 * d30v-opc.c: Likewise.
616 * h8500-dis.c: Likewise.
617 * i370-dis.c: Likewise.
618 * i370-opc.c: Likewise.
619 * m10200-dis.c: Likewise.
620 * m10300-dis.c: Likewise.
621 * micromips-opc.c: Likewise.
622 * mips-opc.c: Likewise.
623 * mips61-opc.c: Likewise.
624 * moxie-dis.c: Likewise.
625 * or32-opc.c: Likewise.
626 * pj-dis.c: Likewise.
627 * ppc-dis.c: Likewise.
628 * ppc-opc.c: Likewise.
629 * s390-dis.c: Likewise.
630 * sh-dis.c: Likewise.
631 * sh64-dis.c: Likewise.
632 * sparc-dis.c: Likewise.
633 * sparc-opc.c: Likewise.
634 * spu-dis.c: Likewise.
635 * tic30-dis.c: Likewise.
636 * tic54x-dis.c: Likewise.
637 * tic80-dis.c: Likewise.
638 * tic80-opc.c: Likewise.
639 * tilegx-dis.c: Likewise.
640 * tilepro-dis.c: Likewise.
641 * v850-dis.c: Likewise.
642 * v850-opc.c: Likewise.
643 * vax-dis.c: Likewise.
644 * w65-dis.c: Likewise.
645 * xgate-dis.c: Likewise.
646 * xtensa-dis.c: Likewise.
647 * rl78-decode.opc: Likewise.
648 * rl78-decode.c: Regenerate.
649 * rx-decode.opc: Likewise.
650 * rx-decode.c: Regenerate.
651
e1dad58d
AM		 6522012-05-17 Alan Modra <amodra@gmail.com>
653
654 * ppc_dis.c: Don't include elf/ppc.h.
655
101af531
NC		 6562012-05-16 Meador Inge <meadori@codesourcery.com>
657
658 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
659 to PUSH/POP {reg}.
660
6927f982
NC		 6612012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
662 Stephane Carrez <stcarrez@nerim.fr>
663
664 * configure.in: Add S12X and XGATE co-processor support to m68hc11
665 target.
666 * disassemble.c: Likewise.
667 * configure: Regenerate.
668 * m68hc11-dis.c: Make objdump output more consistent, use hex
669 instead of decimal and use 0x prefix for hex.
670 * m68hc11-opc.c: Add S12X and XGATE opcodes.
671
b9c361e0
JL		 6722012-05-14 James Lemke <jwlemke@codesourcery.com>
673
674 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
675 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
676 (vle_opcd_indices): New array.
677 (lookup_vle): New function.
678 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
679 (print_insn_powerpc): Likewise.
680 * ppc-opc.c: Likewise.
681
6822012-05-14 Catherine Moore <clm@codesourcery.com>
683 Maciej W. Rozycki <macro@codesourcery.com>
684 Rhonda Wittels <rhonda@codesourcery.com>
685 Nathan Froyd <froydnj@codesourcery.com>
686
687 * ppc-opc.c (insert_arx, extract_arx): New functions.
688 (insert_ary, extract_ary): New functions.
689 (insert_li20, extract_li20): New functions.
690 (insert_rx, extract_rx): New functions.
691 (insert_ry, extract_ry): New functions.
692 (insert_sci8, extract_sci8): New functions.
693 (insert_sci8n, extract_sci8n): New functions.
694 (insert_sd4h, extract_sd4h): New functions.
695 (insert_sd4w, extract_sd4w): New functions.
696 (insert_vlesi, extract_vlesi): New functions.
697 (insert_vlensi, extract_vlensi): New functions.
698 (insert_vleui, extract_vleui): New functions.
699 (insert_vleil, extract_vleil): New functions.
700 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
701 (BI16, BI32, BO32, B8): New.
702 (B15, B24, CRD32, CRS): New.
703 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
704 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
705 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
706 (SH6_MASK): Use PPC_OPSHIFT_INV.
707 (SI8, UI5, OIMM5, UI7, BO16): New.
708 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
709 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
710 (ALLOW8_SPRG): New.
711 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
712 (OPVUP, OPVUP_MASK OPVUP): New
713 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
714 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
715 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
716 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
717 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
718 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
719 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
720 (SE_IM5, SE_IM5_MASK): New.
721 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
722 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
723 (BO32DNZ, BO32DZ): New.
724 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
725 (PPCVLE): New.
726 (powerpc_opcodes): Add new VLE instructions. Update existing
727 instruction to include PPCVLE if supported.
728 * ppc-dis.c (ppc_opts): Add vle entry.
729 (get_powerpc_dialect): New function.
730 (powerpc_init_dialect): VLE support.
731 (print_insn_big_powerpc): Call get_powerpc_dialect.
732 (print_insn_little_powerpc): Likewise.
733 (operand_value_powerpc): Handle negative shift counts.
734 (print_insn_powerpc): Handle 2-byte instruction lengths.
735
208a4923
NC		 7362012-05-11 Daniel Richard G. <skunk@iskunk.org>
737
738 PR binutils/14028
739 * configure.in: Invoke ACX_HEADER_STRING.
740 * configure: Regenerate.
741 * config.in: Regenerate.
742 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
743 string.h and strings.h.
744
6750a3a7
NC		 7452012-05-11 Nick Clifton <nickc@redhat.com>
746
747 PR binutils/14006
748 * arm-dis.c (print_insn): Fix detection of instruction mode in
749 files containing multiple executable sections.
750
f6c1a2d5
NC		 7512012-05-03 Sean Keys <skeys@ipdatasys.com>
752
753 * Makefile.in, configure: regenerate
754 * disassemble.c (disassembler): Recognize ARCH_XGATE.
755 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
756 New functions.
757 * configure.in: Recognize xgate.
758 * xgate-dis.c, xgate-opc.c: New files for support of xgate
759 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
760 and opcode generation for xgate.
761
78e98aab
DD		 7622012-04-30 DJ Delorie <dj@redhat.com>
763
764 * rx-decode.opc (MOV): Do not sign-extend immediates which are
765 already the maximum bit size.
766 * rx-decode.c: Regenerate.
767
ec668d69
DM		 7682012-04-27 David S. Miller <davem@davemloft.net>
769
2e52845b
DM		 770 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
771 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
772
58004e23
DM		 773 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
774 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
775
698544e1
DM		 776 * sparc-opc.c (CBCOND): New define.
777 (CBCOND_XCC): Likewise.
778 (cbcond): New helper macro.
779 (sparc_opcodes): Add compare-and-branch instructions.
780
6cda1326
DM		 781 * sparc-dis.c (print_insn_sparc): Handle ')'.
782 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
783
ec668d69
DM		 784 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
785 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
786
2615994e
DM		 7872012-04-12 David S. Miller <davem@davemloft.net>
788
789 * sparc-dis.c (X_DISP10): Define.
790 (print_insn_sparc): Handle '='.
791
5de10af0
MF		 7922012-04-01 Mike Frysinger <vapier@gentoo.org>
793
794 * bfin-dis.c (fmtconst): Replace decimal handling with a single
795 sprintf call and the '*' field width.
796
55a36193
MK		 7972012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
798
799 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
800
d6688282
AM		 8012012-03-16 Alan Modra <amodra@gmail.com>
802
803 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
804 (powerpc_opcd_indices): Bump array size.
805 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
806 corresponding to unused opcodes to following entry.
807 (lookup_powerpc): New function, extracted and optimised from..
808 (print_insn_powerpc): ..here.
809
b240011a
AM		 8102012-03-15 Alan Modra <amodra@gmail.com>
811 James Lemke <jwlemke@codesourcery.com>
812
813 * disassemble.c (disassemble_init_for_target): Handle ppc init.
814 * ppc-dis.c (private): New var.
815 (powerpc_init_dialect): Don't return calloc failure, instead use
816 private.
817 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
818 (powerpc_opcd_indices): New array.
819 (disassemble_init_powerpc): New function.
820 (print_insn_big_powerpc): Don't init dialect here.
821 (print_insn_little_powerpc): Likewise.
822 (print_insn_powerpc): Start search using powerpc_opcd_indices.
823
aea77599
AM		 8242012-03-10 Edmar Wienskoski <edmar@freescale.com>
825
826 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
827 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
828 (PPCVEC2, PPCTMR, E6500): New short names.
829 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
830 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
831 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
832 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
833 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
834 optional operands on sync instruction for E6500 target.
835
5333187a
AK		 8362012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
837
838 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
839
a597d2d3
AM		 8402012-02-27 Alan Modra <amodra@gmail.com>
841
842 * mt-dis.c: Regenerate.
843
3f26eb3a
AM		 8442012-02-27 Alan Modra <amodra@gmail.com>
845
846 * v850-opc.c (extract_v8): Rearrange to make it obvious this
847 is the inverse of corresponding insert function.
848 (extract_d22, extract_u9, extract_r4): Likewise.
849 (extract_d9): Correct sign extension.
850 (extract_d16_15): Don't assume "long" is 32 bits, and don't
851 rely on implementation defined behaviour for shift right of
852 signed types.
853 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
854 (extract_d23): Likewise, and correct mask.
855
1f42f8b3
AM		 8562012-02-27 Alan Modra <amodra@gmail.com>
857
858 * crx-dis.c (print_arg): Mask constant to 32 bits.
859 * crx-opc.c (cst4_map): Use int array.
860
cdb06235
AM		 8612012-02-27 Alan Modra <amodra@gmail.com>
862
863 * arc-dis.c (BITS): Don't use shifts to mask off bits.
864 (FIELDD): Sign extend with xor,sub.
865
6f7be959
WL		 8662012-02-25 Walter Lee <walt@tilera.com>
867
868 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
869 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
870 TILEPRO_OPC_LW_TLS_SN.
871
82c2def5
L		 8722012-02-21 H.J. Lu <hongjiu.lu@intel.com>
873
874 * i386-opc.h (HLEPrefixNone): New.
875 (HLEPrefixLock): Likewise.
876 (HLEPrefixAny): Likewise.
877 (HLEPrefixRelease): Likewise.
878
42164a71
L		 8792012-02-08 H.J. Lu <hongjiu.lu@intel.com>
880
881 * i386-dis.c (HLE_Fixup1): New.
882 (HLE_Fixup2): Likewise.
883 (HLE_Fixup3): Likewise.
884 (Ebh1): Likewise.
885 (Evh1): Likewise.
886 (Ebh2): Likewise.
887 (Evh2): Likewise.
888 (Ebh3): Likewise.
889 (Evh3): Likewise.
890 (MOD_C6_REG_7): Likewise.
891 (MOD_C7_REG_7): Likewise.
892 (RM_C6_REG_7): Likewise.
893 (RM_C7_REG_7): Likewise.
894 (XACQUIRE_PREFIX): Likewise.
895 (XRELEASE_PREFIX): Likewise.
896 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
897 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
898 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
899 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
900 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
901 MOD_C6_REG_7 and MOD_C7_REG_7.
902 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
903 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
904 xtest.
905 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
906 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
907
908 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
909 CPU_RTM_FLAGS.
910 (cpu_flags): Add CpuHLE and CpuRTM.
911 (opcode_modifiers): Add HLEPrefixOk.
912
913 * i386-opc.h (CpuHLE): New.
914 (CpuRTM): Likewise.
915 (HLEPrefixOk): Likewise.
916 (i386_cpu_flags): Add cpuhle and cpurtm.
917 (i386_opcode_modifier): Add hleprefixok.
918
919 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
920 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
921 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
922 operand. Add xacquire, xrelease, xabort, xbegin, xend and
923 xtest.
924 * i386-init.h: Regenerated.
925 * i386-tbl.h: Likewise.
926
21abe33a
DD		 9272012-01-24 DJ Delorie <dj@redhat.com>
928
929 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
930 * rl78-decode.c: Regenerate.
931
e20cc039
AM		 9322012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
933
934 PR binutils/10173
935 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
936
e143d25c
AS		 9372012-01-17 Andreas Schwab <schwab@linux-m68k.org>
938
939 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
940 register and move them after pmove with PSR/PCSR register.
941
8729a6f6
L		 9422012-01-13 H.J. Lu <hongjiu.lu@intel.com>
943
944 * i386-dis.c (mod_table): Add vmfunc.
945
946 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
947 (cpu_flags): CpuVMFUNC.
948
949 * i386-opc.h (CpuVMFUNC): New.
950 (i386_cpu_flags): Add cpuvmfunc.
951
952 * i386-opc.tbl: Add vmfunc.
953 * i386-init.h: Regenerated.
954 * i386-tbl.h: Likewise.
5011093d 955
23e1d329 956For older changes see ChangeLog-2011
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RH		 957\f
958Local Variables:
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NC		 959mode: change-log
960left-margin: 8
961fill-column: 74
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RH		 962version-control: never
963End:
GDB Binutils - Deliverables
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