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56b13185
JR		 12011-10-26 Joern Rennecke <joern.rennecke@embecosm.com>
2
3 * disassemble.c (ARCH_epiphany): Move into alphasorted spot.
4
cfb8c092
NC		 52011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
6
7 * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
8 (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
9 epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
10 (CLEANFILES): Add stamp-epiphany.
11 (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
12 (stamp-epiphany): New rule.
13 * configure.in: Handle bfd_epiphany_arch.
14 * disassemble.c (ARCH_epiphany): Define.
15 (disassembler): Handle bfd_arch_epiphany.
16 * epiphany-asm.c: New file.
17 * epiphany-desc.c: New file.
18 * epiphany-desc.h: New file.
19 * epiphany-dis.c: New file.
20 * epiphany-ibld.c: New file.
21 * epiphany-opc.c: New file.
22 * epiphany-opc.h: New file.
23 * Makefile.in: Regenerate.
24 * configure: Regenerate.
25 * po/POTFILES.in: Regenerate.
26 * po/opcodes.pot: Regenerate.
27
c3732716
JB		 282011-10-24 Julian Brown <julian@codesourcery.com>
29
30 * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
31
9cae27dc
AK		 322011-10-21 Jan Glauber <jang@linux.vnet.ibm.com>
33
34 * s390-opc.txt: Add CPUMF instructions.
35
a415b1cd
JB		 362011-10-18 Jie Zhang <jie@codesourcery.com>
37 Julian Brown <julian@codesourcery.com>
38
39 * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
40
d5698657
NC		 412011-10-10 Nick Clifton <nickc@redhat.com>
42
43 * po/es.po: Updated Spanish translation.
44 * po/fi.po: Updated Finnish translation.
45
989993d8
JB		 462011-09-28 Jan Beulich <jbeulich@suse.com>
47
48 * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
49 RBX): New.
50 (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
51 (powerpc_opcodes): Use RAX for second and RBXC for third operand of
52 lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
53 lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
54 mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
55 on DFP quad instructions.
56
92a7795b
DM		 572011-09-27 David S. Miller <davem@davemloft.net>
58
59 * sparc-opc.c (sparc_opcodes): Fix random instruction to write
60 to a float instead of an integer register.
61
e91d1076
DM		 622011-09-26 David S. Miller <davem@davemloft.net>
63
64 * sparc-opc.c (sparc_opcodes): Add integer multiply-add
65 instructions.
66
9e8c70f9
DM		 672011-09-21 David S. Miller <davem@davemloft.net>
68
69 * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
70 bits. Fix "fchksm16" mnemonic.
71
9bf29d72
DM		 722011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
73
74 The changes below bring 'mov' and 'ticc' instructions into line
75 with the V8 SPARC Architecture Manual.
76 * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
77 * sparc-opc.c (sparc_opcodes): Add alias entries for
78 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
79 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
80 * sparc-opc.c (sparc_opcodes): Move/Change entries for
81 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
82 and 'mov imm,%tbr'.
83 * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
84 mov aliases.
85
8dbb9eb3
DM		 86 * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
87 This has been reported as being accepted by the Sun assmebler.
88
cdf49201
DM		 892011-09-08 David S. Miller <davem@davemloft.net>
90
91 * sparc-opc.c (pdistn): Destination is integer not float register.
92
96e67898
AS		 932011-09-07 Andreas Schwab <schwab@linux-m68k.org>
94
b2ea1829 95 PR gas/13145
96e67898
AS		 96 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
97
7cf80422
NC		 982011-08-26 Nick Clifton <nickc@redhat.com>
99
100 * po/es.po: Updated Spanish translation.
101
dc15e575
NC		 1022011-08-22 Nick Clifton <nickc@redhat.com>
103
104 * Makefile.am (CPUDIR): Redfine to point to top level cpu
105 directory.
106 (stamp-frv): Use CPUDIR.
107 (stamp-iq2000): Likewise.
108 (stamp-lm32): Likewise.
109 (stamp-m32c): Likewise.
110 (stamp-mt): Likewise.
111 (stamp-xc16x): Likewise.
112 * Makefile.in: Regenerate.
113
dec0624d
MR		 1142011-08-09 Chao-ying Fu <fu@mips.com>
115 Maciej W. Rozycki <macro@codesourcery.com>
116
117 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
118 and "mips64r2".
119 (print_insn_args, print_insn_micromips): Handle MCU.
120 * micromips-opc.c (MC): New macro.
121 (micromips_opcodes): Add "aclr", "aset" and "iret".
122 * mips-opc.c (MC): New macro.
123 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
124
2b0c8b40
MR		 1252011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
126
127 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
128 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
129 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
130 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
131 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
132 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
133 (WR_s): Update macro.
134 (micromips_opcodes): Update register use flags of: "addiu",
135 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
136 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
137 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
138 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
139 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
140 "swm" and "xor" instructions.
141
ea783ef3
DM		 1422011-08-05 David S. Miller <davem@davemloft.net>
143
144 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
145 (X_RS3): New macro.
146 (print_insn_sparc): Handle '4', '5', and '(' format codes.
147 Accept %asr numbers below 28.
148 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
149 instructions.
150
3929df09
QN		 1512011-08-02 Quentin Neill <quentin.neill@amd.com>
152
153 * i386-dis.c (xop_table): Remove spurious bextr insn.
154
d7921315
L		 1552011-08-01 H.J. Lu <hongjiu.lu@intel.com>
156
157 PR ld/13048
158 * i386-dis.c (print_insn): Optimize info->mach check.
159
00f51a41
L		 1602011-08-01 H.J. Lu <hongjiu.lu@intel.com>
161
162 PR gas/13046
163 * i386-opc.tbl: Add Disp32S to 64bit call.
164 * i386-tbl.h: Regenerated.
165
df58fc94
RS		 1662011-07-24 Chao-ying Fu <fu@mips.com>
167 Maciej W. Rozycki <macro@codesourcery.com>
168
169 * micromips-opc.c: New file.
170 * mips-dis.c (micromips_to_32_reg_b_map): New array.
171 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
172 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
173 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
174 (micromips_to_32_reg_q_map): Likewise.
175 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
176 (micromips_ase): New variable.
177 (is_micromips): New function.
178 (set_default_mips_dis_options): Handle microMIPS ASE.
179 (print_insn_micromips): New function.
180 (is_compressed_mode_p): Likewise.
181 (_print_insn_mips): Handle microMIPS instructions.
182 * Makefile.am (CFILES): Add micromips-opc.c.
183 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
184 * Makefile.in: Regenerate.
185 * configure: Regenerate.
186
187 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
188 (micromips_to_32_reg_i_map): Likewise.
189 (micromips_to_32_reg_m_map): Likewise.
190 (micromips_to_32_reg_n_map): New macro.
191
bcd530a7
RS		 1922011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
193
194 * mips-opc.c (NODS): New macro.
195 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
196 (DSP_VOLA): Likewise.
197 (mips_builtin_opcodes): Add NODS annotation to "deret" and
198 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
199 place of TRAP for "wait", "waiti" and "yield".
200 * mips16-opc.c (NODS): New macro.
201 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
202 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
203 "restore" and "save".
204
7a9068fe
L		 2052011-07-22 H.J. Lu <hongjiu.lu@intel.com>
206
207 * configure.in: Handle bfd_k1om_arch.
208 * configure: Regenerated.
209
210 * disassemble.c (disassembler): Handle bfd_k1om_arch.
211
212 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
213 bfd_mach_k1om_intel_syntax.
214
215 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
216 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
217 (cpu_flags): Add CpuK1OM.
218
219 * i386-opc.h (CpuK1OM): New.
220 (i386_cpu_flags): Add cpuk1om.
221
222 * i386-init.h: Regenerated.
223 * i386-tbl.h: Likewise.
224
1b93226d
NC		 2252011-07-12 Nick Clifton <nickc@redhat.com>
226
227 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
228 accidental change.
229
5d73b1f1
NC		 2302011-07-01 Nick Clifton <nickc@redhat.com>
231
232 PR binutils/12329
233 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
234 insns using post-increment addressing.
235
182ae480
L		 2362011-06-30 H.J. Lu <hongjiu.lu@intel.com>
237
238 * i386-dis.c (vex_len_table): Update rorxS.
239
4cb0953d
L		 2402011-06-30 H.J. Lu <hongjiu.lu@intel.com>
241
242 AVX Programming Reference (June, 2011)
243 * i386-dis.c (vex_len_table): Correct rorxS.
244
245 * i386-opc.tbl: Correct rorx.
246 * i386-tbl.h: Regenerated.
247
906efcbc
L		 2482011-06-29 H.J. Lu <hongjiu.lu@intel.com>
249
250 * tilegx-opc.c (find_opcode): Replace "index" with "i".
251 * tilepro-opc.c (find_opcode): Likewise.
252
ceb94aa5
RS		 2532011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
254
255 * mips16-opc.c (jalrc, jrc): Move earlier in file.
256
f7002f42
L		 2572011-06-21 H.J. Lu <hongjiu.lu@intel.com>
258
259 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
260 PREFIX_VEX_0F388E.
261
56300268
AS		 2622011-06-17 Andreas Schwab <schwab@redhat.com>
263
264 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
265 (MOSTLYCLEANFILES): ... here.
266 * Makefile.in: Regenerate.
267
bcf2cf9f
AM		 2682011-06-14 Alan Modra <amodra@gmail.com>
269
270 * Makefile.in: Regenerate.
271
aa137e4d
NC		 2722011-06-13 Walter Lee <walt@tilera.com>
273
274 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
275 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
276 * Makefile.in: Regenerate.
277 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
278 * configure: Regenerate.
279 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
280 * po/POTFILES.in: Regenerate.
281 * tilegx-dis.c: New file.
282 * tilegx-opc.c: New file.
283 * tilepro-dis.c: New file.
284 * tilepro-opc.c: New file.
285
6c30d220
L		 2862011-06-10 H.J. Lu <hongjiu.lu@intel.com>
287
288 AVX Programming Reference (June, 2011)
289 * i386-dis.c (XMGatherQ): New.
290 * i386-dis.c (EXxmm_mb): New.
291 (EXxmm_mb): Likewise.
292 (EXxmm_mw): Likewise.
293 (EXxmm_md): Likewise.
294 (EXxmm_mq): Likewise.
295 (EXxmmdw): Likewise.
296 (EXxmmqd): Likewise.
297 (VexGatherQ): Likewise.
298 (MVexVSIBDWpX): Likewise.
299 (MVexVSIBQWpX): Likewise.
300 (xmm_mb_mode): Likewise.
301 (xmm_mw_mode): Likewise.
302 (xmm_md_mode): Likewise.
303 (xmm_mq_mode): Likewise.
304 (xmmdw_mode): Likewise.
305 (xmmqd_mode): Likewise.
306 (ymmxmm_mode): Likewise.
307 (vex_vsib_d_w_dq_mode): Likewise.
308 (vex_vsib_q_w_dq_mode): Likewise.
309 (MOD_VEX_0F385A_PREFIX_2): Likewise.
310 (MOD_VEX_0F388C_PREFIX_2): Likewise.
311 (MOD_VEX_0F388E_PREFIX_2): Likewise.
312 (PREFIX_0F3882): Likewise.
313 (PREFIX_VEX_0F3816): Likewise.
314 (PREFIX_VEX_0F3836): Likewise.
315 (PREFIX_VEX_0F3845): Likewise.
316 (PREFIX_VEX_0F3846): Likewise.
317 (PREFIX_VEX_0F3847): Likewise.
318 (PREFIX_VEX_0F3858): Likewise.
319 (PREFIX_VEX_0F3859): Likewise.
320 (PREFIX_VEX_0F385A): Likewise.
321 (PREFIX_VEX_0F3878): Likewise.
322 (PREFIX_VEX_0F3879): Likewise.
323 (PREFIX_VEX_0F388C): Likewise.
324 (PREFIX_VEX_0F388E): Likewise.
325 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
326 (PREFIX_VEX_0F38F5): Likewise.
327 (PREFIX_VEX_0F38F6): Likewise.
328 (PREFIX_VEX_0F3A00): Likewise.
329 (PREFIX_VEX_0F3A01): Likewise.
330 (PREFIX_VEX_0F3A02): Likewise.
331 (PREFIX_VEX_0F3A38): Likewise.
332 (PREFIX_VEX_0F3A39): Likewise.
333 (PREFIX_VEX_0F3A46): Likewise.
334 (PREFIX_VEX_0F3AF0): Likewise.
335 (VEX_LEN_0F3816_P_2): Likewise.
336 (VEX_LEN_0F3819_P_2): Likewise.
337 (VEX_LEN_0F3836_P_2): Likewise.
338 (VEX_LEN_0F385A_P_2_M_0): Likewise.
339 (VEX_LEN_0F38F5_P_0): Likewise.
340 (VEX_LEN_0F38F5_P_1): Likewise.
341 (VEX_LEN_0F38F5_P_3): Likewise.
342 (VEX_LEN_0F38F6_P_3): Likewise.
343 (VEX_LEN_0F38F7_P_1): Likewise.
344 (VEX_LEN_0F38F7_P_2): Likewise.
345 (VEX_LEN_0F38F7_P_3): Likewise.
346 (VEX_LEN_0F3A00_P_2): Likewise.
347 (VEX_LEN_0F3A01_P_2): Likewise.
348 (VEX_LEN_0F3A38_P_2): Likewise.
349 (VEX_LEN_0F3A39_P_2): Likewise.
350 (VEX_LEN_0F3A46_P_2): Likewise.
351 (VEX_LEN_0F3AF0_P_3): Likewise.
352 (VEX_W_0F3816_P_2): Likewise.
353 (VEX_W_0F3818_P_2): Likewise.
354 (VEX_W_0F3819_P_2): Likewise.
355 (VEX_W_0F3836_P_2): Likewise.
356 (VEX_W_0F3846_P_2): Likewise.
357 (VEX_W_0F3858_P_2): Likewise.
358 (VEX_W_0F3859_P_2): Likewise.
359 (VEX_W_0F385A_P_2_M_0): Likewise.
360 (VEX_W_0F3878_P_2): Likewise.
361 (VEX_W_0F3879_P_2): Likewise.
362 (VEX_W_0F3A00_P_2): Likewise.
363 (VEX_W_0F3A01_P_2): Likewise.
364 (VEX_W_0F3A02_P_2): Likewise.
365 (VEX_W_0F3A38_P_2): Likewise.
366 (VEX_W_0F3A39_P_2): Likewise.
367 (VEX_W_0F3A46_P_2): Likewise.
368 (MOD_VEX_0F3818_PREFIX_2): Removed.
369 (MOD_VEX_0F3819_PREFIX_2): Likewise.
370 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
371 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
372 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
373 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
374 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
375 (VEX_LEN_0F3A0E_P_2): Likewise.
376 (VEX_LEN_0F3A0F_P_2): Likewise.
377 (VEX_LEN_0F3A42_P_2): Likewise.
378 (VEX_LEN_0F3A4C_P_2): Likewise.
379 (VEX_W_0F3818_P_2_M_0): Likewise.
380 (VEX_W_0F3819_P_2_M_0): Likewise.
381 (prefix_table): Updated.
382 (three_byte_table): Likewise.
383 (vex_table): Likewise.
384 (vex_len_table): Likewise.
385 (vex_w_table): Likewise.
386 (mod_table): Likewise.
387 (putop): Handle "LW".
388 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
389 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
390 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
391 (OP_EX): Likewise.
392 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
393 vex_vsib_q_w_dq_mode.
394 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
395 (OP_VEX): Likewise.
396
397 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
398 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
399 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
400 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
401 (opcode_modifiers): Add VecSIB.
402
403 * i386-opc.h (CpuAVX2): New.
404 (CpuBMI2): Likewise.
405 (CpuLZCNT): Likewise.
406 (CpuINVPCID): Likewise.
407 (VecSIB128): Likewise.
408 (VecSIB256): Likewise.
409 (VecSIB): Likewise.
410 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
411 (i386_opcode_modifier): Add vecsib.
412
413 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
414 * i386-init.h: Regenerated.
415 * i386-tbl.h: Likewise.
416
d535accd
QN		 4172011-06-03 Quentin Neill <quentin.neill@amd.com>
418
419 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
420 * i386-init.h: Regenerated.
421
f8b960bc
NC		 4222011-06-03 Nick Clifton <nickc@redhat.com>
423
424 PR binutils/12752
425 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
426 computing address offsets.
427 (print_arm_address): Likewise.
428 (print_insn_arm): Likewise.
429 (print_insn_thumb16): Likewise.
430 (print_insn_thumb32): Likewise.
431
26d97720
NS		 4322011-06-02 Jie Zhang <jie@codesourcery.com>
433 Nathan Sidwell <nathan@codesourcery.com>
434 Maciej Rozycki <macro@codesourcery.com>
435
436 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
437 as address offset.
438 (print_arm_address): Likewise. Elide positive #0 appropriately.
439 (print_insn_arm): Likewise.
440
f8b960bc
NC		 4412011-06-02 Nick Clifton <nickc@redhat.com>
442
443 PR gas/12752
444 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
445 passed to print_address_func.
446
cc643b88
NC		 4472011-06-02 Nick Clifton <nickc@redhat.com>
448
449 * arm-dis.c: Fix spelling mistakes.
450 * op/opcodes.pot: Regenerate.
451
c8fa16ed
AK		 4522011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
453
454 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
455 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
456 * s390-opc.txt: Fix cxr instruction type.
457
5e4b319c
AK		 4582011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
459
460 * s390-opc.c: Add new instruction types marking register pair
461 operands.
462 * s390-opc.txt: Match instructions having register pair operands
463 to the new instruction types.
464
fda544a2
NC		 4652011-05-19 Nick Clifton <nickc@redhat.com>
466
467 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
468 operands.
469
4cab4add
QN		 4702011-05-10 Quentin Neill <quentin.neill@amd.com>
471
472 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
473 * i386-init.h: Regenerated.
474
b4e7b885
NC		 4752011-04-27 Nick Clifton <nickc@redhat.com>
476
477 * po/da.po: Updated Danish translation.
478
2f7f7710
AM		 4792011-04-26 Anton Blanchard <anton@samba.org>
480
481 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
482
9887672f
DD		 4832011-04-21 DJ Delorie <dj@redhat.com>
484
485 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
486 * rx-decode.c: Regenerate.
487
3251b375
L		 4882011-04-20 H.J. Lu <hongjiu.lu@intel.com>
489
490 * i386-init.h: Regenerated.
491
b13a3ca6
QN		 4922011-04-19 Quentin Neill <quentin.neill@amd.com>
493
494 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
495 from bdver1 flags.
496
7d063384
NC		 4972011-04-13 Nick Clifton <nickc@redhat.com>
498
499 * v850-dis.c (disassemble): Always print a closing square brace if
500 an opening square brace was printed.
501
32a94698
NC		 5022011-04-12 Nick Clifton <nickc@redhat.com>
503
504 PR binutils/12534
505 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
506 patterns.
507 (print_insn_thumb32): Handle %L.
508
d2cd1205
JB		 5092011-04-11 Julian Brown <julian@codesourcery.com>
510
511 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
512 (print_insn_thumb32): Add APSR bitmask support.
513
1fbaefec
PB		 5142011-04-07 Paul Carroll<pcarroll@codesourcery.com>
515
516 * arm-dis.c (print_insn): init vars moved into private_data structure.
517
67171547
MF		 5182011-03-24 Mike Frysinger <vapier@gentoo.org>
519
520 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
521
8cc66334
EW		 5222011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
523
524 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
525 post-increment to support LPM Z+ instruction. Add support for 'E'
526 constraint for DES instruction.
527 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
528
34e77a92
RS		 5292011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
530
531 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
532
35fc36a8
RS		 5332011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
534
535 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
536 Use branch types instead.
537 (print_insn): Likewise.
538
0067d8fc
MR		 5392011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
540
541 * mips-opc.c (mips_builtin_opcodes): Correct register use
542 annotation of "alnv.ps".
543
3eebd5eb
MR		 5442011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
545
546 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
547
500cccad
MF		 5482011-02-22 Mike Frysinger <vapier@gentoo.org>
549
550 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
551
f5caf9f4
MF		 5522011-02-22 Mike Frysinger <vapier@gentoo.org>
553
554 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
555
e5bc4265
MF		 5562011-02-19 Mike Frysinger <vapier@gentoo.org>
557
558 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
559 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
560 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
561 exception, end_of_registers, msize, memory, bfd_mach.
562 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
563 LB0REG, LC1REG, LT1REG, LB1REG): Delete
564 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
565 (get_allreg): Change to new defines. Fallback to abort().
566
602427c4
MF		 5672011-02-14 Mike Frysinger <vapier@gentoo.org>
568
569 * bfin-dis.c: Add whitespace/parenthesis where needed.
570
298c1ec2
MF		 5712011-02-14 Mike Frysinger <vapier@gentoo.org>
572
573 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
574 than 7.
575
822ce8ee
RW		 5762011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
577
578 * configure: Regenerate.
579
13c02f06
MF		 5802011-02-13 Mike Frysinger <vapier@gentoo.org>
581
582 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
583
4db66394
MF		 5842011-02-13 Mike Frysinger <vapier@gentoo.org>
585
586 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
587 dregs only when P is set, and dregs_lo otherwise.
588
36f44611
MF		 5892011-02-13 Mike Frysinger <vapier@gentoo.org>
590
591 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
592
9805c0a5
MF		 5932011-02-12 Mike Frysinger <vapier@gentoo.org>
594
595 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
596
43a6aa65
MF		 5972011-02-12 Mike Frysinger <vapier@gentoo.org>
598
599 * bfin-dis.c (machine_registers): Delete REG_GP.
600 (reg_names): Delete "GP".
601 (decode_allregs): Change REG_GP to REG_LASTREG.
602
26bb3ddd
MF		 6032011-02-12 Mike Frysinger <vapier@gentoo.org>
604
89c0d58c
MR		 605 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
606 M_IH, M_IU): Delete.
26bb3ddd 607
69b8ea4a
MF		 6082011-02-11 Mike Frysinger <vapier@gentoo.org>
609
610 * bfin-dis.c (reg_names): Add const.
611 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
612 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
613 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
614 decode_counters, decode_allregs): Likewise.
615
42d5f9c6
MS		 6162011-02-09 Michael Snyder <msnyder@vmware.com>
617
56300268 618 * i386-dis.c (OP_J): Parenthesize expression to prevent
42d5f9c6
MS		 619 truncated addresses.
620 (print_insn): Fix indentation off-by-one.
621
4be0c941
NC		 6222011-02-01 Nick Clifton <nickc@redhat.com>
623
624 * po/da.po: Updated Danish translation.
625
6b069ee7
AM		 6262011-01-21 Dave Murphy <davem@devkitpro.org>
627
628 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
629
e3949f17
L		 6302011-01-18 H.J. Lu <hongjiu.lu@intel.com>
631
632 * i386-dis.c (sIbT): New.
633 (b_T_mode): Likewise.
634 (dis386): Replace sIb with sIbT on "pushT".
635 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
636 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
637
752573b2
JK		 6382011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
639
640 * i386-init.h: Regenerated.
641 * i386-tbl.h: Regenerated
642
2a2a0f38
QN		 6432011-01-17 Quentin Neill <quentin.neill@amd.com>
644
645 * i386-dis.c (REG_XOP_TBM_01): New.
646 (REG_XOP_TBM_02): New.
647 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
648 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
649 entries, and add bextr instruction.
650
651 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
652 (cpu_flags): Add CpuTBM.
653
654 * i386-opc.h (CpuTBM) New.
655 (i386_cpu_flags): Add bit cputbm.
656
657 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
658 blcs, blsfill, blsic, t1mskc, and tzmsk.
659
90d6ff62
DD		 6602011-01-12 DJ Delorie <dj@redhat.com>
661
662 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
663
c95354ed
MX		 6642011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
665
666 * mips-dis.c (print_insn_args): Adjust the value to print the real
667 offset for "+c" argument.
668
f7465604
NC		 6692011-01-10 Nick Clifton <nickc@redhat.com>
670
671 * po/da.po: Updated Danish translation.
672
639e30d2
NS		 6732011-01-05 Nathan Sidwell <nathan@codesourcery.com>
674
675 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
676
f12dc422
L		 6772011-01-04 H.J. Lu <hongjiu.lu@intel.com>
678
679 * i386-dis.c (REG_VEX_38F3): New.
680 (PREFIX_0FBC): Likewise.
681 (PREFIX_VEX_38F2): Likewise.
682 (PREFIX_VEX_38F3_REG_1): Likewise.
683 (PREFIX_VEX_38F3_REG_2): Likewise.
684 (PREFIX_VEX_38F3_REG_3): Likewise.
685 (PREFIX_VEX_38F7): Likewise.
686 (VEX_LEN_38F2_P_0): Likewise.
687 (VEX_LEN_38F3_R_1_P_0): Likewise.
688 (VEX_LEN_38F3_R_2_P_0): Likewise.
689 (VEX_LEN_38F3_R_3_P_0): Likewise.
690 (VEX_LEN_38F7_P_0): Likewise.
691 (dis386_twobyte): Use PREFIX_0FBC.
692 (reg_table): Add REG_VEX_38F3.
693 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
694 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
695 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
696 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
697 PREFIX_VEX_38F7.
698 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
699 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
700 VEX_LEN_38F7_P_0.
701
702 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
703 (cpu_flags): Add CpuBMI.
704
705 * i386-opc.h (CpuBMI): New.
706 (i386_cpu_flags): Add cpubmi.
707
708 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
709 * i386-init.h: Regenerated.
710 * i386-tbl.h: Likewise.
711
cb21baef
L		 7122011-01-04 H.J. Lu <hongjiu.lu@intel.com>
713
714 * i386-dis.c (VexGdq): New.
715 (OP_VEX): Handle dq_mode.
716
0db46eb4
L		 7172011-01-01 H.J. Lu <hongjiu.lu@intel.com>
718
719 * i386-gen.c (process_copyright): Update copyright to 2011.
720
9e9e0820 721For older changes see ChangeLog-2010
252b5132
RH		 722\f
723Local Variables:
2f6d2f85
NC		 724mode: change-log
725left-margin: 8
726fill-column: 74
252b5132
RH		 727version-control: never
728End:
GDB Binutils - Deliverables
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