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2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
5e5c50d3
NE		 12012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
2
3 * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
4 * i386-init.h: Regenerated.
5
c7a5aa9c
PB		 62012-10-05 Peter Bergner <bergner@vnet.ibm.com>
7
8 * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
9 * ppc-opc.c (VBA): New define.
10 (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
11 mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.
12
04ee5257
NC		 132012-10-04 Nick Clifton <nickc@redhat.com>
14
15 * v850-dis.c (disassemble): Place square parentheses around second
16 register operand of clr1, not1, set1 and tst1 instructions.
17
cfc72779
AK		 182012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
19
20 * s390-mkopc.c: Support new option zEC12.
21 * s390-opc.c: Add new instruction formats.
22 * s390-opc.txt: Add new instructions for zEC12.
23
1415a2a7
AG		 242012-09-27 Anthony Green <green@moxielogic.com>
25
26 * moxie-dis.c (print_insn_moxie): Print 'bad' instructions.
27 * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD.
28
160a30bb
L		 292012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
30
04ee5257
NC		 31 * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
32 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
160a30bb
L		 33 and CPU_BTVER2_FLAGS.
34 * i386-init.h: Regenerated.
35
60aa667e
L		 362012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
37
38 * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
39 CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
40 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
41 CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
42 (cpu_flags): Add CpuCX16.
43 * i386-opc.h (CpuCX16): New.
44 (i386_cpu_flags): Add cpucx16.
45 * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
46 * i386-tbl.h: Regenerate.
47 * i386-init.h: Likewise.
48
4b8c8c02
RE		 492012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
50
60aa667e 51 * arm-dis.c: Changed ldra and strl-form mnemonics
4b8c8c02
RE		 52 to lda and stl-form.
53
83ea18d0
MR		 542012-09-18 Chao-ying Fu <fu@mips.com>
55
56 * micromips-opc.c (micromips_opcodes): Correct the encoding of
57 the "swxc1" instruction.
58
062f38fa
RE		 592012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
60
61 * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
62 the parameter 'inst'.
63 (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
64 (convert_mov_to_movewide): Change to assert (0) when
65 aarch64_wide_constant_p returns FALSE.
66
b132a67d
DE		 672012-09-14 David Edelsohn <dje.gcc@gmail.com>
68
69 * configure: Regenerate.
70
1f9b75dd
AG		 712012-09-14 Anthony Green <green@moxielogic.com>
72
73 * moxie-dis.c (print_insn_moxie): Branch targets are relative to
74 the address after the branch instruction.
75
e202fa84
AG		 762012-09-13 Anthony Green <green@moxielogic.com>
77
78 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
79
00716ab1
AM		 802012-09-10 Matthias Klose <doko@ubuntu.com>
81
82 * config.in: Disable sanity check for kfreebsd.
83
6d2920c8
L		 842012-09-10 H.J. Lu <hongjiu.lu@intel.com>
85
86 * configure: Regenerated.
87
b3e14eda
L		 882012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
89
90 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
91 * ia64-gen.c: Promote completer index type to longlong.
92 (irf_operand): Add new register recognition.
93 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
94 (lookup_specifier): Add new resource recognition.
95 (insert_bit_table_ent): Relax abort condition according to the
96 changed completer index type.
97 (print_dis_table): Fix printf format for completer index.
98 * ia64-ic.tbl: Add a new instruction class.
99 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
100 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
101 * ia64-opc.h: Define short names for new operand types.
102 * ia64-raw.tbl: Add new RAW resource for DAHR register.
103 * ia64-waw.tbl: Add new WAW resource for DAHR register.
104 * ia64-asmtab.c: Regenerate.
105
382c72e9
PB		 1062012-08-29 Peter Bergner <bergner@vnet.ibm.com>
107
108 * ppc-opc.c (VXASHB_MASK): New define.
109 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
110
fb048c26
PB		 1112012-08-28 Peter Bergner <bergner@vnet.ibm.com>
112
113 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
114 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
115 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
116 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
117 vupklsh>: Use VXVA_MASK.
118 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
119 <mfvscr>: Use VXVAVB_MASK.
120 <mtvscr>: Use VXVDVA_MASK.
121 <vspltb>: Use VXUIMM4_MASK.
122 <vsplth>: Use VXUIMM3_MASK.
123 <vspltw>: Use VXUIMM2_MASK.
124
3c9017d2
MGD		 1252012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
126
127 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
128
48adcd8e
MGD		 1292012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
130
131 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
132
4f51b4bd
MGD		 1332012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
134
135 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
136
91ff7894
MGD		 1372012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
138
139 * arm-dis.c (neon_opcodes): Add support for AES instructions.
140
c70a8987
MGD		 1412012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
142
143 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
144 conversions.
145
30bdf752
MGD		 1462012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
147
148 * arm-dis.c (coprocessor_opcodes): Add VRINT.
149 (neon_opcodes): Likewise.
150
7e8e6784
MGD		 1512012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
152
153 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
154 variants.
155 (neon_opcodes): Likewise.
156
73924fbc
MGD		 1572012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
158
159 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
160 (neon_opcodes): Likewise.
161
33399f07
MGD		 1622012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
163
164 * arm-dis.c (coprocessor_opcodes): Add VSEL.
165 (print_insn_coprocessor): Add new %<>c bitfield format
166 specifier.
167
9eb6c0f1
MGD		 1682012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
169
170 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
171 (thumb32_opcodes): Likewise.
172 (print_arm_insn): Add support for %<>T formatter.
173
8884b720
MGD		 1742012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
175
176 * arm-dis.c (arm_opcodes): Add HLT.
177 (thumb_opcodes): Likewise.
178
b79f7053
MGD		 1792012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
180
181 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
182
53c4b28b
MGD		 1832012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
184
185 * arm-dis.c (arm_opcodes): Add SEVL.
186 (thumb_opcodes): Likewise.
187 (thumb32_opcodes): Likewise.
188
e797f7e0
MGD		 1892012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
190
191 * arm-dis.c (data_barrier_option): New function.
192 (print_insn_arm): Use data_barrier_option.
193 (print_insn_thumb32): Use data_barrier_option.
194
e2efe87d
MGD		 1952012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
196
197 * arm-dis.c (COND_UNCOND): New constant.
198 (print_insn_coprocessor): Add support for %u format specifier.
199 (print_insn_neon): Likewise.
200
2c63854f
DM		 2012012-08-21 David S. Miller <davem@davemloft.net>
202
203 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
204 F3F4 macro.
205
e67ed0e8
AM		 2062012-08-20 Edmar Wienskoski <edmar@freescale.com>
207
208 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
209 vabsduh, vabsduw, mviwsplt.
210
7b458c12
L		 2112012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
212
213 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
214 CPU_BTVER2_FLAGS.
215
e67ed0e8 216 * i386-opc.h: Update CpuPRFCHW comment.
7b458c12
L		 217
218 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
219 * i386-init.h: Regenerated.
220 * i386-tbl.h: Likewise.
221
eb80cb87
NC		 2222012-08-17 Nick Clifton <nickc@redhat.com>
223
224 * po/uk.po: New Ukranian translation.
225 * configure.in (ALL_LINGUAS): Add uk.
226 * configure: Regenerate.
227
8baf7b78
PB		 2282012-08-16 Peter Bergner <bergner@vnet.ibm.com>
229
230 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
231 RBX for the third operand.
232 <"lswi">: Use RAX for second and NBI for the third operand.
233
3d557b4c
DD		 2342012-08-15 DJ Delorie <dj@redhat.com>
235
236 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
237 operands, so that data addresses can be corrected when not
238 ES-overridden.
239 * rl78-decode.c: Regenerate.
240 * rl78-dis.c (print_insn_rl78): Make order of modifiers
241 irrelevent. When the 'e' specifier is used on an operand and no
242 ES prefix is provided, adjust address to make it absolute.
243
588925d0
PB		 2442012-08-15 Peter Bergner <bergner@vnet.ibm.com>
245
246 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
247
9f6a6cc0
PB		 2482012-08-15 Peter Bergner <bergner@vnet.ibm.com>
249
250 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
251
fc8c4fd1
MR		 2522012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
253
254 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
255 macros, use local variables for info struct member accesses,
256 update the type of the variable used to hold the instruction
257 word.
258 (print_insn_mips, print_mips16_insn_arg): Likewise.
259 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
260 local variables for info struct member accesses.
261 (print_insn_micromips): Add GET_OP_S local macro.
262 (_print_insn_mips): Update the type of the variable used to hold
263 the instruction word.
264
a06ea964 2652012-08-13 Ian Bolton <ian.bolton@arm.com>
e67ed0e8
AM		 266 Laurent Desnogues <laurent.desnogues@arm.com>
267 Jim MacArthur <jim.macarthur@arm.com>
268 Marcus Shawcroft <marcus.shawcroft@arm.com>
269 Nigel Stephens <nigel.stephens@arm.com>
270 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
271 Richard Earnshaw <rearnsha@arm.com>
272 Sofiane Naci <sofiane.naci@arm.com>
273 Tejas Belagod <tejas.belagod@arm.com>
274 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 275
276 * Makefile.am: Add AArch64.
277 * Makefile.in: Regenerate.
278 * aarch64-asm.c: New file.
279 * aarch64-asm.h: New file.
280 * aarch64-dis.c: New file.
281 * aarch64-dis.h: New file.
282 * aarch64-gen.c: New file.
283 * aarch64-opc.c: New file.
284 * aarch64-opc.h: New file.
285 * aarch64-tbl.h: New file.
286 * configure.in: Add AArch64.
287 * configure: Regenerate.
288 * disassemble.c: Add AArch64.
289 * aarch64-asm-2.c: New file (automatically generated).
290 * aarch64-dis-2.c: New file (automatically generated).
291 * aarch64-opc-2.c: New file (automatically generated).
292 * po/POTFILES.in: Regenerate.
293
35d0a169
MR		 2942012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
295
296 * micromips-opc.c (micromips_opcodes): Update comment.
297 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
298 instructions for IOCT as appropriate.
299 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
300 opcode_is_member.
301 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
302 the result of a check for the -Wno-missing-field-initializers
303 GCC option.
304 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
305 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
306 compilation.
307 (mips16-opc.lo): Likewise.
308 (micromips-opc.lo): Likewise.
309 * aclocal.m4: Regenerate.
310 * configure: Regenerate.
311 * Makefile.in: Regenerate.
312
5c5acbbd
L		 3132012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
314
315 PR gas/14423
316 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
317 * i386-init.h: Regenerated.
318
3c892704
NC		 3192012-08-09 Nick Clifton <nickc@redhat.com>
320
321 * po/vi.po: Updated Vietnamese translation.
322
d7189fa5
RM		 3232012-08-07 Roland McGrath <mcgrathr@google.com>
324
325 * i386-dis.c (reg_table): Fill out REG_0F0D table with
326 AMD-reserved cases as "prefetch".
327 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
328 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
329 (reg_table): Use those under REG_0F18.
330 (mod_table): Add those cases as "nop/reserved".
331
4c692bc7
JB		 3322012-08-07 Jan Beulich <jbeulich@suse.com>
333
334 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
335
de882298
RM		 3362012-08-06 Roland McGrath <mcgrathr@google.com>
337
338 * i386-dis.c (print_insn): Print spaces between multiple excess
339 prefixes. Return actual number of excess prefixes consumed,
340 not always one.
341
342 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
343
7bb15c6f
RM		 3442012-08-06 Roland McGrath <mcgrathr@google.com>
345 Victor Khimenko <khim@google.com>
346 H.J. Lu <hongjiu.lu@intel.com>
347
348 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
349 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
350 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
351 (OP_E_register): Likewise.
352 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
353
3843081d
JBG		 3542012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
355
356 * configure.in: Formatting.
357 * configure: Regenerate.
358
48891606
AM		 3592012-08-01 Alan Modra <amodra@gmail.com>
360
361 * h8300-dis.c: Fix printf arg warnings.
362 * i960-dis.c: Likewise.
363 * mips-dis.c: Likewise.
364 * pdp11-dis.c: Likewise.
365 * sh-dis.c: Likewise.
366 * v850-dis.c: Likewise.
367 * configure.in: Formatting.
368 * configure: Regenerate.
369 * rl78-decode.c: Regenerate.
370 * po/POTFILES.in: Regenerate.
371
03f66e8a 3722012-07-31 Chao-Ying Fu <fu@mips.com>
e67ed0e8
AM		 373 Catherine Moore <clm@codesourcery.com>
374 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 375
376 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
377 (DSP_VOLA): Likewise.
378 (D32, D33): Likewise.
379 (micromips_opcodes): Add DSP ASE instructions.
48891606 380 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
03f66e8a
MR		 381 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
382
94948e64
JB		 3832012-07-31 Jan Beulich <jbeulich@suse.com>
384
385 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
386 instruction group. Mark as requiring AVX2.
387 * i386-tbl.h: Re-generate.
388
a6dc81d2
NC		 3892012-07-30 Nick Clifton <nickc@redhat.com>
390
391 * po/opcodes.pot: Updated template.
392 * po/es.po: Updated Spanish translation.
393 * po/fi.po: Updated Finnish translation.
394
c4dd807e
MF		 3952012-07-27 Mike Frysinger <vapier@gentoo.org>
396
397 * configure.in (BFD_VERSION): Run bfd/configure --version and
398 parse the output of that.
399 * configure: Regenerate.
400
03edbe3b
JL		 4012012-07-25 James Lemke <jwlemke@codesourcery.com>
402
403 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
404
63d08c68
NC		 4052012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
406 Dr David Alan Gilbert <dave@treblig.org>
d908c8af
NC		 407
408 PR binutils/13135
409 * arm-dis.c: Add necessary casts for printing integer values.
410 Use %s when printing string values.
411 * hppa-dis.c: Likewise.
412 * m68k-dis.c: Likewise.
413 * microblaze-dis.c: Likewise.
414 * mips-dis.c: Likewise.
415 * sparc-dis.c: Likewise.
416
ff688e1f
L		 4172012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
418
419 PR binutils/14355
420 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
421 (VEX_LEN_0FXOP_08_CD): Likewise.
422 (VEX_LEN_0FXOP_08_CE): Likewise.
423 (VEX_LEN_0FXOP_08_CF): Likewise.
424 (VEX_LEN_0FXOP_08_EC): Likewise.
425 (VEX_LEN_0FXOP_08_ED): Likewise.
426 (VEX_LEN_0FXOP_08_EE): Likewise.
427 (VEX_LEN_0FXOP_08_EF): Likewise.
428 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
429 vpcomub, vpcomuw, vpcomud, vpcomuq.
430 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
431 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
432 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
433 VEX_LEN_0FXOP_08_EF.
434
e2e1fcde
L		 4352012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
436
437 * i386-dis.c (PREFIX_0F38F6): New.
438 (prefix_table): Add adcx, adox instructions.
439 (three_byte_table): Use PREFIX_0F38F6.
440 (mod_table): Add rdseed instruction.
441 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
442 (cpu_flags): Likewise.
443 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
444 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
445 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
446 prefetchw.
447 * i386-tbl.h: Regenerate.
448 * i386-init.h: Likewise.
449
8b99bf0b
TS		 4502012-07-05 Thomas Schwinge <thomas@codesourcery.com>
451
f4263ca2 452 * mips-dis.c: Remove gratuitous newline.
8b99bf0b 453
416cf80a
SK		 4542012-07-05 Sean Keys <skeys@ipdatasys.com>
455
456 * xgate-dis.c: Removed an IF statement that will
e67ed0e8
AM		 457 always be false due to overlapping operand masks.
458 * xgate-opc.c: Corrected 'com' opcode entry and
459 fixed spacing.
416cf80a 460
9fa0f14a
RM		 4612012-07-02 Roland McGrath <mcgrathr@google.com>
462
463 * i386-opc.tbl: Add RepPrefixOk to nop.
464 * i386-tbl.h: Regenerate.
465
4c6a93d3
NC		 4662012-06-28 Nick Clifton <nickc@redhat.com>
467
468 * po/vi.po: Updated Vietnamese translation.
469
29c048b6
RM		 4702012-06-22 Roland McGrath <mcgrathr@google.com>
471
fe13e45b
RM		 472 * i386-opc.tbl: Add RepPrefixOk to ret.
473 * i386-tbl.h: Regenerate.
474
29c048b6
RM		 475 * i386-opc.h (RepPrefixOk): New enum constant.
476 (i386_opcode_modifier): New bitfield 'repprefixok'.
477 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
478 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
479 instructions that have IsString.
480 * i386-tbl.h: Regenerate.
481
c7a8dbf9
AS		 4822012-06-11 Andreas Schwab <schwab@linux-m68k.org>
483
484 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
485 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
486 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
487 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
488 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
489 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
490 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
491 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
492 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
493
94caa966
AM		 4942012-05-19 Alan Modra <amodra@gmail.com>
495
496 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
497 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
498
5eb3690e
AM		 4992012-05-18 Alan Modra <amodra@gmail.com>
500
71fe7bab
AM		 501 * ia64-opc.c: Remove #include "ansidecl.h".
502 * z8kgen.c: Include sysdep.h first.
503
5eb3690e
AM		 504 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
505 * bfin-dis.c: Likewise.
506 * i860-dis.c: Likewise.
507 * ia64-dis.c: Likewise.
508 * ia64-gen.c: Likewise.
509 * m68hc11-dis.c: Likewise.
510 * mmix-dis.c: Likewise.
511 * msp430-dis.c: Likewise.
512 * or32-dis.c: Likewise.
513 * rl78-dis.c: Likewise.
514 * rx-dis.c: Likewise.
515 * tic4x-dis.c: Likewise.
516 * tilegx-opc.c: Likewise.
517 * tilepro-opc.c: Likewise.
518 * rx-decode.c: Regenerate.
519
a4ebc835
AM		 5202012-05-17 James Lemke <jwlemke@codesourcery.com>
521
522 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
523
98c76446
AM		 5242012-05-17 James Lemke <jwlemke@codesourcery.com>
525
526 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
527
df7b86aa
NC		 5282012-05-17 Daniel Richard G. <skunk@iskunk.org>
529 Nick Clifton <nickc@redhat.com>
530
531 PR 14072
532 * configure.in: Add check that sysdep.h has been included before
533 any system header files.
534 * configure: Regenerate.
535 * config.in: Regenerate.
536 * sysdep.h: Generate an error if included before config.h.
537 * alpha-opc.c: Include sysdep.h before any other header file.
538 * alpha-dis.c: Likewise.
539 * avr-dis.c: Likewise.
540 * cgen-opc.c: Likewise.
541 * cr16-dis.c: Likewise.
542 * cris-dis.c: Likewise.
543 * crx-dis.c: Likewise.
544 * d10v-dis.c: Likewise.
545 * d10v-opc.c: Likewise.
546 * d30v-dis.c: Likewise.
547 * d30v-opc.c: Likewise.
548 * h8500-dis.c: Likewise.
549 * i370-dis.c: Likewise.
550 * i370-opc.c: Likewise.
551 * m10200-dis.c: Likewise.
552 * m10300-dis.c: Likewise.
553 * micromips-opc.c: Likewise.
554 * mips-opc.c: Likewise.
555 * mips61-opc.c: Likewise.
556 * moxie-dis.c: Likewise.
557 * or32-opc.c: Likewise.
558 * pj-dis.c: Likewise.
559 * ppc-dis.c: Likewise.
560 * ppc-opc.c: Likewise.
561 * s390-dis.c: Likewise.
562 * sh-dis.c: Likewise.
563 * sh64-dis.c: Likewise.
564 * sparc-dis.c: Likewise.
565 * sparc-opc.c: Likewise.
566 * spu-dis.c: Likewise.
567 * tic30-dis.c: Likewise.
568 * tic54x-dis.c: Likewise.
569 * tic80-dis.c: Likewise.
570 * tic80-opc.c: Likewise.
571 * tilegx-dis.c: Likewise.
572 * tilepro-dis.c: Likewise.
573 * v850-dis.c: Likewise.
574 * v850-opc.c: Likewise.
575 * vax-dis.c: Likewise.
576 * w65-dis.c: Likewise.
577 * xgate-dis.c: Likewise.
578 * xtensa-dis.c: Likewise.
579 * rl78-decode.opc: Likewise.
580 * rl78-decode.c: Regenerate.
581 * rx-decode.opc: Likewise.
582 * rx-decode.c: Regenerate.
583
e1dad58d
AM		 5842012-05-17 Alan Modra <amodra@gmail.com>
585
586 * ppc_dis.c: Don't include elf/ppc.h.
587
101af531
NC		 5882012-05-16 Meador Inge <meadori@codesourcery.com>
589
590 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
591 to PUSH/POP {reg}.
592
6927f982
NC		 5932012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
594 Stephane Carrez <stcarrez@nerim.fr>
595
596 * configure.in: Add S12X and XGATE co-processor support to m68hc11
597 target.
598 * disassemble.c: Likewise.
599 * configure: Regenerate.
600 * m68hc11-dis.c: Make objdump output more consistent, use hex
601 instead of decimal and use 0x prefix for hex.
602 * m68hc11-opc.c: Add S12X and XGATE opcodes.
603
b9c361e0
JL		 6042012-05-14 James Lemke <jwlemke@codesourcery.com>
605
606 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
607 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
608 (vle_opcd_indices): New array.
609 (lookup_vle): New function.
610 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
611 (print_insn_powerpc): Likewise.
612 * ppc-opc.c: Likewise.
613
6142012-05-14 Catherine Moore <clm@codesourcery.com>
615 Maciej W. Rozycki <macro@codesourcery.com>
616 Rhonda Wittels <rhonda@codesourcery.com>
617 Nathan Froyd <froydnj@codesourcery.com>
618
619 * ppc-opc.c (insert_arx, extract_arx): New functions.
620 (insert_ary, extract_ary): New functions.
621 (insert_li20, extract_li20): New functions.
622 (insert_rx, extract_rx): New functions.
623 (insert_ry, extract_ry): New functions.
624 (insert_sci8, extract_sci8): New functions.
625 (insert_sci8n, extract_sci8n): New functions.
626 (insert_sd4h, extract_sd4h): New functions.
627 (insert_sd4w, extract_sd4w): New functions.
628 (insert_vlesi, extract_vlesi): New functions.
629 (insert_vlensi, extract_vlensi): New functions.
630 (insert_vleui, extract_vleui): New functions.
631 (insert_vleil, extract_vleil): New functions.
632 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
633 (BI16, BI32, BO32, B8): New.
634 (B15, B24, CRD32, CRS): New.
635 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
636 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
637 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
638 (SH6_MASK): Use PPC_OPSHIFT_INV.
639 (SI8, UI5, OIMM5, UI7, BO16): New.
640 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
641 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
642 (ALLOW8_SPRG): New.
643 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
644 (OPVUP, OPVUP_MASK OPVUP): New
645 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
646 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
647 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
648 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
649 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
650 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
651 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
652 (SE_IM5, SE_IM5_MASK): New.
653 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
654 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
655 (BO32DNZ, BO32DZ): New.
656 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
657 (PPCVLE): New.
658 (powerpc_opcodes): Add new VLE instructions. Update existing
659 instruction to include PPCVLE if supported.
660 * ppc-dis.c (ppc_opts): Add vle entry.
661 (get_powerpc_dialect): New function.
662 (powerpc_init_dialect): VLE support.
663 (print_insn_big_powerpc): Call get_powerpc_dialect.
664 (print_insn_little_powerpc): Likewise.
665 (operand_value_powerpc): Handle negative shift counts.
666 (print_insn_powerpc): Handle 2-byte instruction lengths.
667
208a4923
NC		 6682012-05-11 Daniel Richard G. <skunk@iskunk.org>
669
670 PR binutils/14028
671 * configure.in: Invoke ACX_HEADER_STRING.
672 * configure: Regenerate.
673 * config.in: Regenerate.
674 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
675 string.h and strings.h.
676
6750a3a7
NC		 6772012-05-11 Nick Clifton <nickc@redhat.com>
678
679 PR binutils/14006
680 * arm-dis.c (print_insn): Fix detection of instruction mode in
681 files containing multiple executable sections.
682
f6c1a2d5
NC		 6832012-05-03 Sean Keys <skeys@ipdatasys.com>
684
685 * Makefile.in, configure: regenerate
686 * disassemble.c (disassembler): Recognize ARCH_XGATE.
687 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
688 New functions.
689 * configure.in: Recognize xgate.
690 * xgate-dis.c, xgate-opc.c: New files for support of xgate
691 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
692 and opcode generation for xgate.
693
78e98aab
DD		 6942012-04-30 DJ Delorie <dj@redhat.com>
695
696 * rx-decode.opc (MOV): Do not sign-extend immediates which are
697 already the maximum bit size.
698 * rx-decode.c: Regenerate.
699
ec668d69
DM		 7002012-04-27 David S. Miller <davem@davemloft.net>
701
2e52845b
DM		 702 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
703 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
704
58004e23
DM		 705 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
706 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
707
698544e1
DM		 708 * sparc-opc.c (CBCOND): New define.
709 (CBCOND_XCC): Likewise.
710 (cbcond): New helper macro.
711 (sparc_opcodes): Add compare-and-branch instructions.
712
6cda1326
DM		 713 * sparc-dis.c (print_insn_sparc): Handle ')'.
714 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
715
ec668d69
DM		 716 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
717 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
718
2615994e
DM		 7192012-04-12 David S. Miller <davem@davemloft.net>
720
721 * sparc-dis.c (X_DISP10): Define.
722 (print_insn_sparc): Handle '='.
723
5de10af0
MF		 7242012-04-01 Mike Frysinger <vapier@gentoo.org>
725
726 * bfin-dis.c (fmtconst): Replace decimal handling with a single
727 sprintf call and the '*' field width.
728
55a36193
MK		 7292012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
730
731 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
732
d6688282
AM		 7332012-03-16 Alan Modra <amodra@gmail.com>
734
735 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
736 (powerpc_opcd_indices): Bump array size.
737 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
738 corresponding to unused opcodes to following entry.
739 (lookup_powerpc): New function, extracted and optimised from..
740 (print_insn_powerpc): ..here.
741
b240011a
AM		 7422012-03-15 Alan Modra <amodra@gmail.com>
743 James Lemke <jwlemke@codesourcery.com>
744
745 * disassemble.c (disassemble_init_for_target): Handle ppc init.
746 * ppc-dis.c (private): New var.
747 (powerpc_init_dialect): Don't return calloc failure, instead use
748 private.
749 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
750 (powerpc_opcd_indices): New array.
751 (disassemble_init_powerpc): New function.
752 (print_insn_big_powerpc): Don't init dialect here.
753 (print_insn_little_powerpc): Likewise.
754 (print_insn_powerpc): Start search using powerpc_opcd_indices.
755
aea77599
AM		 7562012-03-10 Edmar Wienskoski <edmar@freescale.com>
757
758 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
759 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
760 (PPCVEC2, PPCTMR, E6500): New short names.
761 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
762 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
763 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
764 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
765 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
766 optional operands on sync instruction for E6500 target.
767
5333187a
AK		 7682012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
769
770 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
771
a597d2d3
AM		 7722012-02-27 Alan Modra <amodra@gmail.com>
773
774 * mt-dis.c: Regenerate.
775
3f26eb3a
AM		 7762012-02-27 Alan Modra <amodra@gmail.com>
777
778 * v850-opc.c (extract_v8): Rearrange to make it obvious this
779 is the inverse of corresponding insert function.
780 (extract_d22, extract_u9, extract_r4): Likewise.
781 (extract_d9): Correct sign extension.
782 (extract_d16_15): Don't assume "long" is 32 bits, and don't
783 rely on implementation defined behaviour for shift right of
784 signed types.
785 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
786 (extract_d23): Likewise, and correct mask.
787
1f42f8b3
AM		 7882012-02-27 Alan Modra <amodra@gmail.com>
789
790 * crx-dis.c (print_arg): Mask constant to 32 bits.
791 * crx-opc.c (cst4_map): Use int array.
792
cdb06235
AM		 7932012-02-27 Alan Modra <amodra@gmail.com>
794
795 * arc-dis.c (BITS): Don't use shifts to mask off bits.
796 (FIELDD): Sign extend with xor,sub.
797
6f7be959
WL		 7982012-02-25 Walter Lee <walt@tilera.com>
799
800 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
801 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
802 TILEPRO_OPC_LW_TLS_SN.
803
82c2def5
L		 8042012-02-21 H.J. Lu <hongjiu.lu@intel.com>
805
806 * i386-opc.h (HLEPrefixNone): New.
807 (HLEPrefixLock): Likewise.
808 (HLEPrefixAny): Likewise.
809 (HLEPrefixRelease): Likewise.
810
42164a71
L		 8112012-02-08 H.J. Lu <hongjiu.lu@intel.com>
812
813 * i386-dis.c (HLE_Fixup1): New.
814 (HLE_Fixup2): Likewise.
815 (HLE_Fixup3): Likewise.
816 (Ebh1): Likewise.
817 (Evh1): Likewise.
818 (Ebh2): Likewise.
819 (Evh2): Likewise.
820 (Ebh3): Likewise.
821 (Evh3): Likewise.
822 (MOD_C6_REG_7): Likewise.
823 (MOD_C7_REG_7): Likewise.
824 (RM_C6_REG_7): Likewise.
825 (RM_C7_REG_7): Likewise.
826 (XACQUIRE_PREFIX): Likewise.
827 (XRELEASE_PREFIX): Likewise.
828 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
829 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
830 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
831 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
832 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
833 MOD_C6_REG_7 and MOD_C7_REG_7.
834 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
835 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
836 xtest.
837 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
838 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
839
840 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
841 CPU_RTM_FLAGS.
842 (cpu_flags): Add CpuHLE and CpuRTM.
843 (opcode_modifiers): Add HLEPrefixOk.
844
845 * i386-opc.h (CpuHLE): New.
846 (CpuRTM): Likewise.
847 (HLEPrefixOk): Likewise.
848 (i386_cpu_flags): Add cpuhle and cpurtm.
849 (i386_opcode_modifier): Add hleprefixok.
850
851 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
852 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
853 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
854 operand. Add xacquire, xrelease, xabort, xbegin, xend and
855 xtest.
856 * i386-init.h: Regenerated.
857 * i386-tbl.h: Likewise.
858
21abe33a
DD		 8592012-01-24 DJ Delorie <dj@redhat.com>
860
861 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
862 * rl78-decode.c: Regenerate.
863
e20cc039
AM		 8642012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
865
866 PR binutils/10173
867 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
868
e143d25c
AS		 8692012-01-17 Andreas Schwab <schwab@linux-m68k.org>
870
871 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
872 register and move them after pmove with PSR/PCSR register.
873
8729a6f6
L		 8742012-01-13 H.J. Lu <hongjiu.lu@intel.com>
875
876 * i386-dis.c (mod_table): Add vmfunc.
877
878 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
879 (cpu_flags): CpuVMFUNC.
880
881 * i386-opc.h (CpuVMFUNC): New.
882 (i386_cpu_flags): Add cpuvmfunc.
883
884 * i386-opc.tbl: Add vmfunc.
885 * i386-init.h: Regenerated.
886 * i386-tbl.h: Likewise.
5011093d 887
23e1d329 888For older changes see ChangeLog-2011
252b5132
RH		 889\f
890Local Variables:
2f6d2f85
NC		 891mode: change-log
892left-margin: 8
893fill-column: 74
252b5132
RH		 894version-control: never
895End:
GDB Binutils - Deliverables
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