[gdb/testsuite] Fix target_supports_scheduler_locking raciness
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
780f601c
TC
12018-10-08 Tamar Christina <tamar.christina@arm.com>
2
3 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
4
a4e78aa5
L
52018-10-05 H.J. Lu <hongjiu.lu@intel.com>
6
7 * i386-dis.c (rm_table): Add enclv.
8 * i386-opc.tbl: Add enclv.
9 * i386-tbl.h: Regenerated.
10
7fadb25d
SD
112018-10-05 Sudakshina Das <sudi.das@arm.com>
12
13 * arm-dis.c (arm_opcodes): Add sb.
14 (thumb32_opcodes): Likewise.
15
07f5f4c6
RH
162018-10-05 Richard Henderson <rth@twiddle.net>
17 Stafford Horne <shorne@gmail.com>
18
19 * or1k-desc.c: Regenerate.
20 * or1k-desc.h: Regenerate.
21 * or1k-opc.c: Regenerate.
22 * or1k-opc.h: Regenerate.
23 * or1k-opinst.c: Regenerate.
24
c8e98e36
SH
252018-10-05 Richard Henderson <rth@twiddle.net>
26
27 * or1k-asm.c: Regenerated.
28 * or1k-desc.c: Regenerated.
29 * or1k-desc.h: Regenerated.
30 * or1k-dis.c: Regenerated.
31 * or1k-ibld.c: Regenerated.
32 * or1k-opc.c: Regenerated.
33 * or1k-opc.h: Regenerated.
34 * or1k-opinst.c: Regenerated.
35
1c4f3780
RH
362018-10-05 Richard Henderson <rth@twiddle.net>
37
38 * or1k-asm.c: Regenerate.
39
bde90be2
TC
402018-10-03 Tamar Christina <tamar.christina@arm.com>
41
42 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
43 * aarch64-dis.c (print_operands): Refactor to take notes.
44 (print_verifier_notes): New.
45 (print_aarch64_insn): Apply constraint verifier.
46 (print_insn_aarch64_word): Update call to print_aarch64_insn.
47 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
48
a68f4cd2
TC
492018-10-03 Tamar Christina <tamar.christina@arm.com>
50
51 * aarch64-opc.c (init_insn_block): New.
52 (verify_constraints, aarch64_is_destructive_by_operands): New.
53 * aarch64-opc.h (verify_constraints): New.
54
755b748f
TC
552018-10-03 Tamar Christina <tamar.christina@arm.com>
56
57 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
58 * aarch64-opc.c (verify_ldpsw): Update arguments.
59
1d482394
TC
602018-10-03 Tamar Christina <tamar.christina@arm.com>
61
62 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
63 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
64
7e84b55d
TC
652018-10-03 Tamar Christina <tamar.christina@arm.com>
66
67 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
68 * aarch64-dis.c (insn_sequence): New.
69
eae424ae
TC
702018-10-03 Tamar Christina <tamar.christina@arm.com>
71
72 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
73 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
74 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
75 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
76 constraints.
77 (_SVE_INSNC): New.
78 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
79 constraints.
80 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
81 F_SCAN flags.
82 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
83 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
84 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
85 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
86 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
87 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
88 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
89
64a336ac
PD
902018-10-02 Palmer Dabbelt <palmer@sifive.com>
91
92 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
93
6031ac35
SL
942018-09-23 Sandra Loosemore <sandra@codesourcery.com>
95
96 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
97 are used when extracting signed fields and converting them to
98 potentially 64-bit types.
99
f24ff6e9
SM
1002018-09-21 Simon Marchi <simon.marchi@ericsson.com>
101
102 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
103 * Makefile.in: Re-generate.
104 * aclocal.m4: Re-generate.
105 * configure: Re-generate.
106 * configure.ac: Remove check for -Wno-missing-field-initializers.
107 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
108 (csky_v2_opcodes): Likewise.
109
53b6d6f5
MR
1102018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
111
112 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
113
fbaf61ad
NC
1142018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
115
116 * nds32-asm.c (operand_fields): Remove the unused fields.
117 (nds32_opcodes): Remove the unused instructions.
118 * nds32-dis.c (nds32_ex9_info): Removed.
119 (nds32_parse_opcode): Updated.
120 (print_insn_nds32): Likewise.
121 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
122 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
123 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
124 build_opcode_hash_table): New functions.
125 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
126 nds32_opcode_table): New.
127 (hw_ktabs): Declare it to a pointer rather than an array.
128 (build_hash_table): Removed.
129 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
130 SYN_ROPT and upadte HW_GPR and HW_INT.
131 * nds32-dis.c (keywords): Remove const.
132 (match_field): New function.
133 (nds32_parse_opcode): Updated.
134 * disassemble.c (disassemble_init_for_target):
135 Add disassemble_init_nds32.
136 * nds32-dis.c (eum map_type): New.
137 (nds32_private_data): Likewise.
138 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
139 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
140 (print_insn_nds32): Updated.
141 * nds32-asm.c (parse_aext_reg): Add new parameter.
142 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
143 are allowed to use.
144 All callers changed.
145 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
146 (operand_fields): Add new fields.
147 (nds32_opcodes): Add new instructions.
148 (keyword_aridxi_mx): New keyword.
149 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
150 and NASM_ATTR_ZOL.
151 (ALU2_1, ALU2_2, ALU2_3): New macros.
152 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
153
4e2b1898
JW
1542018-09-17 Kito Cheng <kito@andestech.com>
155
156 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
157
04e2a182
L
1582018-09-17 H.J. Lu <hongjiu.lu@intel.com>
159
160 PR gas/23670
161 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
162 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
163 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
164 (EVEX_LEN_0F7E_P_1): Likewise.
165 (EVEX_LEN_0F7E_P_2): Likewise.
166 (EVEX_LEN_0FD6_P_2): Likewise.
167 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
168 (EVEX_LEN_TABLE): Likewise.
169 (EVEX_LEN_0F6E_P_2): New enum.
170 (EVEX_LEN_0F7E_P_1): Likewise.
171 (EVEX_LEN_0F7E_P_2): Likewise.
172 (EVEX_LEN_0FD6_P_2): Likewise.
173 (evex_len_table): New.
174 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
175 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
176 * i386-tbl.h: Regenerated.
177
d5f787c2
L
1782018-09-17 H.J. Lu <hongjiu.lu@intel.com>
179
180 PR gas/23665
181 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
182 VEX_LEN_0F7E_P_2 entries.
183 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
184 * i386-tbl.h: Regenerated.
185
ec6f095a
L
1862018-09-17 H.J. Lu <hongjiu.lu@intel.com>
187
188 * i386-dis.c (VZERO_Fixup): Removed.
189 (VZERO): Likewise.
190 (VEX_LEN_0F10_P_1): Likewise.
191 (VEX_LEN_0F10_P_3): Likewise.
192 (VEX_LEN_0F11_P_1): Likewise.
193 (VEX_LEN_0F11_P_3): Likewise.
194 (VEX_LEN_0F2E_P_0): Likewise.
195 (VEX_LEN_0F2E_P_2): Likewise.
196 (VEX_LEN_0F2F_P_0): Likewise.
197 (VEX_LEN_0F2F_P_2): Likewise.
198 (VEX_LEN_0F51_P_1): Likewise.
199 (VEX_LEN_0F51_P_3): Likewise.
200 (VEX_LEN_0F52_P_1): Likewise.
201 (VEX_LEN_0F53_P_1): Likewise.
202 (VEX_LEN_0F58_P_1): Likewise.
203 (VEX_LEN_0F58_P_3): Likewise.
204 (VEX_LEN_0F59_P_1): Likewise.
205 (VEX_LEN_0F59_P_3): Likewise.
206 (VEX_LEN_0F5A_P_1): Likewise.
207 (VEX_LEN_0F5A_P_3): Likewise.
208 (VEX_LEN_0F5C_P_1): Likewise.
209 (VEX_LEN_0F5C_P_3): Likewise.
210 (VEX_LEN_0F5D_P_1): Likewise.
211 (VEX_LEN_0F5D_P_3): Likewise.
212 (VEX_LEN_0F5E_P_1): Likewise.
213 (VEX_LEN_0F5E_P_3): Likewise.
214 (VEX_LEN_0F5F_P_1): Likewise.
215 (VEX_LEN_0F5F_P_3): Likewise.
216 (VEX_LEN_0FC2_P_1): Likewise.
217 (VEX_LEN_0FC2_P_3): Likewise.
218 (VEX_LEN_0F3A0A_P_2): Likewise.
219 (VEX_LEN_0F3A0B_P_2): Likewise.
220 (VEX_W_0F10_P_0): Likewise.
221 (VEX_W_0F10_P_1): Likewise.
222 (VEX_W_0F10_P_2): Likewise.
223 (VEX_W_0F10_P_3): Likewise.
224 (VEX_W_0F11_P_0): Likewise.
225 (VEX_W_0F11_P_1): Likewise.
226 (VEX_W_0F11_P_2): Likewise.
227 (VEX_W_0F11_P_3): Likewise.
228 (VEX_W_0F12_P_0_M_0): Likewise.
229 (VEX_W_0F12_P_0_M_1): Likewise.
230 (VEX_W_0F12_P_1): Likewise.
231 (VEX_W_0F12_P_2): Likewise.
232 (VEX_W_0F12_P_3): Likewise.
233 (VEX_W_0F13_M_0): Likewise.
234 (VEX_W_0F14): Likewise.
235 (VEX_W_0F15): Likewise.
236 (VEX_W_0F16_P_0_M_0): Likewise.
237 (VEX_W_0F16_P_0_M_1): Likewise.
238 (VEX_W_0F16_P_1): Likewise.
239 (VEX_W_0F16_P_2): Likewise.
240 (VEX_W_0F17_M_0): Likewise.
241 (VEX_W_0F28): Likewise.
242 (VEX_W_0F29): Likewise.
243 (VEX_W_0F2B_M_0): Likewise.
244 (VEX_W_0F2E_P_0): Likewise.
245 (VEX_W_0F2E_P_2): Likewise.
246 (VEX_W_0F2F_P_0): Likewise.
247 (VEX_W_0F2F_P_2): Likewise.
248 (VEX_W_0F50_M_0): Likewise.
249 (VEX_W_0F51_P_0): Likewise.
250 (VEX_W_0F51_P_1): Likewise.
251 (VEX_W_0F51_P_2): Likewise.
252 (VEX_W_0F51_P_3): Likewise.
253 (VEX_W_0F52_P_0): Likewise.
254 (VEX_W_0F52_P_1): Likewise.
255 (VEX_W_0F53_P_0): Likewise.
256 (VEX_W_0F53_P_1): Likewise.
257 (VEX_W_0F58_P_0): Likewise.
258 (VEX_W_0F58_P_1): Likewise.
259 (VEX_W_0F58_P_2): Likewise.
260 (VEX_W_0F58_P_3): Likewise.
261 (VEX_W_0F59_P_0): Likewise.
262 (VEX_W_0F59_P_1): Likewise.
263 (VEX_W_0F59_P_2): Likewise.
264 (VEX_W_0F59_P_3): Likewise.
265 (VEX_W_0F5A_P_0): Likewise.
266 (VEX_W_0F5A_P_1): Likewise.
267 (VEX_W_0F5A_P_3): Likewise.
268 (VEX_W_0F5B_P_0): Likewise.
269 (VEX_W_0F5B_P_1): Likewise.
270 (VEX_W_0F5B_P_2): Likewise.
271 (VEX_W_0F5C_P_0): Likewise.
272 (VEX_W_0F5C_P_1): Likewise.
273 (VEX_W_0F5C_P_2): Likewise.
274 (VEX_W_0F5C_P_3): Likewise.
275 (VEX_W_0F5D_P_0): Likewise.
276 (VEX_W_0F5D_P_1): Likewise.
277 (VEX_W_0F5D_P_2): Likewise.
278 (VEX_W_0F5D_P_3): Likewise.
279 (VEX_W_0F5E_P_0): Likewise.
280 (VEX_W_0F5E_P_1): Likewise.
281 (VEX_W_0F5E_P_2): Likewise.
282 (VEX_W_0F5E_P_3): Likewise.
283 (VEX_W_0F5F_P_0): Likewise.
284 (VEX_W_0F5F_P_1): Likewise.
285 (VEX_W_0F5F_P_2): Likewise.
286 (VEX_W_0F5F_P_3): Likewise.
287 (VEX_W_0F60_P_2): Likewise.
288 (VEX_W_0F61_P_2): Likewise.
289 (VEX_W_0F62_P_2): Likewise.
290 (VEX_W_0F63_P_2): Likewise.
291 (VEX_W_0F64_P_2): Likewise.
292 (VEX_W_0F65_P_2): Likewise.
293 (VEX_W_0F66_P_2): Likewise.
294 (VEX_W_0F67_P_2): Likewise.
295 (VEX_W_0F68_P_2): Likewise.
296 (VEX_W_0F69_P_2): Likewise.
297 (VEX_W_0F6A_P_2): Likewise.
298 (VEX_W_0F6B_P_2): Likewise.
299 (VEX_W_0F6C_P_2): Likewise.
300 (VEX_W_0F6D_P_2): Likewise.
301 (VEX_W_0F6F_P_1): Likewise.
302 (VEX_W_0F6F_P_2): Likewise.
303 (VEX_W_0F70_P_1): Likewise.
304 (VEX_W_0F70_P_2): Likewise.
305 (VEX_W_0F70_P_3): Likewise.
306 (VEX_W_0F71_R_2_P_2): Likewise.
307 (VEX_W_0F71_R_4_P_2): Likewise.
308 (VEX_W_0F71_R_6_P_2): Likewise.
309 (VEX_W_0F72_R_2_P_2): Likewise.
310 (VEX_W_0F72_R_4_P_2): Likewise.
311 (VEX_W_0F72_R_6_P_2): Likewise.
312 (VEX_W_0F73_R_2_P_2): Likewise.
313 (VEX_W_0F73_R_3_P_2): Likewise.
314 (VEX_W_0F73_R_6_P_2): Likewise.
315 (VEX_W_0F73_R_7_P_2): Likewise.
316 (VEX_W_0F74_P_2): Likewise.
317 (VEX_W_0F75_P_2): Likewise.
318 (VEX_W_0F76_P_2): Likewise.
319 (VEX_W_0F77_P_0): Likewise.
320 (VEX_W_0F7C_P_2): Likewise.
321 (VEX_W_0F7C_P_3): Likewise.
322 (VEX_W_0F7D_P_2): Likewise.
323 (VEX_W_0F7D_P_3): Likewise.
324 (VEX_W_0F7E_P_1): Likewise.
325 (VEX_W_0F7F_P_1): Likewise.
326 (VEX_W_0F7F_P_2): Likewise.
327 (VEX_W_0FAE_R_2_M_0): Likewise.
328 (VEX_W_0FAE_R_3_M_0): Likewise.
329 (VEX_W_0FC2_P_0): Likewise.
330 (VEX_W_0FC2_P_1): Likewise.
331 (VEX_W_0FC2_P_2): Likewise.
332 (VEX_W_0FC2_P_3): Likewise.
333 (VEX_W_0FD0_P_2): Likewise.
334 (VEX_W_0FD0_P_3): Likewise.
335 (VEX_W_0FD1_P_2): Likewise.
336 (VEX_W_0FD2_P_2): Likewise.
337 (VEX_W_0FD3_P_2): Likewise.
338 (VEX_W_0FD4_P_2): Likewise.
339 (VEX_W_0FD5_P_2): Likewise.
340 (VEX_W_0FD6_P_2): Likewise.
341 (VEX_W_0FD7_P_2_M_1): Likewise.
342 (VEX_W_0FD8_P_2): Likewise.
343 (VEX_W_0FD9_P_2): Likewise.
344 (VEX_W_0FDA_P_2): Likewise.
345 (VEX_W_0FDB_P_2): Likewise.
346 (VEX_W_0FDC_P_2): Likewise.
347 (VEX_W_0FDD_P_2): Likewise.
348 (VEX_W_0FDE_P_2): Likewise.
349 (VEX_W_0FDF_P_2): Likewise.
350 (VEX_W_0FE0_P_2): Likewise.
351 (VEX_W_0FE1_P_2): Likewise.
352 (VEX_W_0FE2_P_2): Likewise.
353 (VEX_W_0FE3_P_2): Likewise.
354 (VEX_W_0FE4_P_2): Likewise.
355 (VEX_W_0FE5_P_2): Likewise.
356 (VEX_W_0FE6_P_1): Likewise.
357 (VEX_W_0FE6_P_2): Likewise.
358 (VEX_W_0FE6_P_3): Likewise.
359 (VEX_W_0FE7_P_2_M_0): Likewise.
360 (VEX_W_0FE8_P_2): Likewise.
361 (VEX_W_0FE9_P_2): Likewise.
362 (VEX_W_0FEA_P_2): Likewise.
363 (VEX_W_0FEB_P_2): Likewise.
364 (VEX_W_0FEC_P_2): Likewise.
365 (VEX_W_0FED_P_2): Likewise.
366 (VEX_W_0FEE_P_2): Likewise.
367 (VEX_W_0FEF_P_2): Likewise.
368 (VEX_W_0FF0_P_3_M_0): Likewise.
369 (VEX_W_0FF1_P_2): Likewise.
370 (VEX_W_0FF2_P_2): Likewise.
371 (VEX_W_0FF3_P_2): Likewise.
372 (VEX_W_0FF4_P_2): Likewise.
373 (VEX_W_0FF5_P_2): Likewise.
374 (VEX_W_0FF6_P_2): Likewise.
375 (VEX_W_0FF7_P_2): Likewise.
376 (VEX_W_0FF8_P_2): Likewise.
377 (VEX_W_0FF9_P_2): Likewise.
378 (VEX_W_0FFA_P_2): Likewise.
379 (VEX_W_0FFB_P_2): Likewise.
380 (VEX_W_0FFC_P_2): Likewise.
381 (VEX_W_0FFD_P_2): Likewise.
382 (VEX_W_0FFE_P_2): Likewise.
383 (VEX_W_0F3800_P_2): Likewise.
384 (VEX_W_0F3801_P_2): Likewise.
385 (VEX_W_0F3802_P_2): Likewise.
386 (VEX_W_0F3803_P_2): Likewise.
387 (VEX_W_0F3804_P_2): Likewise.
388 (VEX_W_0F3805_P_2): Likewise.
389 (VEX_W_0F3806_P_2): Likewise.
390 (VEX_W_0F3807_P_2): Likewise.
391 (VEX_W_0F3808_P_2): Likewise.
392 (VEX_W_0F3809_P_2): Likewise.
393 (VEX_W_0F380A_P_2): Likewise.
394 (VEX_W_0F380B_P_2): Likewise.
395 (VEX_W_0F3817_P_2): Likewise.
396 (VEX_W_0F381C_P_2): Likewise.
397 (VEX_W_0F381D_P_2): Likewise.
398 (VEX_W_0F381E_P_2): Likewise.
399 (VEX_W_0F3820_P_2): Likewise.
400 (VEX_W_0F3821_P_2): Likewise.
401 (VEX_W_0F3822_P_2): Likewise.
402 (VEX_W_0F3823_P_2): Likewise.
403 (VEX_W_0F3824_P_2): Likewise.
404 (VEX_W_0F3825_P_2): Likewise.
405 (VEX_W_0F3828_P_2): Likewise.
406 (VEX_W_0F3829_P_2): Likewise.
407 (VEX_W_0F382A_P_2_M_0): Likewise.
408 (VEX_W_0F382B_P_2): Likewise.
409 (VEX_W_0F3830_P_2): Likewise.
410 (VEX_W_0F3831_P_2): Likewise.
411 (VEX_W_0F3832_P_2): Likewise.
412 (VEX_W_0F3833_P_2): Likewise.
413 (VEX_W_0F3834_P_2): Likewise.
414 (VEX_W_0F3835_P_2): Likewise.
415 (VEX_W_0F3837_P_2): Likewise.
416 (VEX_W_0F3838_P_2): Likewise.
417 (VEX_W_0F3839_P_2): Likewise.
418 (VEX_W_0F383A_P_2): Likewise.
419 (VEX_W_0F383B_P_2): Likewise.
420 (VEX_W_0F383C_P_2): Likewise.
421 (VEX_W_0F383D_P_2): Likewise.
422 (VEX_W_0F383E_P_2): Likewise.
423 (VEX_W_0F383F_P_2): Likewise.
424 (VEX_W_0F3840_P_2): Likewise.
425 (VEX_W_0F3841_P_2): Likewise.
426 (VEX_W_0F38DB_P_2): Likewise.
427 (VEX_W_0F3A08_P_2): Likewise.
428 (VEX_W_0F3A09_P_2): Likewise.
429 (VEX_W_0F3A0A_P_2): Likewise.
430 (VEX_W_0F3A0B_P_2): Likewise.
431 (VEX_W_0F3A0C_P_2): Likewise.
432 (VEX_W_0F3A0D_P_2): Likewise.
433 (VEX_W_0F3A0E_P_2): Likewise.
434 (VEX_W_0F3A0F_P_2): Likewise.
435 (VEX_W_0F3A21_P_2): Likewise.
436 (VEX_W_0F3A40_P_2): Likewise.
437 (VEX_W_0F3A41_P_2): Likewise.
438 (VEX_W_0F3A42_P_2): Likewise.
439 (VEX_W_0F3A62_P_2): Likewise.
440 (VEX_W_0F3A63_P_2): Likewise.
441 (VEX_W_0F3ADF_P_2): Likewise.
442 (VEX_LEN_0F77_P_0): New.
443 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
444 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
445 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
446 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
447 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
448 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
449 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
450 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
451 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
452 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
453 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
454 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
455 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
456 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
457 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
458 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
459 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
460 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
461 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
462 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
463 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
464 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
465 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
466 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
467 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
468 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
469 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
470 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
471 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
472 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
473 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
474 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
475 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
476 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
477 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
478 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
479 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
480 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
481 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
482 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
483 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
484 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
485 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
486 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
487 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
488 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
489 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
490 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
491 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
492 (vex_table): Update VEX 0F28 and 0F29 entries.
493 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
494 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
495 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
496 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
497 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
498 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
499 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
500 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
501 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
502 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
503 VEX_LEN_0F3A0B_P_2 entries.
504 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
505 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
506 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
507 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
508 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
509 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
510 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
511 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
512 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
513 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
514 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
515 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
516 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
517 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
518 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
519 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
520 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
521 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
522 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
523 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
524 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
525 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
526 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
527 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
528 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
529 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
530 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
531 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
532 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
533 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
534 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
535 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
536 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
537 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
538 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
539 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
540 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
541 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
542 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
543 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
544 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
545 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
546 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
547 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
548 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
549 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
550 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
551 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
552 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
553 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
554 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
555 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
556 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
557 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
558 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
559 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
560 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
561 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
562 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
563 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
564 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
565 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
566 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
567 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
568 VEX_W_0F3ADF_P_2 entries.
569 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
570 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
571 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
572
6fa52824
L
5732018-09-17 H.J. Lu <hongjiu.lu@intel.com>
574
575 * i386-opc.tbl (VexWIG): New.
576 Replace VexW=3 with VexWIG.
577
db4cc665
L
5782018-09-15 H.J. Lu <hongjiu.lu@intel.com>
579
580 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
581 * i386-tbl.h: Regenerated.
582
3c374143
L
5832018-09-15 H.J. Lu <hongjiu.lu@intel.com>
584
585 PR gas/23665
586 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
587 VEX_LEN_0FD6_P_2 entries.
588 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
589 * i386-tbl.h: Regenerated.
590
6865c043
L
5912018-09-14 H.J. Lu <hongjiu.lu@intel.com>
592
593 PR gas/23642
594 * i386-opc.h (VEXWIG): New.
595 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
596 * i386-tbl.h: Regenerated.
597
70df6fc9
L
5982018-09-14 H.J. Lu <hongjiu.lu@intel.com>
599
600 PR binutils/23655
601 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
602 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
603 * i386-dis.c (EXxEVexR64): New.
604 (evex_rounding_64_mode): Likewise.
605 (OP_Rounding): Handle evex_rounding_64_mode.
606
d20dee9e
L
6072018-09-14 H.J. Lu <hongjiu.lu@intel.com>
608
609 PR binutils/23655
610 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
611 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
612 * i386-dis.c (Edqa): New.
613 (dqa_mode): Likewise.
614 (intel_operand_size): Handle dqa_mode as m_mode.
615 (OP_E_register): Handle dqa_mode as dq_mode.
616 (OP_E_memory): Set shift for dqa_mode based on address_mode.
617
5074ad8a
L
6182018-09-14 H.J. Lu <hongjiu.lu@intel.com>
619
620 * i386-dis.c (OP_E_memory): Reformat.
621
556059dd
JB
6222018-09-14 Jan Beulich <jbeulich@suse.com>
623
624 * i386-opc.tbl (crc32): Fold byte and word forms.
625 * i386-tbl.h: Re-generate.
626
41d1ab6a
L
6272018-09-13 H.J. Lu <hongjiu.lu@intel.com>
628
629 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
630 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
631 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
632 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
633 * i386-tbl.h: Regenerated.
634
57f6375e
JB
6352018-09-13 Jan Beulich <jbeulich@suse.com>
636
637 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
638 meaningless.
639 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
640 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
641 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
642 * i386-tbl.h: Re-generate.
643
2589a7e5
JB
6442018-09-13 Jan Beulich <jbeulich@suse.com>
645
646 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
647 AVX512_4VNNIW insns.
648 * i386-tbl.h: Re-generate.
649
a760eb41
JB
6502018-09-13 Jan Beulich <jbeulich@suse.com>
651
652 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
653 meaningless.
654 * i386-tbl.h: Re-generate.
655
e9042658
JB
6562018-09-13 Jan Beulich <jbeulich@suse.com>
657
658 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
659 meaningless.
660 * i386-tbl.h: Re-generate.
661
9caa306f
JB
6622018-09-13 Jan Beulich <jbeulich@suse.com>
663
664 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
665 meaningless.
666 * i386-tbl.h: Re-generate.
667
fb6ce599
JB
6682018-09-13 Jan Beulich <jbeulich@suse.com>
669
670 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
671 meaningless.
672 * i386-tbl.h: Re-generate.
673
6a8da886
JB
6742018-09-13 Jan Beulich <jbeulich@suse.com>
675
676 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
677 meaningless.
678 * i386-tbl.h: Re-generate.
679
c7f27919
JB
6802018-09-13 Jan Beulich <jbeulich@suse.com>
681
682 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
683 * i386-tbl.h: Re-generate.
684
0f407ee9
JB
6852018-09-13 Jan Beulich <jbeulich@suse.com>
686
687 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
688 * i386-tbl.h: Re-generate.
689
2fbbbee5
JB
6902018-09-13 Jan Beulich <jbeulich@suse.com>
691
692 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
693 meaningless.
694 * i386-tbl.h: Re-generate.
695
2b02b9a2
JB
6962018-09-13 Jan Beulich <jbeulich@suse.com>
697
698 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
699 meaningless.
700 * i386-tbl.h: Re-generate.
701
963c68aa
JB
7022018-09-13 Jan Beulich <jbeulich@suse.com>
703
704 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
705 * i386-tbl.h: Re-generate.
706
64e025c3
JB
7072018-09-13 Jan Beulich <jbeulich@suse.com>
708
709 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
710 * i386-tbl.h: Re-generate.
711
47603f88
JB
7122018-09-13 Jan Beulich <jbeulich@suse.com>
713
714 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
715 * i386-tbl.h: Re-generate.
716
0001cfd0
JB
7172018-09-13 Jan Beulich <jbeulich@suse.com>
718
719 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
720 meaningless.
721 * i386-tbl.h: Re-generate.
722
be4b452e
JB
7232018-09-13 Jan Beulich <jbeulich@suse.com>
724
725 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
726 meaningless.
727 * i386-tbl.h: Re-generate.
728
d09a1394
JB
7292018-09-13 Jan Beulich <jbeulich@suse.com>
730
731 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
732 meaningless.
733 * i386-tbl.h: Re-generate.
734
07599e13
JB
7352018-09-13 Jan Beulich <jbeulich@suse.com>
736
737 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
738 * i386-tbl.h: Re-generate.
739
1ee3e487
JB
7402018-09-13 Jan Beulich <jbeulich@suse.com>
741
742 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
743 * i386-tbl.h: Re-generate.
744
a5f580e5
JB
7452018-09-13 Jan Beulich <jbeulich@suse.com>
746
747 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
748 * i386-tbl.h: Re-generate.
749
49d5d12d
JB
7502018-09-13 Jan Beulich <jbeulich@suse.com>
751
752 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
753 (vpbroadcastw, rdpid): Drop NoRex64.
754 * i386-tbl.h: Re-generate.
755
f5eb1d70
JB
7562018-09-13 Jan Beulich <jbeulich@suse.com>
757
758 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
759 store templates, adding D.
760 * i386-tbl.h: Re-generate.
761
dbbc8b7e
JB
7622018-09-13 Jan Beulich <jbeulich@suse.com>
763
764 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
765 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
766 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
767 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
768 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
769 Fold load and store templates where possible, adding D. Drop
770 IgnoreSize where it was pointlessly present. Drop redundant
771 *word.
772 * i386-tbl.h: Re-generate.
773
d276ec69
JB
7742018-09-13 Jan Beulich <jbeulich@suse.com>
775
776 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
777 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
778 (intel_operand_size): Handle v_bndmk_mode.
779 (OP_E_memory): Likewise. Produce (bad) when also riprel.
780
9da4dfd6
JD
7812018-09-08 John Darrington <john@darrington.wattle.id.au>
782
783 * disassemble.c (ARCH_s12z): Define if ARCH_all.
784
be192bc2
JW
7852018-08-31 Kito Cheng <kito@andestech.com>
786
787 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
788 compressed floating point instructions.
789
43135d3b
JW
7902018-08-30 Kito Cheng <kito@andestech.com>
791
792 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
793 riscv_opcode.xlen_requirement.
794 * riscv-opc.c (riscv_opcodes): Update for struct change.
795
df28970f
MA
7962018-08-29 Martin Aberg <maberg@gaisler.com>
797
798 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
799 psr (PWRPSR) instruction.
800
9108bc33
CX
8012018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
802
803 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
804
bd782c07
CX
8052018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
806
807 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
808
ac8cb70f
CX
8092018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
810
811 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
812 loongson3a as an alias of gs464 for compatibility.
813 * mips-opc.c (mips_opcodes): Change Comments.
814
a693765e
CX
8152018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
816
817 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
818 option.
819 (print_mips_disassembler_options): Document -M loongson-ext.
820 * mips-opc.c (LEXT2): New macro.
821 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
822
bdc6c06e
CX
8232018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
824
825 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
826 descriptors.
827 (parse_mips_ase_option): Handle -M loongson-ext option.
828 (print_mips_disassembler_options): Document -M loongson-ext.
829 * mips-opc.c (IL3A): Delete.
830 * mips-opc.c (LEXT): New macro.
831 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
832 instructions.
833
716c08de
CX
8342018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
835
836 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
837 descriptors.
838 (parse_mips_ase_option): Handle -M loongson-cam option.
839 (print_mips_disassembler_options): Document -M loongson-cam.
840 * mips-opc.c (LCAM): New macro.
841 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
842 instructions.
843
9cf7e568
AM
8442018-08-21 Alan Modra <amodra@gmail.com>
845
846 * ppc-dis.c (operand_value_powerpc): Init "invalid".
847 (skip_optional_operands): Count optional operands, and update
848 ppc_optional_operand_value call.
849 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
850 (extract_vlensi): Likewise.
851 (extract_fxm): Return default value for missing optional operand.
852 (extract_ls, extract_raq, extract_tbr): Likewise.
853 (insert_sxl, extract_sxl): New functions.
854 (insert_esync, extract_esync): Remove Power9 handling and simplify.
855 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
856 flag and extra entry.
857 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
858 extract_sxl.
859
d203b41a 8602018-08-20 Alan Modra <amodra@gmail.com>
f4107842 861
d203b41a 862 * sh-opc.h (MASK): Simplify.
f4107842 863
08a8fe2f 8642018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 865
d203b41a
AM
866 * s12z-dis.c (bm_decode): Deal with cases where the mode is
867 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 868 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 869
08a8fe2f 8702018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM
871
872 * s12z.h: Delete.
7ba3ba91 873
1bc60e56
L
8742018-08-14 H.J. Lu <hongjiu.lu@intel.com>
875
876 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
877 address with the addr32 prefix and without base nor index
878 registers.
879
d871f3f4
L
8802018-08-11 H.J. Lu <hongjiu.lu@intel.com>
881
882 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
883 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
884 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
885 (cpu_flags): Add CpuCMOV and CpuFXSR.
886 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
887 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
888 * i386-init.h: Regenerated.
889 * i386-tbl.h: Likewise.
890
b6523c37 8912018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
892
893 * arc-regs.h: Update auxiliary registers.
894
e968fc9b
JB
8952018-08-06 Jan Beulich <jbeulich@suse.com>
896
897 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
898 (RegIP, RegIZ): Define.
899 * i386-reg.tbl: Adjust comments.
900 (rip): Use Qword instead of BaseIndex. Use RegIP.
901 (eip): Use Dword instead of BaseIndex. Use RegIP.
902 (riz): Add Qword. Use RegIZ.
903 (eiz): Add Dword. Use RegIZ.
904 * i386-tbl.h: Re-generate.
905
dbf8be89
JB
9062018-08-03 Jan Beulich <jbeulich@suse.com>
907
908 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
909 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
910 vpmovzxdq, vpmovzxwd): Remove NoRex64.
911 * i386-tbl.h: Re-generate.
912
c48dadc9
JB
9132018-08-03 Jan Beulich <jbeulich@suse.com>
914
915 * i386-gen.c (operand_types): Remove Mem field.
916 * i386-opc.h (union i386_operand_type): Remove mem field.
917 * i386-init.h, i386-tbl.h: Re-generate.
918
cb86a42a
AM
9192018-08-01 Alan Modra <amodra@gmail.com>
920
921 * po/POTFILES.in: Regenerate.
922
07cc0450
NC
9232018-07-31 Nick Clifton <nickc@redhat.com>
924
925 * po/sv.po: Updated Swedish translation.
926
1424ad86
JB
9272018-07-31 Jan Beulich <jbeulich@suse.com>
928
929 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
930 * i386-init.h, i386-tbl.h: Re-generate.
931
ae2387fe
JB
9322018-07-31 Jan Beulich <jbeulich@suse.com>
933
934 * i386-opc.h (ZEROING_MASKING) Rename to ...
935 (DYNAMIC_MASKING): ... this. Adjust comment.
936 * i386-opc.tbl (MaskingMorZ): Define.
937 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
938 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
939 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
940 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
941 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
942 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
943 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
944 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
945 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
946
6ff00b5e
JB
9472018-07-31 Jan Beulich <jbeulich@suse.com>
948
949 * i386-opc.tbl: Use element rather than vector size for AVX512*
950 scatter/gather insns.
951 * i386-tbl.h: Re-generate.
952
e951d5ca
JB
9532018-07-31 Jan Beulich <jbeulich@suse.com>
954
955 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
956 (cpu_flags): Drop CpuVREX.
957 * i386-opc.h (CpuVREX): Delete.
958 (union i386_cpu_flags): Remove cpuvrex.
959 * i386-init.h, i386-tbl.h: Re-generate.
960
eb41b248
JW
9612018-07-30 Jim Wilson <jimw@sifive.com>
962
963 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
964 fields.
965 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
966
b8891f8d
AJ
9672018-07-30 Andrew Jenner <andrew@codesourcery.com>
968
969 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
970 * Makefile.in: Regenerated.
971 * configure.ac: Add C-SKY.
972 * configure: Regenerated.
973 * csky-dis.c: New file.
974 * csky-opc.h: New file.
975 * disassemble.c (ARCH_csky): Define.
976 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
977 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
978
16065af1
AM
9792018-07-27 Alan Modra <amodra@gmail.com>
980
981 * ppc-opc.c (insert_sprbat): Correct function parameter and
982 return type.
983 (extract_sprbat): Likewise, variable too.
984
fa758a70
AC
9852018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
986 Alan Modra <amodra@gmail.com>
987
988 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
989 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
990 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
991 support disjointed BAT.
992 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
993 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
994 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
995
4a1b91ea
L
9962018-07-25 H.J. Lu <hongjiu.lu@intel.com>
997 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
998
999 * i386-gen.c (adjust_broadcast_modifier): New function.
1000 (process_i386_opcode_modifier): Add an argument for operands.
1001 Adjust the Broadcast value based on operands.
1002 (output_i386_opcode): Pass operand_types to
1003 process_i386_opcode_modifier.
1004 (process_i386_opcodes): Pass NULL as operands to
1005 process_i386_opcode_modifier.
1006 * i386-opc.h (BYTE_BROADCAST): New.
1007 (WORD_BROADCAST): Likewise.
1008 (DWORD_BROADCAST): Likewise.
1009 (QWORD_BROADCAST): Likewise.
1010 (i386_opcode_modifier): Expand broadcast to 3 bits.
1011 * i386-tbl.h: Regenerated.
1012
67ce483b
AM
10132018-07-24 Alan Modra <amodra@gmail.com>
1014
1015 PR 23430
1016 * or1k-desc.h: Regenerate.
1017
4174bfff
JB
10182018-07-24 Jan Beulich <jbeulich@suse.com>
1019
1020 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1021 vcvtusi2ss, and vcvtusi2sd.
1022 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1023 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1024 * i386-tbl.h: Re-generate.
1025
04e65276
CZ
10262018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1027
1028 * arc-opc.c (extract_w6): Fix extending the sign.
1029
47e6f81c
CZ
10302018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1031
1032 * arc-tbl.h (vewt): Allow it for ARC EM family.
1033
bb71536f
AM
10342018-07-23 Alan Modra <amodra@gmail.com>
1035
1036 PR 23419
1037 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1038 opcode variants for mtspr/mfspr encodings.
1039
8095d2f7
CX
10402018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1041 Maciej W. Rozycki <macro@mips.com>
1042
1043 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1044 loongson3a descriptors.
1045 (parse_mips_ase_option): Handle -M loongson-mmi option.
1046 (print_mips_disassembler_options): Document -M loongson-mmi.
1047 * mips-opc.c (LMMI): New macro.
1048 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1049 instructions.
1050
5f32791e
JB
10512018-07-19 Jan Beulich <jbeulich@suse.com>
1052
1053 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1054 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1055 IgnoreSize and [XYZ]MMword where applicable.
1056 * i386-tbl.h: Re-generate.
1057
625cbd7a
JB
10582018-07-19 Jan Beulich <jbeulich@suse.com>
1059
1060 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1061 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1062 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1063 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1064 * i386-tbl.h: Re-generate.
1065
86b15c32
JB
10662018-07-19 Jan Beulich <jbeulich@suse.com>
1067
1068 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1069 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1070 VPCLMULQDQ templates into their respective AVX512VL counterparts
1071 where possible, using Disp8ShiftVL and CheckRegSize instead of
1072 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1073 * i386-tbl.h: Re-generate.
1074
cf769ed5
JB
10752018-07-19 Jan Beulich <jbeulich@suse.com>
1076
1077 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1078 AVX512VL counterparts where possible, using Disp8ShiftVL and
1079 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1080 IgnoreSize) as appropriate.
1081 * i386-tbl.h: Re-generate.
1082
8282b7ad
JB
10832018-07-19 Jan Beulich <jbeulich@suse.com>
1084
1085 * i386-opc.tbl: Fold AVX512BW templates into their respective
1086 AVX512VL counterparts where possible, using Disp8ShiftVL and
1087 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1088 IgnoreSize) as appropriate.
1089 * i386-tbl.h: Re-generate.
1090
755908cc
JB
10912018-07-19 Jan Beulich <jbeulich@suse.com>
1092
1093 * i386-opc.tbl: Fold AVX512CD templates into their respective
1094 AVX512VL counterparts where possible, using Disp8ShiftVL and
1095 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1096 IgnoreSize) as appropriate.
1097 * i386-tbl.h: Re-generate.
1098
7091c612
JB
10992018-07-19 Jan Beulich <jbeulich@suse.com>
1100
1101 * i386-opc.h (DISP8_SHIFT_VL): New.
1102 * i386-opc.tbl (Disp8ShiftVL): Define.
1103 (various): Fold AVX512VL templates into their respective
1104 AVX512F counterparts where possible, using Disp8ShiftVL and
1105 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1106 IgnoreSize) as appropriate.
1107 * i386-tbl.h: Re-generate.
1108
c30be56e
JB
11092018-07-19 Jan Beulich <jbeulich@suse.com>
1110
1111 * Makefile.am: Change dependencies and rule for
1112 $(srcdir)/i386-init.h.
1113 * Makefile.in: Re-generate.
1114 * i386-gen.c (process_i386_opcodes): New local variable
1115 "marker". Drop opening of input file. Recognize marker and line
1116 number directives.
1117 * i386-opc.tbl (OPCODE_I386_H): Define.
1118 (i386-opc.h): Include it.
1119 (None): Undefine.
1120
11a322db
L
11212018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1122
1123 PR gas/23418
1124 * i386-opc.h (Byte): Update comments.
1125 (Word): Likewise.
1126 (Dword): Likewise.
1127 (Fword): Likewise.
1128 (Qword): Likewise.
1129 (Tbyte): Likewise.
1130 (Xmmword): Likewise.
1131 (Ymmword): Likewise.
1132 (Zmmword): Likewise.
1133 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1134 vcvttps2uqq.
1135 * i386-tbl.h: Regenerated.
1136
cde3679e
NC
11372018-07-12 Sudakshina Das <sudi.das@arm.com>
1138
1139 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1140 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1141 * aarch64-asm-2.c: Regenerate.
1142 * aarch64-dis-2.c: Regenerate.
1143 * aarch64-opc-2.c: Regenerate.
1144
45a28947
TC
11452018-07-12 Tamar Christina <tamar.christina@arm.com>
1146
1147 PR binutils/23192
1148 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1149 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1150 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1151 sqdmulh, sqrdmulh): Use Em16.
1152
c597cc3d
SD
11532018-07-11 Sudakshina Das <sudi.das@arm.com>
1154
1155 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1156 csdb together with them.
1157 (thumb32_opcodes): Likewise.
1158
a79eaed6
JB
11592018-07-11 Jan Beulich <jbeulich@suse.com>
1160
1161 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1162 requiring 32-bit registers as operands 2 and 3. Improve
1163 comments.
1164 (mwait, mwaitx): Fold templates. Improve comments.
1165 OPERAND_TYPE_INOUTPORTREG.
1166 * i386-tbl.h: Re-generate.
1167
2fb5be8d
JB
11682018-07-11 Jan Beulich <jbeulich@suse.com>
1169
1170 * i386-gen.c (operand_type_init): Remove
1171 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1172 OPERAND_TYPE_INOUTPORTREG.
1173 * i386-init.h: Re-generate.
1174
7f5cad30
JB
11752018-07-11 Jan Beulich <jbeulich@suse.com>
1176
1177 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1178 (wrssq, wrussq): Add Qword.
1179 * i386-tbl.h: Re-generate.
1180
f0a85b07
JB
11812018-07-11 Jan Beulich <jbeulich@suse.com>
1182
1183 * i386-opc.h: Rename OTMax to OTNum.
1184 (OTNumOfUints): Adjust calculation.
1185 (OTUnused): Directly alias to OTNum.
1186
9dcb0ba4
MR
11872018-07-09 Maciej W. Rozycki <macro@mips.com>
1188
1189 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1190 `reg_xys'.
1191 (lea_reg_xys): Likewise.
1192 (print_insn_loop_primitive): Rename `reg' local variable to
1193 `reg_dxy'.
1194
f311ba7e
TC
11952018-07-06 Tamar Christina <tamar.christina@arm.com>
1196
1197 PR binutils/23242
1198 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1199
cba05feb
TC
12002018-07-06 Tamar Christina <tamar.christina@arm.com>
1201
1202 PR binutils/23369
1203 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1204 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1205
471b9d15
MR
12062018-07-02 Maciej W. Rozycki <macro@mips.com>
1207
1208 PR tdep/8282
1209 * mips-dis.c (mips_option_arg_t): New enumeration.
1210 (mips_options): New variable.
1211 (disassembler_options_mips): New function.
1212 (print_mips_disassembler_options): Reimplement in terms of
1213 `disassembler_options_mips'.
1214 * arm-dis.c (disassembler_options_arm): Adapt to using the
1215 `disasm_options_and_args_t' structure.
1216 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1217 * s390-dis.c (disassembler_options_s390): Likewise.
1218
c0c468d5
TP
12192018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1220
1221 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1222 expected result.
1223 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1224 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1225 * testsuite/ld-arm/tls-longplt.d: Likewise.
1226
369c9167
TC
12272018-06-29 Tamar Christina <tamar.christina@arm.com>
1228
1229 PR binutils/23192
1230 * aarch64-asm-2.c: Regenerate.
1231 * aarch64-dis-2.c: Likewise.
1232 * aarch64-opc-2.c: Likewise.
1233 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1234 * aarch64-opc.c (operand_general_constraint_met_p,
1235 aarch64_print_operand): Likewise.
1236 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1237 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1238 fmlal2, fmlsl2.
1239 (AARCH64_OPERANDS): Add Em2.
1240
30aa1306
NC
12412018-06-26 Nick Clifton <nickc@redhat.com>
1242
1243 * po/uk.po: Updated Ukranian translation.
1244 * po/de.po: Updated German translation.
1245 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1246
eca4b721
NC
12472018-06-26 Nick Clifton <nickc@redhat.com>
1248
1249 * nfp-dis.c: Fix spelling mistake.
1250
71300e2c
NC
12512018-06-24 Nick Clifton <nickc@redhat.com>
1252
1253 * configure: Regenerate.
1254 * po/opcodes.pot: Regenerate.
1255
719d8288
NC
12562018-06-24 Nick Clifton <nickc@redhat.com>
1257
1258 2.31 branch created.
1259
514cd3a0
TC
12602018-06-19 Tamar Christina <tamar.christina@arm.com>
1261
1262 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1263 * aarch64-asm-2.c: Regenerate.
1264 * aarch64-dis-2.c: Likewise.
1265
385e4d0f
MR
12662018-06-21 Maciej W. Rozycki <macro@mips.com>
1267
1268 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1269 `-M ginv' option description.
1270
160d1b3d
SH
12712018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1272
1273 PR gas/23305
1274 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1275 la and lla.
1276
d0ac1c44
SM
12772018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1278
1279 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1280 * configure.ac: Remove AC_PREREQ.
1281 * Makefile.in: Re-generate.
1282 * aclocal.m4: Re-generate.
1283 * configure: Re-generate.
1284
6f20c942
FS
12852018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1286
1287 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1288 mips64r6 descriptors.
1289 (parse_mips_ase_option): Handle -Mginv option.
1290 (print_mips_disassembler_options): Document -Mginv.
1291 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1292 (GINV): New macro.
1293 (mips_opcodes): Define ginvi and ginvt.
1294
730c3174
SE
12952018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1296 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1297
1298 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1299 * mips-opc.c (CRC, CRC64): New macros.
1300 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1301 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1302 crc32cd for CRC64.
1303
cb366992
EB
13042018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1305
1306 PR 20319
1307 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1308 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1309
ce72cd46
AM
13102018-06-06 Alan Modra <amodra@gmail.com>
1311
1312 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1313 setjmp. Move init for some other vars later too.
1314
4b8e28c7
MF
13152018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1316
1317 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1318 (dis_private): Add new fields for property section tracking.
1319 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1320 (xtensa_instruction_fits): New functions.
1321 (fetch_data): Bump minimal fetch size to 4.
1322 (print_insn_xtensa): Make struct dis_private static.
1323 Load and prepare property table on section change.
1324 Don't disassemble literals. Don't disassemble instructions that
1325 cross property table boundaries.
1326
55e99962
L
13272018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1328
1329 * configure: Regenerated.
1330
733bd0ab
JB
13312018-06-01 Jan Beulich <jbeulich@suse.com>
1332
1333 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1334 * i386-tbl.h: Re-generate.
1335
dfd27d41
JB
13362018-06-01 Jan Beulich <jbeulich@suse.com>
1337
1338 * i386-opc.tbl (sldt, str): Add NoRex64.
1339 * i386-tbl.h: Re-generate.
1340
64795710
JB
13412018-06-01 Jan Beulich <jbeulich@suse.com>
1342
1343 * i386-opc.tbl (invpcid): Add Oword.
1344 * i386-tbl.h: Re-generate.
1345
030157d8
AM
13462018-06-01 Alan Modra <amodra@gmail.com>
1347
1348 * sysdep.h (_bfd_error_handler): Don't declare.
1349 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1350 * rl78-decode.opc: Likewise.
1351 * msp430-decode.c: Regenerate.
1352 * rl78-decode.c: Regenerate.
1353
a9660a6f
AP
13542018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1355
1356 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1357 * i386-init.h : Regenerated.
1358
277eb7f6
AM
13592018-05-25 Alan Modra <amodra@gmail.com>
1360
1361 * Makefile.in: Regenerate.
1362 * po/POTFILES.in: Regenerate.
1363
98553ad3
PB
13642018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1365
1366 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1367 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1368 (insert_bab, extract_bab, insert_btab, extract_btab,
1369 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1370 (BAT, BBA VBA RBS XB6S): Delete macros.
1371 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1372 (BB, BD, RBX, XC6): Update for new macros.
1373 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1374 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1375 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1376 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1377
7b4ae824
JD
13782018-05-18 John Darrington <john@darrington.wattle.id.au>
1379
1380 * Makefile.am: Add support for s12z architecture.
1381 * configure.ac: Likewise.
1382 * disassemble.c: Likewise.
1383 * disassemble.h: Likewise.
1384 * Makefile.in: Regenerate.
1385 * configure: Regenerate.
1386 * s12z-dis.c: New file.
1387 * s12z.h: New file.
1388
29e0f0a1
AM
13892018-05-18 Alan Modra <amodra@gmail.com>
1390
1391 * nfp-dis.c: Don't #include libbfd.h.
1392 (init_nfp3200_priv): Use bfd_get_section_contents.
1393 (nit_nfp6000_mecsr_sec): Likewise.
1394
809276d2
NC
13952018-05-17 Nick Clifton <nickc@redhat.com>
1396
1397 * po/zh_CN.po: Updated simplified Chinese translation.
1398
ff329288
TC
13992018-05-16 Tamar Christina <tamar.christina@arm.com>
1400
1401 PR binutils/23109
1402 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1403 * aarch64-dis-2.c: Regenerate.
1404
f9830ec1
TC
14052018-05-15 Tamar Christina <tamar.christina@arm.com>
1406
1407 PR binutils/21446
1408 * aarch64-asm.c (opintl.h): Include.
1409 (aarch64_ins_sysreg): Enforce read/write constraints.
1410 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1411 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1412 (F_REG_READ, F_REG_WRITE): New.
1413 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1414 AARCH64_OPND_SYSREG.
1415 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1416 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1417 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1418 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1419 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1420 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1421 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1422 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1423 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1424 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1425 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1426 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1427 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1428 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1429 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1430 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1431 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1432
7d02540a
TC
14332018-05-15 Tamar Christina <tamar.christina@arm.com>
1434
1435 PR binutils/21446
1436 * aarch64-dis.c (no_notes: New.
1437 (parse_aarch64_dis_option): Support notes.
1438 (aarch64_decode_insn, print_operands): Likewise.
1439 (print_aarch64_disassembler_options): Document notes.
1440 * aarch64-opc.c (aarch64_print_operand): Support notes.
1441
561a72d4
TC
14422018-05-15 Tamar Christina <tamar.christina@arm.com>
1443
1444 PR binutils/21446
1445 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1446 and take error struct.
1447 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1448 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1449 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1450 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1451 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1452 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1453 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1454 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1455 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1456 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1457 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1458 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1459 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1460 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1461 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1462 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1463 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1464 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1465 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1466 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1467 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1468 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1469 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1470 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1471 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1472 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1473 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1474 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1475 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1476 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1477 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1478 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1479 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1480 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1481 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1482 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1483 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1484 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1485 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1486 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1487 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1488 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1489 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1490 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1491 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1492 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1493 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1494 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1495 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1496 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1497 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1498 (determine_disassembling_preference, aarch64_decode_insn,
1499 print_insn_aarch64_word, print_insn_data): Take errors struct.
1500 (print_insn_aarch64): Use errors.
1501 * aarch64-asm-2.c: Regenerate.
1502 * aarch64-dis-2.c: Regenerate.
1503 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1504 boolean in aarch64_insert_operan.
1505 (print_operand_extractor): Likewise.
1506 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1507
1678bd35
FT
15082018-05-15 Francois H. Theron <francois.theron@netronome.com>
1509
1510 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1511
06cfb1c8
L
15122018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1513
1514 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1515
84f9f8c3
AM
15162018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1517
1518 * cr16-opc.c (cr16_instruction): Comment typo fix.
1519 * hppa-dis.c (print_insn_hppa): Likewise.
1520
e6f372ba
JW
15212018-05-08 Jim Wilson <jimw@sifive.com>
1522
1523 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1524 (match_c_slli64, match_srxi_as_c_srxi): New.
1525 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1526 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1527 <c.slli, c.srli, c.srai>: Use match_s_slli.
1528 <c.slli64, c.srli64, c.srai64>: New.
1529
f413a913
AM
15302018-05-08 Alan Modra <amodra@gmail.com>
1531
1532 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1533 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1534 partition opcode space for index lookup.
1535
a87a6478
PB
15362018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1537
1538 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1539 <insn_length>: ...with this. Update usage.
1540 Remove duplicate call to *info->memory_error_func.
1541
c0a30a9f
L
15422018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1543 H.J. Lu <hongjiu.lu@intel.com>
1544
1545 * i386-dis.c (Gva): New.
1546 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1547 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1548 (prefix_table): New instructions (see prefix above).
1549 (mod_table): New instructions (see prefix above).
1550 (OP_G): Handle va_mode.
1551 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1552 CPU_MOVDIR64B_FLAGS.
1553 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1554 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1555 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1556 * i386-opc.tbl: Add movidir{i,64b}.
1557 * i386-init.h: Regenerated.
1558 * i386-tbl.h: Likewise.
1559
75c0a438
L
15602018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1561
1562 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1563 AddrPrefixOpReg.
1564 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1565 (AddrPrefixOpReg): This.
1566 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1567 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1568
2ceb7719
PB
15692018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1570
1571 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1572 (vle_num_opcodes): Likewise.
1573 (spe2_num_opcodes): Likewise.
1574 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1575 initialization loop.
1576 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1577 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1578 only once.
1579
b3ac5c6c
TC
15802018-05-01 Tamar Christina <tamar.christina@arm.com>
1581
1582 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1583
fe944acf
FT
15842018-04-30 Francois H. Theron <francois.theron@netronome.com>
1585
1586 Makefile.am: Added nfp-dis.c.
1587 configure.ac: Added bfd_nfp_arch.
1588 disassemble.h: Added print_insn_nfp prototype.
1589 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1590 nfp-dis.c: New, for NFP support.
1591 po/POTFILES.in: Added nfp-dis.c to the list.
1592 Makefile.in: Regenerate.
1593 configure: Regenerate.
1594
e2195274
JB
15952018-04-26 Jan Beulich <jbeulich@suse.com>
1596
1597 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1598 templates into their base ones.
1599 * i386-tlb.h: Re-generate.
1600
59ef5df4
JB
16012018-04-26 Jan Beulich <jbeulich@suse.com>
1602
1603 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1604 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1605 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1606 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1607 * i386-init.h: Re-generate.
1608
6e041cf4
JB
16092018-04-26 Jan Beulich <jbeulich@suse.com>
1610
1611 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1612 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1613 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1614 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1615 comment.
1616 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1617 and CpuRegMask.
1618 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1619 CpuRegMask: Delete.
1620 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1621 cpuregzmm, and cpuregmask.
1622 * i386-init.h: Re-generate.
1623 * i386-tbl.h: Re-generate.
1624
0e0eea78
JB
16252018-04-26 Jan Beulich <jbeulich@suse.com>
1626
1627 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1628 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1629 * i386-init.h: Re-generate.
1630
2f1bada2
JB
16312018-04-26 Jan Beulich <jbeulich@suse.com>
1632
1633 * i386-gen.c (VexImmExt): Delete.
1634 * i386-opc.h (VexImmExt, veximmext): Delete.
1635 * i386-opc.tbl: Drop all VexImmExt uses.
1636 * i386-tlb.h: Re-generate.
1637
bacd1457
JB
16382018-04-25 Jan Beulich <jbeulich@suse.com>
1639
1640 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1641 register-only forms.
1642 * i386-tlb.h: Re-generate.
1643
10bba94b
TC
16442018-04-25 Tamar Christina <tamar.christina@arm.com>
1645
1646 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1647
c48935d7
IT
16482018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1649
1650 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1651 PREFIX_0F1C.
1652 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1653 (cpu_flags): Add CpuCLDEMOTE.
1654 * i386-init.h: Regenerate.
1655 * i386-opc.h (enum): Add CpuCLDEMOTE,
1656 (i386_cpu_flags): Add cpucldemote.
1657 * i386-opc.tbl: Add cldemote.
1658 * i386-tbl.h: Regenerate.
1659
211dc24b
AM
16602018-04-16 Alan Modra <amodra@gmail.com>
1661
1662 * Makefile.am: Remove sh5 and sh64 support.
1663 * configure.ac: Likewise.
1664 * disassemble.c: Likewise.
1665 * disassemble.h: Likewise.
1666 * sh-dis.c: Likewise.
1667 * sh64-dis.c: Delete.
1668 * sh64-opc.c: Delete.
1669 * sh64-opc.h: Delete.
1670 * Makefile.in: Regenerate.
1671 * configure: Regenerate.
1672 * po/POTFILES.in: Regenerate.
1673
a9a4b302
AM
16742018-04-16 Alan Modra <amodra@gmail.com>
1675
1676 * Makefile.am: Remove w65 support.
1677 * configure.ac: Likewise.
1678 * disassemble.c: Likewise.
1679 * disassemble.h: Likewise.
1680 * w65-dis.c: Delete.
1681 * w65-opc.h: Delete.
1682 * Makefile.in: Regenerate.
1683 * configure: Regenerate.
1684 * po/POTFILES.in: Regenerate.
1685
04cb01fd
AM
16862018-04-16 Alan Modra <amodra@gmail.com>
1687
1688 * configure.ac: Remove we32k support.
1689 * configure: Regenerate.
1690
c2bf1eec
AM
16912018-04-16 Alan Modra <amodra@gmail.com>
1692
1693 * Makefile.am: Remove m88k support.
1694 * configure.ac: Likewise.
1695 * disassemble.c: Likewise.
1696 * disassemble.h: Likewise.
1697 * m88k-dis.c: Delete.
1698 * Makefile.in: Regenerate.
1699 * configure: Regenerate.
1700 * po/POTFILES.in: Regenerate.
1701
6793974d
AM
17022018-04-16 Alan Modra <amodra@gmail.com>
1703
1704 * Makefile.am: Remove i370 support.
1705 * configure.ac: Likewise.
1706 * disassemble.c: Likewise.
1707 * disassemble.h: Likewise.
1708 * i370-dis.c: Delete.
1709 * i370-opc.c: Delete.
1710 * Makefile.in: Regenerate.
1711 * configure: Regenerate.
1712 * po/POTFILES.in: Regenerate.
1713
e82aa794
AM
17142018-04-16 Alan Modra <amodra@gmail.com>
1715
1716 * Makefile.am: Remove h8500 support.
1717 * configure.ac: Likewise.
1718 * disassemble.c: Likewise.
1719 * disassemble.h: Likewise.
1720 * h8500-dis.c: Delete.
1721 * h8500-opc.h: Delete.
1722 * Makefile.in: Regenerate.
1723 * configure: Regenerate.
1724 * po/POTFILES.in: Regenerate.
1725
fceadf09
AM
17262018-04-16 Alan Modra <amodra@gmail.com>
1727
1728 * configure.ac: Remove tahoe support.
1729 * configure: Regenerate.
1730
ae1d3843
L
17312018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1732
1733 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1734 umwait.
1735 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1736 64-bit mode.
1737 * i386-tbl.h: Regenerated.
1738
de89d0a3
IT
17392018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1740
1741 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1742 PREFIX_MOD_1_0FAE_REG_6.
1743 (va_mode): New.
1744 (OP_E_register): Use va_mode.
1745 * i386-dis-evex.h (prefix_table):
1746 New instructions (see prefixes above).
1747 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1748 (cpu_flags): Likewise.
1749 * i386-opc.h (enum): Likewise.
1750 (i386_cpu_flags): Likewise.
1751 * i386-opc.tbl: Add umonitor, umwait, tpause.
1752 * i386-init.h: Regenerate.
1753 * i386-tbl.h: Likewise.
1754
a8eb42a8
AM
17552018-04-11 Alan Modra <amodra@gmail.com>
1756
1757 * opcodes/i860-dis.c: Delete.
1758 * opcodes/i960-dis.c: Delete.
1759 * Makefile.am: Remove i860 and i960 support.
1760 * configure.ac: Likewise.
1761 * disassemble.c: Likewise.
1762 * disassemble.h: Likewise.
1763 * Makefile.in: Regenerate.
1764 * configure: Regenerate.
1765 * po/POTFILES.in: Regenerate.
1766
caf0678c
L
17672018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1768
1769 PR binutils/23025
1770 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1771 to 0.
1772 (print_insn): Clear vex instead of vex.evex.
1773
4fb0d2b9
NC
17742018-04-04 Nick Clifton <nickc@redhat.com>
1775
1776 * po/es.po: Updated Spanish translation.
1777
c39e5b26
JB
17782018-03-28 Jan Beulich <jbeulich@suse.com>
1779
1780 * i386-gen.c (opcode_modifiers): Delete VecESize.
1781 * i386-opc.h (VecESize): Delete.
1782 (struct i386_opcode_modifier): Delete vecesize.
1783 * i386-opc.tbl: Drop VecESize.
1784 * i386-tlb.h: Re-generate.
1785
8e6e0792
JB
17862018-03-28 Jan Beulich <jbeulich@suse.com>
1787
1788 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1789 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1790 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1791 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1792 * i386-tlb.h: Re-generate.
1793
9f123b91
JB
17942018-03-28 Jan Beulich <jbeulich@suse.com>
1795
1796 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1797 Fold AVX512 forms
1798 * i386-tlb.h: Re-generate.
1799
9646c87b
JB
18002018-03-28 Jan Beulich <jbeulich@suse.com>
1801
1802 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1803 (vex_len_table): Drop Y for vcvt*2si.
1804 (putop): Replace plain 'Y' handling by abort().
1805
c8d59609
NC
18062018-03-28 Nick Clifton <nickc@redhat.com>
1807
1808 PR 22988
1809 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1810 instructions with only a base address register.
1811 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1812 handle AARHC64_OPND_SVE_ADDR_R.
1813 (aarch64_print_operand): Likewise.
1814 * aarch64-asm-2.c: Regenerate.
1815 * aarch64_dis-2.c: Regenerate.
1816 * aarch64-opc-2.c: Regenerate.
1817
b8c169f3
JB
18182018-03-22 Jan Beulich <jbeulich@suse.com>
1819
1820 * i386-opc.tbl: Drop VecESize from register only insn forms and
1821 memory forms not allowing broadcast.
1822 * i386-tlb.h: Re-generate.
1823
96bc132a
JB
18242018-03-22 Jan Beulich <jbeulich@suse.com>
1825
1826 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1827 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1828 sha256*): Drop Disp<N>.
1829
9f79e886
JB
18302018-03-22 Jan Beulich <jbeulich@suse.com>
1831
1832 * i386-dis.c (EbndS, bnd_swap_mode): New.
1833 (prefix_table): Use EbndS.
1834 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1835 * i386-opc.tbl (bndmov): Move misplaced Load.
1836 * i386-tlb.h: Re-generate.
1837
d6793fa1
JB
18382018-03-22 Jan Beulich <jbeulich@suse.com>
1839
1840 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1841 templates allowing memory operands and folded ones for register
1842 only flavors.
1843 * i386-tlb.h: Re-generate.
1844
f7768225
JB
18452018-03-22 Jan Beulich <jbeulich@suse.com>
1846
1847 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1848 256-bit templates. Drop redundant leftover Disp<N>.
1849 * i386-tlb.h: Re-generate.
1850
0e35537d
JW
18512018-03-14 Kito Cheng <kito.cheng@gmail.com>
1852
1853 * riscv-opc.c (riscv_insn_types): New.
1854
b4a3689a
NC
18552018-03-13 Nick Clifton <nickc@redhat.com>
1856
1857 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1858
d3d50934
L
18592018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1860
1861 * i386-opc.tbl: Add Optimize to clr.
1862 * i386-tbl.h: Regenerated.
1863
bd5dea88
L
18642018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1865
1866 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1867 * i386-opc.h (OldGcc): Removed.
1868 (i386_opcode_modifier): Remove oldgcc.
1869 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1870 instructions for old (<= 2.8.1) versions of gcc.
1871 * i386-tbl.h: Regenerated.
1872
e771e7c9
JB
18732018-03-08 Jan Beulich <jbeulich@suse.com>
1874
1875 * i386-opc.h (EVEXDYN): New.
1876 * i386-opc.tbl: Fold various AVX512VL templates.
1877 * i386-tlb.h: Re-generate.
1878
ed438a93
JB
18792018-03-08 Jan Beulich <jbeulich@suse.com>
1880
1881 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1882 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1883 vpexpandd, vpexpandq): Fold AFX512VF templates.
1884 * i386-tlb.h: Re-generate.
1885
454172a9
JB
18862018-03-08 Jan Beulich <jbeulich@suse.com>
1887
1888 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1889 Fold 128- and 256-bit VEX-encoded templates.
1890 * i386-tlb.h: Re-generate.
1891
36824150
JB
18922018-03-08 Jan Beulich <jbeulich@suse.com>
1893
1894 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1895 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1896 vpexpandd, vpexpandq): Fold AVX512F templates.
1897 * i386-tlb.h: Re-generate.
1898
e7f5c0a9
JB
18992018-03-08 Jan Beulich <jbeulich@suse.com>
1900
1901 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1902 64-bit templates. Drop Disp<N>.
1903 * i386-tlb.h: Re-generate.
1904
25a4277f
JB
19052018-03-08 Jan Beulich <jbeulich@suse.com>
1906
1907 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1908 and 256-bit templates.
1909 * i386-tlb.h: Re-generate.
1910
d2224064
JB
19112018-03-08 Jan Beulich <jbeulich@suse.com>
1912
1913 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1914 * i386-tlb.h: Re-generate.
1915
1b193f0b
JB
19162018-03-08 Jan Beulich <jbeulich@suse.com>
1917
1918 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1919 Drop NoAVX.
1920 * i386-tlb.h: Re-generate.
1921
f2f6a710
JB
19222018-03-08 Jan Beulich <jbeulich@suse.com>
1923
1924 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1925 * i386-tlb.h: Re-generate.
1926
38e314eb
JB
19272018-03-08 Jan Beulich <jbeulich@suse.com>
1928
1929 * i386-gen.c (opcode_modifiers): Delete FloatD.
1930 * i386-opc.h (FloatD): Delete.
1931 (struct i386_opcode_modifier): Delete floatd.
1932 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1933 FloatD by D.
1934 * i386-tlb.h: Re-generate.
1935
d53e6b98
JB
19362018-03-08 Jan Beulich <jbeulich@suse.com>
1937
1938 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1939
2907c2f5
JB
19402018-03-08 Jan Beulich <jbeulich@suse.com>
1941
1942 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1943 * i386-tlb.h: Re-generate.
1944
73053c1f
JB
19452018-03-08 Jan Beulich <jbeulich@suse.com>
1946
1947 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1948 forms.
1949 * i386-tlb.h: Re-generate.
1950
52fe4420
AM
19512018-03-07 Alan Modra <amodra@gmail.com>
1952
1953 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1954 bfd_arch_rs6000.
1955 * disassemble.h (print_insn_rs6000): Delete.
1956 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1957 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1958 (print_insn_rs6000): Delete.
1959
a6743a54
AM
19602018-03-03 Alan Modra <amodra@gmail.com>
1961
1962 * sysdep.h (opcodes_error_handler): Define.
1963 (_bfd_error_handler): Declare.
1964 * Makefile.am: Remove stray #.
1965 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1966 EDIT" comment.
1967 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1968 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1969 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1970 opcodes_error_handler to print errors. Standardize error messages.
1971 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1972 and include opintl.h.
1973 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1974 * i386-gen.c: Standardize error messages.
1975 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1976 * Makefile.in: Regenerate.
1977 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1978 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1979 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1980 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1981 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1982 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1983 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1984 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1985 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1986 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1987 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1988 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1989 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1990
8305403a
L
19912018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1992
1993 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1994 vpsub[bwdq] instructions.
1995 * i386-tbl.h: Regenerated.
1996
e184813f
AM
19972018-03-01 Alan Modra <amodra@gmail.com>
1998
1999 * configure.ac (ALL_LINGUAS): Sort.
2000 * configure: Regenerate.
2001
5b616bef
TP
20022018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2003
2004 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2005 macro by assignements.
2006
b6f8c7c4
L
20072018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2008
2009 PR gas/22871
2010 * i386-gen.c (opcode_modifiers): Add Optimize.
2011 * i386-opc.h (Optimize): New enum.
2012 (i386_opcode_modifier): Add optimize.
2013 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2014 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2015 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2016 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2017 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2018 vpxord and vpxorq.
2019 * i386-tbl.h: Regenerated.
2020
e95b887f
AM
20212018-02-26 Alan Modra <amodra@gmail.com>
2022
2023 * crx-dis.c (getregliststring): Allocate a large enough buffer
2024 to silence false positive gcc8 warning.
2025
0bccfb29
JW
20262018-02-22 Shea Levy <shea@shealevy.com>
2027
2028 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2029
6b6b6807
L
20302018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2031
2032 * i386-opc.tbl: Add {rex},
2033 * i386-tbl.h: Regenerated.
2034
75f31665
MR
20352018-02-20 Maciej W. Rozycki <macro@mips.com>
2036
2037 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2038 (mips16_opcodes): Replace `M' with `m' for "restore".
2039
e207bc53
TP
20402018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2041
2042 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2043
87993319
MR
20442018-02-13 Maciej W. Rozycki <macro@mips.com>
2045
2046 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2047 variable to `function_index'.
2048
68d20676
NC
20492018-02-13 Nick Clifton <nickc@redhat.com>
2050
2051 PR 22823
2052 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2053 about truncation of printing.
2054
d2159fdc
HW
20552018-02-12 Henry Wong <henry@stuffedcow.net>
2056
2057 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2058
f174ef9f
NC
20592018-02-05 Nick Clifton <nickc@redhat.com>
2060
2061 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2062
be3a8dca
IT
20632018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2064
2065 * i386-dis.c (enum): Add pconfig.
2066 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2067 (cpu_flags): Add CpuPCONFIG.
2068 * i386-opc.h (enum): Add CpuPCONFIG.
2069 (i386_cpu_flags): Add cpupconfig.
2070 * i386-opc.tbl: Add PCONFIG instruction.
2071 * i386-init.h: Regenerate.
2072 * i386-tbl.h: Likewise.
2073
3233d7d0
IT
20742018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2075
2076 * i386-dis.c (enum): Add PREFIX_0F09.
2077 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2078 (cpu_flags): Add CpuWBNOINVD.
2079 * i386-opc.h (enum): Add CpuWBNOINVD.
2080 (i386_cpu_flags): Add cpuwbnoinvd.
2081 * i386-opc.tbl: Add WBNOINVD instruction.
2082 * i386-init.h: Regenerate.
2083 * i386-tbl.h: Likewise.
2084
e925c834
JW
20852018-01-17 Jim Wilson <jimw@sifive.com>
2086
2087 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2088
d777820b
IT
20892018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2090
2091 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2092 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2093 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2094 (cpu_flags): Add CpuIBT, CpuSHSTK.
2095 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2096 (i386_cpu_flags): Add cpuibt, cpushstk.
2097 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2098 * i386-init.h: Regenerate.
2099 * i386-tbl.h: Likewise.
2100
f6efed01
NC
21012018-01-16 Nick Clifton <nickc@redhat.com>
2102
2103 * po/pt_BR.po: Updated Brazilian Portugese translation.
2104 * po/de.po: Updated German translation.
2105
2721d702
JW
21062018-01-15 Jim Wilson <jimw@sifive.com>
2107
2108 * riscv-opc.c (match_c_nop): New.
2109 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2110
616dcb87
NC
21112018-01-15 Nick Clifton <nickc@redhat.com>
2112
2113 * po/uk.po: Updated Ukranian translation.
2114
3957a496
NC
21152018-01-13 Nick Clifton <nickc@redhat.com>
2116
2117 * po/opcodes.pot: Regenerated.
2118
769c7ea5
NC
21192018-01-13 Nick Clifton <nickc@redhat.com>
2120
2121 * configure: Regenerate.
2122
faf766e3
NC
21232018-01-13 Nick Clifton <nickc@redhat.com>
2124
2125 2.30 branch created.
2126
888a89da
IT
21272018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2128
2129 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2130 * i386-tbl.h: Regenerate.
2131
cbda583a
JB
21322018-01-10 Jan Beulich <jbeulich@suse.com>
2133
2134 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2135 * i386-tbl.h: Re-generate.
2136
c9e92278
JB
21372018-01-10 Jan Beulich <jbeulich@suse.com>
2138
2139 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2140 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2141 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2142 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2143 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2144 Disp8MemShift of AVX512VL forms.
2145 * i386-tbl.h: Re-generate.
2146
35fd2b2b
JW
21472018-01-09 Jim Wilson <jimw@sifive.com>
2148
2149 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2150 then the hi_addr value is zero.
2151
91d8b670
JG
21522018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2153
2154 * arm-dis.c (arm_opcodes): Add csdb.
2155 (thumb32_opcodes): Add csdb.
2156
be2e7d95
JG
21572018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2158
2159 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2160 * aarch64-asm-2.c: Regenerate.
2161 * aarch64-dis-2.c: Regenerate.
2162 * aarch64-opc-2.c: Regenerate.
2163
704a705d
L
21642018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2165
2166 PR gas/22681
2167 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2168 Remove AVX512 vmovd with 64-bit operands.
2169 * i386-tbl.h: Regenerated.
2170
35eeb78f
JW
21712018-01-05 Jim Wilson <jimw@sifive.com>
2172
2173 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2174 jalr.
2175
219d1afa
AM
21762018-01-03 Alan Modra <amodra@gmail.com>
2177
2178 Update year range in copyright notice of all files.
2179
1508bbf5
JB
21802018-01-02 Jan Beulich <jbeulich@suse.com>
2181
2182 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2183 and OPERAND_TYPE_REGZMM entries.
2184
1e563868 2185For older changes see ChangeLog-2017
3499769a 2186\f
1e563868 2187Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM
2188
2189Copying and distribution of this file, with or without modification,
2190are permitted in any medium without royalty provided the copyright
2191notice and this notice are preserved.
2192
2193Local Variables:
2194mode: change-log
2195left-margin: 8
2196fill-column: 74
2197version-control: never
2198End:
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