Commit | Line | Data |
---|---|---|
5b616bef TP |
1 | 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com> |
2 | ||
3 | * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY | |
4 | macro by assignements. | |
5 | ||
b6f8c7c4 L |
6 | 2018-02-27 H.J. Lu <hongjiu.lu@intel.com> |
7 | ||
8 | PR gas/22871 | |
9 | * i386-gen.c (opcode_modifiers): Add Optimize. | |
10 | * i386-opc.h (Optimize): New enum. | |
11 | (i386_opcode_modifier): Add optimize. | |
12 | * i386-opc.tbl: Add "Optimize" to "mov $imm, reg", | |
13 | "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem", | |
14 | "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem", | |
15 | "movq $imm, reg" and AVX256 and AVX512 versions of vandnps, | |
16 | vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor, | |
17 | vpxord and vpxorq. | |
18 | * i386-tbl.h: Regenerated. | |
19 | ||
e95b887f AM |
20 | 2018-02-26 Alan Modra <amodra@gmail.com> |
21 | ||
22 | * crx-dis.c (getregliststring): Allocate a large enough buffer | |
23 | to silence false positive gcc8 warning. | |
24 | ||
0bccfb29 JW |
25 | 2018-02-22 Shea Levy <shea@shealevy.com> |
26 | ||
27 | * disassemble.c (ARCH_riscv): Define if ARCH_all. | |
28 | ||
6b6b6807 L |
29 | 2018-02-22 H.J. Lu <hongjiu.lu@intel.com> |
30 | ||
31 | * i386-opc.tbl: Add {rex}, | |
32 | * i386-tbl.h: Regenerated. | |
33 | ||
75f31665 MR |
34 | 2018-02-20 Maciej W. Rozycki <macro@mips.com> |
35 | ||
36 | * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case. | |
37 | (mips16_opcodes): Replace `M' with `m' for "restore". | |
38 | ||
e207bc53 TP |
39 | 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com> |
40 | ||
41 | * arm-dis.c (thumb_opcodes): Fix BXNS mask. | |
42 | ||
87993319 MR |
43 | 2018-02-13 Maciej W. Rozycki <macro@mips.com> |
44 | ||
45 | * wasm32-dis.c (print_insn_wasm32): Rename `index' local | |
46 | variable to `function_index'. | |
47 | ||
68d20676 NC |
48 | 2018-02-13 Nick Clifton <nickc@redhat.com> |
49 | ||
50 | PR 22823 | |
51 | * metag-dis.c (print_fmmov): Double buffer size to avoid warning | |
52 | about truncation of printing. | |
53 | ||
d2159fdc HW |
54 | 2018-02-12 Henry Wong <henry@stuffedcow.net> |
55 | ||
56 | * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding. | |
57 | ||
f174ef9f NC |
58 | 2018-02-05 Nick Clifton <nickc@redhat.com> |
59 | ||
60 | * po/pt_BR.po: Updated Brazilian Portuguese translation. | |
61 | ||
be3a8dca IT |
62 | 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
63 | ||
64 | * i386-dis.c (enum): Add pconfig. | |
65 | * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS. | |
66 | (cpu_flags): Add CpuPCONFIG. | |
67 | * i386-opc.h (enum): Add CpuPCONFIG. | |
68 | (i386_cpu_flags): Add cpupconfig. | |
69 | * i386-opc.tbl: Add PCONFIG instruction. | |
70 | * i386-init.h: Regenerate. | |
71 | * i386-tbl.h: Likewise. | |
72 | ||
3233d7d0 IT |
73 | 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
74 | ||
75 | * i386-dis.c (enum): Add PREFIX_0F09. | |
76 | * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS. | |
77 | (cpu_flags): Add CpuWBNOINVD. | |
78 | * i386-opc.h (enum): Add CpuWBNOINVD. | |
79 | (i386_cpu_flags): Add cpuwbnoinvd. | |
80 | * i386-opc.tbl: Add WBNOINVD instruction. | |
81 | * i386-init.h: Regenerate. | |
82 | * i386-tbl.h: Likewise. | |
83 | ||
e925c834 JW |
84 | 2018-01-17 Jim Wilson <jimw@sifive.com> |
85 | ||
86 | * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0. | |
87 | ||
d777820b IT |
88 | 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
89 | ||
90 | * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET. | |
91 | Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS, | |
92 | CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK. | |
93 | (cpu_flags): Add CpuIBT, CpuSHSTK. | |
94 | * i386-opc.h (enum): Add CpuIBT, CpuSHSTK. | |
95 | (i386_cpu_flags): Add cpuibt, cpushstk. | |
96 | * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT. | |
97 | * i386-init.h: Regenerate. | |
98 | * i386-tbl.h: Likewise. | |
99 | ||
f6efed01 NC |
100 | 2018-01-16 Nick Clifton <nickc@redhat.com> |
101 | ||
102 | * po/pt_BR.po: Updated Brazilian Portugese translation. | |
103 | * po/de.po: Updated German translation. | |
104 | ||
2721d702 JW |
105 | 2018-01-15 Jim Wilson <jimw@sifive.com> |
106 | ||
107 | * riscv-opc.c (match_c_nop): New. | |
108 | (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop. | |
109 | ||
616dcb87 NC |
110 | 2018-01-15 Nick Clifton <nickc@redhat.com> |
111 | ||
112 | * po/uk.po: Updated Ukranian translation. | |
113 | ||
3957a496 NC |
114 | 2018-01-13 Nick Clifton <nickc@redhat.com> |
115 | ||
116 | * po/opcodes.pot: Regenerated. | |
117 | ||
769c7ea5 NC |
118 | 2018-01-13 Nick Clifton <nickc@redhat.com> |
119 | ||
120 | * configure: Regenerate. | |
121 | ||
faf766e3 NC |
122 | 2018-01-13 Nick Clifton <nickc@redhat.com> |
123 | ||
124 | 2.30 branch created. | |
125 | ||
888a89da IT |
126 | 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
127 | ||
128 | * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns. | |
129 | * i386-tbl.h: Regenerate. | |
130 | ||
cbda583a JB |
131 | 2018-01-10 Jan Beulich <jbeulich@suse.com> |
132 | ||
133 | * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift. | |
134 | * i386-tbl.h: Re-generate. | |
135 | ||
c9e92278 JB |
136 | 2018-01-10 Jan Beulich <jbeulich@suse.com> |
137 | ||
138 | * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, | |
139 | vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub, | |
140 | vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew, | |
141 | vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw, | |
142 | vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust | |
143 | Disp8MemShift of AVX512VL forms. | |
144 | * i386-tbl.h: Re-generate. | |
145 | ||
35fd2b2b JW |
146 | 2018-01-09 Jim Wilson <jimw@sifive.com> |
147 | ||
148 | * riscv-dis.c (maybe_print_address): If base_reg is zero, | |
149 | then the hi_addr value is zero. | |
150 | ||
91d8b670 JG |
151 | 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> |
152 | ||
153 | * arm-dis.c (arm_opcodes): Add csdb. | |
154 | (thumb32_opcodes): Add csdb. | |
155 | ||
be2e7d95 JG |
156 | 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> |
157 | ||
158 | * aarch64-tbl.h (aarch64_opcode_table): Add "csdb". | |
159 | * aarch64-asm-2.c: Regenerate. | |
160 | * aarch64-dis-2.c: Regenerate. | |
161 | * aarch64-opc-2.c: Regenerate. | |
162 | ||
704a705d L |
163 | 2018-01-08 H.J. Lu <hongjiu.lu@intel.com> |
164 | ||
165 | PR gas/22681 | |
166 | * i386-opc.tbl: Properly encode vmovd with Qword memeory operand. | |
167 | Remove AVX512 vmovd with 64-bit operands. | |
168 | * i386-tbl.h: Regenerated. | |
169 | ||
35eeb78f JW |
170 | 2018-01-05 Jim Wilson <jimw@sifive.com> |
171 | ||
172 | * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a | |
173 | jalr. | |
174 | ||
219d1afa AM |
175 | 2018-01-03 Alan Modra <amodra@gmail.com> |
176 | ||
177 | Update year range in copyright notice of all files. | |
178 | ||
1508bbf5 JB |
179 | 2018-01-02 Jan Beulich <jbeulich@suse.com> |
180 | ||
181 | * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM | |
182 | and OPERAND_TYPE_REGZMM entries. | |
183 | ||
1e563868 | 184 | For older changes see ChangeLog-2017 |
3499769a | 185 | \f |
1e563868 | 186 | Copyright (C) 2018 Free Software Foundation, Inc. |
3499769a AM |
187 | |
188 | Copying and distribution of this file, with or without modification, | |
189 | are permitted in any medium without royalty provided the copyright | |
190 | notice and this notice are preserved. | |
191 | ||
192 | Local Variables: | |
193 | mode: change-log | |
194 | left-margin: 8 | |
195 | fill-column: 74 | |
196 | version-control: never | |
197 | End: |