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db7b55fa
NC		 12016-12-16 Nick Clifton <nickc@redhat.com>
2
3 * arm-dis.c (print_insn_thumb32): Fix compile time warning
4 computing value_in_comment.
5
5e7fc731
MR		 62016-12-14 Maciej W. Rozycki <macro@imgtec.com>
7
8 * mips-dis.c (mips_convert_abiflags_ases): New function.
9 (set_default_mips_dis_options): Also infer ASE flags from ELF
10 file structures.
11
8184783a
MR		 122016-12-14 Maciej W. Rozycki <macro@imgtec.com>
13
14 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
15 header flag interpretation code.
16
353abf7c
MR		 172016-12-14 Maciej W. Rozycki <macro@imgtec.com>
18
19 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
20 `pinfo2' with SP-relative "sd" entries.
21
63e014fc
MR		 222016-12-14 Maciej W. Rozycki <macro@imgtec.com>
23
24 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
25 compact jumps.
26
a6a51754
RL		 272016-12-13 Renlin Li <renlin.li@arm.com>
28
29 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
30 qualifier.
31 (operand_general_constraint_met_p): Remove case for CP_REG.
32 (aarch64_print_operand): Print CRn, CRm operand using imm field.
33 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
34 (QL_SYSL): Likewise.
35 (aarch64_opcode_table): Change CRn, CRm operand class and type.
36 * aarch64-opc-2.c : Regenerate.
37 * aarch64-asm-2.c : Likewise.
38 * aarch64-dis-2.c : Likewise.
39
029e9d52
YQ		 402016-12-12 Yao Qi <yao.qi@linaro.org>
41
42 * rx-dis.c: Include <setjmp.h>
43 (struct private): New.
44 (rx_get_byte): Check return value of read_memory_func, and
45 call memory_error_func and OPCODES_SIGLONGJMP on error.
46 (print_insn_rx): Call OPCODES_SIGSETJMP.
47
3a0b8f7d
YQ		 482016-12-12 Yao Qi <yao.qi@linaro.org>
49
50 * rl78-dis.c: Include <setjmp.h>.
51 (struct private): New.
52 (rl78_get_byte): Check return value of read_memory_func, and
53 call memory_error_func and OPCODES_SIGLONGJMP on error.
54 (print_insn_rl78_common): Call OPCODES_SIGJMP.
55
64c11183
MR		 562016-12-09 Maciej W. Rozycki <macro@imgtec.com>
57
58 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
59
f17ecb4b
MR		 602016-12-09 Maciej W. Rozycki <macro@imgtec.com>
61
62 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
63 than UINT.
64
55af4784
MR		 652016-12-09 Maciej W. Rozycki <macro@imgtec.com>
66
67 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
68 to separate `extend' and its uninterpreted argument output.
69 Separate hexadecimal halves of undecoded extended instructions
70 output.
71
39f66f3a
MR		 722016-12-08 Maciej W. Rozycki <macro@imgtec.com>
73
74 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
75 indentation space across.
76
860b03a8
MR		 772016-12-08 Maciej W. Rozycki <macro@imgtec.com>
78
79 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
80 adjustment for PC-relative operations following MIPS16e compact
81 jumps or undefined RR/J(AL)R(C) encodings.
82
329d01f7
MR		 832016-12-08 Maciej W. Rozycki <macro@imgtec.com>
84
85 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
86 variable to `reglane_index'.
87
3a2488dd
LM		 882016-12-08 Luis Machado <lgustavo@codesourcery.com>
89
90 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
91
5f5c6e03
MR		 922016-12-07 Maciej W. Rozycki <macro@imgtec.com>
93
94 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
95
343fa690
MR		 962016-12-07 Maciej W. Rozycki <macro@imgtec.com>
97
98 * mips16-opc.c (mips16_opcodes): Update comment naming structure
99 members.
100
6725647c
MR		 1012016-12-07 Maciej W. Rozycki <macro@imgtec.com>
102
103 * mips-dis.c (print_mips_disassembler_options): Reformat output.
104
c28eeff2
SN		 1052016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
106
107 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
108 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
109
49e8a725
SN		 1102016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
111
112 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
113
a37a2806
NC		 1142016-12-01 Nick Clifton <nickc@redhat.com>
115
116 PR binutils/20893
117 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
118 opcode designator.
119
abe7c33b
CZ		 1202016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
121
122 * arc-opc.c (insert_ra_chk): New function.
123 (insert_rb_chk): Likewise.
124 (insert_rad): Update text error message.
125 (insert_rcd): Likewise.
126 (insert_rhv2): Likewise.
127 (insert_r0): Likewise.
128 (insert_r1): Likewise.
129 (insert_r2): Likewise.
130 (insert_r3): Likewise.
131 (insert_sp): Likewise.
132 (insert_gp): Likewise.
133 (insert_pcl): Likewise.
134 (insert_blink): Likewise.
135 (insert_ilink1): Likewise.
136 (insert_ilink2): Likewise.
137 (insert_ras): Likewise.
138 (insert_rbs): Likewise.
139 (insert_rcs): Likewise.
140 (insert_simm3s): Likewise.
141 (insert_rrange): Likewise.
142 (insert_fpel): Likewise.
143 (insert_blinkel): Likewise.
144 (insert_pcel): Likewise.
145 (insert_nps_3bit_dst): Likewise.
146 (insert_nps_3bit_dst_short): Likewise.
147 (insert_nps_3bit_src2_short): Likewise.
148 (insert_nps_bitop_size_2b): Likewise.
149 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
150 (RA_CHK): Define.
151 (RB): Adjust.
152 (RB_CHK): Define.
153 (RC): Adjust.
154 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
155 * arc-tbl.h (div, divu): All instructions are DIVREM class.
156 Change first insn argument to check for LP_COUNT usage.
157 (rem): Likewise.
158 (ld, ldd): All instructions are LOAD class. Change first insn
159 argument to check for LP_COUNT usage.
160 (st, std): All instructions are STORE class.
161 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
162 Change first insn argument to check for LP_COUNT usage.
163 (mov): All instructions are MOVE class. Change first insn
164 argument to check for LP_COUNT usage.
165
ee881e5d
CZ		 1662016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
167
168 * arc-dis.c (is_compatible_p): Remove function.
169 (skip_this_opcode): Don't add any decoding class to decode list.
170 Remove warning.
171 (find_format_from_table): Go through all opcodes, and warn if we
172 use a guessed mnemonic.
173
abfcb414
AP		 1742016-11-28 Ramiro Polla <ramiro@hex-rays.com>
175 Amit Pawar <amit.pawar@amd.com>
176
177 PR binutils/20637
178 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
179 instructions.
180
96fe4562
AM		 1812016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
182
183 * configure: Regenerate.
184
6884417a
JM		 1852016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
186
187 * sparc-opc.c (HWS_V8): Definition moved from
188 gas/config/tc-sparc.c.
189 (HWS_V9): Likewise.
190 (HWS_VA): Likewise.
191 (HWS_VB): Likewise.
192 (HWS_VC): Likewise.
193 (HWS_VD): Likewise.
194 (HWS_VE): Likewise.
195 (HWS_VV): Likewise.
196 (HWS_VM): Likewise.
197 (HWS2_VM): Likewise.
198 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
199 existing entries.
200
c4b943d7
CZ		 2012016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
202
203 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
204 instructions.
205
c2c4ff8d
SN		 2062016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
207
208 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
209 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
210 (aarch64_opcode_table): Add fcmla and fcadd.
211 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
212 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
213 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
214 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
215 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
216 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
217 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
218 (operand_general_constraint_met_p): Rotate and index range check.
219 (aarch64_print_operand): Handle rotate operand.
220 * aarch64-asm-2.c: Regenerate.
221 * aarch64-dis-2.c: Likewise.
222 * aarch64-opc-2.c: Likewise.
223
28617675
SN		 2242016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
225
226 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
227 * aarch64-asm-2.c: Regenerate.
228 * aarch64-dis-2.c: Regenerate.
229 * aarch64-opc-2.c: Regenerate.
230
ccfc90a3
SN		 2312016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
232
233 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
234 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
235 * aarch64-asm-2.c: Regenerate.
236 * aarch64-dis-2.c: Regenerate.
237 * aarch64-opc-2.c: Regenerate.
238
3f06e550
SN		 2392016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
240
241 * aarch64-tbl.h (QL_X1NIL): New.
242 (arch64_opcode_table): Add ldraa, ldrab.
243 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
244 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
245 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
246 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
247 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
248 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
249 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
250 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
251 (aarch64_print_operand): Likewise.
252 * aarch64-asm-2.c: Regenerate.
253 * aarch64-dis-2.c: Regenerate.
254 * aarch64-opc-2.c: Regenerate.
255
74f5402d
SN		 2562016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
257
258 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
259 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
260 * aarch64-asm-2.c: Regenerate.
261 * aarch64-dis-2.c: Regenerate.
262 * aarch64-opc-2.c: Regenerate.
263
c84364ec
SN		 2642016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
265
266 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
267 (AARCH64_OPERANDS): Add Rm_SP.
268 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
269 * aarch64-asm-2.c: Regenerate.
270 * aarch64-dis-2.c: Regenerate.
271 * aarch64-opc-2.c: Regenerate.
272
a2cfc830
SN		 2732016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
274
275 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
276 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
277 autdzb, xpaci, xpacd.
278 * aarch64-asm-2.c: Regenerate.
279 * aarch64-dis-2.c: Regenerate.
280 * aarch64-opc-2.c: Regenerate.
281
b0bfa7b5
SN		 2822016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
283
284 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
285 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
286 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
287 (aarch64_sys_reg_supported_p): Add feature test for new registers.
288
8787d804
SN		 2892016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
290
291 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
292 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
293 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
294 autibsp.
295 * aarch64-asm-2.c: Regenerate.
296 * aarch64-dis-2.c: Regenerate.
297
3d731f69
SN		 2982016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
299
300 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
301
60227d64
L		 3022016-11-09 H.J. Lu <hongjiu.lu@intel.com>
303
304 PR binutils/20799
305 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
306 * i386-dis.c (EdqwS): Removed.
307 (dqw_swap_mode): Likewise.
308 (intel_operand_size): Don't check dqw_swap_mode.
309 (OP_E_register): Likewise.
310 (OP_E_memory): Likewise.
311 (OP_G): Likewise.
312 (OP_EX): Likewise.
313 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
314 * i386-tbl.h: Regerated.
315
7efeed17
L		 3162016-11-09 H.J. Lu <hongjiu.lu@intel.com>
317
318 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 319 * i386-tbl.h: Regerated.
7efeed17 320
1f334aeb
L		 3212016-11-08 H.J. Lu <hongjiu.lu@intel.com>
322
323 PR binutils/20701
324 * i386-dis.c (THREE_BYTE_0F7A): Removed.
325 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
326 (three_byte_table): Remove THREE_BYTE_0F7A.
327
48c97fa1
L		 3282016-11-07 H.J. Lu <hongjiu.lu@intel.com>
329
330 PR binutils/20775
331 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
332 (FGRPd9_4): Replace 1 with 2.
333 (FGRPd9_5): Replace 2 with 3.
334 (FGRPd9_6): Replace 3 with 4.
335 (FGRPd9_7): Replace 4 with 5.
336 (FGRPda_5): Replace 5 with 6.
337 (FGRPdb_4): Replace 6 with 7.
338 (FGRPde_3): Replace 7 with 8.
339 (FGRPdf_4): Replace 8 with 9.
340 (fgrps): Add an entry for Bad_Opcode.
341
b437d035
AB		 3422016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
343
344 * arc-opc.c (arc_flag_operands): Add F_DI14.
345 (arc_flag_classes): Add C_DI14.
346 * arc-nps400-tbl.h: Add new exc instructions.
347
5a736821
GM		 3482016-11-03 Graham Markall <graham.markall@embecosm.com>
349
350 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
351 major opcode 0xa.
352 * arc-nps-400-tbl.h: Add dcmac instruction.
353 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
354 (insert_nps_rbdouble_64): Added.
355 (extract_nps_rbdouble_64): Added.
356 (insert_nps_proto_size): Added.
357 (extract_nps_proto_size): Added.
358
bdfe53e3
AB		 3592016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
360
361 * arc-dis.c (struct arc_operand_iterator): Remove all fields
362 relating to long instruction processing, add new limm field.
363 (OPCODE): Rename to...
364 (OPCODE_32BIT_INSN): ...this.
365 (OPCODE_AC): Delete.
366 (skip_this_opcode): Handle different instruction lengths, update
367 macro name.
368 (special_flag_p): Update parameter type.
369 (find_format_from_table): Update for more instruction lengths.
370 (find_format_long_instructions): Delete.
371 (find_format): Update for more instruction lengths.
372 (arc_insn_length): Likewise.
373 (extract_operand_value): Update for more instruction lengths.
374 (operand_iterator_next): Remove code relating to long
375 instructions.
376 (arc_opcode_to_insn_type): New function.
377 (print_insn_arc):Update for more instructions lengths.
378 * arc-ext.c (extInstruction_t): Change argument type.
379 * arc-ext.h (extInstruction_t): Change argument type.
380 * arc-fxi.h: Change type unsigned to unsigned long long
381 extensively throughout.
382 * arc-nps400-tbl.h: Add long instructions taken from
383 arc_long_opcodes table in arc-opc.c.
384 * arc-opc.c: Update parameter types on insert/extract handlers.
385 (arc_long_opcodes): Delete.
386 (arc_num_long_opcodes): Delete.
387 (arc_opcode_len): Update for more instruction lengths.
388
90f61cce
GM		 3892016-11-03 Graham Markall <graham.markall@embecosm.com>
390
391 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
392
06fe285f
GM		 3932016-11-03 Graham Markall <graham.markall@embecosm.com>
394
395 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
396 with arc_opcode_len.
397 (find_format_long_instructions): Likewise.
398 * arc-opc.c (arc_opcode_len): New function.
399
ecf64ec6
AB		 4002016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
401
402 * arc-nps400-tbl.h: Fix some instruction masks.
403
d039fef3
L		 4042016-11-03 H.J. Lu <hongjiu.lu@intel.com>
405
406 * i386-dis.c (REG_82): Removed.
407 (X86_64_82_REG_0): Likewise.
408 (X86_64_82_REG_1): Likewise.
409 (X86_64_82_REG_2): Likewise.
410 (X86_64_82_REG_3): Likewise.
411 (X86_64_82_REG_4): Likewise.
412 (X86_64_82_REG_5): Likewise.
413 (X86_64_82_REG_6): Likewise.
414 (X86_64_82_REG_7): Likewise.
415 (X86_64_82): New.
416 (dis386): Use X86_64_82 instead of REG_82.
417 (reg_table): Remove REG_82.
418 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
419 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
420 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
421 X86_64_82_REG_7.
422
8b89fe14
L		 4232016-11-03 H.J. Lu <hongjiu.lu@intel.com>
424
425 PR binutils/20754
426 * i386-dis.c (REG_82): New.
427 (X86_64_82_REG_0): Likewise.
428 (X86_64_82_REG_1): Likewise.
429 (X86_64_82_REG_2): Likewise.
430 (X86_64_82_REG_3): Likewise.
431 (X86_64_82_REG_4): Likewise.
432 (X86_64_82_REG_5): Likewise.
433 (X86_64_82_REG_6): Likewise.
434 (X86_64_82_REG_7): Likewise.
435 (dis386): Use REG_82.
436 (reg_table): Add REG_82.
437 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
438 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
439 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
440
7148c369
L		 4412016-11-03 H.J. Lu <hongjiu.lu@intel.com>
442
443 * i386-dis.c (REG_82): Renamed to ...
444 (REG_83): This.
445 (dis386): Updated.
446 (reg_table): Likewise.
447
47acf0bd
IT		 4482016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
449
450 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
451 * i386-dis-evex.h (evex_table): Updated.
452 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
453 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
454 (cpu_flags): Add CpuAVX512_4VNNIW.
455 * i386-opc.h (enum): (AVX512_4VNNIW): New.
456 (i386_cpu_flags): Add cpuavx512_4vnniw.
457 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
458 * i386-init.h: Regenerate.
459 * i386-tbl.h: Ditto.
460
920d2ddc
IT		 4612016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
462
463 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
464 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
465 * i386-dis-evex.h (evex_table): Updated.
466 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
467 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
468 (cpu_flags): Add CpuAVX512_4FMAPS.
469 (opcode_modifiers): Add ImplicitQuadGroup modifier.
470 * i386-opc.h (AVX512_4FMAP): New.
471 (i386_cpu_flags): Add cpuavx512_4fmaps.
472 (ImplicitQuadGroup): New.
473 (i386_opcode_modifier): Add implicitquadgroup.
474 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
475 * i386-init.h: Regenerate.
476 * i386-tbl.h: Ditto.
477
e23eba97
NC		 4782016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
479 Andrew Waterman <andrew@sifive.com>
480
481 Add support for RISC-V architecture.
482 * configure.ac: Add entry for bfd_riscv_arch.
483 * configure: Regenerate.
484 * disassemble.c (disassembler): Add support for riscv.
485 (disassembler_usage): Likewise.
486 * riscv-dis.c: New file.
487 * riscv-opc.c: New file.
488
b5cefcca
L		 4892016-10-21 H.J. Lu <hongjiu.lu@intel.com>
490
491 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
492 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
493 (rm_table): Update the RM_0FAE_REG_7 entry.
494 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
495 (cpu_flags): Remove CpuPCOMMIT.
496 * i386-opc.h (CpuPCOMMIT): Removed.
497 (i386_cpu_flags): Remove cpupcommit.
498 * i386-opc.tbl: Remove pcommit.
499 * i386-init.h: Regenerated.
500 * i386-tbl.h: Likewise.
501
9889cbb1
L		 5022016-10-20 H.J. Lu <hongjiu.lu@intel.com>
503
504 PR binutis/20705
505 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
506 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
507 32-bit mode. Don't check vex.register_specifier in 32-bit
508 mode.
509 (OP_VEX): Check for invalid mask registers.
510
28596323
L		 5112016-10-18 H.J. Lu <hongjiu.lu@intel.com>
512
513 PR binutis/20699
514 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
515 sizeflag.
516
da8d7d66
L		 5172016-10-18 H.J. Lu <hongjiu.lu@intel.com>
518
519 PR binutis/20704
520 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
521
eaf02703
MR		 5222016-10-18 Maciej W. Rozycki <macro@imgtec.com>
523
524 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
525 local variable to `index_regno'.
526
decf5bd1
CM		 5272016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
528
529 * arc-tbl.h: Removed any "inv.+" instructions from the table.
530
e5b06ef0
CZ		 5312016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
532
533 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
534 usage on ISA basis.
535
93562a34
JW		 5362016-10-11 Jiong Wang <jiong.wang@arm.com>
537
538 PR target/20666
539 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
540
362c0c4d
JW		 5412016-10-07 Jiong Wang <jiong.wang@arm.com>
542
543 PR target/20667
544 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
545 available.
546
1047201f
AM		 5472016-10-07 Alan Modra <amodra@gmail.com>
548
549 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
550
1a0670f3
AM		 5512016-10-06 Alan Modra <amodra@gmail.com>
552
553 * aarch64-opc.c: Spell fall through comments consistently.
554 * i386-dis.c: Likewise.
555 * aarch64-dis.c: Add missing fall through comments.
556 * aarch64-opc.c: Likewise.
557 * arc-dis.c: Likewise.
558 * arm-dis.c: Likewise.
559 * i386-dis.c: Likewise.
560 * m68k-dis.c: Likewise.
561 * mep-asm.c: Likewise.
562 * ns32k-dis.c: Likewise.
563 * sh-dis.c: Likewise.
564 * tic4x-dis.c: Likewise.
565 * tic6x-dis.c: Likewise.
566 * vax-dis.c: Likewise.
567
2b804145
AM		 5682016-10-06 Alan Modra <amodra@gmail.com>
569
570 * arc-ext.c (create_map): Add missing break.
571 * msp430-decode.opc (encode_as): Likewise.
572 * msp430-decode.c: Regenerate.
573
616ec358
AM		 5742016-10-06 Alan Modra <amodra@gmail.com>
575
576 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
577 * crx-dis.c (print_insn_crx): Likewise.
578
72da393d
L		 5792016-09-30 H.J. Lu <hongjiu.lu@intel.com>
580
581 PR binutils/20657
582 * i386-dis.c (putop): Don't assign alt twice.
583
744ce302
JW		 5842016-09-29 Jiong Wang <jiong.wang@arm.com>
585
586 PR target/20553
587 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
588
a5721ba2
AM		 5892016-09-29 Alan Modra <amodra@gmail.com>
590
591 * ppc-opc.c (L): Make compulsory.
592 (LOPT): New, optional form of L.
593 (HTM_R): Define as LOPT.
594 (L0, L1): Delete.
595 (L32OPT): New, optional for 32-bit L.
596 (L2OPT): New, 2-bit L for dcbf.
597 (SVC_LEC): Update.
598 (L2): Define.
599 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
600 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
601 <dcbf>: Use L2OPT.
602 <tlbiel, tlbie>: Use LOPT.
603 <wclr, wclrall>: Use L2.
604
c5da1932
VZ		 6052016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
606
607 * Makefile.in: Regenerate.
608 * configure: Likewise.
609
2b848ebd
CZ		 6102016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
611
612 * arc-ext-tbl.h (EXTINSN2OPF): Define.
613 (EXTINSN2OP): Use EXTINSN2OPF.
614 (bspeekm, bspop, modapp): New extension instructions.
615 * arc-opc.c (F_DNZ_ND): Define.
616 (F_DNZ_D): Likewise.
617 (F_SIZEB1): Changed.
618 (C_DNZ_D): Define.
619 (C_HARD): Changed.
620 * arc-tbl.h (dbnz): New instruction.
621 (prealloc): Allow it for ARC EM.
622 (xbfu): Likewise.
623
ad43e107
RS		 6242016-09-21 Richard Sandiford <richard.sandiford@arm.com>
625
626 * aarch64-opc.c (print_immediate_offset_address): Print spaces
627 after commas in addresses.
628 (aarch64_print_operand): Likewise.
629
ab3b8fcf
RS		 6302016-09-21 Richard Sandiford <richard.sandiford@arm.com>
631
632 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
633 rather than "should be" or "expected to be" in error messages.
634
bb7eff52
RS		 6352016-09-21 Richard Sandiford <richard.sandiford@arm.com>
636
637 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
638 (print_mnemonic_name): ...here.
639 (print_comment): New function.
640 (print_aarch64_insn): Call it.
641 * aarch64-opc.c (aarch64_conds): Add SVE names.
642 (aarch64_print_operand): Print alternative condition names in
643 a comment.
644
c0890d26
RS		 6452016-09-21 Richard Sandiford <richard.sandiford@arm.com>
646
647 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
648 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
649 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
650 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
651 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
652 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
653 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
654 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
655 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
656 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
657 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
658 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
659 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
660 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
661 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
662 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
663 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
664 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
665 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
666 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
667 (OP_SVE_XWU, OP_SVE_XXU): New macros.
668 (aarch64_feature_sve): New variable.
669 (SVE): New macro.
670 (_SVE_INSN): Likewise.
671 (aarch64_opcode_table): Add SVE instructions.
672 * aarch64-opc.h (extract_fields): Declare.
673 * aarch64-opc-2.c: Regenerate.
674 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
675 * aarch64-asm-2.c: Regenerate.
676 * aarch64-dis.c (extract_fields): Make global.
677 (do_misc_decoding): Handle the new SVE aarch64_ops.
678 * aarch64-dis-2.c: Regenerate.
679
116b6019
RS		 6802016-09-21 Richard Sandiford <richard.sandiford@arm.com>
681
682 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
683 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
684 aarch64_field_kinds.
685 * aarch64-opc.c (fields): Add corresponding entries.
686 * aarch64-asm.c (aarch64_get_variant): New function.
687 (aarch64_encode_variant_using_iclass): Likewise.
688 (aarch64_opcode_encode): Call it.
689 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
690 (aarch64_opcode_decode): Call it.
691
047cd301
RS		 6922016-09-21 Richard Sandiford <richard.sandiford@arm.com>
693
694 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
695 and FP register operands.
696 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
697 (FLD_SVE_Vn): New aarch64_field_kinds.
698 * aarch64-opc.c (fields): Add corresponding entries.
699 (aarch64_print_operand): Handle the new SVE core and FP register
700 operands.
701 * aarch64-opc-2.c: Regenerate.
702 * aarch64-asm-2.c: Likewise.
703 * aarch64-dis-2.c: Likewise.
704
165d4950
RS		 7052016-09-21 Richard Sandiford <richard.sandiford@arm.com>
706
707 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
708 immediate operands.
709 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
710 * aarch64-opc.c (fields): Add corresponding entry.
711 (operand_general_constraint_met_p): Handle the new SVE FP immediate
712 operands.
713 (aarch64_print_operand): Likewise.
714 * aarch64-opc-2.c: Regenerate.
715 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
716 (ins_sve_float_zero_one): New inserters.
717 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
718 (aarch64_ins_sve_float_half_two): Likewise.
719 (aarch64_ins_sve_float_zero_one): Likewise.
720 * aarch64-asm-2.c: Regenerate.
721 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
722 (ext_sve_float_zero_one): New extractors.
723 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
724 (aarch64_ext_sve_float_half_two): Likewise.
725 (aarch64_ext_sve_float_zero_one): Likewise.
726 * aarch64-dis-2.c: Regenerate.
727
e950b345
RS		 7282016-09-21 Richard Sandiford <richard.sandiford@arm.com>
729
730 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
731 integer immediate operands.
732 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
733 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
734 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
735 * aarch64-opc.c (fields): Add corresponding entries.
736 (operand_general_constraint_met_p): Handle the new SVE integer
737 immediate operands.
738 (aarch64_print_operand): Likewise.
739 (aarch64_sve_dupm_mov_immediate_p): New function.
740 * aarch64-opc-2.c: Regenerate.
741 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
742 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
743 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
744 (aarch64_ins_limm): ...here.
745 (aarch64_ins_inv_limm): New function.
746 (aarch64_ins_sve_aimm): Likewise.
747 (aarch64_ins_sve_asimm): Likewise.
748 (aarch64_ins_sve_limm_mov): Likewise.
749 (aarch64_ins_sve_shlimm): Likewise.
750 (aarch64_ins_sve_shrimm): Likewise.
751 * aarch64-asm-2.c: Regenerate.
752 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
753 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
754 * aarch64-dis.c (decode_limm): New function, split out from...
755 (aarch64_ext_limm): ...here.
756 (aarch64_ext_inv_limm): New function.
757 (decode_sve_aimm): Likewise.
758 (aarch64_ext_sve_aimm): Likewise.
759 (aarch64_ext_sve_asimm): Likewise.
760 (aarch64_ext_sve_limm_mov): Likewise.
761 (aarch64_top_bit): Likewise.
762 (aarch64_ext_sve_shlimm): Likewise.
763 (aarch64_ext_sve_shrimm): Likewise.
764 * aarch64-dis-2.c: Regenerate.
765
98907a70
RS		 7662016-09-21 Richard Sandiford <richard.sandiford@arm.com>
767
768 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
769 operands.
770 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
771 the AARCH64_MOD_MUL_VL entry.
772 (value_aligned_p): Cope with non-power-of-two alignments.
773 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
774 (print_immediate_offset_address): Likewise.
775 (aarch64_print_operand): Likewise.
776 * aarch64-opc-2.c: Regenerate.
777 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
778 (ins_sve_addr_ri_s9xvl): New inserters.
779 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
780 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
781 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
782 * aarch64-asm-2.c: Regenerate.
783 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
784 (ext_sve_addr_ri_s9xvl): New extractors.
785 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
786 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
787 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
788 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
789 * aarch64-dis-2.c: Regenerate.
790
4df068de
RS		 7912016-09-21 Richard Sandiford <richard.sandiford@arm.com>
792
793 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
794 address operands.
795 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
796 (FLD_SVE_xs_22): New aarch64_field_kinds.
797 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
798 (get_operand_specific_data): New function.
799 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
800 FLD_SVE_xs_14 and FLD_SVE_xs_22.
801 (operand_general_constraint_met_p): Handle the new SVE address
802 operands.
803 (sve_reg): New array.
804 (get_addr_sve_reg_name): New function.
805 (aarch64_print_operand): Handle the new SVE address operands.
806 * aarch64-opc-2.c: Regenerate.
807 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
808 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
809 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
810 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
811 (aarch64_ins_sve_addr_rr_lsl): Likewise.
812 (aarch64_ins_sve_addr_rz_xtw): Likewise.
813 (aarch64_ins_sve_addr_zi_u5): Likewise.
814 (aarch64_ins_sve_addr_zz): Likewise.
815 (aarch64_ins_sve_addr_zz_lsl): Likewise.
816 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
817 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
818 * aarch64-asm-2.c: Regenerate.
819 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
820 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
821 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
822 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
823 (aarch64_ext_sve_addr_ri_u6): Likewise.
824 (aarch64_ext_sve_addr_rr_lsl): Likewise.
825 (aarch64_ext_sve_addr_rz_xtw): Likewise.
826 (aarch64_ext_sve_addr_zi_u5): Likewise.
827 (aarch64_ext_sve_addr_zz): Likewise.
828 (aarch64_ext_sve_addr_zz_lsl): Likewise.
829 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
830 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
831 * aarch64-dis-2.c: Regenerate.
832
2442d846
RS		 8332016-09-21 Richard Sandiford <richard.sandiford@arm.com>
834
835 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
836 AARCH64_OPND_SVE_PATTERN_SCALED.
837 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
838 * aarch64-opc.c (fields): Add a corresponding entry.
839 (set_multiplier_out_of_range_error): New function.
840 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
841 (operand_general_constraint_met_p): Handle
842 AARCH64_OPND_SVE_PATTERN_SCALED.
843 (print_register_offset_address): Use PRIi64 to print the
844 shift amount.
845 (aarch64_print_operand): Likewise. Handle
846 AARCH64_OPND_SVE_PATTERN_SCALED.
847 * aarch64-opc-2.c: Regenerate.
848 * aarch64-asm.h (ins_sve_scale): New inserter.
849 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
850 * aarch64-asm-2.c: Regenerate.
851 * aarch64-dis.h (ext_sve_scale): New inserter.
852 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
853 * aarch64-dis-2.c: Regenerate.
854
245d2e3f
RS		 8552016-09-21 Richard Sandiford <richard.sandiford@arm.com>
856
857 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
858 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
859 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
860 (FLD_SVE_prfop): Likewise.
861 * aarch64-opc.c: Include libiberty.h.
862 (aarch64_sve_pattern_array): New variable.
863 (aarch64_sve_prfop_array): Likewise.
864 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
865 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
866 AARCH64_OPND_SVE_PRFOP.
867 * aarch64-asm-2.c: Regenerate.
868 * aarch64-dis-2.c: Likewise.
869 * aarch64-opc-2.c: Likewise.
870
d50c751e
RS		 8712016-09-21 Richard Sandiford <richard.sandiford@arm.com>
872
873 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
874 AARCH64_OPND_QLF_P_[ZM].
875 (aarch64_print_operand): Print /z and /m where appropriate.
876
f11ad6bc
RS		 8772016-09-21 Richard Sandiford <richard.sandiford@arm.com>
878
879 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
880 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
881 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
882 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
883 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
884 * aarch64-opc.c (fields): Add corresponding entries here.
885 (operand_general_constraint_met_p): Check that SVE register lists
886 have the correct length. Check the ranges of SVE index registers.
887 Check for cases where p8-p15 are used in 3-bit predicate fields.
888 (aarch64_print_operand): Handle the new SVE operands.
889 * aarch64-opc-2.c: Regenerate.
890 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
891 * aarch64-asm.c (aarch64_ins_sve_index): New function.
892 (aarch64_ins_sve_reglist): Likewise.
893 * aarch64-asm-2.c: Regenerate.
894 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
895 * aarch64-dis.c (aarch64_ext_sve_index): New function.
896 (aarch64_ext_sve_reglist): Likewise.
897 * aarch64-dis-2.c: Regenerate.
898
0c608d6b
RS		 8992016-09-21 Richard Sandiford <richard.sandiford@arm.com>
900
901 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
902 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
903 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
904 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
905 tied operands.
906
01dbfe4c
RS		 9072016-09-21 Richard Sandiford <richard.sandiford@arm.com>
908
909 * aarch64-opc.c (get_offset_int_reg_name): New function.
910 (print_immediate_offset_address): Likewise.
911 (print_register_offset_address): Take the base and offset
912 registers as parameters.
913 (aarch64_print_operand): Update caller accordingly. Use
914 print_immediate_offset_address.
915
72e9f319
RS		 9162016-09-21 Richard Sandiford <richard.sandiford@arm.com>
917
918 * aarch64-opc.c (BANK): New macro.
919 (R32, R64): Take a register number as argument
920 (int_reg): Use BANK.
921
8a7f0c1b
RS		 9222016-09-21 Richard Sandiford <richard.sandiford@arm.com>
923
924 * aarch64-opc.c (print_register_list): Add a prefix parameter.
925 (aarch64_print_operand): Update accordingly.
926
aa2aa4c6
RS		 9272016-09-21 Richard Sandiford <richard.sandiford@arm.com>
928
929 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
930 for FPIMM.
931 * aarch64-asm.h (ins_fpimm): New inserter.
932 * aarch64-asm.c (aarch64_ins_fpimm): New function.
933 * aarch64-asm-2.c: Regenerate.
934 * aarch64-dis.h (ext_fpimm): New extractor.
935 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
936 (aarch64_ext_fpimm): New function.
937 * aarch64-dis-2.c: Regenerate.
938
b5464a68
RS		 9392016-09-21 Richard Sandiford <richard.sandiford@arm.com>
940
941 * aarch64-asm.c: Include libiberty.h.
942 (insert_fields): New function.
943 (aarch64_ins_imm): Use it.
944 * aarch64-dis.c (extract_fields): New function.
945 (aarch64_ext_imm): Use it.
946
42408347
RS		 9472016-09-21 Richard Sandiford <richard.sandiford@arm.com>
948
949 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
950 with an esize parameter.
951 (operand_general_constraint_met_p): Update accordingly.
952 Fix misindented code.
953 * aarch64-asm.c (aarch64_ins_limm): Update call to
954 aarch64_logical_immediate_p.
955
4989adac
RS		 9562016-09-21 Richard Sandiford <richard.sandiford@arm.com>
957
958 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
959
bd11d5d8
RS		 9602016-09-21 Richard Sandiford <richard.sandiford@arm.com>
961
962 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
963
f807f43d
CZ		 9642016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
965
966 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
967
fd486b63
PB		 9682016-09-14 Peter Bergner <bergner@vnet.ibm.com>
969
970 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
971 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
972 xor3>: Delete mnemonics.
973 <cp_abort>: Rename mnemonic from ...
974 <cpabort>: ...to this.
975 <setb>: Change to a X form instruction.
976 <sync>: Change to 1 operand form.
977 <copy>: Delete mnemonic.
978 <copy_first>: Rename mnemonic from ...
979 <copy>: ...to this.
980 <paste, paste.>: Delete mnemonics.
981 <paste_last>: Rename mnemonic from ...
982 <paste.>: ...to this.
983
dce08442
AK		 9842016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
985
986 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
987
952c3f51
AK		 9882016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
989
990 * s390-mkopc.c (main): Support alternate arch strings.
991
8b71537b
PS		 9922016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
993
994 * s390-opc.txt: Fix kmctr instruction type.
995
5b64d091
L		 9962016-09-07 H.J. Lu <hongjiu.lu@intel.com>
997
998 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
999 * i386-init.h: Regenerated.
1000
7763838e
CM		 10012016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1002
1003 * opcodes/arc-dis.c (print_insn_arc): Changed.
1004
1b8b6532
JM		 10052016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1006
1007 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1008 camellia_fl.
1009
1a336194
TP		 10102016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1011
1012 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1013 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1014 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1015
6b40c462
L		 10162016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1017
1018 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1019 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1020 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1021 PREFIX_MOD_3_0FAE_REG_4.
1022 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1023 PREFIX_MOD_3_0FAE_REG_4.
1024 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1025 (cpu_flags): Add CpuPTWRITE.
1026 * i386-opc.h (CpuPTWRITE): New.
1027 (i386_cpu_flags): Add cpuptwrite.
1028 * i386-opc.tbl: Add ptwrite instruction.
1029 * i386-init.h: Regenerated.
1030 * i386-tbl.h: Likewise.
1031
ab548d2d
AK		 10322016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1033
1034 * arc-dis.h: Wrap around in extern "C".
1035
344bde0a
RS		 10362016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1037
1038 * aarch64-tbl.h (V8_2_INSN): New macro.
1039 (aarch64_opcode_table): Use it.
1040
5ce912d8
RS		 10412016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1042
1043 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1044 CORE_INSN, __FP_INSN and SIMD_INSN.
1045
9d30b0bd
RS		 10462016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1047
1048 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1049 (aarch64_opcode_table): Update uses accordingly.
1050
dfdaec14
AJ		 10512016-07-25 Andrew Jenner <andrew@codesourcery.com>
1052 Kwok Cheung Yeung <kcy@codesourcery.com>
1053
1054 opcodes/
1055 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1056 'e_cmplwi' to 'e_cmpli' instead.
1057 (OPVUPRT, OPVUPRT_MASK): Define.
1058 (powerpc_opcodes): Add E200Z4 insns.
1059 (vle_opcodes): Add context save/restore insns.
1060
7bd374a4
MR		 10612016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1062
1063 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1064 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1065 "j".
1066
db18dbab
GM		 10672016-07-27 Graham Markall <graham.markall@embecosm.com>
1068
1069 * arc-nps400-tbl.h: Change block comments to GNU format.
1070 * arc-dis.c: Add new globals addrtypenames,
1071 addrtypenames_max, and addtypeunknown.
1072 (get_addrtype): New function.
1073 (print_insn_arc): Print colons and address types when
1074 required.
1075 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1076 define insert and extract functions for all address types.
1077 (arc_operands): Add operands for colon and all address
1078 types.
1079 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1080 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1081 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1082 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1083 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1084 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1085
fecd57f9
L		 10862016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1087
1088 * configure: Regenerated.
1089
37fd5ef3
CZ		 10902016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1091
1092 * arc-dis.c (skipclass): New structure.
1093 (decodelist): New variable.
1094 (is_compatible_p): New function.
1095 (new_element): Likewise.
1096 (skip_class_p): Likewise.
1097 (find_format_from_table): Use skip_class_p function.
1098 (find_format): Decode first the extension instructions.
1099 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1100 e_flags.
1101 (parse_option): New function.
1102 (parse_disassembler_options): Likewise.
1103 (print_arc_disassembler_options): Likewise.
1104 (print_insn_arc): Use parse_disassembler_options function. Proper
1105 select ARCv2 cpu variant.
1106 * disassemble.c (disassembler_usage): Add ARC disassembler
1107 options.
1108
92281a5b
MR		 11092016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1110
1111 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1112 annotation from the "nal" entry and reorder it beyond "bltzal".
1113
6e7ced37
JM		 11142016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1115
1116 * sparc-opc.c (ldtxa): New macro.
1117 (sparc_opcodes): Use the macro defined above to add entries for
1118 the LDTXA instructions.
1119 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1120 instruction.
1121
2f831b9a 11222016-07-07 James Bowman <james.bowman@ftdichip.com>
1123
1124 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1125 and "jmpc".
1126
c07315e0
JB		 11272016-07-01 Jan Beulich <jbeulich@suse.com>
1128
1129 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1130 (movzb): Adjust to cover all permitted suffixes.
1131 (movzw): New.
1132 * i386-tbl.h: Re-generate.
1133
9243100a
JB		 11342016-07-01 Jan Beulich <jbeulich@suse.com>
1135
1136 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1137 (lgdt): Remove Tbyte from non-64-bit variant.
1138 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1139 xsaves64, xsavec64): Remove Disp16.
1140 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1141 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1142 64-bit variants.
1143 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1144 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1145 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1146 64-bit variants.
1147 * i386-tbl.h: Re-generate.
1148
8325cc63
JB		 11492016-07-01 Jan Beulich <jbeulich@suse.com>
1150
1151 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1152 * i386-tbl.h: Re-generate.
1153
838441e4
YQ		 11542016-06-30 Yao Qi <yao.qi@linaro.org>
1155
1156 * arm-dis.c (print_insn): Fix typo in comment.
1157
dab26bf4
RS		 11582016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1159
1160 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1161 range of ldst_elemlist operands.
1162 (print_register_list): Use PRIi64 to print the index.
1163 (aarch64_print_operand): Likewise.
1164
5703197e
TS		 11652016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1166
1167 * mcore-opc.h: Remove sentinal.
1168 * mcore-dis.c (print_insn_mcore): Adjust.
1169
ce440d63
GM		 11702016-06-23 Graham Markall <graham.markall@embecosm.com>
1171
1172 * arc-opc.c: Correct description of availability of NPS400
1173 features.
1174
6fd3a02d
PB		 11752016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1176
1177 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1178 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1179 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1180 xor3>: New mnemonics.
1181 <setb>: Change to a VX form instruction.
1182 (insert_sh6): Add support for rldixor.
1183 (extract_sh6): Likewise.
1184
6b477896
TS		 11852016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1186
1187 * arc-ext.h: Wrap in extern C.
1188
bdd582db
GM		 11892016-06-21 Graham Markall <graham.markall@embecosm.com>
1190
1191 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1192 Use same method for determining instruction length on ARC700 and
1193 NPS-400.
1194 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1195 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1196 with the NPS400 subclass.
1197 * arc-opc.c: Likewise.
1198
96074adc
JM		 11992016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1200
1201 * sparc-opc.c (rdasr): New macro.
1202 (wrasr): Likewise.
1203 (rdpr): Likewise.
1204 (wrpr): Likewise.
1205 (rdhpr): Likewise.
1206 (wrhpr): Likewise.
1207 (sparc_opcodes): Use the macros above to fix and expand the
1208 definition of read/write instructions from/to
1209 asr/privileged/hyperprivileged instructions.
1210 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1211 %hva_mask_nz. Prefer softint_set and softint_clear over
1212 set_softint and clear_softint.
1213 (print_insn_sparc): Support %ver in Rd.
1214
7a10c22f
JM		 12152016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1216
1217 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1218 architecture according to the hardware capabilities they require.
1219
4f26fb3a
JM		 12202016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1221
1222 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1223 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1224 bfd_mach_sparc_v9{c,d,e,v,m}.
1225 * sparc-opc.c (MASK_V9C): Define.
1226 (MASK_V9D): Likewise.
1227 (MASK_V9E): Likewise.
1228 (MASK_V9V): Likewise.
1229 (MASK_V9M): Likewise.
1230 (v6): Add MASK_V9{C,D,E,V,M}.
1231 (v6notlet): Likewise.
1232 (v7): Likewise.
1233 (v8): Likewise.
1234 (v9): Likewise.
1235 (v9andleon): Likewise.
1236 (v9a): Likewise.
1237 (v9b): Likewise.
1238 (v9c): Define.
1239 (v9d): Likewise.
1240 (v9e): Likewise.
1241 (v9v): Likewise.
1242 (v9m): Likewise.
1243 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1244
3ee6e4fb
NC		 12452016-06-15 Nick Clifton <nickc@redhat.com>
1246
1247 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1248 constants to match expected behaviour.
1249 (nds32_parse_opcode): Likewise. Also for whitespace.
1250
02f3be19
AB		 12512016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1252
1253 * arc-opc.c (extract_rhv1): Extract value from insn.
1254
6f9f37ed 12552016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 1256
1257 * arc-nps400-tbl.h: Add ldbit instruction.
1258 * arc-opc.c: Add flag classes required for ldbit.
1259
6f9f37ed 12602016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 1261
1262 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1263 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1264 support the above instructions.
1265
6f9f37ed 12662016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 1267
1268 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1269 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1270 csma, cbba, zncv, and hofs.
1271 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1272 support the above instructions.
1273
12742016-06-06 Graham Markall <graham.markall@embecosm.com>
1275
1276 * arc-nps400-tbl.h: Add andab and orab instructions.
1277
12782016-06-06 Graham Markall <graham.markall@embecosm.com>
1279
1280 * arc-nps400-tbl.h: Add addl-like instructions.
1281
12822016-06-06 Graham Markall <graham.markall@embecosm.com>
1283
1284 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1285
12862016-06-06 Graham Markall <graham.markall@embecosm.com>
1287
1288 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1289 instructions.
1290
b2cc3f6f
AK		 12912016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1292
1293 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1294 variable.
1295 (init_disasm): Handle new command line option "insnlength".
1296 (print_s390_disassembler_options): Mention new option in help
1297 output.
1298 (print_insn_s390): Use the encoded insn length when dumping
1299 unknown instructions.
1300
1857fe72
DC		 13012016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1302
1303 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1304 to the address and set as symbol address for LDS/ STS immediate operands.
1305
14b57c7c
AM		 13062016-06-07 Alan Modra <amodra@gmail.com>
1307
1308 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1309 cpu for "vle" to e500.
1310 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1311 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1312 (PPCNONE): Delete, substitute throughout.
1313 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1314 except for major opcode 4 and 31.
1315 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1316
4d1464f2
MW		 13172016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1318
1319 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1320 ARM_EXT_RAS in relevant entries.
1321
026122a6
PB		 13222016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1323
1324 PR binutils/20196
1325 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1326 opcodes for E6500.
1327
07f5af7d
L		 13282016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1329
1330 PR binutis/18386
1331 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1332 (indir_v_mode): New.
1333 Add comments for '&'.
1334 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1335 (putop): Handle '&'.
1336 (intel_operand_size): Handle indir_v_mode.
1337 (OP_E_register): Likewise.
1338 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1339 64-bit indirect call/jmp for AMD64.
1340 * i386-tbl.h: Regenerated
1341
4eb6f892
AB		 13422016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1343
1344 * arc-dis.c (struct arc_operand_iterator): New structure.
1345 (find_format_from_table): All the old content from find_format,
1346 with some minor adjustments, and parameter renaming.
1347 (find_format_long_instructions): New function.
1348 (find_format): Rewritten.
1349 (arc_insn_length): Add LSB parameter.
1350 (extract_operand_value): New function.
1351 (operand_iterator_next): New function.
1352 (print_insn_arc): Use new functions to find opcode, and iterator
1353 over operands.
1354 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1355 (extract_nps_3bit_dst_short): New function.
1356 (insert_nps_3bit_src2_short): New function.
1357 (extract_nps_3bit_src2_short): New function.
1358 (insert_nps_bitop1_size): New function.
1359 (extract_nps_bitop1_size): New function.
1360 (insert_nps_bitop2_size): New function.
1361 (extract_nps_bitop2_size): New function.
1362 (insert_nps_bitop_mod4_msb): New function.
1363 (extract_nps_bitop_mod4_msb): New function.
1364 (insert_nps_bitop_mod4_lsb): New function.
1365 (extract_nps_bitop_mod4_lsb): New function.
1366 (insert_nps_bitop_dst_pos3_pos4): New function.
1367 (extract_nps_bitop_dst_pos3_pos4): New function.
1368 (insert_nps_bitop_ins_ext): New function.
1369 (extract_nps_bitop_ins_ext): New function.
1370 (arc_operands): Add new operands.
1371 (arc_long_opcodes): New global array.
1372 (arc_num_long_opcodes): New global.
1373 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1374
1fe0971e
TS		 13752016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1376
1377 * nds32-asm.h: Add extern "C".
1378 * sh-opc.h: Likewise.
1379
315f180f
GM		 13802016-06-01 Graham Markall <graham.markall@embecosm.com>
1381
1382 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1383 0,b,limm to the rflt instruction.
1384
a2b5fccc
TS		 13852016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1386
1387 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1388 constant.
1389
0cbd0046
L		 13902016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1391
1392 PR gas/20145
1393 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1394 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1395 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1396 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1397 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1398 * i386-init.h: Regenerated.
1399
1848e567
L		 14002016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1401
1402 PR gas/20145
1403 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1404 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1405 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1406 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1407 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1408 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1409 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1410 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1411 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1412 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1413 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1414 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1415 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1416 CpuRegMask for AVX512.
1417 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1418 and CpuRegMask.
1419 (set_bitfield_from_cpu_flag_init): New function.
1420 (set_bitfield): Remove const on f. Call
1421 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1422 * i386-opc.h (CpuRegMMX): New.
1423 (CpuRegXMM): Likewise.
1424 (CpuRegYMM): Likewise.
1425 (CpuRegZMM): Likewise.
1426 (CpuRegMask): Likewise.
1427 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1428 and cpuregmask.
1429 * i386-init.h: Regenerated.
1430 * i386-tbl.h: Likewise.
1431
e92bae62
L		 14322016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1433
1434 PR gas/20154
1435 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1436 (opcode_modifiers): Add AMD64 and Intel64.
1437 (main): Properly verify CpuMax.
1438 * i386-opc.h (CpuAMD64): Removed.
1439 (CpuIntel64): Likewise.
1440 (CpuMax): Set to CpuNo64.
1441 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1442 (AMD64): New.
1443 (Intel64): Likewise.
1444 (i386_opcode_modifier): Add amd64 and intel64.
1445 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1446 on call and jmp.
1447 * i386-init.h: Regenerated.
1448 * i386-tbl.h: Likewise.
1449
e89c5eaa
L		 14502016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1451
1452 PR gas/20154
1453 * i386-gen.c (main): Fail if CpuMax is incorrect.
1454 * i386-opc.h (CpuMax): Set to CpuIntel64.
1455 * i386-tbl.h: Regenerated.
1456
77d66e7b
NC		 14572016-05-27 Nick Clifton <nickc@redhat.com>
1458
1459 PR target/20150
1460 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1461 (msp430dis_opcode_unsigned): New function.
1462 (msp430dis_opcode_signed): New function.
1463 (msp430_singleoperand): Use the new opcode reading functions.
1464 Only disassenmble bytes if they were successfully read.
1465 (msp430_doubleoperand): Likewise.
1466 (msp430_branchinstr): Likewise.
1467 (msp430x_callx_instr): Likewise.
1468 (print_insn_msp430): Check that it is safe to read bytes before
1469 attempting disassembly. Use the new opcode reading functions.
1470
19dfcc89
PB		 14712016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1472
1473 * ppc-opc.c (CY): New define. Document it.
1474 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1475
f3ad7637
L		 14762016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1477
1478 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1479 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1480 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1481 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1482 CPU_ANY_AVX_FLAGS.
1483 * i386-init.h: Regenerated.
1484
f1360d58
L		 14852016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1486
1487 PR gas/20141
1488 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1489 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1490 * i386-init.h: Regenerated.
1491
293f5f65
L		 14922016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1493
1494 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1495 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1496 * i386-init.h: Regenerated.
1497
d9eca1df
CZ		 14982016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1499
1500 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1501 information.
1502 (print_insn_arc): Set insn_type information.
1503 * arc-opc.c (C_CC): Add F_CLASS_COND.
1504 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1505 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1506 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1507 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1508 (brne, brne_s, jeq_s, jne_s): Likewise.
1509
87789e08
CZ		 15102016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1511
1512 * arc-tbl.h (neg): New instruction variant.
1513
c810e0b8
CZ		 15142016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1515
1516 * arc-dis.c (find_format, find_format, get_auxreg)
1517 (print_insn_arc): Changed.
1518 * arc-ext.h (INSERT_XOP): Likewise.
1519
3d207518
TS		 15202016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1521
1522 * tic54x-dis.c (sprint_mmr): Adjust.
1523 * tic54x-opc.c: Likewise.
1524
514e58b7
AM		 15252016-05-19 Alan Modra <amodra@gmail.com>
1526
1527 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1528
e43de63c
AM		 15292016-05-19 Alan Modra <amodra@gmail.com>
1530
1531 * ppc-opc.c: Formatting.
1532 (NSISIGNOPT): Define.
1533 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1534
1401d2fe
MR		 15352016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1536
1537 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1538 replacing references to `micromips_ase' throughout.
1539 (_print_insn_mips): Don't use file-level microMIPS annotation to
1540 determine the disassembly mode with the symbol table.
1541
1178da44
PB		 15422016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1543
1544 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1545
8f4f9071
MF		 15462016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1547
1548 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1549 mips64r6.
1550 * mips-opc.c (D34): New macro.
1551 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1552
8bc52696
AF		 15532016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1554
1555 * i386-dis.c (prefix_table): Add RDPID instruction.
1556 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1557 (cpu_flags): Add RDPID bitfield.
1558 * i386-opc.h (enum): Add RDPID element.
1559 (i386_cpu_flags): Add RDPID field.
1560 * i386-opc.tbl: Add RDPID instruction.
1561 * i386-init.h: Regenerate.
1562 * i386-tbl.h: Regenerate.
1563
39d911fc
TP		 15642016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1565
1566 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1567 branch type of a symbol.
1568 (print_insn): Likewise.
1569
16a1fa25
TP		 15702016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1571
1572 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1573 Mainline Security Extensions instructions.
1574 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1575 Extensions instructions.
1576 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1577 instructions.
1578 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1579 special registers.
1580
d751b79e
JM		 15812016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1582
1583 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1584
945e0f82
CZ		 15852016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1586
1587 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1588 (arcExtMap_genOpcode): Likewise.
1589 * arc-opc.c (arg_32bit_rc): Define new variable.
1590 (arg_32bit_u6): Likewise.
1591 (arg_32bit_limm): Likewise.
1592
20f55f38
SN		 15932016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1594
1595 * aarch64-gen.c (VERIFIER): Define.
1596 * aarch64-opc.c (VERIFIER): Define.
1597 (verify_ldpsw): Use static linkage.
1598 * aarch64-opc.h (verify_ldpsw): Remove.
1599 * aarch64-tbl.h: Use VERIFIER for verifiers.
1600
4bd13cde
NC		 16012016-04-28 Nick Clifton <nickc@redhat.com>
1602
1603 PR target/19722
1604 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1605 * aarch64-opc.c (verify_ldpsw): New function.
1606 * aarch64-opc.h (verify_ldpsw): New prototype.
1607 * aarch64-tbl.h: Add initialiser for verifier field.
1608 (LDPSW): Set verifier to verify_ldpsw.
1609
c0f92bf9
L		 16102016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1611
1612 PR binutils/19983
1613 PR binutils/19984
1614 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1615 smaller than address size.
1616
e6c7cdec
TS		 16172016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1618
1619 * alpha-dis.c: Regenerate.
1620 * crx-dis.c: Likewise.
1621 * disassemble.c: Likewise.
1622 * epiphany-opc.c: Likewise.
1623 * fr30-opc.c: Likewise.
1624 * frv-opc.c: Likewise.
1625 * ip2k-opc.c: Likewise.
1626 * iq2000-opc.c: Likewise.
1627 * lm32-opc.c: Likewise.
1628 * lm32-opinst.c: Likewise.
1629 * m32c-opc.c: Likewise.
1630 * m32r-opc.c: Likewise.
1631 * m32r-opinst.c: Likewise.
1632 * mep-opc.c: Likewise.
1633 * mt-opc.c: Likewise.
1634 * or1k-opc.c: Likewise.
1635 * or1k-opinst.c: Likewise.
1636 * tic80-opc.c: Likewise.
1637 * xc16x-opc.c: Likewise.
1638 * xstormy16-opc.c: Likewise.
1639
537aefaf
AB		 16402016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1641
1642 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1643 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1644 calcsd, and calcxd instructions.
1645 * arc-opc.c (insert_nps_bitop_size): Delete.
1646 (extract_nps_bitop_size): Delete.
1647 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1648 (extract_nps_qcmp_m3): Define.
1649 (extract_nps_qcmp_m2): Define.
1650 (extract_nps_qcmp_m1): Define.
1651 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1652 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1653 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1654 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1655 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1656 NPS_QCMP_M3.
1657
c8f785f2
AB		 16582016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1659
1660 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1661
6fd8e7c2
L		 16622016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1663
1664 * Makefile.in: Regenerated with automake 1.11.6.
1665 * aclocal.m4: Likewise.
1666
4b0c052e
AB		 16672016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1668
1669 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1670 instructions.
1671 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1672 (extract_nps_cmem_uimm16): New function.
1673 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1674
cb040366
AB		 16752016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1676
1677 * arc-dis.c (arc_insn_length): New function.
1678 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1679 (find_format): Change insnLen parameter to unsigned.
1680
accc0180
NC		 16812016-04-13 Nick Clifton <nickc@redhat.com>
1682
1683 PR target/19937
1684 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1685 the LD.B and LD.BU instructions.
1686
f36e33da
CZ		 16872016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1688
1689 * arc-dis.c (find_format): Check for extension flags.
1690 (print_flags): New function.
1691 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1692 .extAuxRegister.
1693 * arc-ext.c (arcExtMap_coreRegName): Use
1694 LAST_EXTENSION_CORE_REGISTER.
1695 (arcExtMap_coreReadWrite): Likewise.
1696 (dump_ARC_extmap): Update printing.
1697 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1698 (arc_aux_regs): Add cpu field.
1699 * arc-regs.h: Add cpu field, lower case name aux registers.
1700
1c2e355e
CZ		 17012016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1702
1703 * arc-tbl.h: Add rtsc, sleep with no arguments.
1704
b99747ae
CZ		 17052016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1706
1707 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1708 Initialize.
1709 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1710 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1711 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1712 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1713 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1714 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1715 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1716 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1717 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1718 (arc_opcode arc_opcodes): Null terminate the array.
1719 (arc_num_opcodes): Remove.
1720 * arc-ext.h (INSERT_XOP): Define.
1721 (extInstruction_t): Likewise.
1722 (arcExtMap_instName): Delete.
1723 (arcExtMap_insn): New function.
1724 (arcExtMap_genOpcode): Likewise.
1725 * arc-ext.c (ExtInstruction): Remove.
1726 (create_map): Zero initialize instruction fields.
1727 (arcExtMap_instName): Remove.
1728 (arcExtMap_insn): New function.
1729 (dump_ARC_extmap): More info while debuging.
1730 (arcExtMap_genOpcode): New function.
1731 * arc-dis.c (find_format): New function.
1732 (print_insn_arc): Use find_format.
1733 (arc_get_disassembler): Enable dump_ARC_extmap only when
1734 debugging.
1735
92708cec
MR		 17362016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1737
1738 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1739 instruction bits out.
1740
a42a4f84
AB		 17412016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1742
1743 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1744 * arc-opc.c (arc_flag_operands): Add new flags.
1745 (arc_flag_classes): Add new classes.
1746
1328504b
AB		 17472016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1748
1749 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1750
820f03ff
AB		 17512016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1752
1753 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1754 encode1, rflt, crc16, and crc32 instructions.
1755 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1756 (arc_flag_classes): Add C_NPS_R.
1757 (insert_nps_bitop_size_2b): New function.
1758 (extract_nps_bitop_size_2b): Likewise.
1759 (insert_nps_bitop_uimm8): Likewise.
1760 (extract_nps_bitop_uimm8): Likewise.
1761 (arc_operands): Add new operand entries.
1762
8ddf6b2a
CZ		 17632016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1764
b99747ae
CZ		 1765 * arc-regs.h: Add a new subclass field. Add double assist
1766 accumulator register values.
1767 * arc-tbl.h: Use DPA subclass to mark the double assist
1768 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1769 * arc-opc.c (RSP): Define instead of SP.
1770 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1771
589a7d88
JW		 17722016-04-05 Jiong Wang <jiong.wang@arm.com>
1773
1774 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1775
0a191de9 17762016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1777
1778 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1779 NPS_R_SRC1.
1780
0a106562
AB		 17812016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1782
1783 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1784 issues. No functional changes.
1785
bd05ac5f
CZ		 17862016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1787
b99747ae
CZ		 1788 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1789 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1790 (RTT): Remove duplicate.
1791 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1792 (PCT_CONFIG*): Remove.
1793 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1794
9885948f
CZ		 17952016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1796
b99747ae 1797 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1798
f2dd8838
CZ		 17992016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1800
b99747ae
CZ		 1801 * arc-tbl.h (invld07): Remove.
1802 * arc-ext-tbl.h: New file.
1803 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1804 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1805
0d2f91fe
JK		 18062016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1807
1808 Fix -Wstack-usage warnings.
1809 * aarch64-dis.c (print_operands): Substitute size.
1810 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1811
a6b71f42
JM		 18122016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1813
1814 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1815 to get a proper diagnostic when an invalid ASR register is used.
1816
9780e045
NC		 18172016-03-22 Nick Clifton <nickc@redhat.com>
1818
1819 * configure: Regenerate.
1820
e23e8ebe
AB		 18212016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1822
1823 * arc-nps400-tbl.h: New file.
1824 * arc-opc.c: Add top level comment.
1825 (insert_nps_3bit_dst): New function.
1826 (extract_nps_3bit_dst): New function.
1827 (insert_nps_3bit_src2): New function.
1828 (extract_nps_3bit_src2): New function.
1829 (insert_nps_bitop_size): New function.
1830 (extract_nps_bitop_size): New function.
1831 (arc_flag_operands): Add nps400 entries.
1832 (arc_flag_classes): Add nps400 entries.
1833 (arc_operands): Add nps400 entries.
1834 (arc_opcodes): Add nps400 include.
1835
1ae8ab47
AB		 18362016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1837
1838 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1839 the new class enum values.
1840
8699fc3e
AB		 18412016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1842
1843 * arc-dis.c (print_insn_arc): Handle nps400.
1844
24740d83
AB		 18452016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1846
1847 * arc-opc.c (BASE): Delete.
1848
8678914f
NC		 18492016-03-18 Nick Clifton <nickc@redhat.com>
1850
1851 PR target/19721
1852 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1853 of MOV insn that aliases an ORR insn.
1854
cc933301
JW		 18552016-03-16 Jiong Wang <jiong.wang@arm.com>
1856
1857 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1858
f86f5863
TS		 18592016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1860
1861 * mcore-opc.h: Add const qualifiers.
1862 * microblaze-opc.h (struct op_code_struct): Likewise.
1863 * sh-opc.h: Likewise.
1864 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1865 (tic4x_print_op): Likewise.
1866
62de1c63
AM		 18672016-03-02 Alan Modra <amodra@gmail.com>
1868
d11698cd 1869 * or1k-desc.h: Regenerate.
62de1c63 1870 * fr30-ibld.c: Regenerate.
c697cf0b 1871 * rl78-decode.c: Regenerate.
62de1c63 1872
020efce5
NC		 18732016-03-01 Nick Clifton <nickc@redhat.com>
1874
1875 PR target/19747
1876 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1877
b0c11777
RL		 18782016-02-24 Renlin Li <renlin.li@arm.com>
1879
1880 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1881 (print_insn_coprocessor): Support fp16 instructions.
1882
3e309328
RL		 18832016-02-24 Renlin Li <renlin.li@arm.com>
1884
1885 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1886 vminnm, vrint(mpna).
1887
8afc7bea
RL		 18882016-02-24 Renlin Li <renlin.li@arm.com>
1889
1890 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1891 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1892
4fd7268a
L		 18932016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1894
1895 * i386-dis.c (print_insn): Parenthesize expression to prevent
1896 truncated addresses.
1897 (OP_J): Likewise.
1898
4670103e
CZ		 18992016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1900 Janek van Oirschot <jvanoirs@synopsys.com>
1901
b99747ae
CZ		 1902 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1903 variable.
4670103e 1904
c1d9289f
NC		 19052016-02-04 Nick Clifton <nickc@redhat.com>
1906
1907 PR target/19561
1908 * msp430-dis.c (print_insn_msp430): Add a special case for
1909 decoding an RRC instruction with the ZC bit set in the extension
1910 word.
1911
a143b004
AB		 19122016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1913
1914 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1915 * epiphany-ibld.c: Regenerate.
1916 * fr30-ibld.c: Regenerate.
1917 * frv-ibld.c: Regenerate.
1918 * ip2k-ibld.c: Regenerate.
1919 * iq2000-ibld.c: Regenerate.
1920 * lm32-ibld.c: Regenerate.
1921 * m32c-ibld.c: Regenerate.
1922 * m32r-ibld.c: Regenerate.
1923 * mep-ibld.c: Regenerate.
1924 * mt-ibld.c: Regenerate.
1925 * or1k-ibld.c: Regenerate.
1926 * xc16x-ibld.c: Regenerate.
1927 * xstormy16-ibld.c: Regenerate.
1928
b89807c6
AB		 19292016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1930
1931 * epiphany-dis.c: Regenerated from latest cpu files.
1932
d8c823c8
MM		 19332016-02-01 Michael McConville <mmcco@mykolab.com>
1934
1935 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1936 test bit.
1937
5bc5ae88
RL		 19382016-01-25 Renlin Li <renlin.li@arm.com>
1939
1940 * arm-dis.c (mapping_symbol_for_insn): New function.
1941 (find_ifthen_state): Call mapping_symbol_for_insn().
1942
0bff6e2d
MW		 19432016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1944
1945 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1946 of MSR UAO immediate operand.
1947
100b4f2e
MR		 19482016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1949
1950 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1951 instruction support.
1952
5c14705f
AM		 19532016-01-17 Alan Modra <amodra@gmail.com>
1954
1955 * configure: Regenerate.
1956
4d82fe66
NC		 19572016-01-14 Nick Clifton <nickc@redhat.com>
1958
1959 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1960 instructions that can support stack pointer operations.
1961 * rl78-decode.c: Regenerate.
1962 * rl78-dis.c: Fix display of stack pointer in MOVW based
1963 instructions.
1964
651657fa
MW		 19652016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1966
1967 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1968 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1969 erxtatus_el1 and erxaddr_el1.
1970
105bde57
MW		 19712016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1972
1973 * arm-dis.c (arm_opcodes): Add "esb".
1974 (thumb_opcodes): Likewise.
1975
afa8d405
PB		 19762016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1977
1978 * ppc-opc.c <xscmpnedp>: Delete.
1979 <xvcmpnedp>: Likewise.
1980 <xvcmpnedp.>: Likewise.
1981 <xvcmpnesp>: Likewise.
1982 <xvcmpnesp.>: Likewise.
1983
83c3256e
AS		 19842016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1985
1986 PR gas/13050
1987 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1988 addition to ISA_A.
1989
6f2750fe
AM		 19902016-01-01 Alan Modra <amodra@gmail.com>
1991
1992 Update year range in copyright notice of all files.
1993
3499769a
AM		 1994For older changes see ChangeLog-2015
1995\f
1996Copyright (C) 2016 Free Software Foundation, Inc.
1997
1998Copying and distribution of this file, with or without modification,
1999are permitted in any medium without royalty provided the copyright
2000notice and this notice are preserved.
2001
2002Local Variables:
2003mode: change-log
2004left-margin: 8
2005fill-column: 74
2006version-control: never
2007End:
GDB Binutils - Deliverables
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