projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
NDS32/BFD: Correct an aliasing error in `nds32_elf_check_relocs'
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
decf5bd1
CM		 12016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
2
3 * arc-tbl.h: Removed any "inv.+" instructions from the table.
4
e5b06ef0
CZ		 52016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
6
7 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
8 usage on ISA basis.
9
93562a34
JW		 102016-10-11 Jiong Wang <jiong.wang@arm.com>
11
12 PR target/20666
13 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
14
362c0c4d
JW		 152016-10-07 Jiong Wang <jiong.wang@arm.com>
16
17 PR target/20667
18 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
19 available.
20
1047201f
AM		 212016-10-07 Alan Modra <amodra@gmail.com>
22
23 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
24
1a0670f3
AM		 252016-10-06 Alan Modra <amodra@gmail.com>
26
27 * aarch64-opc.c: Spell fall through comments consistently.
28 * i386-dis.c: Likewise.
29 * aarch64-dis.c: Add missing fall through comments.
30 * aarch64-opc.c: Likewise.
31 * arc-dis.c: Likewise.
32 * arm-dis.c: Likewise.
33 * i386-dis.c: Likewise.
34 * m68k-dis.c: Likewise.
35 * mep-asm.c: Likewise.
36 * ns32k-dis.c: Likewise.
37 * sh-dis.c: Likewise.
38 * tic4x-dis.c: Likewise.
39 * tic6x-dis.c: Likewise.
40 * vax-dis.c: Likewise.
41
2b804145
AM		 422016-10-06 Alan Modra <amodra@gmail.com>
43
44 * arc-ext.c (create_map): Add missing break.
45 * msp430-decode.opc (encode_as): Likewise.
46 * msp430-decode.c: Regenerate.
47
616ec358
AM		 482016-10-06 Alan Modra <amodra@gmail.com>
49
50 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
51 * crx-dis.c (print_insn_crx): Likewise.
52
72da393d
L		 532016-09-30 H.J. Lu <hongjiu.lu@intel.com>
54
55 PR binutils/20657
56 * i386-dis.c (putop): Don't assign alt twice.
57
744ce302
JW		 582016-09-29 Jiong Wang <jiong.wang@arm.com>
59
60 PR target/20553
61 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
62
a5721ba2
AM		 632016-09-29 Alan Modra <amodra@gmail.com>
64
65 * ppc-opc.c (L): Make compulsory.
66 (LOPT): New, optional form of L.
67 (HTM_R): Define as LOPT.
68 (L0, L1): Delete.
69 (L32OPT): New, optional for 32-bit L.
70 (L2OPT): New, 2-bit L for dcbf.
71 (SVC_LEC): Update.
72 (L2): Define.
73 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
74 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
75 <dcbf>: Use L2OPT.
76 <tlbiel, tlbie>: Use LOPT.
77 <wclr, wclrall>: Use L2.
78
c5da1932
VZ		 792016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
80
81 * Makefile.in: Regenerate.
82 * configure: Likewise.
83
2b848ebd
CZ		 842016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
85
86 * arc-ext-tbl.h (EXTINSN2OPF): Define.
87 (EXTINSN2OP): Use EXTINSN2OPF.
88 (bspeekm, bspop, modapp): New extension instructions.
89 * arc-opc.c (F_DNZ_ND): Define.
90 (F_DNZ_D): Likewise.
91 (F_SIZEB1): Changed.
92 (C_DNZ_D): Define.
93 (C_HARD): Changed.
94 * arc-tbl.h (dbnz): New instruction.
95 (prealloc): Allow it for ARC EM.
96 (xbfu): Likewise.
97
ad43e107
RS		 982016-09-21 Richard Sandiford <richard.sandiford@arm.com>
99
100 * aarch64-opc.c (print_immediate_offset_address): Print spaces
101 after commas in addresses.
102 (aarch64_print_operand): Likewise.
103
ab3b8fcf
RS		 1042016-09-21 Richard Sandiford <richard.sandiford@arm.com>
105
106 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
107 rather than "should be" or "expected to be" in error messages.
108
bb7eff52
RS		 1092016-09-21 Richard Sandiford <richard.sandiford@arm.com>
110
111 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
112 (print_mnemonic_name): ...here.
113 (print_comment): New function.
114 (print_aarch64_insn): Call it.
115 * aarch64-opc.c (aarch64_conds): Add SVE names.
116 (aarch64_print_operand): Print alternative condition names in
117 a comment.
118
c0890d26
RS		 1192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
120
121 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
122 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
123 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
124 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
125 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
126 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
127 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
128 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
129 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
130 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
131 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
132 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
133 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
134 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
135 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
136 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
137 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
138 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
139 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
140 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
141 (OP_SVE_XWU, OP_SVE_XXU): New macros.
142 (aarch64_feature_sve): New variable.
143 (SVE): New macro.
144 (_SVE_INSN): Likewise.
145 (aarch64_opcode_table): Add SVE instructions.
146 * aarch64-opc.h (extract_fields): Declare.
147 * aarch64-opc-2.c: Regenerate.
148 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
149 * aarch64-asm-2.c: Regenerate.
150 * aarch64-dis.c (extract_fields): Make global.
151 (do_misc_decoding): Handle the new SVE aarch64_ops.
152 * aarch64-dis-2.c: Regenerate.
153
116b6019
RS		 1542016-09-21 Richard Sandiford <richard.sandiford@arm.com>
155
156 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
157 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
158 aarch64_field_kinds.
159 * aarch64-opc.c (fields): Add corresponding entries.
160 * aarch64-asm.c (aarch64_get_variant): New function.
161 (aarch64_encode_variant_using_iclass): Likewise.
162 (aarch64_opcode_encode): Call it.
163 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
164 (aarch64_opcode_decode): Call it.
165
047cd301
RS		 1662016-09-21 Richard Sandiford <richard.sandiford@arm.com>
167
168 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
169 and FP register operands.
170 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
171 (FLD_SVE_Vn): New aarch64_field_kinds.
172 * aarch64-opc.c (fields): Add corresponding entries.
173 (aarch64_print_operand): Handle the new SVE core and FP register
174 operands.
175 * aarch64-opc-2.c: Regenerate.
176 * aarch64-asm-2.c: Likewise.
177 * aarch64-dis-2.c: Likewise.
178
165d4950
RS		 1792016-09-21 Richard Sandiford <richard.sandiford@arm.com>
180
181 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
182 immediate operands.
183 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
184 * aarch64-opc.c (fields): Add corresponding entry.
185 (operand_general_constraint_met_p): Handle the new SVE FP immediate
186 operands.
187 (aarch64_print_operand): Likewise.
188 * aarch64-opc-2.c: Regenerate.
189 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
190 (ins_sve_float_zero_one): New inserters.
191 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
192 (aarch64_ins_sve_float_half_two): Likewise.
193 (aarch64_ins_sve_float_zero_one): Likewise.
194 * aarch64-asm-2.c: Regenerate.
195 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
196 (ext_sve_float_zero_one): New extractors.
197 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
198 (aarch64_ext_sve_float_half_two): Likewise.
199 (aarch64_ext_sve_float_zero_one): Likewise.
200 * aarch64-dis-2.c: Regenerate.
201
e950b345
RS		 2022016-09-21 Richard Sandiford <richard.sandiford@arm.com>
203
204 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
205 integer immediate operands.
206 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
207 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
208 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
209 * aarch64-opc.c (fields): Add corresponding entries.
210 (operand_general_constraint_met_p): Handle the new SVE integer
211 immediate operands.
212 (aarch64_print_operand): Likewise.
213 (aarch64_sve_dupm_mov_immediate_p): New function.
214 * aarch64-opc-2.c: Regenerate.
215 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
216 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
217 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
218 (aarch64_ins_limm): ...here.
219 (aarch64_ins_inv_limm): New function.
220 (aarch64_ins_sve_aimm): Likewise.
221 (aarch64_ins_sve_asimm): Likewise.
222 (aarch64_ins_sve_limm_mov): Likewise.
223 (aarch64_ins_sve_shlimm): Likewise.
224 (aarch64_ins_sve_shrimm): Likewise.
225 * aarch64-asm-2.c: Regenerate.
226 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
227 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
228 * aarch64-dis.c (decode_limm): New function, split out from...
229 (aarch64_ext_limm): ...here.
230 (aarch64_ext_inv_limm): New function.
231 (decode_sve_aimm): Likewise.
232 (aarch64_ext_sve_aimm): Likewise.
233 (aarch64_ext_sve_asimm): Likewise.
234 (aarch64_ext_sve_limm_mov): Likewise.
235 (aarch64_top_bit): Likewise.
236 (aarch64_ext_sve_shlimm): Likewise.
237 (aarch64_ext_sve_shrimm): Likewise.
238 * aarch64-dis-2.c: Regenerate.
239
98907a70
RS		 2402016-09-21 Richard Sandiford <richard.sandiford@arm.com>
241
242 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
243 operands.
244 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
245 the AARCH64_MOD_MUL_VL entry.
246 (value_aligned_p): Cope with non-power-of-two alignments.
247 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
248 (print_immediate_offset_address): Likewise.
249 (aarch64_print_operand): Likewise.
250 * aarch64-opc-2.c: Regenerate.
251 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
252 (ins_sve_addr_ri_s9xvl): New inserters.
253 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
254 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
255 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
256 * aarch64-asm-2.c: Regenerate.
257 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
258 (ext_sve_addr_ri_s9xvl): New extractors.
259 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
260 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
261 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
262 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
263 * aarch64-dis-2.c: Regenerate.
264
4df068de
RS		 2652016-09-21 Richard Sandiford <richard.sandiford@arm.com>
266
267 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
268 address operands.
269 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
270 (FLD_SVE_xs_22): New aarch64_field_kinds.
271 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
272 (get_operand_specific_data): New function.
273 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
274 FLD_SVE_xs_14 and FLD_SVE_xs_22.
275 (operand_general_constraint_met_p): Handle the new SVE address
276 operands.
277 (sve_reg): New array.
278 (get_addr_sve_reg_name): New function.
279 (aarch64_print_operand): Handle the new SVE address operands.
280 * aarch64-opc-2.c: Regenerate.
281 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
282 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
283 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
284 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
285 (aarch64_ins_sve_addr_rr_lsl): Likewise.
286 (aarch64_ins_sve_addr_rz_xtw): Likewise.
287 (aarch64_ins_sve_addr_zi_u5): Likewise.
288 (aarch64_ins_sve_addr_zz): Likewise.
289 (aarch64_ins_sve_addr_zz_lsl): Likewise.
290 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
291 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
292 * aarch64-asm-2.c: Regenerate.
293 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
294 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
295 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
296 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
297 (aarch64_ext_sve_addr_ri_u6): Likewise.
298 (aarch64_ext_sve_addr_rr_lsl): Likewise.
299 (aarch64_ext_sve_addr_rz_xtw): Likewise.
300 (aarch64_ext_sve_addr_zi_u5): Likewise.
301 (aarch64_ext_sve_addr_zz): Likewise.
302 (aarch64_ext_sve_addr_zz_lsl): Likewise.
303 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
304 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
305 * aarch64-dis-2.c: Regenerate.
306
2442d846
RS		 3072016-09-21 Richard Sandiford <richard.sandiford@arm.com>
308
309 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
310 AARCH64_OPND_SVE_PATTERN_SCALED.
311 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
312 * aarch64-opc.c (fields): Add a corresponding entry.
313 (set_multiplier_out_of_range_error): New function.
314 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
315 (operand_general_constraint_met_p): Handle
316 AARCH64_OPND_SVE_PATTERN_SCALED.
317 (print_register_offset_address): Use PRIi64 to print the
318 shift amount.
319 (aarch64_print_operand): Likewise. Handle
320 AARCH64_OPND_SVE_PATTERN_SCALED.
321 * aarch64-opc-2.c: Regenerate.
322 * aarch64-asm.h (ins_sve_scale): New inserter.
323 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
324 * aarch64-asm-2.c: Regenerate.
325 * aarch64-dis.h (ext_sve_scale): New inserter.
326 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
327 * aarch64-dis-2.c: Regenerate.
328
245d2e3f
RS		 3292016-09-21 Richard Sandiford <richard.sandiford@arm.com>
330
331 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
332 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
333 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
334 (FLD_SVE_prfop): Likewise.
335 * aarch64-opc.c: Include libiberty.h.
336 (aarch64_sve_pattern_array): New variable.
337 (aarch64_sve_prfop_array): Likewise.
338 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
339 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
340 AARCH64_OPND_SVE_PRFOP.
341 * aarch64-asm-2.c: Regenerate.
342 * aarch64-dis-2.c: Likewise.
343 * aarch64-opc-2.c: Likewise.
344
d50c751e
RS		 3452016-09-21 Richard Sandiford <richard.sandiford@arm.com>
346
347 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
348 AARCH64_OPND_QLF_P_[ZM].
349 (aarch64_print_operand): Print /z and /m where appropriate.
350
f11ad6bc
RS		 3512016-09-21 Richard Sandiford <richard.sandiford@arm.com>
352
353 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
354 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
355 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
356 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
357 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
358 * aarch64-opc.c (fields): Add corresponding entries here.
359 (operand_general_constraint_met_p): Check that SVE register lists
360 have the correct length. Check the ranges of SVE index registers.
361 Check for cases where p8-p15 are used in 3-bit predicate fields.
362 (aarch64_print_operand): Handle the new SVE operands.
363 * aarch64-opc-2.c: Regenerate.
364 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
365 * aarch64-asm.c (aarch64_ins_sve_index): New function.
366 (aarch64_ins_sve_reglist): Likewise.
367 * aarch64-asm-2.c: Regenerate.
368 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
369 * aarch64-dis.c (aarch64_ext_sve_index): New function.
370 (aarch64_ext_sve_reglist): Likewise.
371 * aarch64-dis-2.c: Regenerate.
372
0c608d6b
RS		 3732016-09-21 Richard Sandiford <richard.sandiford@arm.com>
374
375 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
376 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
377 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
378 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
379 tied operands.
380
01dbfe4c
RS		 3812016-09-21 Richard Sandiford <richard.sandiford@arm.com>
382
383 * aarch64-opc.c (get_offset_int_reg_name): New function.
384 (print_immediate_offset_address): Likewise.
385 (print_register_offset_address): Take the base and offset
386 registers as parameters.
387 (aarch64_print_operand): Update caller accordingly. Use
388 print_immediate_offset_address.
389
72e9f319
RS		 3902016-09-21 Richard Sandiford <richard.sandiford@arm.com>
391
392 * aarch64-opc.c (BANK): New macro.
393 (R32, R64): Take a register number as argument
394 (int_reg): Use BANK.
395
8a7f0c1b
RS		 3962016-09-21 Richard Sandiford <richard.sandiford@arm.com>
397
398 * aarch64-opc.c (print_register_list): Add a prefix parameter.
399 (aarch64_print_operand): Update accordingly.
400
aa2aa4c6
RS		 4012016-09-21 Richard Sandiford <richard.sandiford@arm.com>
402
403 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
404 for FPIMM.
405 * aarch64-asm.h (ins_fpimm): New inserter.
406 * aarch64-asm.c (aarch64_ins_fpimm): New function.
407 * aarch64-asm-2.c: Regenerate.
408 * aarch64-dis.h (ext_fpimm): New extractor.
409 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
410 (aarch64_ext_fpimm): New function.
411 * aarch64-dis-2.c: Regenerate.
412
b5464a68
RS		 4132016-09-21 Richard Sandiford <richard.sandiford@arm.com>
414
415 * aarch64-asm.c: Include libiberty.h.
416 (insert_fields): New function.
417 (aarch64_ins_imm): Use it.
418 * aarch64-dis.c (extract_fields): New function.
419 (aarch64_ext_imm): Use it.
420
42408347
RS		 4212016-09-21 Richard Sandiford <richard.sandiford@arm.com>
422
423 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
424 with an esize parameter.
425 (operand_general_constraint_met_p): Update accordingly.
426 Fix misindented code.
427 * aarch64-asm.c (aarch64_ins_limm): Update call to
428 aarch64_logical_immediate_p.
429
4989adac
RS		 4302016-09-21 Richard Sandiford <richard.sandiford@arm.com>
431
432 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
433
bd11d5d8
RS		 4342016-09-21 Richard Sandiford <richard.sandiford@arm.com>
435
436 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
437
f807f43d
CZ		 4382016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
439
440 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
441
fd486b63
PB		 4422016-09-14 Peter Bergner <bergner@vnet.ibm.com>
443
444 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
445 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
446 xor3>: Delete mnemonics.
447 <cp_abort>: Rename mnemonic from ...
448 <cpabort>: ...to this.
449 <setb>: Change to a X form instruction.
450 <sync>: Change to 1 operand form.
451 <copy>: Delete mnemonic.
452 <copy_first>: Rename mnemonic from ...
453 <copy>: ...to this.
454 <paste, paste.>: Delete mnemonics.
455 <paste_last>: Rename mnemonic from ...
456 <paste.>: ...to this.
457
dce08442
AK		 4582016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
459
460 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
461
952c3f51
AK		 4622016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
463
464 * s390-mkopc.c (main): Support alternate arch strings.
465
8b71537b
PS		 4662016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
467
468 * s390-opc.txt: Fix kmctr instruction type.
469
5b64d091
L		 4702016-09-07 H.J. Lu <hongjiu.lu@intel.com>
471
472 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
473 * i386-init.h: Regenerated.
474
7763838e
CM		 4752016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
476
477 * opcodes/arc-dis.c (print_insn_arc): Changed.
478
1b8b6532
JM		 4792016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
480
481 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
482 camellia_fl.
483
1a336194
TP		 4842016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
485
486 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
487 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
488 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
489
6b40c462
L		 4902016-08-24 H.J. Lu <hongjiu.lu@intel.com>
491
492 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
493 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
494 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
495 PREFIX_MOD_3_0FAE_REG_4.
496 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
497 PREFIX_MOD_3_0FAE_REG_4.
498 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
499 (cpu_flags): Add CpuPTWRITE.
500 * i386-opc.h (CpuPTWRITE): New.
501 (i386_cpu_flags): Add cpuptwrite.
502 * i386-opc.tbl: Add ptwrite instruction.
503 * i386-init.h: Regenerated.
504 * i386-tbl.h: Likewise.
505
ab548d2d
AK		 5062016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
507
508 * arc-dis.h: Wrap around in extern "C".
509
344bde0a
RS		 5102016-08-23 Richard Sandiford <richard.sandiford@arm.com>
511
512 * aarch64-tbl.h (V8_2_INSN): New macro.
513 (aarch64_opcode_table): Use it.
514
5ce912d8
RS		 5152016-08-23 Richard Sandiford <richard.sandiford@arm.com>
516
517 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
518 CORE_INSN, __FP_INSN and SIMD_INSN.
519
9d30b0bd
RS		 5202016-08-23 Richard Sandiford <richard.sandiford@arm.com>
521
522 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
523 (aarch64_opcode_table): Update uses accordingly.
524
dfdaec14
AJ		 5252016-07-25 Andrew Jenner <andrew@codesourcery.com>
526 Kwok Cheung Yeung <kcy@codesourcery.com>
527
528 opcodes/
529 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
530 'e_cmplwi' to 'e_cmpli' instead.
531 (OPVUPRT, OPVUPRT_MASK): Define.
532 (powerpc_opcodes): Add E200Z4 insns.
533 (vle_opcodes): Add context save/restore insns.
534
7bd374a4
MR		 5352016-07-27 Maciej W. Rozycki <macro@imgtec.com>
536
537 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
538 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
539 "j".
540
db18dbab
GM		 5412016-07-27 Graham Markall <graham.markall@embecosm.com>
542
543 * arc-nps400-tbl.h: Change block comments to GNU format.
544 * arc-dis.c: Add new globals addrtypenames,
545 addrtypenames_max, and addtypeunknown.
546 (get_addrtype): New function.
547 (print_insn_arc): Print colons and address types when
548 required.
549 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
550 define insert and extract functions for all address types.
551 (arc_operands): Add operands for colon and all address
552 types.
553 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
554 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
555 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
556 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
557 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
558 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
559
fecd57f9
L		 5602016-07-21 H.J. Lu <hongjiu.lu@intel.com>
561
562 * configure: Regenerated.
563
37fd5ef3
CZ		 5642016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
565
566 * arc-dis.c (skipclass): New structure.
567 (decodelist): New variable.
568 (is_compatible_p): New function.
569 (new_element): Likewise.
570 (skip_class_p): Likewise.
571 (find_format_from_table): Use skip_class_p function.
572 (find_format): Decode first the extension instructions.
573 (print_insn_arc): Select either ARCEM or ARCHS based on elf
574 e_flags.
575 (parse_option): New function.
576 (parse_disassembler_options): Likewise.
577 (print_arc_disassembler_options): Likewise.
578 (print_insn_arc): Use parse_disassembler_options function. Proper
579 select ARCv2 cpu variant.
580 * disassemble.c (disassembler_usage): Add ARC disassembler
581 options.
582
92281a5b
MR		 5832016-07-13 Maciej W. Rozycki <macro@imgtec.com>
584
585 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
586 annotation from the "nal" entry and reorder it beyond "bltzal".
587
6e7ced37
JM		 5882016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
589
590 * sparc-opc.c (ldtxa): New macro.
591 (sparc_opcodes): Use the macro defined above to add entries for
592 the LDTXA instructions.
593 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
594 instruction.
595
2f831b9a 5962016-07-07 James Bowman <james.bowman@ftdichip.com>
597
598 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
599 and "jmpc".
600
c07315e0
JB		 6012016-07-01 Jan Beulich <jbeulich@suse.com>
602
603 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
604 (movzb): Adjust to cover all permitted suffixes.
605 (movzw): New.
606 * i386-tbl.h: Re-generate.
607
9243100a
JB		 6082016-07-01 Jan Beulich <jbeulich@suse.com>
609
610 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
611 (lgdt): Remove Tbyte from non-64-bit variant.
612 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
613 xsaves64, xsavec64): Remove Disp16.
614 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
615 Remove Disp32S from non-64-bit variants. Remove Disp16 from
616 64-bit variants.
617 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
618 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
619 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
620 64-bit variants.
621 * i386-tbl.h: Re-generate.
622
8325cc63
JB		 6232016-07-01 Jan Beulich <jbeulich@suse.com>
624
625 * i386-opc.tbl (xlat): Remove RepPrefixOk.
626 * i386-tbl.h: Re-generate.
627
838441e4
YQ		 6282016-06-30 Yao Qi <yao.qi@linaro.org>
629
630 * arm-dis.c (print_insn): Fix typo in comment.
631
dab26bf4
RS		 6322016-06-28 Richard Sandiford <richard.sandiford@arm.com>
633
634 * aarch64-opc.c (operand_general_constraint_met_p): Check the
635 range of ldst_elemlist operands.
636 (print_register_list): Use PRIi64 to print the index.
637 (aarch64_print_operand): Likewise.
638
5703197e
TS		 6392016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
640
641 * mcore-opc.h: Remove sentinal.
642 * mcore-dis.c (print_insn_mcore): Adjust.
643
ce440d63
GM		 6442016-06-23 Graham Markall <graham.markall@embecosm.com>
645
646 * arc-opc.c: Correct description of availability of NPS400
647 features.
648
6fd3a02d
PB		 6492016-06-22 Peter Bergner <bergner@vnet.ibm.com>
650
651 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
652 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
653 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
654 xor3>: New mnemonics.
655 <setb>: Change to a VX form instruction.
656 (insert_sh6): Add support for rldixor.
657 (extract_sh6): Likewise.
658
6b477896
TS		 6592016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
660
661 * arc-ext.h: Wrap in extern C.
662
bdd582db
GM		 6632016-06-21 Graham Markall <graham.markall@embecosm.com>
664
665 * arc-dis.c (arc_insn_length): Add comment on instruction length.
666 Use same method for determining instruction length on ARC700 and
667 NPS-400.
668 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
669 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
670 with the NPS400 subclass.
671 * arc-opc.c: Likewise.
672
96074adc
JM		 6732016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
674
675 * sparc-opc.c (rdasr): New macro.
676 (wrasr): Likewise.
677 (rdpr): Likewise.
678 (wrpr): Likewise.
679 (rdhpr): Likewise.
680 (wrhpr): Likewise.
681 (sparc_opcodes): Use the macros above to fix and expand the
682 definition of read/write instructions from/to
683 asr/privileged/hyperprivileged instructions.
684 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
685 %hva_mask_nz. Prefer softint_set and softint_clear over
686 set_softint and clear_softint.
687 (print_insn_sparc): Support %ver in Rd.
688
7a10c22f
JM		 6892016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
690
691 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
692 architecture according to the hardware capabilities they require.
693
4f26fb3a
JM		 6942016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
695
696 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
697 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
698 bfd_mach_sparc_v9{c,d,e,v,m}.
699 * sparc-opc.c (MASK_V9C): Define.
700 (MASK_V9D): Likewise.
701 (MASK_V9E): Likewise.
702 (MASK_V9V): Likewise.
703 (MASK_V9M): Likewise.
704 (v6): Add MASK_V9{C,D,E,V,M}.
705 (v6notlet): Likewise.
706 (v7): Likewise.
707 (v8): Likewise.
708 (v9): Likewise.
709 (v9andleon): Likewise.
710 (v9a): Likewise.
711 (v9b): Likewise.
712 (v9c): Define.
713 (v9d): Likewise.
714 (v9e): Likewise.
715 (v9v): Likewise.
716 (v9m): Likewise.
717 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
718
3ee6e4fb
NC		 7192016-06-15 Nick Clifton <nickc@redhat.com>
720
721 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
722 constants to match expected behaviour.
723 (nds32_parse_opcode): Likewise. Also for whitespace.
724
02f3be19
AB		 7252016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
726
727 * arc-opc.c (extract_rhv1): Extract value from insn.
728
6f9f37ed 7292016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 730
731 * arc-nps400-tbl.h: Add ldbit instruction.
732 * arc-opc.c: Add flag classes required for ldbit.
733
6f9f37ed 7342016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 735
736 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
737 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
738 support the above instructions.
739
6f9f37ed 7402016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 741
742 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
743 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
744 csma, cbba, zncv, and hofs.
745 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
746 support the above instructions.
747
7482016-06-06 Graham Markall <graham.markall@embecosm.com>
749
750 * arc-nps400-tbl.h: Add andab and orab instructions.
751
7522016-06-06 Graham Markall <graham.markall@embecosm.com>
753
754 * arc-nps400-tbl.h: Add addl-like instructions.
755
7562016-06-06 Graham Markall <graham.markall@embecosm.com>
757
758 * arc-nps400-tbl.h: Add mxb and imxb instructions.
759
7602016-06-06 Graham Markall <graham.markall@embecosm.com>
761
762 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
763 instructions.
764
b2cc3f6f
AK		 7652016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
766
767 * s390-dis.c (option_use_insn_len_bits_p): New file scope
768 variable.
769 (init_disasm): Handle new command line option "insnlength".
770 (print_s390_disassembler_options): Mention new option in help
771 output.
772 (print_insn_s390): Use the encoded insn length when dumping
773 unknown instructions.
774
1857fe72
DC		 7752016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
776
777 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
778 to the address and set as symbol address for LDS/ STS immediate operands.
779
14b57c7c
AM		 7802016-06-07 Alan Modra <amodra@gmail.com>
781
782 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
783 cpu for "vle" to e500.
784 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
785 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
786 (PPCNONE): Delete, substitute throughout.
787 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
788 except for major opcode 4 and 31.
789 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
790
4d1464f2
MW		 7912016-06-07 Matthew Wahab <matthew.wahab@arm.com>
792
793 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
794 ARM_EXT_RAS in relevant entries.
795
026122a6
PB		 7962016-06-03 Peter Bergner <bergner@vnet.ibm.com>
797
798 PR binutils/20196
799 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
800 opcodes for E6500.
801
07f5af7d
L		 8022016-06-03 H.J. Lu <hongjiu.lu@intel.com>
803
804 PR binutis/18386
805 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
806 (indir_v_mode): New.
807 Add comments for '&'.
808 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
809 (putop): Handle '&'.
810 (intel_operand_size): Handle indir_v_mode.
811 (OP_E_register): Likewise.
812 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
813 64-bit indirect call/jmp for AMD64.
814 * i386-tbl.h: Regenerated
815
4eb6f892
AB		 8162016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
817
818 * arc-dis.c (struct arc_operand_iterator): New structure.
819 (find_format_from_table): All the old content from find_format,
820 with some minor adjustments, and parameter renaming.
821 (find_format_long_instructions): New function.
822 (find_format): Rewritten.
823 (arc_insn_length): Add LSB parameter.
824 (extract_operand_value): New function.
825 (operand_iterator_next): New function.
826 (print_insn_arc): Use new functions to find opcode, and iterator
827 over operands.
828 * arc-opc.c (insert_nps_3bit_dst_short): New function.
829 (extract_nps_3bit_dst_short): New function.
830 (insert_nps_3bit_src2_short): New function.
831 (extract_nps_3bit_src2_short): New function.
832 (insert_nps_bitop1_size): New function.
833 (extract_nps_bitop1_size): New function.
834 (insert_nps_bitop2_size): New function.
835 (extract_nps_bitop2_size): New function.
836 (insert_nps_bitop_mod4_msb): New function.
837 (extract_nps_bitop_mod4_msb): New function.
838 (insert_nps_bitop_mod4_lsb): New function.
839 (extract_nps_bitop_mod4_lsb): New function.
840 (insert_nps_bitop_dst_pos3_pos4): New function.
841 (extract_nps_bitop_dst_pos3_pos4): New function.
842 (insert_nps_bitop_ins_ext): New function.
843 (extract_nps_bitop_ins_ext): New function.
844 (arc_operands): Add new operands.
845 (arc_long_opcodes): New global array.
846 (arc_num_long_opcodes): New global.
847 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
848
1fe0971e
TS		 8492016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
850
851 * nds32-asm.h: Add extern "C".
852 * sh-opc.h: Likewise.
853
315f180f
GM		 8542016-06-01 Graham Markall <graham.markall@embecosm.com>
855
856 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
857 0,b,limm to the rflt instruction.
858
a2b5fccc
TS		 8592016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
860
861 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
862 constant.
863
0cbd0046
L		 8642016-05-29 H.J. Lu <hongjiu.lu@intel.com>
865
866 PR gas/20145
867 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
868 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
869 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
870 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
871 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
872 * i386-init.h: Regenerated.
873
1848e567
L		 8742016-05-27 H.J. Lu <hongjiu.lu@intel.com>
875
876 PR gas/20145
877 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
878 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
879 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
880 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
881 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
882 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
883 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
884 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
885 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
886 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
887 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
888 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
889 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
890 CpuRegMask for AVX512.
891 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
892 and CpuRegMask.
893 (set_bitfield_from_cpu_flag_init): New function.
894 (set_bitfield): Remove const on f. Call
895 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
896 * i386-opc.h (CpuRegMMX): New.
897 (CpuRegXMM): Likewise.
898 (CpuRegYMM): Likewise.
899 (CpuRegZMM): Likewise.
900 (CpuRegMask): Likewise.
901 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
902 and cpuregmask.
903 * i386-init.h: Regenerated.
904 * i386-tbl.h: Likewise.
905
e92bae62
L		 9062016-05-27 H.J. Lu <hongjiu.lu@intel.com>
907
908 PR gas/20154
909 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
910 (opcode_modifiers): Add AMD64 and Intel64.
911 (main): Properly verify CpuMax.
912 * i386-opc.h (CpuAMD64): Removed.
913 (CpuIntel64): Likewise.
914 (CpuMax): Set to CpuNo64.
915 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
916 (AMD64): New.
917 (Intel64): Likewise.
918 (i386_opcode_modifier): Add amd64 and intel64.
919 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
920 on call and jmp.
921 * i386-init.h: Regenerated.
922 * i386-tbl.h: Likewise.
923
e89c5eaa
L		 9242016-05-27 H.J. Lu <hongjiu.lu@intel.com>
925
926 PR gas/20154
927 * i386-gen.c (main): Fail if CpuMax is incorrect.
928 * i386-opc.h (CpuMax): Set to CpuIntel64.
929 * i386-tbl.h: Regenerated.
930
77d66e7b
NC		 9312016-05-27 Nick Clifton <nickc@redhat.com>
932
933 PR target/20150
934 * msp430-dis.c (msp430dis_read_two_bytes): New function.
935 (msp430dis_opcode_unsigned): New function.
936 (msp430dis_opcode_signed): New function.
937 (msp430_singleoperand): Use the new opcode reading functions.
938 Only disassenmble bytes if they were successfully read.
939 (msp430_doubleoperand): Likewise.
940 (msp430_branchinstr): Likewise.
941 (msp430x_callx_instr): Likewise.
942 (print_insn_msp430): Check that it is safe to read bytes before
943 attempting disassembly. Use the new opcode reading functions.
944
19dfcc89
PB		 9452016-05-26 Peter Bergner <bergner@vnet.ibm.com>
946
947 * ppc-opc.c (CY): New define. Document it.
948 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
949
f3ad7637
L		 9502016-05-25 H.J. Lu <hongjiu.lu@intel.com>
951
952 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
953 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
954 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
955 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
956 CPU_ANY_AVX_FLAGS.
957 * i386-init.h: Regenerated.
958
f1360d58
L		 9592016-05-25 H.J. Lu <hongjiu.lu@intel.com>
960
961 PR gas/20141
962 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
963 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
964 * i386-init.h: Regenerated.
965
293f5f65
L		 9662016-05-25 H.J. Lu <hongjiu.lu@intel.com>
967
968 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
969 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
970 * i386-init.h: Regenerated.
971
d9eca1df
CZ		 9722016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
973
974 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
975 information.
976 (print_insn_arc): Set insn_type information.
977 * arc-opc.c (C_CC): Add F_CLASS_COND.
978 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
979 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
980 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
981 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
982 (brne, brne_s, jeq_s, jne_s): Likewise.
983
87789e08
CZ		 9842016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
985
986 * arc-tbl.h (neg): New instruction variant.
987
c810e0b8
CZ		 9882016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
989
990 * arc-dis.c (find_format, find_format, get_auxreg)
991 (print_insn_arc): Changed.
992 * arc-ext.h (INSERT_XOP): Likewise.
993
3d207518
TS		 9942016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
995
996 * tic54x-dis.c (sprint_mmr): Adjust.
997 * tic54x-opc.c: Likewise.
998
514e58b7
AM		 9992016-05-19 Alan Modra <amodra@gmail.com>
1000
1001 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1002
e43de63c
AM		 10032016-05-19 Alan Modra <amodra@gmail.com>
1004
1005 * ppc-opc.c: Formatting.
1006 (NSISIGNOPT): Define.
1007 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1008
1401d2fe
MR		 10092016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1010
1011 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1012 replacing references to `micromips_ase' throughout.
1013 (_print_insn_mips): Don't use file-level microMIPS annotation to
1014 determine the disassembly mode with the symbol table.
1015
1178da44
PB		 10162016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1017
1018 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1019
8f4f9071
MF		 10202016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1021
1022 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1023 mips64r6.
1024 * mips-opc.c (D34): New macro.
1025 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1026
8bc52696
AF		 10272016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1028
1029 * i386-dis.c (prefix_table): Add RDPID instruction.
1030 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1031 (cpu_flags): Add RDPID bitfield.
1032 * i386-opc.h (enum): Add RDPID element.
1033 (i386_cpu_flags): Add RDPID field.
1034 * i386-opc.tbl: Add RDPID instruction.
1035 * i386-init.h: Regenerate.
1036 * i386-tbl.h: Regenerate.
1037
39d911fc
TP		 10382016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1039
1040 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1041 branch type of a symbol.
1042 (print_insn): Likewise.
1043
16a1fa25
TP		 10442016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1045
1046 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1047 Mainline Security Extensions instructions.
1048 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1049 Extensions instructions.
1050 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1051 instructions.
1052 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1053 special registers.
1054
d751b79e
JM		 10552016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1056
1057 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1058
945e0f82
CZ		 10592016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1060
1061 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1062 (arcExtMap_genOpcode): Likewise.
1063 * arc-opc.c (arg_32bit_rc): Define new variable.
1064 (arg_32bit_u6): Likewise.
1065 (arg_32bit_limm): Likewise.
1066
20f55f38
SN		 10672016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1068
1069 * aarch64-gen.c (VERIFIER): Define.
1070 * aarch64-opc.c (VERIFIER): Define.
1071 (verify_ldpsw): Use static linkage.
1072 * aarch64-opc.h (verify_ldpsw): Remove.
1073 * aarch64-tbl.h: Use VERIFIER for verifiers.
1074
4bd13cde
NC		 10752016-04-28 Nick Clifton <nickc@redhat.com>
1076
1077 PR target/19722
1078 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1079 * aarch64-opc.c (verify_ldpsw): New function.
1080 * aarch64-opc.h (verify_ldpsw): New prototype.
1081 * aarch64-tbl.h: Add initialiser for verifier field.
1082 (LDPSW): Set verifier to verify_ldpsw.
1083
c0f92bf9
L		 10842016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1085
1086 PR binutils/19983
1087 PR binutils/19984
1088 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1089 smaller than address size.
1090
e6c7cdec
TS		 10912016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1092
1093 * alpha-dis.c: Regenerate.
1094 * crx-dis.c: Likewise.
1095 * disassemble.c: Likewise.
1096 * epiphany-opc.c: Likewise.
1097 * fr30-opc.c: Likewise.
1098 * frv-opc.c: Likewise.
1099 * ip2k-opc.c: Likewise.
1100 * iq2000-opc.c: Likewise.
1101 * lm32-opc.c: Likewise.
1102 * lm32-opinst.c: Likewise.
1103 * m32c-opc.c: Likewise.
1104 * m32r-opc.c: Likewise.
1105 * m32r-opinst.c: Likewise.
1106 * mep-opc.c: Likewise.
1107 * mt-opc.c: Likewise.
1108 * or1k-opc.c: Likewise.
1109 * or1k-opinst.c: Likewise.
1110 * tic80-opc.c: Likewise.
1111 * xc16x-opc.c: Likewise.
1112 * xstormy16-opc.c: Likewise.
1113
537aefaf
AB		 11142016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1115
1116 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1117 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1118 calcsd, and calcxd instructions.
1119 * arc-opc.c (insert_nps_bitop_size): Delete.
1120 (extract_nps_bitop_size): Delete.
1121 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1122 (extract_nps_qcmp_m3): Define.
1123 (extract_nps_qcmp_m2): Define.
1124 (extract_nps_qcmp_m1): Define.
1125 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1126 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1127 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1128 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1129 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1130 NPS_QCMP_M3.
1131
c8f785f2
AB		 11322016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1133
1134 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1135
6fd8e7c2
L		 11362016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1137
1138 * Makefile.in: Regenerated with automake 1.11.6.
1139 * aclocal.m4: Likewise.
1140
4b0c052e
AB		 11412016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1142
1143 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1144 instructions.
1145 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1146 (extract_nps_cmem_uimm16): New function.
1147 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1148
cb040366
AB		 11492016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1150
1151 * arc-dis.c (arc_insn_length): New function.
1152 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1153 (find_format): Change insnLen parameter to unsigned.
1154
accc0180
NC		 11552016-04-13 Nick Clifton <nickc@redhat.com>
1156
1157 PR target/19937
1158 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1159 the LD.B and LD.BU instructions.
1160
f36e33da
CZ		 11612016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1162
1163 * arc-dis.c (find_format): Check for extension flags.
1164 (print_flags): New function.
1165 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1166 .extAuxRegister.
1167 * arc-ext.c (arcExtMap_coreRegName): Use
1168 LAST_EXTENSION_CORE_REGISTER.
1169 (arcExtMap_coreReadWrite): Likewise.
1170 (dump_ARC_extmap): Update printing.
1171 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1172 (arc_aux_regs): Add cpu field.
1173 * arc-regs.h: Add cpu field, lower case name aux registers.
1174
1c2e355e
CZ		 11752016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1176
1177 * arc-tbl.h: Add rtsc, sleep with no arguments.
1178
b99747ae
CZ		 11792016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1180
1181 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1182 Initialize.
1183 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1184 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1185 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1186 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1187 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1188 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1189 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1190 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1191 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1192 (arc_opcode arc_opcodes): Null terminate the array.
1193 (arc_num_opcodes): Remove.
1194 * arc-ext.h (INSERT_XOP): Define.
1195 (extInstruction_t): Likewise.
1196 (arcExtMap_instName): Delete.
1197 (arcExtMap_insn): New function.
1198 (arcExtMap_genOpcode): Likewise.
1199 * arc-ext.c (ExtInstruction): Remove.
1200 (create_map): Zero initialize instruction fields.
1201 (arcExtMap_instName): Remove.
1202 (arcExtMap_insn): New function.
1203 (dump_ARC_extmap): More info while debuging.
1204 (arcExtMap_genOpcode): New function.
1205 * arc-dis.c (find_format): New function.
1206 (print_insn_arc): Use find_format.
1207 (arc_get_disassembler): Enable dump_ARC_extmap only when
1208 debugging.
1209
92708cec
MR		 12102016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1211
1212 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1213 instruction bits out.
1214
a42a4f84
AB		 12152016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1216
1217 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1218 * arc-opc.c (arc_flag_operands): Add new flags.
1219 (arc_flag_classes): Add new classes.
1220
1328504b
AB		 12212016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1222
1223 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1224
820f03ff
AB		 12252016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1226
1227 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1228 encode1, rflt, crc16, and crc32 instructions.
1229 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1230 (arc_flag_classes): Add C_NPS_R.
1231 (insert_nps_bitop_size_2b): New function.
1232 (extract_nps_bitop_size_2b): Likewise.
1233 (insert_nps_bitop_uimm8): Likewise.
1234 (extract_nps_bitop_uimm8): Likewise.
1235 (arc_operands): Add new operand entries.
1236
8ddf6b2a
CZ		 12372016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1238
b99747ae
CZ		 1239 * arc-regs.h: Add a new subclass field. Add double assist
1240 accumulator register values.
1241 * arc-tbl.h: Use DPA subclass to mark the double assist
1242 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1243 * arc-opc.c (RSP): Define instead of SP.
1244 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1245
589a7d88
JW		 12462016-04-05 Jiong Wang <jiong.wang@arm.com>
1247
1248 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1249
0a191de9 12502016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1251
1252 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1253 NPS_R_SRC1.
1254
0a106562
AB		 12552016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1256
1257 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1258 issues. No functional changes.
1259
bd05ac5f
CZ		 12602016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1261
b99747ae
CZ		 1262 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1263 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1264 (RTT): Remove duplicate.
1265 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1266 (PCT_CONFIG*): Remove.
1267 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1268
9885948f
CZ		 12692016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1270
b99747ae 1271 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1272
f2dd8838
CZ		 12732016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1274
b99747ae
CZ		 1275 * arc-tbl.h (invld07): Remove.
1276 * arc-ext-tbl.h: New file.
1277 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1278 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1279
0d2f91fe
JK		 12802016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1281
1282 Fix -Wstack-usage warnings.
1283 * aarch64-dis.c (print_operands): Substitute size.
1284 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1285
a6b71f42
JM		 12862016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1287
1288 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1289 to get a proper diagnostic when an invalid ASR register is used.
1290
9780e045
NC		 12912016-03-22 Nick Clifton <nickc@redhat.com>
1292
1293 * configure: Regenerate.
1294
e23e8ebe
AB		 12952016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1296
1297 * arc-nps400-tbl.h: New file.
1298 * arc-opc.c: Add top level comment.
1299 (insert_nps_3bit_dst): New function.
1300 (extract_nps_3bit_dst): New function.
1301 (insert_nps_3bit_src2): New function.
1302 (extract_nps_3bit_src2): New function.
1303 (insert_nps_bitop_size): New function.
1304 (extract_nps_bitop_size): New function.
1305 (arc_flag_operands): Add nps400 entries.
1306 (arc_flag_classes): Add nps400 entries.
1307 (arc_operands): Add nps400 entries.
1308 (arc_opcodes): Add nps400 include.
1309
1ae8ab47
AB		 13102016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1311
1312 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1313 the new class enum values.
1314
8699fc3e
AB		 13152016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1316
1317 * arc-dis.c (print_insn_arc): Handle nps400.
1318
24740d83
AB		 13192016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1320
1321 * arc-opc.c (BASE): Delete.
1322
8678914f
NC		 13232016-03-18 Nick Clifton <nickc@redhat.com>
1324
1325 PR target/19721
1326 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1327 of MOV insn that aliases an ORR insn.
1328
cc933301
JW		 13292016-03-16 Jiong Wang <jiong.wang@arm.com>
1330
1331 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1332
f86f5863
TS		 13332016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1334
1335 * mcore-opc.h: Add const qualifiers.
1336 * microblaze-opc.h (struct op_code_struct): Likewise.
1337 * sh-opc.h: Likewise.
1338 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1339 (tic4x_print_op): Likewise.
1340
62de1c63
AM		 13412016-03-02 Alan Modra <amodra@gmail.com>
1342
d11698cd 1343 * or1k-desc.h: Regenerate.
62de1c63 1344 * fr30-ibld.c: Regenerate.
c697cf0b 1345 * rl78-decode.c: Regenerate.
62de1c63 1346
020efce5
NC		 13472016-03-01 Nick Clifton <nickc@redhat.com>
1348
1349 PR target/19747
1350 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1351
b0c11777
RL		 13522016-02-24 Renlin Li <renlin.li@arm.com>
1353
1354 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1355 (print_insn_coprocessor): Support fp16 instructions.
1356
3e309328
RL		 13572016-02-24 Renlin Li <renlin.li@arm.com>
1358
1359 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1360 vminnm, vrint(mpna).
1361
8afc7bea
RL		 13622016-02-24 Renlin Li <renlin.li@arm.com>
1363
1364 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1365 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1366
4fd7268a
L		 13672016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1368
1369 * i386-dis.c (print_insn): Parenthesize expression to prevent
1370 truncated addresses.
1371 (OP_J): Likewise.
1372
4670103e
CZ		 13732016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1374 Janek van Oirschot <jvanoirs@synopsys.com>
1375
b99747ae
CZ		 1376 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1377 variable.
4670103e 1378
c1d9289f
NC		 13792016-02-04 Nick Clifton <nickc@redhat.com>
1380
1381 PR target/19561
1382 * msp430-dis.c (print_insn_msp430): Add a special case for
1383 decoding an RRC instruction with the ZC bit set in the extension
1384 word.
1385
a143b004
AB		 13862016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1387
1388 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1389 * epiphany-ibld.c: Regenerate.
1390 * fr30-ibld.c: Regenerate.
1391 * frv-ibld.c: Regenerate.
1392 * ip2k-ibld.c: Regenerate.
1393 * iq2000-ibld.c: Regenerate.
1394 * lm32-ibld.c: Regenerate.
1395 * m32c-ibld.c: Regenerate.
1396 * m32r-ibld.c: Regenerate.
1397 * mep-ibld.c: Regenerate.
1398 * mt-ibld.c: Regenerate.
1399 * or1k-ibld.c: Regenerate.
1400 * xc16x-ibld.c: Regenerate.
1401 * xstormy16-ibld.c: Regenerate.
1402
b89807c6
AB		 14032016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1404
1405 * epiphany-dis.c: Regenerated from latest cpu files.
1406
d8c823c8
MM		 14072016-02-01 Michael McConville <mmcco@mykolab.com>
1408
1409 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1410 test bit.
1411
5bc5ae88
RL		 14122016-01-25 Renlin Li <renlin.li@arm.com>
1413
1414 * arm-dis.c (mapping_symbol_for_insn): New function.
1415 (find_ifthen_state): Call mapping_symbol_for_insn().
1416
0bff6e2d
MW		 14172016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1418
1419 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1420 of MSR UAO immediate operand.
1421
100b4f2e
MR		 14222016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1423
1424 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1425 instruction support.
1426
5c14705f
AM		 14272016-01-17 Alan Modra <amodra@gmail.com>
1428
1429 * configure: Regenerate.
1430
4d82fe66
NC		 14312016-01-14 Nick Clifton <nickc@redhat.com>
1432
1433 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1434 instructions that can support stack pointer operations.
1435 * rl78-decode.c: Regenerate.
1436 * rl78-dis.c: Fix display of stack pointer in MOVW based
1437 instructions.
1438
651657fa
MW		 14392016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1440
1441 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1442 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1443 erxtatus_el1 and erxaddr_el1.
1444
105bde57
MW		 14452016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1446
1447 * arm-dis.c (arm_opcodes): Add "esb".
1448 (thumb_opcodes): Likewise.
1449
afa8d405
PB		 14502016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1451
1452 * ppc-opc.c <xscmpnedp>: Delete.
1453 <xvcmpnedp>: Likewise.
1454 <xvcmpnedp.>: Likewise.
1455 <xvcmpnesp>: Likewise.
1456 <xvcmpnesp.>: Likewise.
1457
83c3256e
AS		 14582016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1459
1460 PR gas/13050
1461 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1462 addition to ISA_A.
1463
6f2750fe
AM		 14642016-01-01 Alan Modra <amodra@gmail.com>
1465
1466 Update year range in copyright notice of all files.
1467
3499769a
AM		 1468For older changes see ChangeLog-2015
1469\f
1470Copyright (C) 2016 Free Software Foundation, Inc.
1471
1472Copying and distribution of this file, with or without modification,
1473are permitted in any medium without royalty provided the copyright
1474notice and this notice are preserved.
1475
1476Local Variables:
1477mode: change-log
1478left-margin: 8
1479fill-column: 74
1480version-control: never
1481End:
GDB Binutils - Deliverables
This page took 0.118701 seconds and 4 git commands to generate.