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[AArch64] Fix errors rebasing the ARMv8.2 AT and system registers patch
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
63511907
MW		 12015-12-14 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
4 removed statement.
5 (aarch64_pstatefield_supported_p): Move feature checks for AT
6 registers ..
7 (aarch64_sys_ins_reg_supported_p): .. to here.
8
b817670b
AM		 92015-12-12 Alan Modra <amodra@gmail.com>
10
11 PR 19359
12 * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
13 (powerpc_opcodes): Remove single-operand mfcr.
14
9ed608f9
MW		 152015-12-11 Matthew Wahab <matthew.wahab@arm.com>
16
17 * aarch64-asm.c (aarch64_ins_hint): New.
18 * aarch64-asm.h (aarch64_ins_hint): Declare.
19 * aarch64-dis.c (aarch64_ext_hint): New.
20 * aarch64-dis.h (aarch64_ext_hint): Declare.
21 * aarch64-opc-2.c: Regenerate.
22 * aarch64-opc.c (aarch64_hint_options): New.
23 * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
24
a0f7013a
MW		 252015-12-11 Matthew Wahab <matthew.wahab@arm.com>
26
27 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
28
55c144e6
MW		 292015-12-11 Matthew Wahab <matthew.wahab@arm.com>
30
31 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
32 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
33 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
34 pmscr_el2.
35 (aarch64_sys_reg_supported_p): Add architecture feature tests for
36 the new registers.
37
22a5455c
MW		 382015-12-10 Matthew Wahab <matthew.wahab@arm.com>
39
40 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
41 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
42 feature test for "s1e1rp" and "s1e1wp".
43
d6bf7ce6
MW		 442015-12-10 Matthew Wahab <matthew.wahab@arm.com>
45
46 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
47 (aarch64_sys_ins_reg_supported_p): New.
48
ea2deeec
MW		 492015-12-10 Matthew Wahab <matthew.wahab@arm.com>
50
51 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
52 with aarch64_sys_ins_reg_has_xt.
53 (aarch64_ext_sysins_op): Likewise.
54 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
55 (F_HASXT): New.
56 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
57 (aarch64_sys_regs_dc): Likewise.
58 (aarch64_sys_regs_at): Likewise.
59 (aarch64_sys_regs_tlbi): Likewise.
60 (aarch64_sys_ins_reg_has_xt): New.
61
6479e48e
MW		 622015-12-10 Matthew Wahab <matthew.wahab@arm.com>
63
64 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
65 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
66 (aarch64_pstatefields): Add "uao".
67 (aarch64_pstatefield_supported_p): Add checks for "uao".
68
47f81142
MW		 692015-12-10 Matthew Wahab <matthew.wahab@arm.com>
70
71 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
72 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
73 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
74 (aarch64_sys_reg_supported_p): Add architecture feature tests for
75 new registers.
76
c8a6db6f
MW		 772015-12-10 Matthew Wahab <matthew.wahab@arm.com>
78
79 * aarch64-asm-2.c: Regenerate.
80 * aarch64-dis-2.c: Regenerate.
81 * aarch64-tbl.h (aarch64_feature_ras): New.
82 (RAS): New.
83 (aarch64_opcode_table): Add "esb".
84
8eab4136
L		 852015-12-09 H.J. Lu <hongjiu.lu@intel.com>
86
87 * i386-dis.c (MOD_0F01_REG_5): New.
88 (RM_0F01_REG_5): Likewise.
89 (reg_table): Use MOD_0F01_REG_5.
90 (mod_table): Add MOD_0F01_REG_5.
91 (rm_table): Add RM_0F01_REG_5.
92 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
93 (cpu_flags): Add CpuOSPKE.
94 * i386-opc.h (CpuOSPKE): New.
95 (i386_cpu_flags): Add cpuospke.
96 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
97 * i386-init.h: Regenerated.
98 * i386-tbl.h: Likewise.
99
1eac08cc
DD		 1002015-12-07 DJ Delorie <dj@redhat.com>
101
102 * rl78-decode.opc: Enable MULU for all ISAs.
103 * rl78-decode.c: Regenerate.
104
dd2887fc
AM		 1052015-12-07 Alan Modra <amodra@gmail.com>
106
107 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
108 major opcode/xop.
109
24b368f8
CZ		 1102015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
111
112 * arc-dis.c (special_flag_p): Match full mnemonic.
113 * arc-opc.c (print_insn_arc): Check section size to read
114 appropriate number of bytes. Fix printing.
115 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
116 arguments.
117
3395762e
AV		 1182015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
119
120 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
121 <ldah>: ... to this.
122
622b9eb1
MW		 1232015-11-27 Matthew Wahab <matthew.wahab@arm.com>
124
125 * aarch64-asm-2.c: Regenerate.
126 * aarch64-dis-2.c: Regenerate.
127 * aarch64-opc-2.c: Regenerate.
128 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
129 (QL_INT2FP_H, QL_FP2INT_H): New.
130 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
131 (QL_DST_H): New.
132 (QL_FCCMP_H): New.
133 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
134 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
135 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
136 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
137 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
138 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
139 fcsel.
140
cf86120b
MW		 1412015-11-27 Matthew Wahab <matthew.wahab@arm.com>
142
143 * aarch64-opc.c (half_conv_t): New.
144 (expand_fp_imm): Replace is_dp flag with the parameter size to
145 specify the number of bytes for the required expansion. Treat
146 a 16-bit expansion like a 32-bit expansion. Add check for an
147 unsupported size request. Update comment.
148 (aarch64_print_operand): Update to support 16-bit floating point
149 values. Update for changes to expand_fp_imm.
150
3bd894a7
MW		 1512015-11-27 Matthew Wahab <matthew.wahab@arm.com>
152
153 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
154 (FP_F16): New.
155
64357d2e
MW		 1562015-11-27 Matthew Wahab <matthew.wahab@arm.com>
157
158 * aarch64-asm-2.c: Regenerate.
159 * aarch64-dis-2.c: Regenerate.
160 * aarch64-opc-2.c: Regenerate.
161 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
162 "rev64".
163
d685192a
MW		 1642015-11-27 Matthew Wahab <matthew.wahab@arm.com>
165
166 * aarch64-asm-2.c: Regenerate.
167 * aarch64-asm.c (convert_bfc_to_bfm): New.
168 (convert_to_real): Add case for OP_BFC.
169 * aarch64-dis-2.c: Regenerate.
170 * aarch64-dis.c: (convert_bfm_to_bfc): New.
171 (convert_to_alias): Add case for OP_BFC.
172 * aarch64-opc-2.c: Regenerate.
173 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
174 to allow width operand in three-operand instructions.
175 * aarch64-tbl.h (QL_BF1): New.
176 (aarch64_feature_v8_2): New.
177 (ARMV8_2): New.
178 (aarch64_opcode_table): Add "bfc".
179
35822b38
MW		 1802015-11-27 Matthew Wahab <matthew.wahab@arm.com>
181
182 * aarch64-asm-2.c: Regenerate.
183 * aarch64-dis-2.c: Regenerate.
184 * aarch64-dis.c: Weaken assert.
185 * aarch64-gen.c: Include the instruction in the list of its
186 possible aliases.
187
1a04d1a7
MW		 1882015-11-27 Matthew Wahab <matthew.wahab@arm.com>
189
190 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
191 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
192 feature test.
193
e49d43ff
TG		 1942015-11-23 Tristan Gingold <gingold@adacore.com>
195
196 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
197
250aafa4
MW		 1982015-11-20 Matthew Wahab <matthew.wahab@arm.com>
199
200 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
201 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
202 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
203 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
204 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
205 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
206 cnthv_ctl_el2, cnthv_cval_el2.
207 (aarch64_sys_reg_supported_p): Update for the new system
208 registers.
209
a915c10f
NC		 2102015-11-20 Nick Clifton <nickc@redhat.com>
211
212 PR binutils/19224
213 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
214
f8c2a965
NC		 2152015-11-20 Nick Clifton <nickc@redhat.com>
216
217 * po/zh_CN.po: Updated simplified Chinese translation.
218
c2825638
MW		 2192015-11-19 Matthew Wahab <matthew.wahab@arm.com>
220
221 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
222 of MSR PAN immediate operand.
223
e7286c56
NC		 2242015-11-16 Nick Clifton <nickc@redhat.com>
225
226 * rx-dis.c (condition_names): Replace always and never with
227 invalid, since the always/never conditions can never be legal.
228
d8bd95ef
TG		 2292015-11-13 Tristan Gingold <gingold@adacore.com>
230
231 * configure: Regenerate.
232
a680de9a
PB		 2332015-11-11 Alan Modra <amodra@gmail.com>
234 Peter Bergner <bergner@vnet.ibm.com>
235
236 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
237 Add PPC_OPCODE_VSX3 to the vsx entry.
238 (powerpc_init_dialect): Set default dialect to power9.
239 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
240 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
241 extract_l1 insert_xtq6, extract_xtq6): New static functions.
242 (insert_esync): Test for illegal L operand value.
243 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
244 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
245 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
246 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
247 PPCVSX3): New defines.
248 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
249 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
250 <mcrxr>: Use XBFRARB_MASK.
251 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
252 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
253 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
254 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
255 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
256 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
257 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
258 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
259 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
260 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
261 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
262 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
263 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
264 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
265 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
266 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
267 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
268 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
269 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
270 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
271 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
272 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
273 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
274 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
275 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
276 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
277 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
278 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
279 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
280 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
281 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
282 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
283
854eb72b
NC		 2842015-11-02 Nick Clifton <nickc@redhat.com>
285
286 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
287 instructions.
288 * rx-decode.c: Regenerate.
289
e292aa7a
NC		 2902015-11-02 Nick Clifton <nickc@redhat.com>
291
292 * rx-decode.opc (rx_disp): If the displacement is zero, set the
293 type to RX_Operand_Zero_Indirect.
294 * rx-decode.c: Regenerate.
295 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
296
43cdf5ae
YQ		 2972015-10-28 Yao Qi <yao.qi@linaro.org>
298
299 * aarch64-dis.c (aarch64_decode_insn): Add one argument
300 noaliases_p. Update comments. Pass noaliases_p rather than
301 no_aliases to aarch64_opcode_decode.
302 (print_insn_aarch64_word): Pass no_aliases to
303 aarch64_decode_insn.
304
c2f28758
VK		 3052015-10-27 Vinay <Vinay.G@kpit.com>
306
307 PR binutils/19159
308 * rl78-decode.opc (MOV): Added offset to DE register in index
309 addressing mode.
310 * rl78-decode.c: Regenerate.
311
46662804
VK		 3122015-10-27 Vinay Kumar <vinay.g@kpit.com>
313
314 PR binutils/19158
315 * rl78-decode.opc: Add 's' print operator to instructions that
316 access system registers.
317 * rl78-decode.c: Regenerate.
318 * rl78-dis.c (print_insn_rl78_common): Decode all system
319 registers.
320
02f12cd4
VK		 3212015-10-27 Vinay Kumar <vinay.g@kpit.com>
322
323 PR binutils/19157
324 * rl78-decode.opc: Add 'a' print operator to mov instructions
325 using stack pointer plus index addressing.
326 * rl78-decode.c: Regenerate.
327
485f23cf
AK		 3282015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
329
330 * s390-opc.c: Fix comment.
331 * s390-opc.txt: Change instruction type for troo, trot, trto, and
332 trtt to RRF_U0RER since the second parameter does not need to be a
333 register pair.
334
3f94e60d
NC		 3352015-10-08 Nick Clifton <nickc@redhat.com>
336
337 * arc-dis.c (print_insn_arc): Initiallise insn array.
338
875880c6
YQ		 3392015-10-07 Yao Qi <yao.qi@linaro.org>
340
341 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
342 'name' rather than 'template'.
343 * aarch64-opc.c (aarch64_print_operand): Likewise.
344
886a2506
NC		 3452015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
346
347 * arc-dis.c: Revamped file for ARC support
348 * arc-dis.h: Likewise.
349 * arc-ext.c: Likewise.
350 * arc-ext.h: Likewise.
351 * arc-opc.c: Likewise.
352 * arc-fxi.h: New file.
353 * arc-regs.h: Likewise.
354 * arc-tbl.h: Likewise.
355
36f4aab1
YQ		 3562015-10-02 Yao Qi <yao.qi@linaro.org>
357
358 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
359 argument insn type to aarch64_insn. Rename to ...
360 (aarch64_decode_insn): ... it.
361 (print_insn_aarch64_word): Caller updated.
362
7232d389
YQ		 3632015-10-02 Yao Qi <yao.qi@linaro.org>
364
365 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
366 (print_insn_aarch64_word): Caller updated.
367
7ecc513a
DV		 3682015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
369
370 * s390-mkopc.c (main): Parse htm and vx flag.
371 * s390-opc.txt: Mark instructions from the hardware transactional
372 memory and vector facilities with the "htm"/"vx" flag.
373
b08b78e7
NC		 3742015-09-28 Nick Clifton <nickc@redhat.com>
375
376 * po/de.po: Updated German translation.
377
36f7a941
TR		 3782015-09-28 Tom Rix <tom@bumblecow.com>
379
380 * ppc-opc.c (PPC500): Mark some opcodes as invalid
381
b6518b38
NC		 3822015-09-23 Nick Clifton <nickc@redhat.com>
383
384 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
385 function.
386 * tic30-dis.c (print_branch): Likewise.
387 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
388 value before left shifting.
389 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
390 * hppa-dis.c (print_insn_hppa): Likewise.
391 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
392 array.
393 * msp430-dis.c (msp430_singleoperand): Likewise.
394 (msp430_doubleoperand): Likewise.
395 (print_insn_msp430): Likewise.
396 * nds32-asm.c (parse_operand): Likewise.
397 * sh-opc.h (MASK): Likewise.
398 * v850-dis.c (get_operand_value): Likewise.
399
f04265ec
NC		 4002015-09-22 Nick Clifton <nickc@redhat.com>
401
402 * rx-decode.opc (bwl): Use RX_Bad_Size.
403 (sbwl): Likewise.
404 (ubwl): Likewise. Rename to ubw.
405 (uBWL): Rename to uBW.
406 Replace all references to uBWL with uBW.
407 * rx-decode.c: Regenerate.
408 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
409 (opsize_names): Likewise.
410 (print_insn_rx): Detect and report RX_Bad_Size.
411
6dca4fd1
AB		 4122015-09-22 Anton Blanchard <anton@samba.org>
413
414 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
415
38074311
JM		 4162015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
417
418 * sparc-dis.c (print_insn_sparc): Handle the privileged register
419 %pmcdper.
420
5f40e14d
JS		 4212015-08-24 Jan Stancek <jstancek@redhat.com>
422
423 * i386-dis.c (print_insn): Fix decoding of three byte operands.
424
ab4e4ed5
AF		 4252015-08-21 Alexander Fomin <alexander.fomin@intel.com>
426
427 PR binutils/18257
428 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
429 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
430 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
431 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
432 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
433 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
434 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
435 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
436 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
437 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
438 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
439 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
440 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
441 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
442 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
443 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
444 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
445 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
446 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
447 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
448 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
449 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
450 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
451 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
452 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
453 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
454 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
455 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
456 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
457 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
458 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
459 (vex_w_table): Replace terminals with MOD_TABLE entries for
460 most of mask instructions.
461
919b75f7
AM		 4622015-08-17 Alan Modra <amodra@gmail.com>
463
464 * cgen.sh: Trim trailing space from cgen output.
465 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
466 (print_dis_table): Likewise.
467 * opc2c.c (dump_lines): Likewise.
468 (orig_filename): Warning fix.
469 * ia64-asmtab.c: Regenerate.
470
4ab90a7a
AV		 4712015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
472
473 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
474 and higher with ARM instruction set will now mark the 26-bit
475 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
476 (arm_opcodes): Fix for unpredictable nop being recognized as a
477 teq.
478
40fc1451
SD		 4792015-08-12 Simon Dardis <simon.dardis@imgtec.com>
480
481 * micromips-opc.c (micromips_opcodes): Re-order table so that move
482 based on 'or' is first.
483 * mips-opc.c (mips_builtin_opcodes): Ditto.
484
922c5db5
NC		 4852015-08-11 Nick Clifton <nickc@redhat.com>
486
487 PR 18800
488 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
489 instruction.
490
75fb7498
RS		 4912015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
492
493 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
494
36aed29d
AP		 4952015-08-07 Amit Pawar <Amit.Pawar@amd.com>
496
497 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
498 * i386-init.h: Regenerated.
499
a8484f96
L		 5002015-07-30 H.J. Lu <hongjiu.lu@intel.com>
501
502 PR binutils/13571
503 * i386-dis.c (MOD_0FC3): New.
504 (PREFIX_0FC3): Renamed to ...
505 (PREFIX_MOD_0_0FC3): This.
506 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
507 (prefix_table): Replace Ma with Ev on movntiS.
508 (mod_table): Add MOD_0FC3.
509
37a42ee9
L		 5102015-07-27 H.J. Lu <hongjiu.lu@intel.com>
511
512 * configure: Regenerated.
513
070fe95d
AM		 5142015-07-23 Alan Modra <amodra@gmail.com>
515
516 PR 18708
517 * i386-dis.c (get64): Avoid signed integer overflow.
518
20c2a615
L		 5192015-07-22 Alexander Fomin <alexander.fomin@intel.com>
520
521 PR binutils/18631
522 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
523 "EXEvexHalfBcstXmmq" for the second operand.
524 (EVEX_W_0F79_P_2): Likewise.
525 (EVEX_W_0F7A_P_2): Likewise.
526 (EVEX_W_0F7B_P_2): Likewise.
527
6f1c2142
AM		 5282015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
529
530 * arm-dis.c (print_insn_coprocessor): Added support for quarter
531 float bitfield format.
532 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
533 quarter float bitfield format.
534
8a643cc3
L		 5352015-07-14 H.J. Lu <hongjiu.lu@intel.com>
536
537 * configure: Regenerated.
538
ef5a96d5
AM		 5392015-07-03 Alan Modra <amodra@gmail.com>
540
541 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
542 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
543 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
544
c8c8175b
SL		 5452015-07-01 Sandra Loosemore <sandra@codesourcery.com>
546 Cesar Philippidis <cesar@codesourcery.com>
547
548 * nios2-dis.c (nios2_extract_opcode): New.
549 (nios2_disassembler_state): New.
550 (nios2_find_opcode_hash): Use mach parameter to select correct
551 disassembler state.
552 (nios2_print_insn_arg): Extend to support new R2 argument letters
553 and formats.
554 (print_insn_nios2): Check for 16-bit instruction at end of memory.
555 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
556 (NIOS2_NUM_OPCODES): Rename to...
557 (NIOS2_NUM_R1_OPCODES): This.
558 (nios2_r2_opcodes): New.
559 (NIOS2_NUM_R2_OPCODES): New.
560 (nios2_num_r2_opcodes): New.
561 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
562 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
563 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
564 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
565 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
566
9916071f
AP		 5672015-06-30 Amit Pawar <Amit.Pawar@amd.com>
568
569 * i386-dis.c (OP_Mwaitx): New.
570 (rm_table): Add monitorx/mwaitx.
571 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
572 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
573 (operand_type_init): Add CpuMWAITX.
574 * i386-opc.h (CpuMWAITX): New.
575 (i386_cpu_flags): Add cpumwaitx.
576 * i386-opc.tbl: Add monitorx and mwaitx.
577 * i386-init.h: Regenerated.
578 * i386-tbl.h: Likewise.
579
7b934113
PB		 5802015-06-22 Peter Bergner <bergner@vnet.ibm.com>
581
582 * ppc-opc.c (insert_ls): Test for invalid LS operands.
583 (insert_esync): New function.
584 (LS, WC): Use insert_ls.
585 (ESYNC): Use insert_esync.
586
bdc4de1b
NC		 5872015-06-22 Nick Clifton <nickc@redhat.com>
588
589 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
590 requested region lies beyond it.
591 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
592 looking for 32-bit insns.
593 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
594 data.
595 * sh-dis.c (print_insn_sh): Likewise.
596 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
597 blocks of instructions.
598 * vax-dis.c (print_insn_vax): Check that the requested address
599 does not clash with the stop_vma.
600
11a0cf2e
PB		 6012015-06-19 Peter Bergner <bergner@vnet.ibm.com>
602
070fe95d 603 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 604 * ppc-opc.c (FXM4): Add non-zero optional value.
605 (TBR): Likewise.
606 (SXL): Likewise.
607 (insert_fxm): Handle new default operand value.
608 (extract_fxm): Likewise.
609 (insert_tbr): Likewise.
610 (extract_tbr): Likewise.
611
bdfa8b95
MW		 6122015-06-16 Matthew Wahab <matthew.wahab@arm.com>
613
614 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
615
24b4cf66
SN		 6162015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
617
618 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
619
99a2c561
PB		 6202015-06-12 Peter Bergner <bergner@vnet.ibm.com>
621
622 * ppc-opc.c: Add comment accidentally removed by old commit.
623 (MTMSRD_L): Delete.
624
40f77f82
AM		 6252015-06-04 Peter Bergner <bergner@vnet.ibm.com>
626
627 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
628
13be46a2
NC		 6292015-06-04 Nick Clifton <nickc@redhat.com>
630
631 PR 18474
632 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
633
ddfded2f
MW		 6342015-06-02 Matthew Wahab <matthew.wahab@arm.com>
635
636 * arm-dis.c (arm_opcodes): Add "setpan".
637 (thumb_opcodes): Add "setpan".
638
1af1dd51
MW		 6392015-06-02 Matthew Wahab <matthew.wahab@arm.com>
640
641 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
642 macros.
643
9e1f0fa7
MW		 6442015-06-02 Matthew Wahab <matthew.wahab@arm.com>
645
646 * aarch64-tbl.h (aarch64_feature_rdma): New.
647 (RDMA): New.
648 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
649 * aarch64-asm-2.c: Regenerate.
650 * aarch64-dis-2.c: Regenerate.
651 * aarch64-opc-2.c: Regenerate.
652
290806fd
MW		 6532015-06-02 Matthew Wahab <matthew.wahab@arm.com>
654
655 * aarch64-tbl.h (aarch64_feature_lor): New.
656 (LOR): New.
657 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
658 "stllrb", "stllrh".
659 * aarch64-asm-2.c: Regenerate.
660 * aarch64-dis-2.c: Regenerate.
661 * aarch64-opc-2.c: Regenerate.
662
f21cce2c
MW		 6632015-06-01 Matthew Wahab <matthew.wahab@arm.com>
664
665 * aarch64-opc.c (F_ARCHEXT): New.
666 (aarch64_sys_regs): Add "pan".
667 (aarch64_sys_reg_supported_p): New.
668 (aarch64_pstatefields): Add "pan".
669 (aarch64_pstatefield_supported_p): New.
670
d194d186
JB		 6712015-06-01 Jan Beulich <jbeulich@suse.com>
672
673 * i386-tbl.h: Regenerate.
674
3a8547d2
JB		 6752015-06-01 Jan Beulich <jbeulich@suse.com>
676
677 * i386-dis.c (print_insn): Swap rounding mode specifier and
678 general purpose register in Intel mode.
679
015c54d5
JB		 6802015-06-01 Jan Beulich <jbeulich@suse.com>
681
682 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
683 * i386-tbl.h: Regenerate.
684
071f0063
L		 6852015-05-18 H.J. Lu <hongjiu.lu@intel.com>
686
687 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
688 * i386-init.h: Regenerated.
689
5db04b09
L		 6902015-05-15 H.J. Lu <hongjiu.lu@intel.com>
691
692 PR binutis/18386
693 * i386-dis.c: Add comments for '@'.
694 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
695 (enum x86_64_isa): New.
696 (isa64): Likewise.
697 (print_i386_disassembler_options): Add amd64 and intel64.
698 (print_insn): Handle amd64 and intel64.
699 (putop): Handle '@'.
700 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
701 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
702 * i386-opc.h (AMD64): New.
703 (CpuIntel64): Likewise.
704 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
705 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
706 Mark direct call/jmp without Disp16|Disp32 as Intel64.
707 * i386-init.h: Regenerated.
708 * i386-tbl.h: Likewise.
709
4bc0608a
PB		 7102015-05-14 Peter Bergner <bergner@vnet.ibm.com>
711
712 * ppc-opc.c (IH) New define.
713 (powerpc_opcodes) <wait>: Do not enable for POWER7.
714 <tlbie>: Add RS operand for POWER7.
715 <slbia>: Add IH operand for POWER6.
716
70cead07
L		 7172015-05-11 H.J. Lu <hongjiu.lu@intel.com>
718
719 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
720 direct branch.
721 (jmp): Likewise.
722 * i386-tbl.h: Regenerated.
723
7b6d09fb
L		 7242015-05-11 H.J. Lu <hongjiu.lu@intel.com>
725
726 * configure.ac: Support bfd_iamcu_arch.
727 * disassemble.c (disassembler): Support bfd_iamcu_arch.
728 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
729 CPU_IAMCU_COMPAT_FLAGS.
730 (cpu_flags): Add CpuIAMCU.
731 * i386-opc.h (CpuIAMCU): New.
732 (i386_cpu_flags): Add cpuiamcu.
733 * configure: Regenerated.
734 * i386-init.h: Likewise.
735 * i386-tbl.h: Likewise.
736
31955f99
L		 7372015-05-08 H.J. Lu <hongjiu.lu@intel.com>
738
739 PR binutis/18386
740 * i386-dis.c (X86_64_E8): New.
741 (X86_64_E9): Likewise.
742 Update comments on 'T', 'U', 'V'. Add comments for '^'.
743 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
744 (x86_64_table): Add X86_64_E8 and X86_64_E9.
745 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
746 (putop): Handle '^'.
747 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
748 REX_W.
749
0952813b
DD		 7502015-04-30 DJ Delorie <dj@redhat.com>
751
752 * disassemble.c (disassembler): Choose suitable disassembler based
753 on E_ABI.
754 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
755 it to decode mul/div insns.
756 * rl78-decode.c: Regenerate.
757 * rl78-dis.c (print_insn_rl78): Rename to...
758 (print_insn_rl78_common): ...this, take ISA parameter.
759 (print_insn_rl78): New.
760 (print_insn_rl78_g10): New.
761 (print_insn_rl78_g13): New.
762 (print_insn_rl78_g14): New.
763 (rl78_get_disassembler): New.
764
f9d3ecaa
NC		 7652015-04-29 Nick Clifton <nickc@redhat.com>
766
767 * po/fr.po: Updated French translation.
768
4fff86c5
PB		 7692015-04-27 Peter Bergner <bergner@vnet.ibm.com>
770
771 * ppc-opc.c (DCBT_EO): New define.
772 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
773 <lharx>: Likewise.
774 <stbcx.>: Likewise.
775 <sthcx.>: Likewise.
776 <waitrsv>: Do not enable for POWER7 and later.
777 <waitimpl>: Likewise.
778 <dcbt>: Default to the two operand form of the instruction for all
779 "old" cpus. For "new" cpus, use the operand ordering that matches
780 whether the cpu is server or embedded.
781 <dcbtst>: Likewise.
782
3b78cfe1
AK		 7832015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
784
785 * s390-opc.c: New instruction type VV0UU2.
786 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
787 and WFC.
788
04d824a4
JB		 7892015-04-23 Jan Beulich <jbeulich@suse.com>
790
791 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
792 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
793 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
794 (vfpclasspd, vfpclassps): Add %XZ.
795
09708981
L		 7962015-04-15 H.J. Lu <hongjiu.lu@intel.com>
797
798 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
799 (PREFIX_UD_REPZ): Likewise.
800 (PREFIX_UD_REPNZ): Likewise.
801 (PREFIX_UD_DATA): Likewise.
802 (PREFIX_UD_ADDR): Likewise.
803 (PREFIX_UD_LOCK): Likewise.
804
3888916d
L		 8052015-04-15 H.J. Lu <hongjiu.lu@intel.com>
806
807 * i386-dis.c (prefix_requirement): Removed.
808 (print_insn): Don't set prefix_requirement. Check
809 dp->prefix_requirement instead of prefix_requirement.
810
f24bcbaa
L		 8112015-04-15 H.J. Lu <hongjiu.lu@intel.com>
812
813 PR binutils/17898
814 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
815 (PREFIX_MOD_0_0FC7_REG_6): This.
816 (PREFIX_MOD_3_0FC7_REG_6): New.
817 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
818 (prefix_table): Replace PREFIX_0FC7_REG_6 with
819 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
820 PREFIX_MOD_3_0FC7_REG_7.
821 (mod_table): Replace PREFIX_0FC7_REG_6 with
822 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
823 PREFIX_MOD_3_0FC7_REG_7.
824
507bd325
L		 8252015-04-15 H.J. Lu <hongjiu.lu@intel.com>
826
827 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
828 (PREFIX_MANDATORY_REPNZ): Likewise.
829 (PREFIX_MANDATORY_DATA): Likewise.
830 (PREFIX_MANDATORY_ADDR): Likewise.
831 (PREFIX_MANDATORY_LOCK): Likewise.
832 (PREFIX_MANDATORY): Likewise.
833 (PREFIX_UD_SHIFT): Set to 8
834 (PREFIX_UD_REPZ): Updated.
835 (PREFIX_UD_REPNZ): Likewise.
836 (PREFIX_UD_DATA): Likewise.
837 (PREFIX_UD_ADDR): Likewise.
838 (PREFIX_UD_LOCK): Likewise.
839 (PREFIX_IGNORED_SHIFT): New.
840 (PREFIX_IGNORED_REPZ): Likewise.
841 (PREFIX_IGNORED_REPNZ): Likewise.
842 (PREFIX_IGNORED_DATA): Likewise.
843 (PREFIX_IGNORED_ADDR): Likewise.
844 (PREFIX_IGNORED_LOCK): Likewise.
845 (PREFIX_OPCODE): Likewise.
846 (PREFIX_IGNORED): Likewise.
847 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
848 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
849 (three_byte_table): Likewise.
850 (mod_table): Likewise.
851 (mandatory_prefix): Renamed to ...
852 (prefix_requirement): This.
853 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
854 Update PREFIX_90 entry.
855 (get_valid_dis386): Check prefix_requirement to see if a prefix
856 should be ignored.
857 (print_insn): Replace mandatory_prefix with prefix_requirement.
858
f0fba320
RL		 8592015-04-15 Renlin Li <renlin.li@arm.com>
860
861 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
862 use it for ssat and ssat16.
863 (print_insn_thumb32): Add handle case for 'D' control code.
864
bf890a93
IT		 8652015-04-06 Ilya Tocar <ilya.tocar@intel.com>
866 H.J. Lu <hongjiu.lu@intel.com>
867
868 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
869 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
870 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
871 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
872 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
873 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
874 Fill prefix_requirement field.
875 (struct dis386): Add prefix_requirement field.
876 (dis386): Fill prefix_requirement field.
877 (dis386_twobyte): Ditto.
878 (twobyte_has_mandatory_prefix_: Remove.
879 (reg_table): Fill prefix_requirement field.
880 (prefix_table): Ditto.
881 (x86_64_table): Ditto.
882 (three_byte_table): Ditto.
883 (xop_table): Ditto.
884 (vex_table): Ditto.
885 (vex_len_table): Ditto.
886 (vex_w_table): Ditto.
887 (mod_table): Ditto.
888 (bad_opcode): Ditto.
889 (print_insn): Use prefix_requirement.
890 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
891 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
892 (float_reg): Ditto.
893
2f783c1f
MF		 8942015-03-30 Mike Frysinger <vapier@gentoo.org>
895
896 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
897
b9d94d62
L		 8982015-03-29 H.J. Lu <hongjiu.lu@intel.com>
899
900 * Makefile.in: Regenerated.
901
27c49e9a
AB		 9022015-03-25 Anton Blanchard <anton@samba.org>
903
904 * ppc-dis.c (disassemble_init_powerpc): Only initialise
905 powerpc_opcd_indices and vle_opcd_indices once.
906
c4e676f1
AB		 9072015-03-25 Anton Blanchard <anton@samba.org>
908
909 * ppc-opc.c (powerpc_opcodes): Add slbfee.
910
823d2571
TG		 9112015-03-24 Terry Guo <terry.guo@arm.com>
912
913 * arm-dis.c (opcode32): Updated to use new arm feature struct.
914 (opcode16): Likewise.
915 (coprocessor_opcodes): Replace bit with feature struct.
916 (neon_opcodes): Likewise.
917 (arm_opcodes): Likewise.
918 (thumb_opcodes): Likewise.
919 (thumb32_opcodes): Likewise.
920 (print_insn_coprocessor): Likewise.
921 (print_insn_arm): Likewise.
922 (select_arm_features): Follow new feature struct.
923
029f3522
GG		 9242015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
925
926 * i386-dis.c (rm_table): Add clzero.
927 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
928 Add CPU_CLZERO_FLAGS.
929 (cpu_flags): Add CpuCLZERO.
930 * i386-opc.h: Add CpuCLZERO.
931 * i386-opc.tbl: Add clzero.
932 * i386-init.h: Re-generated.
933 * i386-tbl.h: Re-generated.
934
6914869a
AB		 9352015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
936
937 * mips-opc.c (decode_mips_operand): Fix constraint issues
938 with u and y operands.
939
21e20815
AB		 9402015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
941
942 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
943
6b1d7593
AK		 9442015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
945
946 * s390-opc.c: Add new IBM z13 instructions.
947 * s390-opc.txt: Likewise.
948
c8f89a34
JW		 9492015-03-10 Renlin Li <renlin.li@arm.com>
950
951 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
952 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
953 related alias.
954 * aarch64-asm-2.c: Regenerate.
955 * aarch64-dis-2.c: Likewise.
956 * aarch64-opc-2.c: Likewise.
957
d8282f0e
JW		 9582015-03-03 Jiong Wang <jiong.wang@arm.com>
959
960 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
961
ac994365
OE		 9622015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
963
964 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
965 arch_sh_up.
966 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
967 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
968
fd63f640
V		 9692015-02-23 Vinay <Vinay.G@kpit.com>
970
971 * rl78-decode.opc (MOV): Added space between two operands for
972 'mov' instruction in index addressing mode.
973 * rl78-decode.c: Regenerate.
974
f63c1776
PA		 9752015-02-19 Pedro Alves <palves@redhat.com>
976
977 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
978
07774fcc
PA		 9792015-02-10 Pedro Alves <palves@redhat.com>
980 Tom Tromey <tromey@redhat.com>
981
982 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
983 microblaze_and, microblaze_xor.
984 * microblaze-opc.h (opcodes): Adjust.
985
3f8107ab
AM		 9862015-01-28 James Bowman <james.bowman@ftdichip.com>
987
988 * Makefile.am: Add FT32 files.
989 * configure.ac: Handle FT32.
990 * disassemble.c (disassembler): Call print_insn_ft32.
991 * ft32-dis.c: New file.
992 * ft32-opc.c: New file.
993 * Makefile.in: Regenerate.
994 * configure: Regenerate.
995 * po/POTFILES.in: Regenerate.
996
e5fe4957
KLC		 9972015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
998
999 * nds32-asm.c (keyword_sr): Add new system registers.
1000
1e2e8c52
AK		 10012015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1002
1003 * s390-dis.c (s390_extract_operand): Support vector register
1004 operands.
1005 (s390_print_insn_with_opcode): Support new operands types and add
1006 new handling of optional operands.
1007 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1008 and include opcode/s390.h instead.
1009 (struct op_struct): New field `flags'.
1010 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1011 (dumpTable): Dump flags.
1012 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
1013 string.
1014 * s390-opc.c: Add new operands types, instruction formats, and
1015 instruction masks.
1016 (s390_opformats): Add new formats for .insn.
1017 * s390-opc.txt: Add new instructions.
1018
b90efa5b 10192015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 1020
b90efa5b 1021 Update year range in copyright notice of all files.
bffb6004 1022
b90efa5b 1023For older changes see ChangeLog-2014
252b5132 1024\f
b90efa5b 1025Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 1026
1027Copying and distribution of this file, with or without modification,
1028are permitted in any medium without royalty provided the copyright
1029notice and this notice are preserved.
1030
252b5132 1031Local Variables:
2f6d2f85
NC		 1032mode: change-log
1033left-margin: 8
1034fill-column: 74
252b5132
RH		 1035version-control: never
1036End:
GDB Binutils - Deliverables
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