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Make sure that undefined symbols added to the linker command line via the -u option...
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
fe4e2a3c
IT		 12017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2
3 * i386-init.h: Regenerate
4 * i386-tbl.h: Likewise
5
2a6969e1
EB		 62017-10-18 Eric Botcazou <ebotcazou@adacore.com>
7
8 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
9
3b4b0a62
JB		 102017-10-12 James Bowman <james.bowman@ftdichip.com>
11
12 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
13 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
14 K15. Add jmpix pattern.
15
8e464506
AK		 162017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
17
18 * s390-opc.txt (prno, tpei, irbm): New instructions added.
19
ee6767da
AK		 202017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
21
22 * s390-opc.c (INSTR_SI_RD): New macro.
23 (INSTR_S_RD): Adjust example instruction.
24 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
25 SI_RD.
26
d2e6c9a3
AF		 272017-10-01 Alexander Fedotov <alfedotov@gmail.com>
28
29 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
30 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
31 VLE multimple load/store instructions. Old e_ldm* variants are
32 kept as aliases.
33 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
34
8e43602e
NC		 352017-09-27 Nick Clifton <nickc@redhat.com>
36
37 PR 22179
38 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
39 names for the fmv.x.s and fmv.s.x instructions respectively.
40
58a0b827
NC		 412017-09-26 do <do@nerilex.org>
42
43 PR 22123
44 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
45 be used on CPUs that have emacs support.
46
57a024f4
SDJ		 472017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
48
49 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
50
4ec521f2
KLC		 512017-09-09 Kamil Rytarowski <n54@gmx.com>
52
53 * nds32-asm.c: Rename __BIT() to N32_BIT().
54 * nds32-asm.h: Likewise.
55 * nds32-dis.c: Likewise.
56
4e9ac44a
L		 572017-09-09 H.J. Lu <hongjiu.lu@intel.com>
58
59 * i386-dis.c (last_active_prefix): Removed.
60 (ckprefix): Don't set last_active_prefix.
61 (NOTRACK_Fixup): Don't check last_active_prefix.
62
b55f3386
NC		 632017-08-31 Nick Clifton <nickc@redhat.com>
64
65 * po/fr.po: Updated French translation.
66
59e8523b
JB		 672017-08-31 James Bowman <james.bowman@ftdichip.com>
68
69 * ft32-dis.c (print_insn_ft32): Correct display of non-address
70 fields.
71
74081948
AF		 722017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
73 Edmar Wienskoski <edmar.wienskoski@nxp.com>
74
75 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
76 PPC_OPCODE_EFS2 flag to "e200z4" entry.
77 New entries efs2 and spe2.
78 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
79 (SPE2_OPCD_SEGS): New macro.
80 (spe2_opcd_indices): New.
81 (disassemble_init_powerpc): Handle SPE2 opcodes.
82 (lookup_spe2): New function.
83 (print_insn_powerpc): call lookup_spe2.
84 * ppc-opc.c (insert_evuimm1_ex0): New function.
85 (extract_evuimm1_ex0): Likewise.
86 (insert_evuimm_lt8): Likewise.
87 (extract_evuimm_lt8): Likewise.
88 (insert_off_spe2): Likewise.
89 (extract_off_spe2): Likewise.
90 (insert_Ddd): Likewise.
91 (extract_Ddd): Likewise.
92 (DD): New operand.
93 (EVUIMM_LT8): Likewise.
94 (EVUIMM_LT16): Adjust.
95 (MMMM): New operand.
96 (EVUIMM_1): Likewise.
97 (EVUIMM_1_EX0): Likewise.
98 (EVUIMM_2): Adjust.
99 (NNN): New operand.
100 (VX_OFF_SPE2): Likewise.
101 (BBB): Likewise.
102 (DDD): Likewise.
103 (VX_MASK_DDD): New mask.
104 (HH): New operand.
105 (VX_RA_CONST): New macro.
106 (VX_RA_CONST_MASK): Likewise.
107 (VX_RB_CONST): Likewise.
108 (VX_RB_CONST_MASK): Likewise.
109 (VX_OFF_SPE2_MASK): Likewise.
110 (VX_SPE_CRFD): Likewise.
111 (VX_SPE_CRFD_MASK VX): Likewise.
112 (VX_SPE2_CLR): Likewise.
113 (VX_SPE2_CLR_MASK): Likewise.
114 (VX_SPE2_SPLATB): Likewise.
115 (VX_SPE2_SPLATB_MASK): Likewise.
116 (VX_SPE2_OCTET): Likewise.
117 (VX_SPE2_OCTET_MASK): Likewise.
118 (VX_SPE2_DDHH): Likewise.
119 (VX_SPE2_DDHH_MASK): Likewise.
120 (VX_SPE2_HH): Likewise.
121 (VX_SPE2_HH_MASK): Likewise.
122 (VX_SPE2_EVMAR): Likewise.
123 (VX_SPE2_EVMAR_MASK): Likewise.
124 (PPCSPE2): Likewise.
125 (PPCEFS2): Likewise.
126 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
127 (powerpc_macros): Map old SPE instructions have new names
128 with the same opcodes. Add SPE2 instructions which just are
129 mapped to SPE2.
130 (spe2_opcodes): Add SPE2 opcodes.
131
b80c7270
AM		 1322017-08-23 Alan Modra <amodra@gmail.com>
133
134 * ppc-opc.c: Formatting and comment fixes. Move insert and
135 extract functions earlier, deleting forward declarations.
136 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
137 RA_MASK.
138
67d888f5
PD		 1392017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
140
141 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
142
e3c2f928
AF		 1432017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
144 Edmar Wienskoski <edmar.wienskoski@nxp.com>
145
146 * ppc-opc.c (insert_evuimm2_ex0): New function.
147 (extract_evuimm2_ex0): Likewise.
148 (insert_evuimm4_ex0): Likewise.
149 (extract_evuimm4_ex0): Likewise.
150 (insert_evuimm8_ex0): Likewise.
151 (extract_evuimm8_ex0): Likewise.
152 (insert_evuimm_lt16): Likewise.
153 (extract_evuimm_lt16): Likewise.
154 (insert_rD_rS_even): Likewise.
155 (extract_rD_rS_even): Likewise.
156 (insert_off_lsp): Likewise.
157 (extract_off_lsp): Likewise.
158 (RD_EVEN): New operand.
159 (RS_EVEN): Likewise.
160 (RSQ): Adjust.
161 (EVUIMM_LT16): New operand.
162 (HTM_SI): Adjust.
163 (EVUIMM_2_EX0): New operand.
164 (EVUIMM_4): Adjust.
165 (EVUIMM_4_EX0): New operand.
166 (EVUIMM_8): Adjust.
167 (EVUIMM_8_EX0): New operand.
168 (WS): Adjust.
169 (VX_OFF): New operand.
170 (VX_LSP): New macro.
171 (VX_LSP_MASK): Likewise.
172 (VX_LSP_OFF_MASK): Likewise.
173 (PPC_OPCODE_LSP): Likewise.
174 (vle_opcodes): Add LSP opcodes.
175 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
176
cc4a945a
JW		 1772017-08-09 Jiong Wang <jiong.wang@arm.com>
178
179 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
180 register operands in CRC instructions.
181 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
182 comments.
183
b28b8b5e
L		 1842017-08-07 H.J. Lu <hongjiu.lu@intel.com>
185
186 * disassemble.c (disassembler): Mark big and mach with
187 ATTRIBUTE_UNUSED.
188
e347efc3
MR		 1892017-08-07 Maciej W. Rozycki <macro@imgtec.com>
190
191 * disassemble.c (disassembler): Remove arch/mach/endian
192 assertions.
193
7cbc739c
NC		 1942017-07-25 Nick Clifton <nickc@redhat.com>
195
196 PR 21739
197 * arc-opc.c (insert_rhv2): Use lower case first letter in error
198 message.
199 (insert_r0): Likewise.
200 (insert_r1): Likewise.
201 (insert_r2): Likewise.
202 (insert_r3): Likewise.
203 (insert_sp): Likewise.
204 (insert_gp): Likewise.
205 (insert_pcl): Likewise.
206 (insert_blink): Likewise.
207 (insert_ilink1): Likewise.
208 (insert_ilink2): Likewise.
209 (insert_ras): Likewise.
210 (insert_rbs): Likewise.
211 (insert_rcs): Likewise.
212 (insert_simm3s): Likewise.
213 (insert_rrange): Likewise.
214 (insert_r13el): Likewise.
215 (insert_fpel): Likewise.
216 (insert_blinkel): Likewise.
217 (insert_pclel): Likewise.
218 (insert_nps_bitop_size_2b): Likewise.
219 (insert_nps_imm_offset): Likewise.
220 (insert_nps_imm_entry): Likewise.
221 (insert_nps_size_16bit): Likewise.
222 (insert_nps_##NAME##_pos): Likewise.
223 (insert_nps_##NAME): Likewise.
224 (insert_nps_bitop_ins_ext): Likewise.
225 (insert_nps_##NAME): Likewise.
226 (insert_nps_min_hofs): Likewise.
227 (insert_nps_##NAME): Likewise.
228 (insert_nps_rbdouble_64): Likewise.
229 (insert_nps_misc_imm_offset): Likewise.
230 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
231 option description.
232
7684e580
JW		 2332017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
234 Jiong Wang <jiong.wang@arm.com>
235
236 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
237 correct the print.
238 * aarch64-dis-2.c: Regenerated.
239
47826cdb
AK		 2402017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
241
242 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
243 table.
244
2d2dbad0
NC		 2452017-07-20 Nick Clifton <nickc@redhat.com>
246
247 * po/de.po: Updated German translation.
248
70b448ba 2492017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
250
251 * arc-regs.h (sec_stat): New aux register.
252 (aux_kernel_sp): Likewise.
253 (aux_sec_u_sp): Likewise.
254 (aux_sec_k_sp): Likewise.
255 (sec_vecbase_build): Likewise.
256 (nsc_table_top): Likewise.
257 (nsc_table_base): Likewise.
258 (ersec_stat): Likewise.
259 (aux_sec_except): Likewise.
260
7179e0e6
CZ		 2612017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
262
263 * arc-opc.c (extract_uimm12_20): New function.
264 (UIMM12_20): New operand.
265 (SIMM3_5_S): Adjust.
266 * arc-tbl.h (sjli): Add new instruction.
267
684d5a10
JEM		 2682017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
269 John Eric Martin <John.Martin@emmicro-us.com>
270
271 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
272 (UIMM3_23): Adjust accordingly.
273 * arc-regs.h: Add/correct jli_base register.
274 * arc-tbl.h (jli_s): Likewise.
275
de194d85
YC		 2762017-07-18 Nick Clifton <nickc@redhat.com>
277
278 PR 21775
279 * aarch64-opc.c: Fix spelling typos.
280 * i386-dis.c: Likewise.
281
0f6329bd
RB		 2822017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
283
284 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
285 max_addr_offset and octets variables to size_t.
286
429d795d
AM		 2872017-07-12 Alan Modra <amodra@gmail.com>
288
289 * po/da.po: Update from translationproject.org/latest/opcodes/.
290 * po/de.po: Likewise.
291 * po/es.po: Likewise.
292 * po/fi.po: Likewise.
293 * po/fr.po: Likewise.
294 * po/id.po: Likewise.
295 * po/it.po: Likewise.
296 * po/nl.po: Likewise.
297 * po/pt_BR.po: Likewise.
298 * po/ro.po: Likewise.
299 * po/sv.po: Likewise.
300 * po/tr.po: Likewise.
301 * po/uk.po: Likewise.
302 * po/vi.po: Likewise.
303 * po/zh_CN.po: Likewise.
304
4162bb66
AM		 3052017-07-11 Yao Qi <yao.qi@linaro.org>
306 Alan Modra <amodra@gmail.com>
307
308 * cgen.sh: Mark generated files read-only.
309 * epiphany-asm.c: Regenerate.
310 * epiphany-desc.c: Regenerate.
311 * epiphany-desc.h: Regenerate.
312 * epiphany-dis.c: Regenerate.
313 * epiphany-ibld.c: Regenerate.
314 * epiphany-opc.c: Regenerate.
315 * epiphany-opc.h: Regenerate.
316 * fr30-asm.c: Regenerate.
317 * fr30-desc.c: Regenerate.
318 * fr30-desc.h: Regenerate.
319 * fr30-dis.c: Regenerate.
320 * fr30-ibld.c: Regenerate.
321 * fr30-opc.c: Regenerate.
322 * fr30-opc.h: Regenerate.
323 * frv-asm.c: Regenerate.
324 * frv-desc.c: Regenerate.
325 * frv-desc.h: Regenerate.
326 * frv-dis.c: Regenerate.
327 * frv-ibld.c: Regenerate.
328 * frv-opc.c: Regenerate.
329 * frv-opc.h: Regenerate.
330 * ip2k-asm.c: Regenerate.
331 * ip2k-desc.c: Regenerate.
332 * ip2k-desc.h: Regenerate.
333 * ip2k-dis.c: Regenerate.
334 * ip2k-ibld.c: Regenerate.
335 * ip2k-opc.c: Regenerate.
336 * ip2k-opc.h: Regenerate.
337 * iq2000-asm.c: Regenerate.
338 * iq2000-desc.c: Regenerate.
339 * iq2000-desc.h: Regenerate.
340 * iq2000-dis.c: Regenerate.
341 * iq2000-ibld.c: Regenerate.
342 * iq2000-opc.c: Regenerate.
343 * iq2000-opc.h: Regenerate.
344 * lm32-asm.c: Regenerate.
345 * lm32-desc.c: Regenerate.
346 * lm32-desc.h: Regenerate.
347 * lm32-dis.c: Regenerate.
348 * lm32-ibld.c: Regenerate.
349 * lm32-opc.c: Regenerate.
350 * lm32-opc.h: Regenerate.
351 * lm32-opinst.c: Regenerate.
352 * m32c-asm.c: Regenerate.
353 * m32c-desc.c: Regenerate.
354 * m32c-desc.h: Regenerate.
355 * m32c-dis.c: Regenerate.
356 * m32c-ibld.c: Regenerate.
357 * m32c-opc.c: Regenerate.
358 * m32c-opc.h: Regenerate.
359 * m32r-asm.c: Regenerate.
360 * m32r-desc.c: Regenerate.
361 * m32r-desc.h: Regenerate.
362 * m32r-dis.c: Regenerate.
363 * m32r-ibld.c: Regenerate.
364 * m32r-opc.c: Regenerate.
365 * m32r-opc.h: Regenerate.
366 * m32r-opinst.c: Regenerate.
367 * mep-asm.c: Regenerate.
368 * mep-desc.c: Regenerate.
369 * mep-desc.h: Regenerate.
370 * mep-dis.c: Regenerate.
371 * mep-ibld.c: Regenerate.
372 * mep-opc.c: Regenerate.
373 * mep-opc.h: Regenerate.
374 * mt-asm.c: Regenerate.
375 * mt-desc.c: Regenerate.
376 * mt-desc.h: Regenerate.
377 * mt-dis.c: Regenerate.
378 * mt-ibld.c: Regenerate.
379 * mt-opc.c: Regenerate.
380 * mt-opc.h: Regenerate.
381 * or1k-asm.c: Regenerate.
382 * or1k-desc.c: Regenerate.
383 * or1k-desc.h: Regenerate.
384 * or1k-dis.c: Regenerate.
385 * or1k-ibld.c: Regenerate.
386 * or1k-opc.c: Regenerate.
387 * or1k-opc.h: Regenerate.
388 * or1k-opinst.c: Regenerate.
389 * xc16x-asm.c: Regenerate.
390 * xc16x-desc.c: Regenerate.
391 * xc16x-desc.h: Regenerate.
392 * xc16x-dis.c: Regenerate.
393 * xc16x-ibld.c: Regenerate.
394 * xc16x-opc.c: Regenerate.
395 * xc16x-opc.h: Regenerate.
396 * xstormy16-asm.c: Regenerate.
397 * xstormy16-desc.c: Regenerate.
398 * xstormy16-desc.h: Regenerate.
399 * xstormy16-dis.c: Regenerate.
400 * xstormy16-ibld.c: Regenerate.
401 * xstormy16-opc.c: Regenerate.
402 * xstormy16-opc.h: Regenerate.
403
7639175c
AM		 4042017-07-07 Alan Modra <amodra@gmail.com>
405
406 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
407 * m32c-dis.c: Regenerate.
408 * mep-dis.c: Regenerate.
409
e4bdd679
BP		 4102017-07-05 Borislav Petkov <bp@suse.de>
411
412 * i386-dis.c: Enable ModRM.reg /6 aliases.
413
60c96dbf
RR		 4142017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
415
416 * opcodes/arm-dis.c: Support MVFR2 in disassembly
417 with vmrs and vmsr.
418
0d702cfe
TG		 4192017-07-04 Tristan Gingold <gingold@adacore.com>
420
421 * configure: Regenerate.
422
15e6ed8c
TG		 4232017-07-03 Tristan Gingold <gingold@adacore.com>
424
425 * po/opcodes.pot: Regenerate.
426
b1d3c886
MR		 4272017-06-30 Maciej W. Rozycki <macro@imgtec.com>
428
429 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
430 entries to the MSA ASE instruction block.
431
909b4e3d
MR		 4322017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
433 Maciej W. Rozycki <macro@imgtec.com>
434
435 * micromips-opc.c (XPA, XPAVZ): New macros.
436 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
437 "mthgc0".
438
f5b2fd52
MR		 4392017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
440 Maciej W. Rozycki <macro@imgtec.com>
441
442 * micromips-opc.c (I36): New macro.
443 (micromips_opcodes): Add "eretnc".
444
9785fc2a
MR		 4452017-06-30 Maciej W. Rozycki <macro@imgtec.com>
446 Andrew Bennett <andrew.bennett@imgtec.com>
447
448 * mips-dis.c (mips_calculate_combination_ases): Handle the
449 ASE_XPA_VIRT flag.
450 (parse_mips_ase_option): New function.
451 (parse_mips_dis_option): Factor out ASE option handling to the
452 new function. Call `mips_calculate_combination_ases'.
453 * mips-opc.c (XPAVZ): New macro.
454 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
455 "mfhgc0", "mthc0" and "mthgc0".
456
60804c53
MR		 4572017-06-29 Maciej W. Rozycki <macro@imgtec.com>
458
459 * mips-dis.c (mips_calculate_combination_ases): New function.
460 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
461 calculation to the new function.
462 (set_default_mips_dis_options): Call the new function.
463
2e74f9dd
AK		 4642017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
465
466 * arc-dis.c (parse_disassembler_options): Use
467 FOR_EACH_DISASSEMBLER_OPTION.
468
e1e94c49
AK		 4692017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
470
471 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
472 disassembler option strings.
473 (parse_cpu_option): Likewise.
474
65a55fbb
TC		 4752017-06-28 Tamar Christina <tamar.christina@arm.com>
476
477 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
478 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
479 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
480 (aarch64_feature_dotprod, DOT_INSN): New.
481 (udot, sdot): New.
482 * aarch64-dis-2.c: Regenerated.
483
c604a79a
JW		 4842017-06-28 Jiong Wang <jiong.wang@arm.com>
485
486 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
487
38bf472a
MR		 4882017-06-28 Maciej W. Rozycki <macro@imgtec.com>
489 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 490 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 491
492 * mips-formats.h (INT_BIAS): New macro.
493 (INT_ADJ): Redefine in INT_BIAS terms.
494 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
495 (mips_print_save_restore): New function.
496 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
497 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
498 call.
499 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
500 (print_mips16_insn_arg): Call `mips_print_save_restore' for
501 OP_SAVE_RESTORE_LIST handling, factored out from here.
502 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
503 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
504 (mips_builtin_opcodes): Add "restore" and "save" entries.
505 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
506 (IAMR2): New macro.
507 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
508
9bdfdbf9
AW		 5092017-06-23 Andrew Waterman <andrew@sifive.com>
510
511 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
512 alias; do not mark SLTI instruction as an alias.
513
2234eee6
L		 5142017-06-21 H.J. Lu <hongjiu.lu@intel.com>
515
516 * i386-dis.c (RM_0FAE_REG_5): Removed.
517 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
518 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
519 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
520 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
521 PREFIX_MOD_3_0F01_REG_5_RM_0.
522 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
523 PREFIX_MOD_3_0FAE_REG_5.
524 (mod_table): Update MOD_0FAE_REG_5.
525 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
526 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
527 * i386-tbl.h: Regenerated.
528
c2f76402
L		 5292017-06-21 H.J. Lu <hongjiu.lu@intel.com>
530
531 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
532 * i386-opc.tbl: Likewise.
533 * i386-tbl.h: Regenerated.
534
9fef80d6
L		 5352017-06-21 H.J. Lu <hongjiu.lu@intel.com>
536
537 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
538 and "jmp{&|}".
539 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
540 prefix.
541
0f6d864d
NC		 5422017-06-19 Nick Clifton <nickc@redhat.com>
543
544 PR binutils/21614
545 * score-dis.c (score_opcodes): Add sentinel.
546
e197589b
AM		 5472017-06-16 Alan Modra <amodra@gmail.com>
548
549 * rx-decode.c: Regenerate.
550
0d96e4df
L		 5512017-06-15 H.J. Lu <hongjiu.lu@intel.com>
552
553 PR binutils/21594
554 * i386-dis.c (OP_E_register): Check valid bnd register.
555 (OP_G): Likewise.
556
cd3ea7c6
NC		 5572017-06-15 Nick Clifton <nickc@redhat.com>
558
559 PR binutils/21595
560 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
561 range value.
562
63323b5b
NC		 5632017-06-15 Nick Clifton <nickc@redhat.com>
564
565 PR binutils/21588
566 * rl78-decode.opc (OP_BUF_LEN): Define.
567 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
568 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
569 array.
570 * rl78-decode.c: Regenerate.
571
08c7881b
NC		 5722017-06-15 Nick Clifton <nickc@redhat.com>
573
574 PR binutils/21586
575 * bfin-dis.c (gregs): Clip index to prevent overflow.
576 (regs): Likewise.
577 (regs_lo): Likewise.
578 (regs_hi): Likewise.
579
e64519d1
NC		 5802017-06-14 Nick Clifton <nickc@redhat.com>
581
582 PR binutils/21576
583 * score7-dis.c (score_opcodes): Add sentinel.
584
6394c606
YQ		 5852017-06-14 Yao Qi <yao.qi@linaro.org>
586
587 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
588 * arm-dis.c: Likewise.
589 * ia64-dis.c: Likewise.
590 * mips-dis.c: Likewise.
591 * spu-dis.c: Likewise.
592 * disassemble.h (print_insn_aarch64): New declaration, moved from
593 include/dis-asm.h.
594 (print_insn_big_arm, print_insn_big_mips): Likewise.
595 (print_insn_i386, print_insn_ia64): Likewise.
596 (print_insn_little_arm, print_insn_little_mips): Likewise.
597
db5fa770
NC		 5982017-06-14 Nick Clifton <nickc@redhat.com>
599
600 PR binutils/21587
601 * rx-decode.opc: Include libiberty.h
602 (GET_SCALE): New macro - validates access to SCALE array.
603 (GET_PSCALE): New macro - validates access to PSCALE array.
604 (DIs, SIs, S2Is, rx_disp): Use new macros.
605 * rx-decode.c: Regenerate.
606
05c966f3
AV		 6072017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
608
609 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
610
10045478
AK		 6112017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
612
613 * arc-dis.c (enforced_isa_mask): Declare.
614 (cpu_types): Likewise.
615 (parse_cpu_option): New function.
616 (parse_disassembler_options): Use it.
617 (print_insn_arc): Use enforced_isa_mask.
618 (print_arc_disassembler_options): Document new options.
619
88c1242d
YQ		 6202017-05-24 Yao Qi <yao.qi@linaro.org>
621
622 * alpha-dis.c: Include disassemble.h, don't include
623 dis-asm.h.
624 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
625 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
626 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
627 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
628 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
629 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
630 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
631 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
632 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
633 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
634 * moxie-dis.c, msp430-dis.c, mt-dis.c:
635 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
636 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
637 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
638 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
639 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
640 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
641 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
642 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
643 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
644 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
645 * z80-dis.c, z8k-dis.c: Likewise.
646 * disassemble.h: New file.
647
ab20fa4a
YQ		 6482017-05-24 Yao Qi <yao.qi@linaro.org>
649
650 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
651 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
652
003ca0fd
YQ		 6532017-05-24 Yao Qi <yao.qi@linaro.org>
654
655 * disassemble.c (disassembler): Add arguments a, big and mach.
656 Use them.
657
04ef582a
L		 6582017-05-22 H.J. Lu <hongjiu.lu@intel.com>
659
660 * i386-dis.c (NOTRACK_Fixup): New.
661 (NOTRACK): Likewise.
662 (NOTRACK_PREFIX): Likewise.
663 (last_active_prefix): Likewise.
664 (reg_table): Use NOTRACK on indirect call and jmp.
665 (ckprefix): Set last_active_prefix.
666 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
667 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
668 * i386-opc.h (NoTrackPrefixOk): New.
669 (i386_opcode_modifier): Add notrackprefixok.
670 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
671 Add notrack.
672 * i386-tbl.h: Regenerated.
673
64517994
JM		 6742017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
675
676 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
677 (X_IMM2): Define.
678 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
679 bfd_mach_sparc_v9m8.
680 (print_insn_sparc): Handle new operand types.
681 * sparc-opc.c (MASK_M8): Define.
682 (v6): Add MASK_M8.
683 (v6notlet): Likewise.
684 (v7): Likewise.
685 (v8): Likewise.
686 (v9): Likewise.
687 (v9a): Likewise.
688 (v9b): Likewise.
689 (v9c): Likewise.
690 (v9d): Likewise.
691 (v9e): Likewise.
692 (v9v): Likewise.
693 (v9m): Likewise.
694 (v9andleon): Likewise.
695 (m8): Define.
696 (HWS_VM8): Define.
697 (HWS2_VM8): Likewise.
698 (sparc_opcode_archs): Add entry for "m8".
699 (sparc_opcodes): Add OSA2017 and M8 instructions
700 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
701 fpx{ll,ra,rl}64x,
702 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
703 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
704 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
705 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
706 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
707 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
708 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
709 ASI_CORE_SELECT_COMMIT_NHT.
710
535b785f
AM		 7112017-05-18 Alan Modra <amodra@gmail.com>
712
713 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
714 * aarch64-dis.c: Likewise.
715 * aarch64-gen.c: Likewise.
716 * aarch64-opc.c: Likewise.
717
25499ac7
MR		 7182017-05-15 Maciej W. Rozycki <macro@imgtec.com>
719 Matthew Fortune <matthew.fortune@imgtec.com>
720
721 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
722 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
723 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
724 (print_insn_arg) <OP_REG28>: Add handler.
725 (validate_insn_args) <OP_REG28>: Handle.
726 (print_mips16_insn_arg): Handle MIPS16 instructions that require
727 32-bit encoding and 9-bit immediates.
728 (print_insn_mips16): Handle MIPS16 instructions that require
729 32-bit encoding and MFC0/MTC0 operand decoding.
730 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
731 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
732 (RD_C0, WR_C0, E2, E2MT): New macros.
733 (mips16_opcodes): Add entries for MIPS16e2 instructions:
734 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
735 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
736 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
737 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
738 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
739 instructions, "swl", "swr", "sync" and its "sync_acquire",
740 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
741 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
742 regular/extended entries for original MIPS16 ISA revision
743 instructions whose extended forms are subdecoded in the MIPS16e2
744 ISA revision: "li", "sll" and "srl".
745
fdfb4752
MR		 7462017-05-15 Maciej W. Rozycki <macro@imgtec.com>
747
748 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
749 reference in CP0 move operand decoding.
750
a4f89915
MR		 7512017-05-12 Maciej W. Rozycki <macro@imgtec.com>
752
753 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
754 type to hexadecimal.
755 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
756
99e2d67a
MR		 7572017-05-11 Maciej W. Rozycki <macro@imgtec.com>
758
759 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
760 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
761 "sync_rmb" and "sync_wmb" as aliases.
762 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
763 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
764
53a346d8
CZ		 7652017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
766
767 * arc-dis.c (parse_option): Update quarkse_em option..
768 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
769 QUARKSE1.
770 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
771
f91d48de
KC		 7722017-05-03 Kito Cheng <kito.cheng@gmail.com>
773
774 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
775
43e379d7
MC		 7762017-05-01 Michael Clark <michaeljclark@mac.com>
777
778 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
779 register.
780
a4ddc54e
MR		 7812017-05-02 Maciej W. Rozycki <macro@imgtec.com>
782
783 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
784 and branches and not synthetic data instructions.
785
fe50e98c
BE		 7862017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
787
788 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
789
126124cc
CZ		 7902017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
791
792 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
793 * arc-opc.c (insert_r13el): New function.
794 (R13_EL): Define.
795 * arc-tbl.h: Add new enter/leave variants.
796
be6a24d8
CZ		 7972017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
798
799 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
800
0348fd79
MR		 8012017-04-25 Maciej W. Rozycki <macro@imgtec.com>
802
803 * mips-dis.c (print_mips_disassembler_options): Add
804 `no-aliases'.
805
6e3d1f07
MR		 8062017-04-25 Maciej W. Rozycki <macro@imgtec.com>
807
808 * mips16-opc.c (AL): New macro.
809 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
810 of "ld" and "lw" as aliases.
811
957f6b39
TC		 8122017-04-24 Tamar Christina <tamar.christina@arm.com>
813
814 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
815 arguments.
816
a8cc8a54
AM		 8172017-04-22 Alexander Fedotov <alfedotov@gmail.com>
818 Alan Modra <amodra@gmail.com>
819
820 * ppc-opc.c (ELEV): Define.
821 (vle_opcodes): Add se_rfgi and e_sc.
822 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
823 for E200Z4.
824
3ab87b68
JM		 8252017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
826
827 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
828
792f174f
NC		 8292017-04-21 Nick Clifton <nickc@redhat.com>
830
831 PR binutils/21380
832 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
833 LD3R and LD4R.
834
42742084
AM		 8352017-04-13 Alan Modra <amodra@gmail.com>
836
837 * epiphany-desc.c: Regenerate.
838 * fr30-desc.c: Regenerate.
839 * frv-desc.c: Regenerate.
840 * ip2k-desc.c: Regenerate.
841 * iq2000-desc.c: Regenerate.
842 * lm32-desc.c: Regenerate.
843 * m32c-desc.c: Regenerate.
844 * m32r-desc.c: Regenerate.
845 * mep-desc.c: Regenerate.
846 * mt-desc.c: Regenerate.
847 * or1k-desc.c: Regenerate.
848 * xc16x-desc.c: Regenerate.
849 * xstormy16-desc.c: Regenerate.
850
9a85b496
AM		 8512017-04-11 Alan Modra <amodra@gmail.com>
852
ef85eab0 853 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 854 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
855 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 856 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
857 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 858 (PPCVSX2): Define as PPC_OPCODE_POWER8.
859 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 860 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 861 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 862
62adc510
AM		 8632017-04-10 Alan Modra <amodra@gmail.com>
864
865 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
866 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
867 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
868 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
869
aa808707
PC		 8702017-04-09 Pip Cet <pipcet@gmail.com>
871
872 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
873 appropriate floating-point precision directly.
874
ac8f0f72
AM		 8752017-04-07 Alan Modra <amodra@gmail.com>
876
877 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
878 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
879 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
880 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
881 vector instructions with E6500 not PPCVEC2.
882
62ecb94c
PC		 8832017-04-06 Pip Cet <pipcet@gmail.com>
884
885 * Makefile.am: Add wasm32-dis.c.
886 * configure.ac: Add wasm32-dis.c to wasm32 target.
887 * disassemble.c: Add wasm32 disassembler code.
888 * wasm32-dis.c: New file.
889 * Makefile.in: Regenerate.
890 * configure: Regenerate.
891 * po/POTFILES.in: Regenerate.
892 * po/opcodes.pot: Regenerate.
893
f995bbe8
PA		 8942017-04-05 Pedro Alves <palves@redhat.com>
895
896 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
897 * arm-dis.c (parse_arm_disassembler_options): Constify.
898 * ppc-dis.c (powerpc_init_dialect): Constify local.
899 * vax-dis.c (parse_disassembler_options): Constify.
900
b5292032
PD		 9012017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
902
903 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
904 RISCV_GP_SYMBOL.
905
f96bd6c2
PC		 9062017-03-30 Pip Cet <pipcet@gmail.com>
907
908 * configure.ac: Add (empty) bfd_wasm32_arch target.
909 * configure: Regenerate
910 * po/opcodes.pot: Regenerate.
911
f7c514a3
JM		 9122017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
913
914 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
915 OSA2015.
916 * opcodes/sparc-opc.c (asi_table): New ASIs.
917
52be03fd
AM		 9182017-03-29 Alan Modra <amodra@gmail.com>
919
920 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
921 "raw" option.
922 (lookup_powerpc): Don't special case -1 dialect. Handle
923 PPC_OPCODE_RAW.
924 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
925 lookup_powerpc call, pass it on second.
926
9b753937
AM		 9272017-03-27 Alan Modra <amodra@gmail.com>
928
929 PR 21303
930 * ppc-dis.c (struct ppc_mopt): Comment.
931 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
932
c0c31e91
RZ		 9332017-03-27 Rinat Zelig <rinat@mellanox.com>
934
935 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
936 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
937 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
938 (insert_nps_misc_imm_offset): New function.
939 (extract_nps_misc imm_offset): New function.
940 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
941 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
942
2253c8f0
AK		 9432017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
944
945 * s390-mkopc.c (main): Remove vx2 check.
946 * s390-opc.txt: Remove vx2 instruction flags.
947
645d3342
RZ		 9482017-03-21 Rinat Zelig <rinat@mellanox.com>
949
950 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
951 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
952 (insert_nps_imm_offset): New function.
953 (extract_nps_imm_offset): New function.
954 (insert_nps_imm_entry): New function.
955 (extract_nps_imm_entry): New function.
956
4b94dd2d
AM		 9572017-03-17 Alan Modra <amodra@gmail.com>
958
959 PR 21248
960 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
961 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
962 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
963
b416fe87
KC		 9642017-03-14 Kito Cheng <kito.cheng@gmail.com>
965
966 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
967 <c.andi>: Likewise.
968 <c.addiw> Likewise.
969
03b039a5
KC		 9702017-03-14 Kito Cheng <kito.cheng@gmail.com>
971
972 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
973
2c232b83
AW		 9742017-03-13 Andrew Waterman <andrew@sifive.com>
975
976 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
977 <srl> Likewise.
978 <srai> Likewise.
979 <sra> Likewise.
980
86fa6981
L		 9812017-03-09 H.J. Lu <hongjiu.lu@intel.com>
982
983 * i386-gen.c (opcode_modifiers): Replace S with Load.
984 * i386-opc.h (S): Removed.
985 (Load): New.
986 (i386_opcode_modifier): Replace s with load.
987 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
988 and {evex}. Replace S with Load.
989 * i386-tbl.h: Regenerated.
990
c1fe188b
L		 9912017-03-09 H.J. Lu <hongjiu.lu@intel.com>
992
993 * i386-opc.tbl: Use CpuCET on rdsspq.
994 * i386-tbl.h: Regenerated.
995
4b8b687e
PB		 9962017-03-08 Peter Bergner <bergner@vnet.ibm.com>
997
998 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
999 <vsx>: Do not use PPC_OPCODE_VSX3;
1000
1437d063
PB		 10012017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1002
1003 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1004
603555e5
L		 10052017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1006
1007 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1008 (MOD_0F1E_PREFIX_1): Likewise.
1009 (MOD_0F38F5_PREFIX_2): Likewise.
1010 (MOD_0F38F6_PREFIX_0): Likewise.
1011 (RM_0F1E_MOD_3_REG_7): Likewise.
1012 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1013 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1014 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1015 (PREFIX_0F1E): Likewise.
1016 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1017 (PREFIX_0F38F5): Likewise.
1018 (dis386_twobyte): Use PREFIX_0F1E.
1019 (reg_table): Add REG_0F1E_MOD_3.
1020 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1021 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1022 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1023 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1024 (three_byte_table): Use PREFIX_0F38F5.
1025 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1026 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1027 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1028 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1029 PREFIX_MOD_3_0F01_REG_5_RM_2.
1030 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1031 (cpu_flags): Add CpuCET.
1032 * i386-opc.h (CpuCET): New enum.
1033 (CpuUnused): Commented out.
1034 (i386_cpu_flags): Add cpucet.
1035 * i386-opc.tbl: Add Intel CET instructions.
1036 * i386-init.h: Regenerated.
1037 * i386-tbl.h: Likewise.
1038
73f07bff
AM		 10392017-03-06 Alan Modra <amodra@gmail.com>
1040
1041 PR 21124
1042 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1043 (extract_raq, extract_ras, extract_rbx): New functions.
1044 (powerpc_operands): Use opposite corresponding insert function.
1045 (Q_MASK): Define.
1046 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1047 register restriction.
1048
65b48a81
PB		 10492017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1050
1051 * disassemble.c Include "safe-ctype.h".
1052 (disassemble_init_for_target): Handle s390 init.
1053 (remove_whitespace_and_extra_commas): New function.
1054 (disassembler_options_cmp): Likewise.
1055 * arm-dis.c: Include "libiberty.h".
1056 (NUM_ELEM): Delete.
1057 (regnames): Use long disassembler style names.
1058 Add force-thumb and no-force-thumb options.
1059 (NUM_ARM_REGNAMES): Rename from this...
1060 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1061 (get_arm_regname_num_options): Delete.
1062 (set_arm_regname_option): Likewise.
1063 (get_arm_regnames): Likewise.
1064 (parse_disassembler_options): Likewise.
1065 (parse_arm_disassembler_option): Rename from this...
1066 (parse_arm_disassembler_options): ...to this. Make static.
1067 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1068 (print_insn): Use parse_arm_disassembler_options.
1069 (disassembler_options_arm): New function.
1070 (print_arm_disassembler_options): Handle updated regnames.
1071 * ppc-dis.c: Include "libiberty.h".
1072 (ppc_opts): Add "32" and "64" entries.
1073 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1074 (powerpc_init_dialect): Add break to switch statement.
1075 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1076 (disassembler_options_powerpc): New function.
1077 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1078 Remove printing of "32" and "64".
1079 * s390-dis.c: Include "libiberty.h".
1080 (init_flag): Remove unneeded variable.
1081 (struct s390_options_t): New structure type.
1082 (options): New structure.
1083 (init_disasm): Rename from this...
1084 (disassemble_init_s390): ...to this. Add initializations for
1085 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1086 (print_insn_s390): Delete call to init_disasm.
1087 (disassembler_options_s390): New function.
1088 (print_s390_disassembler_options): Print using information from
1089 struct 'options'.
1090 * po/opcodes.pot: Regenerate.
1091
15c7c1d8
JB		 10922017-02-28 Jan Beulich <jbeulich@suse.com>
1093
1094 * i386-dis.c (PCMPESTR_Fixup): New.
1095 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1096 (prefix_table): Use PCMPESTR_Fixup.
1097 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1098 PCMPESTR_Fixup.
1099 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1100 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1101 Split 64-bit and non-64-bit variants.
1102 * opcodes/i386-tbl.h: Re-generate.
1103
582e12bf
RS		 11042017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1105
1106 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1107 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1108 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1109 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1110 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1111 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1112 (OP_SVE_V_HSD): New macros.
1113 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1114 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1115 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1116 (aarch64_opcode_table): Add new SVE instructions.
1117 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1118 for rotation operands. Add new SVE operands.
1119 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1120 (ins_sve_quad_index): Likewise.
1121 (ins_imm_rotate): Split into...
1122 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1123 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1124 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1125 functions.
1126 (aarch64_ins_sve_addr_ri_s4): New function.
1127 (aarch64_ins_sve_quad_index): Likewise.
1128 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1129 * aarch64-asm-2.c: Regenerate.
1130 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1131 (ext_sve_quad_index): Likewise.
1132 (ext_imm_rotate): Split into...
1133 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1134 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1135 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1136 functions.
1137 (aarch64_ext_sve_addr_ri_s4): New function.
1138 (aarch64_ext_sve_quad_index): Likewise.
1139 (aarch64_ext_sve_index): Allow quad indices.
1140 (do_misc_decoding): Likewise.
1141 * aarch64-dis-2.c: Regenerate.
1142 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1143 aarch64_field_kinds.
1144 (OPD_F_OD_MASK): Widen by one bit.
1145 (OPD_F_NO_ZR): Bump accordingly.
1146 (get_operand_field_width): New function.
1147 * aarch64-opc.c (fields): Add new SVE fields.
1148 (operand_general_constraint_met_p): Handle new SVE operands.
1149 (aarch64_print_operand): Likewise.
1150 * aarch64-opc-2.c: Regenerate.
1151
f482d304
RS		 11522017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1153
1154 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1155 (aarch64_feature_compnum): ...this.
1156 (SIMD_V8_3): Replace with...
1157 (COMPNUM): ...this.
1158 (CNUM_INSN): New macro.
1159 (aarch64_opcode_table): Use it for the complex number instructions.
1160
7db2c588
JB		 11612017-02-24 Jan Beulich <jbeulich@suse.com>
1162
1163 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1164
1e9d41d4
SL		 11652017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1166
1167 Add support for associating SPARC ASIs with an architecture level.
1168 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1169 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1170 decoding of SPARC ASIs.
1171
53c4d625
JB		 11722017-02-23 Jan Beulich <jbeulich@suse.com>
1173
1174 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1175 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1176
11648de5
JB		 11772017-02-21 Jan Beulich <jbeulich@suse.com>
1178
1179 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1180 1 (instead of to itself). Correct typo.
1181
f98d33be
AW		 11822017-02-14 Andrew Waterman <andrew@sifive.com>
1183
1184 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1185 pseudoinstructions.
1186
773fb663
RS		 11872017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1188
1189 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1190 (aarch64_sys_reg_supported_p): Handle them.
1191
cc07cda6
CZ		 11922017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1193
1194 * arc-opc.c (UIMM6_20R): Define.
1195 (SIMM12_20): Use above.
1196 (SIMM12_20R): Define.
1197 (SIMM3_5_S): Use above.
1198 (UIMM7_A32_11R_S): Define.
1199 (UIMM7_9_S): Use above.
1200 (UIMM3_13R_S): Define.
1201 (SIMM11_A32_7_S): Use above.
1202 (SIMM9_8R): Define.
1203 (UIMM10_A32_8_S): Use above.
1204 (UIMM8_8R_S): Define.
1205 (W6): Use above.
1206 (arc_relax_opcodes): Use all above defines.
1207
66a5a740
VG		 12082017-02-15 Vineet Gupta <vgupta@synopsys.com>
1209
1210 * arc-regs.h: Distinguish some of the registers different on
1211 ARC700 and HS38 cpus.
1212
7e0de605
AM		 12132017-02-14 Alan Modra <amodra@gmail.com>
1214
1215 PR 21118
1216 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1217 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1218
54064fdb
AM		 12192017-02-11 Stafford Horne <shorne@gmail.com>
1220 Alan Modra <amodra@gmail.com>
1221
1222 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1223 Use insn_bytes_value and insn_int_value directly instead. Don't
1224 free allocated memory until function exit.
1225
dce75bf9
NP		 12262017-02-10 Nicholas Piggin <npiggin@gmail.com>
1227
1228 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1229
1b7e3d2f
NC		 12302017-02-03 Nick Clifton <nickc@redhat.com>
1231
1232 PR 21096
1233 * aarch64-opc.c (print_register_list): Ensure that the register
1234 list index will fir into the tb buffer.
1235 (print_register_offset_address): Likewise.
1236 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1237
8ec5cf65
AD		 12382017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1239
1240 PR 21056
1241 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1242 instructions when the previous fetch packet ends with a 32-bit
1243 instruction.
1244
a1aa5e81
DD		 12452017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1246
1247 * pru-opc.c: Remove vague reference to a future GDB port.
1248
add3afb2
NC		 12492017-01-20 Nick Clifton <nickc@redhat.com>
1250
1251 * po/ga.po: Updated Irish translation.
1252
c13a63b0
SN		 12532017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1254
1255 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1256
9608051a
YQ		 12572017-01-13 Yao Qi <yao.qi@linaro.org>
1258
1259 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1260 if FETCH_DATA returns 0.
1261 (m68k_scan_mask): Likewise.
1262 (print_insn_m68k): Update code to handle -1 return value.
1263
f622ea96
YQ		 12642017-01-13 Yao Qi <yao.qi@linaro.org>
1265
1266 * m68k-dis.c (enum print_insn_arg_error): New.
1267 (NEXTBYTE): Replace -3 with
1268 PRINT_INSN_ARG_MEMORY_ERROR.
1269 (NEXTULONG): Likewise.
1270 (NEXTSINGLE): Likewise.
1271 (NEXTDOUBLE): Likewise.
1272 (NEXTDOUBLE): Likewise.
1273 (NEXTPACKED): Likewise.
1274 (FETCH_ARG): Likewise.
1275 (FETCH_DATA): Update comments.
1276 (print_insn_arg): Update comments. Replace magic numbers with
1277 enum.
1278 (match_insn_m68k): Likewise.
1279
620214f7
IT		 12802017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1281
1282 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1283 * i386-dis-evex.h (evex_table): Updated.
1284 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1285 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1286 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1287 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1288 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1289 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1290 * i386-init.h: Regenerate.
1291 * i386-tbl.h: Ditto.
1292
d95014a2
YQ		 12932017-01-12 Yao Qi <yao.qi@linaro.org>
1294
1295 * msp430-dis.c (msp430_singleoperand): Return -1 if
1296 msp430dis_opcode_signed returns false.
1297 (msp430_doubleoperand): Likewise.
1298 (msp430_branchinstr): Return -1 if
1299 msp430dis_opcode_unsigned returns false.
1300 (msp430x_calla_instr): Likewise.
1301 (print_insn_msp430): Likewise.
1302
0ae60c3e
NC		 13032017-01-05 Nick Clifton <nickc@redhat.com>
1304
1305 PR 20946
1306 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1307 could not be matched.
1308 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1309 NULL.
1310
d74d4880
SN		 13112017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1312
1313 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1314 (aarch64_opcode_table): Use RCPC_INSN.
1315
cc917fd9
KC		 13162017-01-03 Kito Cheng <kito.cheng@gmail.com>
1317
1318 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1319 extension.
1320 * riscv-opcodes/all-opcodes: Likewise.
1321
b52d3cfc
DP		 13222017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1323
1324 * riscv-dis.c (print_insn_args): Add fall through comment.
1325
f90c58d5
NC		 13262017-01-03 Nick Clifton <nickc@redhat.com>
1327
1328 * po/sr.po: New Serbian translation.
1329 * configure.ac (ALL_LINGUAS): Add sr.
1330 * configure: Regenerate.
1331
f47b0d4a
AM		 13322017-01-02 Alan Modra <amodra@gmail.com>
1333
1334 * epiphany-desc.h: Regenerate.
1335 * epiphany-opc.h: Regenerate.
1336 * fr30-desc.h: Regenerate.
1337 * fr30-opc.h: Regenerate.
1338 * frv-desc.h: Regenerate.
1339 * frv-opc.h: Regenerate.
1340 * ip2k-desc.h: Regenerate.
1341 * ip2k-opc.h: Regenerate.
1342 * iq2000-desc.h: Regenerate.
1343 * iq2000-opc.h: Regenerate.
1344 * lm32-desc.h: Regenerate.
1345 * lm32-opc.h: Regenerate.
1346 * m32c-desc.h: Regenerate.
1347 * m32c-opc.h: Regenerate.
1348 * m32r-desc.h: Regenerate.
1349 * m32r-opc.h: Regenerate.
1350 * mep-desc.h: Regenerate.
1351 * mep-opc.h: Regenerate.
1352 * mt-desc.h: Regenerate.
1353 * mt-opc.h: Regenerate.
1354 * or1k-desc.h: Regenerate.
1355 * or1k-opc.h: Regenerate.
1356 * xc16x-desc.h: Regenerate.
1357 * xc16x-opc.h: Regenerate.
1358 * xstormy16-desc.h: Regenerate.
1359 * xstormy16-opc.h: Regenerate.
1360
2571583a
AM		 13612017-01-02 Alan Modra <amodra@gmail.com>
1362
1363 Update year range in copyright notice of all files.
1364
5c1ad6b5 1365For older changes see ChangeLog-2016
3499769a 1366\f
5c1ad6b5 1367Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1368
1369Copying and distribution of this file, with or without modification,
1370are permitted in any medium without royalty provided the copyright
1371notice and this notice are preserved.
1372
1373Local Variables:
1374mode: change-log
1375left-margin: 8
1376fill-column: 74
1377version-control: never
1378End:
GDB Binutils - Deliverables
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