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[ARC] Add JLI support.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
684d5a10
JEM		 12017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
2 John Eric Martin <John.Martin@emmicro-us.com>
3
4 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
5 (UIMM3_23): Adjust accordingly.
6 * arc-regs.h: Add/correct jli_base register.
7 * arc-tbl.h (jli_s): Likewise.
8
de194d85
YC		 92017-07-18 Nick Clifton <nickc@redhat.com>
10
11 PR 21775
12 * aarch64-opc.c: Fix spelling typos.
13 * i386-dis.c: Likewise.
14
0f6329bd
RB		 152017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
16
17 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
18 max_addr_offset and octets variables to size_t.
19
429d795d
AM		 202017-07-12 Alan Modra <amodra@gmail.com>
21
22 * po/da.po: Update from translationproject.org/latest/opcodes/.
23 * po/de.po: Likewise.
24 * po/es.po: Likewise.
25 * po/fi.po: Likewise.
26 * po/fr.po: Likewise.
27 * po/id.po: Likewise.
28 * po/it.po: Likewise.
29 * po/nl.po: Likewise.
30 * po/pt_BR.po: Likewise.
31 * po/ro.po: Likewise.
32 * po/sv.po: Likewise.
33 * po/tr.po: Likewise.
34 * po/uk.po: Likewise.
35 * po/vi.po: Likewise.
36 * po/zh_CN.po: Likewise.
37
4162bb66
AM		 382017-07-11 Yao Qi <yao.qi@linaro.org>
39 Alan Modra <amodra@gmail.com>
40
41 * cgen.sh: Mark generated files read-only.
42 * epiphany-asm.c: Regenerate.
43 * epiphany-desc.c: Regenerate.
44 * epiphany-desc.h: Regenerate.
45 * epiphany-dis.c: Regenerate.
46 * epiphany-ibld.c: Regenerate.
47 * epiphany-opc.c: Regenerate.
48 * epiphany-opc.h: Regenerate.
49 * fr30-asm.c: Regenerate.
50 * fr30-desc.c: Regenerate.
51 * fr30-desc.h: Regenerate.
52 * fr30-dis.c: Regenerate.
53 * fr30-ibld.c: Regenerate.
54 * fr30-opc.c: Regenerate.
55 * fr30-opc.h: Regenerate.
56 * frv-asm.c: Regenerate.
57 * frv-desc.c: Regenerate.
58 * frv-desc.h: Regenerate.
59 * frv-dis.c: Regenerate.
60 * frv-ibld.c: Regenerate.
61 * frv-opc.c: Regenerate.
62 * frv-opc.h: Regenerate.
63 * ip2k-asm.c: Regenerate.
64 * ip2k-desc.c: Regenerate.
65 * ip2k-desc.h: Regenerate.
66 * ip2k-dis.c: Regenerate.
67 * ip2k-ibld.c: Regenerate.
68 * ip2k-opc.c: Regenerate.
69 * ip2k-opc.h: Regenerate.
70 * iq2000-asm.c: Regenerate.
71 * iq2000-desc.c: Regenerate.
72 * iq2000-desc.h: Regenerate.
73 * iq2000-dis.c: Regenerate.
74 * iq2000-ibld.c: Regenerate.
75 * iq2000-opc.c: Regenerate.
76 * iq2000-opc.h: Regenerate.
77 * lm32-asm.c: Regenerate.
78 * lm32-desc.c: Regenerate.
79 * lm32-desc.h: Regenerate.
80 * lm32-dis.c: Regenerate.
81 * lm32-ibld.c: Regenerate.
82 * lm32-opc.c: Regenerate.
83 * lm32-opc.h: Regenerate.
84 * lm32-opinst.c: Regenerate.
85 * m32c-asm.c: Regenerate.
86 * m32c-desc.c: Regenerate.
87 * m32c-desc.h: Regenerate.
88 * m32c-dis.c: Regenerate.
89 * m32c-ibld.c: Regenerate.
90 * m32c-opc.c: Regenerate.
91 * m32c-opc.h: Regenerate.
92 * m32r-asm.c: Regenerate.
93 * m32r-desc.c: Regenerate.
94 * m32r-desc.h: Regenerate.
95 * m32r-dis.c: Regenerate.
96 * m32r-ibld.c: Regenerate.
97 * m32r-opc.c: Regenerate.
98 * m32r-opc.h: Regenerate.
99 * m32r-opinst.c: Regenerate.
100 * mep-asm.c: Regenerate.
101 * mep-desc.c: Regenerate.
102 * mep-desc.h: Regenerate.
103 * mep-dis.c: Regenerate.
104 * mep-ibld.c: Regenerate.
105 * mep-opc.c: Regenerate.
106 * mep-opc.h: Regenerate.
107 * mt-asm.c: Regenerate.
108 * mt-desc.c: Regenerate.
109 * mt-desc.h: Regenerate.
110 * mt-dis.c: Regenerate.
111 * mt-ibld.c: Regenerate.
112 * mt-opc.c: Regenerate.
113 * mt-opc.h: Regenerate.
114 * or1k-asm.c: Regenerate.
115 * or1k-desc.c: Regenerate.
116 * or1k-desc.h: Regenerate.
117 * or1k-dis.c: Regenerate.
118 * or1k-ibld.c: Regenerate.
119 * or1k-opc.c: Regenerate.
120 * or1k-opc.h: Regenerate.
121 * or1k-opinst.c: Regenerate.
122 * xc16x-asm.c: Regenerate.
123 * xc16x-desc.c: Regenerate.
124 * xc16x-desc.h: Regenerate.
125 * xc16x-dis.c: Regenerate.
126 * xc16x-ibld.c: Regenerate.
127 * xc16x-opc.c: Regenerate.
128 * xc16x-opc.h: Regenerate.
129 * xstormy16-asm.c: Regenerate.
130 * xstormy16-desc.c: Regenerate.
131 * xstormy16-desc.h: Regenerate.
132 * xstormy16-dis.c: Regenerate.
133 * xstormy16-ibld.c: Regenerate.
134 * xstormy16-opc.c: Regenerate.
135 * xstormy16-opc.h: Regenerate.
136
7639175c
AM		 1372017-07-07 Alan Modra <amodra@gmail.com>
138
139 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
140 * m32c-dis.c: Regenerate.
141 * mep-dis.c: Regenerate.
142
e4bdd679
BP		 1432017-07-05 Borislav Petkov <bp@suse.de>
144
145 * i386-dis.c: Enable ModRM.reg /6 aliases.
146
60c96dbf
RR		 1472017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
148
149 * opcodes/arm-dis.c: Support MVFR2 in disassembly
150 with vmrs and vmsr.
151
0d702cfe
TG		 1522017-07-04 Tristan Gingold <gingold@adacore.com>
153
154 * configure: Regenerate.
155
15e6ed8c
TG		 1562017-07-03 Tristan Gingold <gingold@adacore.com>
157
158 * po/opcodes.pot: Regenerate.
159
b1d3c886
MR		 1602017-06-30 Maciej W. Rozycki <macro@imgtec.com>
161
162 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
163 entries to the MSA ASE instruction block.
164
909b4e3d
MR		 1652017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
166 Maciej W. Rozycki <macro@imgtec.com>
167
168 * micromips-opc.c (XPA, XPAVZ): New macros.
169 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
170 "mthgc0".
171
f5b2fd52
MR		 1722017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
173 Maciej W. Rozycki <macro@imgtec.com>
174
175 * micromips-opc.c (I36): New macro.
176 (micromips_opcodes): Add "eretnc".
177
9785fc2a
MR		 1782017-06-30 Maciej W. Rozycki <macro@imgtec.com>
179 Andrew Bennett <andrew.bennett@imgtec.com>
180
181 * mips-dis.c (mips_calculate_combination_ases): Handle the
182 ASE_XPA_VIRT flag.
183 (parse_mips_ase_option): New function.
184 (parse_mips_dis_option): Factor out ASE option handling to the
185 new function. Call `mips_calculate_combination_ases'.
186 * mips-opc.c (XPAVZ): New macro.
187 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
188 "mfhgc0", "mthc0" and "mthgc0".
189
60804c53
MR		 1902017-06-29 Maciej W. Rozycki <macro@imgtec.com>
191
192 * mips-dis.c (mips_calculate_combination_ases): New function.
193 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
194 calculation to the new function.
195 (set_default_mips_dis_options): Call the new function.
196
2e74f9dd
AK		 1972017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
198
199 * arc-dis.c (parse_disassembler_options): Use
200 FOR_EACH_DISASSEMBLER_OPTION.
201
e1e94c49
AK		 2022017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
203
204 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
205 disassembler option strings.
206 (parse_cpu_option): Likewise.
207
65a55fbb
TC		 2082017-06-28 Tamar Christina <tamar.christina@arm.com>
209
210 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
211 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
212 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
213 (aarch64_feature_dotprod, DOT_INSN): New.
214 (udot, sdot): New.
215 * aarch64-dis-2.c: Regenerated.
216
c604a79a
JW		 2172017-06-28 Jiong Wang <jiong.wang@arm.com>
218
219 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
220
38bf472a
MR		 2212017-06-28 Maciej W. Rozycki <macro@imgtec.com>
222 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 223 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 224
225 * mips-formats.h (INT_BIAS): New macro.
226 (INT_ADJ): Redefine in INT_BIAS terms.
227 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
228 (mips_print_save_restore): New function.
229 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
230 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
231 call.
232 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
233 (print_mips16_insn_arg): Call `mips_print_save_restore' for
234 OP_SAVE_RESTORE_LIST handling, factored out from here.
235 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
236 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
237 (mips_builtin_opcodes): Add "restore" and "save" entries.
238 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
239 (IAMR2): New macro.
240 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
241
9bdfdbf9
AW		 2422017-06-23 Andrew Waterman <andrew@sifive.com>
243
244 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
245 alias; do not mark SLTI instruction as an alias.
246
2234eee6
L		 2472017-06-21 H.J. Lu <hongjiu.lu@intel.com>
248
249 * i386-dis.c (RM_0FAE_REG_5): Removed.
250 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
251 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
252 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
253 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
254 PREFIX_MOD_3_0F01_REG_5_RM_0.
255 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
256 PREFIX_MOD_3_0FAE_REG_5.
257 (mod_table): Update MOD_0FAE_REG_5.
258 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
259 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
260 * i386-tbl.h: Regenerated.
261
c2f76402
L		 2622017-06-21 H.J. Lu <hongjiu.lu@intel.com>
263
264 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
265 * i386-opc.tbl: Likewise.
266 * i386-tbl.h: Regenerated.
267
9fef80d6
L		 2682017-06-21 H.J. Lu <hongjiu.lu@intel.com>
269
270 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
271 and "jmp{&|}".
272 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
273 prefix.
274
0f6d864d
NC		 2752017-06-19 Nick Clifton <nickc@redhat.com>
276
277 PR binutils/21614
278 * score-dis.c (score_opcodes): Add sentinel.
279
e197589b
AM		 2802017-06-16 Alan Modra <amodra@gmail.com>
281
282 * rx-decode.c: Regenerate.
283
0d96e4df
L		 2842017-06-15 H.J. Lu <hongjiu.lu@intel.com>
285
286 PR binutils/21594
287 * i386-dis.c (OP_E_register): Check valid bnd register.
288 (OP_G): Likewise.
289
cd3ea7c6
NC		 2902017-06-15 Nick Clifton <nickc@redhat.com>
291
292 PR binutils/21595
293 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
294 range value.
295
63323b5b
NC		 2962017-06-15 Nick Clifton <nickc@redhat.com>
297
298 PR binutils/21588
299 * rl78-decode.opc (OP_BUF_LEN): Define.
300 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
301 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
302 array.
303 * rl78-decode.c: Regenerate.
304
08c7881b
NC		 3052017-06-15 Nick Clifton <nickc@redhat.com>
306
307 PR binutils/21586
308 * bfin-dis.c (gregs): Clip index to prevent overflow.
309 (regs): Likewise.
310 (regs_lo): Likewise.
311 (regs_hi): Likewise.
312
e64519d1
NC		 3132017-06-14 Nick Clifton <nickc@redhat.com>
314
315 PR binutils/21576
316 * score7-dis.c (score_opcodes): Add sentinel.
317
6394c606
YQ		 3182017-06-14 Yao Qi <yao.qi@linaro.org>
319
320 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
321 * arm-dis.c: Likewise.
322 * ia64-dis.c: Likewise.
323 * mips-dis.c: Likewise.
324 * spu-dis.c: Likewise.
325 * disassemble.h (print_insn_aarch64): New declaration, moved from
326 include/dis-asm.h.
327 (print_insn_big_arm, print_insn_big_mips): Likewise.
328 (print_insn_i386, print_insn_ia64): Likewise.
329 (print_insn_little_arm, print_insn_little_mips): Likewise.
330
db5fa770
NC		 3312017-06-14 Nick Clifton <nickc@redhat.com>
332
333 PR binutils/21587
334 * rx-decode.opc: Include libiberty.h
335 (GET_SCALE): New macro - validates access to SCALE array.
336 (GET_PSCALE): New macro - validates access to PSCALE array.
337 (DIs, SIs, S2Is, rx_disp): Use new macros.
338 * rx-decode.c: Regenerate.
339
05c966f3
AV		 3402017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
341
342 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
343
10045478
AK		 3442017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
345
346 * arc-dis.c (enforced_isa_mask): Declare.
347 (cpu_types): Likewise.
348 (parse_cpu_option): New function.
349 (parse_disassembler_options): Use it.
350 (print_insn_arc): Use enforced_isa_mask.
351 (print_arc_disassembler_options): Document new options.
352
88c1242d
YQ		 3532017-05-24 Yao Qi <yao.qi@linaro.org>
354
355 * alpha-dis.c: Include disassemble.h, don't include
356 dis-asm.h.
357 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
358 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
359 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
360 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
361 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
362 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
363 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
364 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
365 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
366 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
367 * moxie-dis.c, msp430-dis.c, mt-dis.c:
368 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
369 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
370 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
371 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
372 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
373 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
374 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
375 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
376 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
377 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
378 * z80-dis.c, z8k-dis.c: Likewise.
379 * disassemble.h: New file.
380
ab20fa4a
YQ		 3812017-05-24 Yao Qi <yao.qi@linaro.org>
382
383 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
384 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
385
003ca0fd
YQ		 3862017-05-24 Yao Qi <yao.qi@linaro.org>
387
388 * disassemble.c (disassembler): Add arguments a, big and mach.
389 Use them.
390
04ef582a
L		 3912017-05-22 H.J. Lu <hongjiu.lu@intel.com>
392
393 * i386-dis.c (NOTRACK_Fixup): New.
394 (NOTRACK): Likewise.
395 (NOTRACK_PREFIX): Likewise.
396 (last_active_prefix): Likewise.
397 (reg_table): Use NOTRACK on indirect call and jmp.
398 (ckprefix): Set last_active_prefix.
399 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
400 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
401 * i386-opc.h (NoTrackPrefixOk): New.
402 (i386_opcode_modifier): Add notrackprefixok.
403 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
404 Add notrack.
405 * i386-tbl.h: Regenerated.
406
64517994
JM		 4072017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
408
409 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
410 (X_IMM2): Define.
411 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
412 bfd_mach_sparc_v9m8.
413 (print_insn_sparc): Handle new operand types.
414 * sparc-opc.c (MASK_M8): Define.
415 (v6): Add MASK_M8.
416 (v6notlet): Likewise.
417 (v7): Likewise.
418 (v8): Likewise.
419 (v9): Likewise.
420 (v9a): Likewise.
421 (v9b): Likewise.
422 (v9c): Likewise.
423 (v9d): Likewise.
424 (v9e): Likewise.
425 (v9v): Likewise.
426 (v9m): Likewise.
427 (v9andleon): Likewise.
428 (m8): Define.
429 (HWS_VM8): Define.
430 (HWS2_VM8): Likewise.
431 (sparc_opcode_archs): Add entry for "m8".
432 (sparc_opcodes): Add OSA2017 and M8 instructions
433 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
434 fpx{ll,ra,rl}64x,
435 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
436 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
437 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
438 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
439 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
440 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
441 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
442 ASI_CORE_SELECT_COMMIT_NHT.
443
535b785f
AM		 4442017-05-18 Alan Modra <amodra@gmail.com>
445
446 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
447 * aarch64-dis.c: Likewise.
448 * aarch64-gen.c: Likewise.
449 * aarch64-opc.c: Likewise.
450
25499ac7
MR		 4512017-05-15 Maciej W. Rozycki <macro@imgtec.com>
452 Matthew Fortune <matthew.fortune@imgtec.com>
453
454 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
455 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
456 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
457 (print_insn_arg) <OP_REG28>: Add handler.
458 (validate_insn_args) <OP_REG28>: Handle.
459 (print_mips16_insn_arg): Handle MIPS16 instructions that require
460 32-bit encoding and 9-bit immediates.
461 (print_insn_mips16): Handle MIPS16 instructions that require
462 32-bit encoding and MFC0/MTC0 operand decoding.
463 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
464 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
465 (RD_C0, WR_C0, E2, E2MT): New macros.
466 (mips16_opcodes): Add entries for MIPS16e2 instructions:
467 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
468 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
469 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
470 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
471 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
472 instructions, "swl", "swr", "sync" and its "sync_acquire",
473 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
474 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
475 regular/extended entries for original MIPS16 ISA revision
476 instructions whose extended forms are subdecoded in the MIPS16e2
477 ISA revision: "li", "sll" and "srl".
478
fdfb4752
MR		 4792017-05-15 Maciej W. Rozycki <macro@imgtec.com>
480
481 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
482 reference in CP0 move operand decoding.
483
a4f89915
MR		 4842017-05-12 Maciej W. Rozycki <macro@imgtec.com>
485
486 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
487 type to hexadecimal.
488 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
489
99e2d67a
MR		 4902017-05-11 Maciej W. Rozycki <macro@imgtec.com>
491
492 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
493 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
494 "sync_rmb" and "sync_wmb" as aliases.
495 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
496 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
497
53a346d8
CZ		 4982017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
499
500 * arc-dis.c (parse_option): Update quarkse_em option..
501 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
502 QUARKSE1.
503 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
504
f91d48de
KC		 5052017-05-03 Kito Cheng <kito.cheng@gmail.com>
506
507 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
508
43e379d7
MC		 5092017-05-01 Michael Clark <michaeljclark@mac.com>
510
511 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
512 register.
513
a4ddc54e
MR		 5142017-05-02 Maciej W. Rozycki <macro@imgtec.com>
515
516 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
517 and branches and not synthetic data instructions.
518
fe50e98c
BE		 5192017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
520
521 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
522
126124cc
CZ		 5232017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
524
525 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
526 * arc-opc.c (insert_r13el): New function.
527 (R13_EL): Define.
528 * arc-tbl.h: Add new enter/leave variants.
529
be6a24d8
CZ		 5302017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
531
532 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
533
0348fd79
MR		 5342017-04-25 Maciej W. Rozycki <macro@imgtec.com>
535
536 * mips-dis.c (print_mips_disassembler_options): Add
537 `no-aliases'.
538
6e3d1f07
MR		 5392017-04-25 Maciej W. Rozycki <macro@imgtec.com>
540
541 * mips16-opc.c (AL): New macro.
542 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
543 of "ld" and "lw" as aliases.
544
957f6b39
TC		 5452017-04-24 Tamar Christina <tamar.christina@arm.com>
546
547 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
548 arguments.
549
a8cc8a54
AM		 5502017-04-22 Alexander Fedotov <alfedotov@gmail.com>
551 Alan Modra <amodra@gmail.com>
552
553 * ppc-opc.c (ELEV): Define.
554 (vle_opcodes): Add se_rfgi and e_sc.
555 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
556 for E200Z4.
557
3ab87b68
JM		 5582017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
559
560 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
561
792f174f
NC		 5622017-04-21 Nick Clifton <nickc@redhat.com>
563
564 PR binutils/21380
565 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
566 LD3R and LD4R.
567
42742084
AM		 5682017-04-13 Alan Modra <amodra@gmail.com>
569
570 * epiphany-desc.c: Regenerate.
571 * fr30-desc.c: Regenerate.
572 * frv-desc.c: Regenerate.
573 * ip2k-desc.c: Regenerate.
574 * iq2000-desc.c: Regenerate.
575 * lm32-desc.c: Regenerate.
576 * m32c-desc.c: Regenerate.
577 * m32r-desc.c: Regenerate.
578 * mep-desc.c: Regenerate.
579 * mt-desc.c: Regenerate.
580 * or1k-desc.c: Regenerate.
581 * xc16x-desc.c: Regenerate.
582 * xstormy16-desc.c: Regenerate.
583
9a85b496
AM		 5842017-04-11 Alan Modra <amodra@gmail.com>
585
ef85eab0 586 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 587 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
588 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 589 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
590 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 591 (PPCVSX2): Define as PPC_OPCODE_POWER8.
592 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 593 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 594 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 595
62adc510
AM		 5962017-04-10 Alan Modra <amodra@gmail.com>
597
598 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
599 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
600 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
601 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
602
aa808707
PC		 6032017-04-09 Pip Cet <pipcet@gmail.com>
604
605 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
606 appropriate floating-point precision directly.
607
ac8f0f72
AM		 6082017-04-07 Alan Modra <amodra@gmail.com>
609
610 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
611 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
612 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
613 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
614 vector instructions with E6500 not PPCVEC2.
615
62ecb94c
PC		 6162017-04-06 Pip Cet <pipcet@gmail.com>
617
618 * Makefile.am: Add wasm32-dis.c.
619 * configure.ac: Add wasm32-dis.c to wasm32 target.
620 * disassemble.c: Add wasm32 disassembler code.
621 * wasm32-dis.c: New file.
622 * Makefile.in: Regenerate.
623 * configure: Regenerate.
624 * po/POTFILES.in: Regenerate.
625 * po/opcodes.pot: Regenerate.
626
f995bbe8
PA		 6272017-04-05 Pedro Alves <palves@redhat.com>
628
629 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
630 * arm-dis.c (parse_arm_disassembler_options): Constify.
631 * ppc-dis.c (powerpc_init_dialect): Constify local.
632 * vax-dis.c (parse_disassembler_options): Constify.
633
b5292032
PD		 6342017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
635
636 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
637 RISCV_GP_SYMBOL.
638
f96bd6c2
PC		 6392017-03-30 Pip Cet <pipcet@gmail.com>
640
641 * configure.ac: Add (empty) bfd_wasm32_arch target.
642 * configure: Regenerate
643 * po/opcodes.pot: Regenerate.
644
f7c514a3
JM		 6452017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
646
647 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
648 OSA2015.
649 * opcodes/sparc-opc.c (asi_table): New ASIs.
650
52be03fd
AM		 6512017-03-29 Alan Modra <amodra@gmail.com>
652
653 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
654 "raw" option.
655 (lookup_powerpc): Don't special case -1 dialect. Handle
656 PPC_OPCODE_RAW.
657 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
658 lookup_powerpc call, pass it on second.
659
9b753937
AM		 6602017-03-27 Alan Modra <amodra@gmail.com>
661
662 PR 21303
663 * ppc-dis.c (struct ppc_mopt): Comment.
664 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
665
c0c31e91
RZ		 6662017-03-27 Rinat Zelig <rinat@mellanox.com>
667
668 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
669 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
670 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
671 (insert_nps_misc_imm_offset): New function.
672 (extract_nps_misc imm_offset): New function.
673 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
674 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
675
2253c8f0
AK		 6762017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
677
678 * s390-mkopc.c (main): Remove vx2 check.
679 * s390-opc.txt: Remove vx2 instruction flags.
680
645d3342
RZ		 6812017-03-21 Rinat Zelig <rinat@mellanox.com>
682
683 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
684 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
685 (insert_nps_imm_offset): New function.
686 (extract_nps_imm_offset): New function.
687 (insert_nps_imm_entry): New function.
688 (extract_nps_imm_entry): New function.
689
4b94dd2d
AM		 6902017-03-17 Alan Modra <amodra@gmail.com>
691
692 PR 21248
693 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
694 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
695 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
696
b416fe87
KC		 6972017-03-14 Kito Cheng <kito.cheng@gmail.com>
698
699 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
700 <c.andi>: Likewise.
701 <c.addiw> Likewise.
702
03b039a5
KC		 7032017-03-14 Kito Cheng <kito.cheng@gmail.com>
704
705 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
706
2c232b83
AW		 7072017-03-13 Andrew Waterman <andrew@sifive.com>
708
709 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
710 <srl> Likewise.
711 <srai> Likewise.
712 <sra> Likewise.
713
86fa6981
L		 7142017-03-09 H.J. Lu <hongjiu.lu@intel.com>
715
716 * i386-gen.c (opcode_modifiers): Replace S with Load.
717 * i386-opc.h (S): Removed.
718 (Load): New.
719 (i386_opcode_modifier): Replace s with load.
720 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
721 and {evex}. Replace S with Load.
722 * i386-tbl.h: Regenerated.
723
c1fe188b
L		 7242017-03-09 H.J. Lu <hongjiu.lu@intel.com>
725
726 * i386-opc.tbl: Use CpuCET on rdsspq.
727 * i386-tbl.h: Regenerated.
728
4b8b687e
PB		 7292017-03-08 Peter Bergner <bergner@vnet.ibm.com>
730
731 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
732 <vsx>: Do not use PPC_OPCODE_VSX3;
733
1437d063
PB		 7342017-03-08 Peter Bergner <bergner@vnet.ibm.com>
735
736 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
737
603555e5
L		 7382017-03-06 H.J. Lu <hongjiu.lu@intel.com>
739
740 * i386-dis.c (REG_0F1E_MOD_3): New enum.
741 (MOD_0F1E_PREFIX_1): Likewise.
742 (MOD_0F38F5_PREFIX_2): Likewise.
743 (MOD_0F38F6_PREFIX_0): Likewise.
744 (RM_0F1E_MOD_3_REG_7): Likewise.
745 (PREFIX_MOD_0_0F01_REG_5): Likewise.
746 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
747 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
748 (PREFIX_0F1E): Likewise.
749 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
750 (PREFIX_0F38F5): Likewise.
751 (dis386_twobyte): Use PREFIX_0F1E.
752 (reg_table): Add REG_0F1E_MOD_3.
753 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
754 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
755 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
756 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
757 (three_byte_table): Use PREFIX_0F38F5.
758 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
759 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
760 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
761 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
762 PREFIX_MOD_3_0F01_REG_5_RM_2.
763 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
764 (cpu_flags): Add CpuCET.
765 * i386-opc.h (CpuCET): New enum.
766 (CpuUnused): Commented out.
767 (i386_cpu_flags): Add cpucet.
768 * i386-opc.tbl: Add Intel CET instructions.
769 * i386-init.h: Regenerated.
770 * i386-tbl.h: Likewise.
771
73f07bff
AM		 7722017-03-06 Alan Modra <amodra@gmail.com>
773
774 PR 21124
775 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
776 (extract_raq, extract_ras, extract_rbx): New functions.
777 (powerpc_operands): Use opposite corresponding insert function.
778 (Q_MASK): Define.
779 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
780 register restriction.
781
65b48a81
PB		 7822017-02-28 Peter Bergner <bergner@vnet.ibm.com>
783
784 * disassemble.c Include "safe-ctype.h".
785 (disassemble_init_for_target): Handle s390 init.
786 (remove_whitespace_and_extra_commas): New function.
787 (disassembler_options_cmp): Likewise.
788 * arm-dis.c: Include "libiberty.h".
789 (NUM_ELEM): Delete.
790 (regnames): Use long disassembler style names.
791 Add force-thumb and no-force-thumb options.
792 (NUM_ARM_REGNAMES): Rename from this...
793 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
794 (get_arm_regname_num_options): Delete.
795 (set_arm_regname_option): Likewise.
796 (get_arm_regnames): Likewise.
797 (parse_disassembler_options): Likewise.
798 (parse_arm_disassembler_option): Rename from this...
799 (parse_arm_disassembler_options): ...to this. Make static.
800 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
801 (print_insn): Use parse_arm_disassembler_options.
802 (disassembler_options_arm): New function.
803 (print_arm_disassembler_options): Handle updated regnames.
804 * ppc-dis.c: Include "libiberty.h".
805 (ppc_opts): Add "32" and "64" entries.
806 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
807 (powerpc_init_dialect): Add break to switch statement.
808 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
809 (disassembler_options_powerpc): New function.
810 (print_ppc_disassembler_options): Use ARRAY_SIZE.
811 Remove printing of "32" and "64".
812 * s390-dis.c: Include "libiberty.h".
813 (init_flag): Remove unneeded variable.
814 (struct s390_options_t): New structure type.
815 (options): New structure.
816 (init_disasm): Rename from this...
817 (disassemble_init_s390): ...to this. Add initializations for
818 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
819 (print_insn_s390): Delete call to init_disasm.
820 (disassembler_options_s390): New function.
821 (print_s390_disassembler_options): Print using information from
822 struct 'options'.
823 * po/opcodes.pot: Regenerate.
824
15c7c1d8
JB		 8252017-02-28 Jan Beulich <jbeulich@suse.com>
826
827 * i386-dis.c (PCMPESTR_Fixup): New.
828 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
829 (prefix_table): Use PCMPESTR_Fixup.
830 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
831 PCMPESTR_Fixup.
832 (vex_w_table): Delete VPCMPESTR{I,M} entries.
833 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
834 Split 64-bit and non-64-bit variants.
835 * opcodes/i386-tbl.h: Re-generate.
836
582e12bf
RS		 8372017-02-24 Richard Sandiford <richard.sandiford@arm.com>
838
839 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
840 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
841 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
842 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
843 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
844 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
845 (OP_SVE_V_HSD): New macros.
846 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
847 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
848 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
849 (aarch64_opcode_table): Add new SVE instructions.
850 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
851 for rotation operands. Add new SVE operands.
852 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
853 (ins_sve_quad_index): Likewise.
854 (ins_imm_rotate): Split into...
855 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
856 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
857 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
858 functions.
859 (aarch64_ins_sve_addr_ri_s4): New function.
860 (aarch64_ins_sve_quad_index): Likewise.
861 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
862 * aarch64-asm-2.c: Regenerate.
863 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
864 (ext_sve_quad_index): Likewise.
865 (ext_imm_rotate): Split into...
866 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
867 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
868 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
869 functions.
870 (aarch64_ext_sve_addr_ri_s4): New function.
871 (aarch64_ext_sve_quad_index): Likewise.
872 (aarch64_ext_sve_index): Allow quad indices.
873 (do_misc_decoding): Likewise.
874 * aarch64-dis-2.c: Regenerate.
875 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
876 aarch64_field_kinds.
877 (OPD_F_OD_MASK): Widen by one bit.
878 (OPD_F_NO_ZR): Bump accordingly.
879 (get_operand_field_width): New function.
880 * aarch64-opc.c (fields): Add new SVE fields.
881 (operand_general_constraint_met_p): Handle new SVE operands.
882 (aarch64_print_operand): Likewise.
883 * aarch64-opc-2.c: Regenerate.
884
f482d304
RS		 8852017-02-24 Richard Sandiford <richard.sandiford@arm.com>
886
887 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
888 (aarch64_feature_compnum): ...this.
889 (SIMD_V8_3): Replace with...
890 (COMPNUM): ...this.
891 (CNUM_INSN): New macro.
892 (aarch64_opcode_table): Use it for the complex number instructions.
893
7db2c588
JB		 8942017-02-24 Jan Beulich <jbeulich@suse.com>
895
896 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
897
1e9d41d4
SL		 8982017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
899
900 Add support for associating SPARC ASIs with an architecture level.
901 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
902 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
903 decoding of SPARC ASIs.
904
53c4d625
JB		 9052017-02-23 Jan Beulich <jbeulich@suse.com>
906
907 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
908 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
909
11648de5
JB		 9102017-02-21 Jan Beulich <jbeulich@suse.com>
911
912 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
913 1 (instead of to itself). Correct typo.
914
f98d33be
AW		 9152017-02-14 Andrew Waterman <andrew@sifive.com>
916
917 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
918 pseudoinstructions.
919
773fb663
RS		 9202017-02-15 Richard Sandiford <richard.sandiford@arm.com>
921
922 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
923 (aarch64_sys_reg_supported_p): Handle them.
924
cc07cda6
CZ		 9252017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
926
927 * arc-opc.c (UIMM6_20R): Define.
928 (SIMM12_20): Use above.
929 (SIMM12_20R): Define.
930 (SIMM3_5_S): Use above.
931 (UIMM7_A32_11R_S): Define.
932 (UIMM7_9_S): Use above.
933 (UIMM3_13R_S): Define.
934 (SIMM11_A32_7_S): Use above.
935 (SIMM9_8R): Define.
936 (UIMM10_A32_8_S): Use above.
937 (UIMM8_8R_S): Define.
938 (W6): Use above.
939 (arc_relax_opcodes): Use all above defines.
940
66a5a740
VG		 9412017-02-15 Vineet Gupta <vgupta@synopsys.com>
942
943 * arc-regs.h: Distinguish some of the registers different on
944 ARC700 and HS38 cpus.
945
7e0de605
AM		 9462017-02-14 Alan Modra <amodra@gmail.com>
947
948 PR 21118
949 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
950 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
951
54064fdb
AM		 9522017-02-11 Stafford Horne <shorne@gmail.com>
953 Alan Modra <amodra@gmail.com>
954
955 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
956 Use insn_bytes_value and insn_int_value directly instead. Don't
957 free allocated memory until function exit.
958
dce75bf9
NP		 9592017-02-10 Nicholas Piggin <npiggin@gmail.com>
960
961 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
962
1b7e3d2f
NC		 9632017-02-03 Nick Clifton <nickc@redhat.com>
964
965 PR 21096
966 * aarch64-opc.c (print_register_list): Ensure that the register
967 list index will fir into the tb buffer.
968 (print_register_offset_address): Likewise.
969 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
970
8ec5cf65
AD		 9712017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
972
973 PR 21056
974 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
975 instructions when the previous fetch packet ends with a 32-bit
976 instruction.
977
a1aa5e81
DD		 9782017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
979
980 * pru-opc.c: Remove vague reference to a future GDB port.
981
add3afb2
NC		 9822017-01-20 Nick Clifton <nickc@redhat.com>
983
984 * po/ga.po: Updated Irish translation.
985
c13a63b0
SN		 9862017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
987
988 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
989
9608051a
YQ		 9902017-01-13 Yao Qi <yao.qi@linaro.org>
991
992 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
993 if FETCH_DATA returns 0.
994 (m68k_scan_mask): Likewise.
995 (print_insn_m68k): Update code to handle -1 return value.
996
f622ea96
YQ		 9972017-01-13 Yao Qi <yao.qi@linaro.org>
998
999 * m68k-dis.c (enum print_insn_arg_error): New.
1000 (NEXTBYTE): Replace -3 with
1001 PRINT_INSN_ARG_MEMORY_ERROR.
1002 (NEXTULONG): Likewise.
1003 (NEXTSINGLE): Likewise.
1004 (NEXTDOUBLE): Likewise.
1005 (NEXTDOUBLE): Likewise.
1006 (NEXTPACKED): Likewise.
1007 (FETCH_ARG): Likewise.
1008 (FETCH_DATA): Update comments.
1009 (print_insn_arg): Update comments. Replace magic numbers with
1010 enum.
1011 (match_insn_m68k): Likewise.
1012
620214f7
IT		 10132017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1014
1015 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1016 * i386-dis-evex.h (evex_table): Updated.
1017 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1018 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1019 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1020 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1021 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1022 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1023 * i386-init.h: Regenerate.
1024 * i386-tbl.h: Ditto.
1025
d95014a2
YQ		 10262017-01-12 Yao Qi <yao.qi@linaro.org>
1027
1028 * msp430-dis.c (msp430_singleoperand): Return -1 if
1029 msp430dis_opcode_signed returns false.
1030 (msp430_doubleoperand): Likewise.
1031 (msp430_branchinstr): Return -1 if
1032 msp430dis_opcode_unsigned returns false.
1033 (msp430x_calla_instr): Likewise.
1034 (print_insn_msp430): Likewise.
1035
0ae60c3e
NC		 10362017-01-05 Nick Clifton <nickc@redhat.com>
1037
1038 PR 20946
1039 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1040 could not be matched.
1041 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1042 NULL.
1043
d74d4880
SN		 10442017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1045
1046 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1047 (aarch64_opcode_table): Use RCPC_INSN.
1048
cc917fd9
KC		 10492017-01-03 Kito Cheng <kito.cheng@gmail.com>
1050
1051 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1052 extension.
1053 * riscv-opcodes/all-opcodes: Likewise.
1054
b52d3cfc
DP		 10552017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1056
1057 * riscv-dis.c (print_insn_args): Add fall through comment.
1058
f90c58d5
NC		 10592017-01-03 Nick Clifton <nickc@redhat.com>
1060
1061 * po/sr.po: New Serbian translation.
1062 * configure.ac (ALL_LINGUAS): Add sr.
1063 * configure: Regenerate.
1064
f47b0d4a
AM		 10652017-01-02 Alan Modra <amodra@gmail.com>
1066
1067 * epiphany-desc.h: Regenerate.
1068 * epiphany-opc.h: Regenerate.
1069 * fr30-desc.h: Regenerate.
1070 * fr30-opc.h: Regenerate.
1071 * frv-desc.h: Regenerate.
1072 * frv-opc.h: Regenerate.
1073 * ip2k-desc.h: Regenerate.
1074 * ip2k-opc.h: Regenerate.
1075 * iq2000-desc.h: Regenerate.
1076 * iq2000-opc.h: Regenerate.
1077 * lm32-desc.h: Regenerate.
1078 * lm32-opc.h: Regenerate.
1079 * m32c-desc.h: Regenerate.
1080 * m32c-opc.h: Regenerate.
1081 * m32r-desc.h: Regenerate.
1082 * m32r-opc.h: Regenerate.
1083 * mep-desc.h: Regenerate.
1084 * mep-opc.h: Regenerate.
1085 * mt-desc.h: Regenerate.
1086 * mt-opc.h: Regenerate.
1087 * or1k-desc.h: Regenerate.
1088 * or1k-opc.h: Regenerate.
1089 * xc16x-desc.h: Regenerate.
1090 * xc16x-opc.h: Regenerate.
1091 * xstormy16-desc.h: Regenerate.
1092 * xstormy16-opc.h: Regenerate.
1093
2571583a
AM		 10942017-01-02 Alan Modra <amodra@gmail.com>
1095
1096 Update year range in copyright notice of all files.
1097
5c1ad6b5 1098For older changes see ChangeLog-2016
3499769a 1099\f
5c1ad6b5 1100Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1101
1102Copying and distribution of this file, with or without modification,
1103are permitted in any medium without royalty provided the copyright
1104notice and this notice are preserved.
1105
1106Local Variables:
1107mode: change-log
1108left-margin: 8
1109fill-column: 74
1110version-control: never
1111End:
GDB Binutils - Deliverables
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