[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
	    Stephane Carrez <stcarrez@nerim.fr>

	* configure.in: Add S12X and XGATE co-processor support to m68hc11
	target.
	* disassemble.c: Likewise.
	* configure: Regenerate.
	* m68hc11-dis.c: Make objdump output more consistent, use hex
	instead of decimal and use 0x prefix for hex.
	* m68hc11-opc.c: Add S12X and XGATE opcodes.

2012-05-14  James Lemke  <jwlemke@codesourcery.com>

	* ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
	(PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
	(vle_opcd_indices): New array.
	(lookup_vle): New function.
	(disassemble_init_powerpc): Revise for second (VLE) opcode table.
	(print_insn_powerpc): Likewise.
	* ppc-opc.c: Likewise.

2012-05-14  Catherine Moore  <clm@codesourcery.com>
	    Maciej W. Rozycki  <macro@codesourcery.com>
	    Rhonda Wittels  <rhonda@codesourcery.com>
	    Nathan Froyd <froydnj@codesourcery.com>

	* ppc-opc.c (insert_arx, extract_arx): New functions.
	(insert_ary, extract_ary): New functions.
	(insert_li20, extract_li20): New functions.
	(insert_rx, extract_rx): New functions.
	(insert_ry, extract_ry): New functions.
	(insert_sci8, extract_sci8): New functions.
	(insert_sci8n, extract_sci8n): New functions.
	(insert_sd4h, extract_sd4h): New functions.
	(insert_sd4w, extract_sd4w): New functions.
	(insert_vlesi, extract_vlesi): New functions.
	(insert_vlensi, extract_vlensi): New functions.
	(insert_vleui, extract_vleui): New functions.
	(insert_vleil, extract_vleil): New functions.
	(BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
	(BI16, BI32, BO32, B8): New.
	(B15, B24, CRD32, CRS): New.
	(CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
	(DB, IMM20, RD, Rx, ARX, RY, RZ): New.
	(ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
	(SH6_MASK): Use PPC_OPSHIFT_INV.
	(SI8, UI5, OIMM5, UI7, BO16): New.
	(VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
	(XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
	(ALLOW8_SPRG): New.
	(insert_sprg, extract_sprg): Check ALLOW8_SPRG.
	(OPVUP, OPVUP_MASK OPVUP): New
	(BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
	(EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
	(BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
	(BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
	(IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
	(IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
	(SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
	(SE_IM5, SE_IM5_MASK): New.
	(SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
	(EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
	(BO32DNZ, BO32DZ): New.
	(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
	(PPCVLE): New.
	(powerpc_opcodes): Add new VLE instructions.  Update existing
	instruction to include PPCVLE if supported.
	* ppc-dis.c (ppc_opts): Add vle entry.
	(get_powerpc_dialect): New function.
	(powerpc_init_dialect): VLE support.
	(print_insn_big_powerpc): Call get_powerpc_dialect.
	(print_insn_little_powerpc): Likewise.
	(operand_value_powerpc): Handle negative shift counts.
	(print_insn_powerpc): Handle 2-byte instruction lengths.

2012-05-11  Daniel Richard G.  <skunk@iskunk.org>

	PR binutils/14028
	* configure.in: Invoke ACX_HEADER_STRING.
	* configure: Regenerate.
	* config.in: Regenerate.
	* sysdep.h: If STRINGS_WITH_STRING is defined then include both
	string.h and strings.h.

2012-05-11  Nick Clifton  <nickc@redhat.com>

	PR binutils/14006
	* arm-dis.c (print_insn): Fix detection of instruction mode in
	files containing multiple executable sections.

2012-05-03  Sean Keys  <skeys@ipdatasys.com>

	* Makefile.in, configure: regenerate
	* disassemble.c (disassembler): Recognize ARCH_XGATE.
	* xgate-dis.c (read_memory, print_insn, print_insn_xgate):
	New functions.
	* configure.in: Recognize xgate.
	* xgate-dis.c, xgate-opc.c: New files for support of xgate
	* Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
	and opcode generation for xgate.

2012-04-30  DJ Delorie  <dj@redhat.com>

	* rx-decode.opc (MOV): Do not sign-extend immediates which are
	already the maximum bit size.
	* rx-decode.c: Regenerate.

2012-04-27  David S. Miller  <davem@davemloft.net>

	* sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
	* sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.

	* sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
	* sparc-dis.c (v9a_asr_reg_names): Add 'pause'.

	* sparc-opc.c (CBCOND): New define.
	(CBCOND_XCC): Likewise.
	(cbcond): New helper macro.
	(sparc_opcodes): Add compare-and-branch instructions.

	* sparc-dis.c (print_insn_sparc): Handle ')'.
	* sparc-opc.c (sparc_opcodes): Add crypto instructions.

	* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
	into new struct sparc_opcode 'hwcaps' field instead of 'flags'.

2012-04-12  David S. Miller  <davem@davemloft.net>

	* sparc-dis.c (X_DISP10): Define.
	(print_insn_sparc): Handle '='.

2012-04-01  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (fmtconst): Replace decimal handling with a single
	sprintf call and the '*' field width.

2012-03-23  Maxim Kuvyrkov  <maxim@codesourcery.com>

	* mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.

2012-03-16  Alan Modra  <amodra@gmail.com>

	* ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
	(powerpc_opcd_indices): Bump array size.
	(disassemble_init_powerpc): Set powerpc_opcd_indices entries
	corresponding to unused opcodes to following entry.
	(lookup_powerpc): New function, extracted and optimised from..
	(print_insn_powerpc): ..here.

2012-03-15  Alan Modra  <amodra@gmail.com>
	    James Lemke  <jwlemke@codesourcery.com>

	* disassemble.c (disassemble_init_for_target): Handle ppc init.
	* ppc-dis.c (private): New var.
	(powerpc_init_dialect): Don't return calloc failure, instead use
	private.
	(PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
	(powerpc_opcd_indices): New array.
	(disassemble_init_powerpc): New function.
	(print_insn_big_powerpc): Don't init dialect here.
	(print_insn_little_powerpc): Likewise.
	(print_insn_powerpc): Start search using powerpc_opcd_indices.

2012-03-10  Edmar Wienskoski  <edmar@freescale.com>

	* ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
	* ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
	(PPCVEC2, PPCTMR, E6500): New short names.
	(powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
	mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
	lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
	lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
	lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
	optional operands on sync instruction for E6500 target.

2012-03-08  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* s390-opc.txt: Set instruction type of pku to SS_L2RDRD.

2012-02-27  Alan Modra  <amodra@gmail.com>

	* mt-dis.c: Regenerate.

2012-02-27  Alan Modra  <amodra@gmail.com>

	* v850-opc.c (extract_v8): Rearrange to make it obvious this
	is the inverse of corresponding insert function.
	(extract_d22, extract_u9, extract_r4): Likewise.
	(extract_d9): Correct sign extension.
	(extract_d16_15): Don't assume "long" is 32 bits, and don't
	rely on implementation defined behaviour for shift right of
	signed types.
	(extract_d16_16, extract_d17_16, extract_i9): Likewise.
	(extract_d23): Likewise, and correct mask.

2012-02-27  Alan Modra  <amodra@gmail.com>

	* crx-dis.c (print_arg): Mask constant to 32 bits.
	* crx-opc.c (cst4_map): Use int array.

2012-02-27  Alan Modra  <amodra@gmail.com>

	* arc-dis.c (BITS): Don't use shifts to mask off bits.
	(FIELDD): Sign extend with xor,sub.

2012-02-25  Walter Lee  <walt@tilera.com>

	* tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
	* tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
	TILEPRO_OPC_LW_TLS_SN.

2012-02-21  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h (HLEPrefixNone): New.
	(HLEPrefixLock): Likewise.
	(HLEPrefixAny): Likewise.
	(HLEPrefixRelease): Likewise.

2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (HLE_Fixup1): New.
	(HLE_Fixup2): Likewise.
	(HLE_Fixup3): Likewise.
	(Ebh1): Likewise.
	(Evh1): Likewise.
	(Ebh2): Likewise.
	(Evh2): Likewise.
	(Ebh3): Likewise.
	(Evh3): Likewise.
	(MOD_C6_REG_7): Likewise.
	(MOD_C7_REG_7): Likewise.
	(RM_C6_REG_7): Likewise.
	(RM_C7_REG_7): Likewise.
	(XACQUIRE_PREFIX): Likewise.
	(XRELEASE_PREFIX): Likewise.
	(dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
	cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
	Ebh2/Evh2 on xchg.  Use Ebh3/Evh3 on mov.
	(reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
	not, or, sbb, sub and xor.  Use Ebh3/Evh3 on mov.  Use
	MOD_C6_REG_7 and MOD_C7_REG_7.
	(mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
	(rm_table): Add RM_C6_REG_7 and RM_C7_REG_7.  Add xend and
	xtest.
	(prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
	(CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.

	* i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
	CPU_RTM_FLAGS.
	(cpu_flags): Add CpuHLE and CpuRTM.
	(opcode_modifiers): Add HLEPrefixOk.

	* i386-opc.h (CpuHLE): New.
	(CpuRTM): Likewise.
	(HLEPrefixOk): Likewise.
	(i386_cpu_flags): Add cpuhle and cpurtm.
	(i386_opcode_modifier): Add hleprefixok.

	* i386-opc.tbl: Add HLEPrefixOk=3 to mov.  Add HLEPrefixOk to
	add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
	sbb, sub, xor and xadd.  Add HLEPrefixOk=2 to xchg with memory
	operand.  Add xacquire, xrelease, xabort, xbegin, xend and
	xtest.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2012-01-24  DJ Delorie  <dj@redhat.com>

	* rl78-decode.opc (rl78_decode_opcode): Add NOT1.
	* rl78-decode.c: Regenerate.

2012-01-17  James Murray  <jsm@jsm-net.demon.co.uk>

	PR binutils/10173
	* cr16-dis.c (print_arg): Test symtab_size not num_symbols.

2012-01-17  Andreas Schwab  <schwab@linux-m68k.org>

	* m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
	register and move them after pmove with PSR/PCSR register.

2012-01-13  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (mod_table): Add vmfunc.

	* i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
	(cpu_flags): CpuVMFUNC.

	* i386-opc.h (CpuVMFUNC): New.
	(i386_cpu_flags): Add cpuvmfunc.

	* i386-opc.tbl: Add vmfunc.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

For older changes see ChangeLog-2011
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
6927f982 NC	1	2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
	2	Stephane Carrez <stcarrez@nerim.fr>
	3
	4	* configure.in: Add S12X and XGATE co-processor support to m68hc11
	5	target.
	6	* disassemble.c: Likewise.
	7	* configure: Regenerate.
	8	* m68hc11-dis.c: Make objdump output more consistent, use hex
	9	instead of decimal and use 0x prefix for hex.
	10	* m68hc11-opc.c: Add S12X and XGATE opcodes.
	11
b9c361e0 JL	12	2012-05-14 James Lemke <jwlemke@codesourcery.com>
	13
	14	* ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
	15	(PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
	16	(vle_opcd_indices): New array.
	17	(lookup_vle): New function.
	18	(disassemble_init_powerpc): Revise for second (VLE) opcode table.
	19	(print_insn_powerpc): Likewise.
	20	* ppc-opc.c: Likewise.
	21
	22	2012-05-14 Catherine Moore <clm@codesourcery.com>
	23	Maciej W. Rozycki <macro@codesourcery.com>
	24	Rhonda Wittels <rhonda@codesourcery.com>
	25	Nathan Froyd <froydnj@codesourcery.com>
	26
	27	* ppc-opc.c (insert_arx, extract_arx): New functions.
	28	(insert_ary, extract_ary): New functions.
	29	(insert_li20, extract_li20): New functions.
	30	(insert_rx, extract_rx): New functions.
	31	(insert_ry, extract_ry): New functions.
	32	(insert_sci8, extract_sci8): New functions.
	33	(insert_sci8n, extract_sci8n): New functions.
	34	(insert_sd4h, extract_sd4h): New functions.
	35	(insert_sd4w, extract_sd4w): New functions.
	36	(insert_vlesi, extract_vlesi): New functions.
	37	(insert_vlensi, extract_vlensi): New functions.
	38	(insert_vleui, extract_vleui): New functions.
	39	(insert_vleil, extract_vleil): New functions.
	40	(BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
	41	(BI16, BI32, BO32, B8): New.
	42	(B15, B24, CRD32, CRS): New.
	43	(CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
	44	(DB, IMM20, RD, Rx, ARX, RY, RZ): New.
	45	(ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
	46	(SH6_MASK): Use PPC_OPSHIFT_INV.
	47	(SI8, UI5, OIMM5, UI7, BO16): New.
	48	(VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
	49	(XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
	50	(ALLOW8_SPRG): New.
	51	(insert_sprg, extract_sprg): Check ALLOW8_SPRG.
	52	(OPVUP, OPVUP_MASK OPVUP): New
	53	(BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
	54	(EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
	55	(BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
	56	(BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
	57	(IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
	58	(IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
	59	(SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
	60	(SE_IM5, SE_IM5_MASK): New.
	61	(SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
	62	(EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
	63	(BO32DNZ, BO32DZ): New.
	64	(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
	65	(PPCVLE): New.
	66	(powerpc_opcodes): Add new VLE instructions. Update existing
	67	instruction to include PPCVLE if supported.
	68	* ppc-dis.c (ppc_opts): Add vle entry.
	69	(get_powerpc_dialect): New function.
	70	(powerpc_init_dialect): VLE support.
	71	(print_insn_big_powerpc): Call get_powerpc_dialect.
	72	(print_insn_little_powerpc): Likewise.
	73	(operand_value_powerpc): Handle negative shift counts.
	74	(print_insn_powerpc): Handle 2-byte instruction lengths.
	75
208a4923 NC	76	2012-05-11 Daniel Richard G. <skunk@iskunk.org>
	77
	78	PR binutils/14028
	79	* configure.in: Invoke ACX_HEADER_STRING.
	80	* configure: Regenerate.
	81	* config.in: Regenerate.
	82	* sysdep.h: If STRINGS_WITH_STRING is defined then include both
	83	string.h and strings.h.
	84
6750a3a7 NC	85	2012-05-11 Nick Clifton <nickc@redhat.com>
	86
	87	PR binutils/14006
	88	* arm-dis.c (print_insn): Fix detection of instruction mode in
	89	files containing multiple executable sections.
	90
f6c1a2d5 NC	91	2012-05-03 Sean Keys <skeys@ipdatasys.com>
	92
	93	* Makefile.in, configure: regenerate
	94	* disassemble.c (disassembler): Recognize ARCH_XGATE.
	95	* xgate-dis.c (read_memory, print_insn, print_insn_xgate):
	96	New functions.
	97	* configure.in: Recognize xgate.
	98	* xgate-dis.c, xgate-opc.c: New files for support of xgate
	99	* Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
	100	and opcode generation for xgate.
	101
78e98aab DD	102	2012-04-30 DJ Delorie <dj@redhat.com>
	103
	104	* rx-decode.opc (MOV): Do not sign-extend immediates which are
	105	already the maximum bit size.
	106	* rx-decode.c: Regenerate.
	107
ec668d69 DM	108	2012-04-27 David S. Miller <davem@davemloft.net>
ec668d69 DM	109
2e52845b DM	110	* sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
	111	* sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
	112
58004e23 DM	113	* sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
	114	* sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
	115
698544e1 DM	116	* sparc-opc.c (CBCOND): New define.
	117	(CBCOND_XCC): Likewise.
	118	(cbcond): New helper macro.
	119	(sparc_opcodes): Add compare-and-branch instructions.
	120
6cda1326 DM	121	* sparc-dis.c (print_insn_sparc): Handle ')'.
	122	* sparc-opc.c (sparc_opcodes): Add crypto instructions.
	123
ec668d69 DM	124	* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
	125	into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
	126
2615994e DM	127	2012-04-12 David S. Miller <davem@davemloft.net>
	128
	129	* sparc-dis.c (X_DISP10): Define.
	130	(print_insn_sparc): Handle '='.
	131
5de10af0 MF	132	2012-04-01 Mike Frysinger <vapier@gentoo.org>
	133
	134	* bfin-dis.c (fmtconst): Replace decimal handling with a single
	135	sprintf call and the '*' field width.
	136
55a36193 MK	137	2012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
	138
	139	* mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
	140
d6688282 AM	141	2012-03-16 Alan Modra <amodra@gmail.com>
	142
	143	* ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
	144	(powerpc_opcd_indices): Bump array size.
	145	(disassemble_init_powerpc): Set powerpc_opcd_indices entries
	146	corresponding to unused opcodes to following entry.
	147	(lookup_powerpc): New function, extracted and optimised from..
	148	(print_insn_powerpc): ..here.
	149
b240011a AM	150	2012-03-15 Alan Modra <amodra@gmail.com>
	151	James Lemke <jwlemke@codesourcery.com>
	152
	153	* disassemble.c (disassemble_init_for_target): Handle ppc init.
	154	* ppc-dis.c (private): New var.
	155	(powerpc_init_dialect): Don't return calloc failure, instead use
	156	private.
	157	(PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
	158	(powerpc_opcd_indices): New array.
	159	(disassemble_init_powerpc): New function.
	160	(print_insn_big_powerpc): Don't init dialect here.
	161	(print_insn_little_powerpc): Likewise.
	162	(print_insn_powerpc): Start search using powerpc_opcd_indices.
	163
aea77599 AM	164	2012-03-10 Edmar Wienskoski <edmar@freescale.com>
	165
	166	* ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
	167	* ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
	168	(PPCVEC2, PPCTMR, E6500): New short names.
	169	(powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
	170	mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
	171	lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
	172	lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
	173	lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
	174	optional operands on sync instruction for E6500 target.
	175
5333187a AK	176	2012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
	177
	178	* s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
	179
a597d2d3 AM	180	2012-02-27 Alan Modra <amodra@gmail.com>
	181
	182	* mt-dis.c: Regenerate.
	183
3f26eb3a AM	184	2012-02-27 Alan Modra <amodra@gmail.com>
	185
	186	* v850-opc.c (extract_v8): Rearrange to make it obvious this
	187	is the inverse of corresponding insert function.
	188	(extract_d22, extract_u9, extract_r4): Likewise.
	189	(extract_d9): Correct sign extension.
	190	(extract_d16_15): Don't assume "long" is 32 bits, and don't
	191	rely on implementation defined behaviour for shift right of
	192	signed types.
	193	(extract_d16_16, extract_d17_16, extract_i9): Likewise.
	194	(extract_d23): Likewise, and correct mask.
	195
1f42f8b3 AM	196	2012-02-27 Alan Modra <amodra@gmail.com>
	197
	198	* crx-dis.c (print_arg): Mask constant to 32 bits.
	199	* crx-opc.c (cst4_map): Use int array.
	200
cdb06235 AM	201	2012-02-27 Alan Modra <amodra@gmail.com>
	202
	203	* arc-dis.c (BITS): Don't use shifts to mask off bits.
	204	(FIELDD): Sign extend with xor,sub.
	205
6f7be959 WL	206	2012-02-25 Walter Lee <walt@tilera.com>
	207
	208	* tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
	209	* tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
	210	TILEPRO_OPC_LW_TLS_SN.
	211
82c2def5 L	212	2012-02-21 H.J. Lu <hongjiu.lu@intel.com>
	213
	214	* i386-opc.h (HLEPrefixNone): New.
	215	(HLEPrefixLock): Likewise.
	216	(HLEPrefixAny): Likewise.
	217	(HLEPrefixRelease): Likewise.
	218
42164a71 L	219	2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
	220
	221	* i386-dis.c (HLE_Fixup1): New.
	222	(HLE_Fixup2): Likewise.
	223	(HLE_Fixup3): Likewise.
	224	(Ebh1): Likewise.
	225	(Evh1): Likewise.
	226	(Ebh2): Likewise.
	227	(Evh2): Likewise.
	228	(Ebh3): Likewise.
	229	(Evh3): Likewise.
	230	(MOD_C6_REG_7): Likewise.
	231	(MOD_C7_REG_7): Likewise.
	232	(RM_C6_REG_7): Likewise.
	233	(RM_C7_REG_7): Likewise.
	234	(XACQUIRE_PREFIX): Likewise.
	235	(XRELEASE_PREFIX): Likewise.
	236	(dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
	237	cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
	238	Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
	239	(reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
	240	not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
	241	MOD_C6_REG_7 and MOD_C7_REG_7.
	242	(mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
	243	(rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
	244	xtest.
	245	(prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
	246	(CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
	247
	248	* i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
	249	CPU_RTM_FLAGS.
	250	(cpu_flags): Add CpuHLE and CpuRTM.
	251	(opcode_modifiers): Add HLEPrefixOk.
	252
	253	* i386-opc.h (CpuHLE): New.
	254	(CpuRTM): Likewise.
	255	(HLEPrefixOk): Likewise.
	256	(i386_cpu_flags): Add cpuhle and cpurtm.
	257	(i386_opcode_modifier): Add hleprefixok.
	258
	259	* i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
	260	add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
	261	sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
	262	operand. Add xacquire, xrelease, xabort, xbegin, xend and
	263	xtest.
	264	* i386-init.h: Regenerated.
	265	* i386-tbl.h: Likewise.
	266
21abe33a DD	267	2012-01-24 DJ Delorie <dj@redhat.com>
	268
	269	* rl78-decode.opc (rl78_decode_opcode): Add NOT1.
	270	* rl78-decode.c: Regenerate.
	271
e20cc039 AM	272	2012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
	273
	274	PR binutils/10173
	275	* cr16-dis.c (print_arg): Test symtab_size not num_symbols.
	276
e143d25c AS	277	2012-01-17 Andreas Schwab <schwab@linux-m68k.org>
	278
	279	* m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
	280	register and move them after pmove with PSR/PCSR register.
	281
8729a6f6 L	282	2012-01-13 H.J. Lu <hongjiu.lu@intel.com>
	283
	284	* i386-dis.c (mod_table): Add vmfunc.
	285
	286	* i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
	287	(cpu_flags): CpuVMFUNC.
	288
	289	* i386-opc.h (CpuVMFUNC): New.
	290	(i386_cpu_flags): Add cpuvmfunc.
	291
	292	* i386-opc.tbl: Add vmfunc.
	293	* i386-init.h: Regenerated.
	294	* i386-tbl.h: Likewise.
5011093d	295
23e1d329	296	For older changes see ChangeLog-2011
252b5132 RH	297	\f
252b5132 RH	298	Local Variables:
2f6d2f85 NC	299	mode: change-log
	300	left-margin: 8
	301	fill-column: 74
252b5132 RH	302	version-control: never
252b5132 RH	303	End: