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X86: Add ptwrite instruction
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
6b40c462
L		 12016-08-24 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
4 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
5 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
6 PREFIX_MOD_3_0FAE_REG_4.
7 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
8 PREFIX_MOD_3_0FAE_REG_4.
9 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
10 (cpu_flags): Add CpuPTWRITE.
11 * i386-opc.h (CpuPTWRITE): New.
12 (i386_cpu_flags): Add cpuptwrite.
13 * i386-opc.tbl: Add ptwrite instruction.
14 * i386-init.h: Regenerated.
15 * i386-tbl.h: Likewise.
16
ab548d2d
AK		 172016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
18
19 * arc-dis.h: Wrap around in extern "C".
20
344bde0a
RS		 212016-08-23 Richard Sandiford <richard.sandiford@arm.com>
22
23 * aarch64-tbl.h (V8_2_INSN): New macro.
24 (aarch64_opcode_table): Use it.
25
5ce912d8
RS		 262016-08-23 Richard Sandiford <richard.sandiford@arm.com>
27
28 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
29 CORE_INSN, __FP_INSN and SIMD_INSN.
30
9d30b0bd
RS		 312016-08-23 Richard Sandiford <richard.sandiford@arm.com>
32
33 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
34 (aarch64_opcode_table): Update uses accordingly.
35
dfdaec14
AJ		 362016-07-25 Andrew Jenner <andrew@codesourcery.com>
37 Kwok Cheung Yeung <kcy@codesourcery.com>
38
39 opcodes/
40 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
41 'e_cmplwi' to 'e_cmpli' instead.
42 (OPVUPRT, OPVUPRT_MASK): Define.
43 (powerpc_opcodes): Add E200Z4 insns.
44 (vle_opcodes): Add context save/restore insns.
45
7bd374a4
MR		 462016-07-27 Maciej W. Rozycki <macro@imgtec.com>
47
48 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
49 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
50 "j".
51
db18dbab
GM		 522016-07-27 Graham Markall <graham.markall@embecosm.com>
53
54 * arc-nps400-tbl.h: Change block comments to GNU format.
55 * arc-dis.c: Add new globals addrtypenames,
56 addrtypenames_max, and addtypeunknown.
57 (get_addrtype): New function.
58 (print_insn_arc): Print colons and address types when
59 required.
60 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
61 define insert and extract functions for all address types.
62 (arc_operands): Add operands for colon and all address
63 types.
64 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
65 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
66 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
67 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
68 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
69 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
70
fecd57f9
L		 712016-07-21 H.J. Lu <hongjiu.lu@intel.com>
72
73 * configure: Regenerated.
74
37fd5ef3
CZ		 752016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
76
77 * arc-dis.c (skipclass): New structure.
78 (decodelist): New variable.
79 (is_compatible_p): New function.
80 (new_element): Likewise.
81 (skip_class_p): Likewise.
82 (find_format_from_table): Use skip_class_p function.
83 (find_format): Decode first the extension instructions.
84 (print_insn_arc): Select either ARCEM or ARCHS based on elf
85 e_flags.
86 (parse_option): New function.
87 (parse_disassembler_options): Likewise.
88 (print_arc_disassembler_options): Likewise.
89 (print_insn_arc): Use parse_disassembler_options function. Proper
90 select ARCv2 cpu variant.
91 * disassemble.c (disassembler_usage): Add ARC disassembler
92 options.
93
92281a5b
MR		 942016-07-13 Maciej W. Rozycki <macro@imgtec.com>
95
96 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
97 annotation from the "nal" entry and reorder it beyond "bltzal".
98
6e7ced37
JM		 992016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
100
101 * sparc-opc.c (ldtxa): New macro.
102 (sparc_opcodes): Use the macro defined above to add entries for
103 the LDTXA instructions.
104 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
105 instruction.
106
2f831b9a 1072016-07-07 James Bowman <james.bowman@ftdichip.com>
108
109 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
110 and "jmpc".
111
c07315e0
JB		 1122016-07-01 Jan Beulich <jbeulich@suse.com>
113
114 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
115 (movzb): Adjust to cover all permitted suffixes.
116 (movzw): New.
117 * i386-tbl.h: Re-generate.
118
9243100a
JB		 1192016-07-01 Jan Beulich <jbeulich@suse.com>
120
121 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
122 (lgdt): Remove Tbyte from non-64-bit variant.
123 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
124 xsaves64, xsavec64): Remove Disp16.
125 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
126 Remove Disp32S from non-64-bit variants. Remove Disp16 from
127 64-bit variants.
128 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
129 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
130 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
131 64-bit variants.
132 * i386-tbl.h: Re-generate.
133
8325cc63
JB		 1342016-07-01 Jan Beulich <jbeulich@suse.com>
135
136 * i386-opc.tbl (xlat): Remove RepPrefixOk.
137 * i386-tbl.h: Re-generate.
138
838441e4
YQ		 1392016-06-30 Yao Qi <yao.qi@linaro.org>
140
141 * arm-dis.c (print_insn): Fix typo in comment.
142
dab26bf4
RS		 1432016-06-28 Richard Sandiford <richard.sandiford@arm.com>
144
145 * aarch64-opc.c (operand_general_constraint_met_p): Check the
146 range of ldst_elemlist operands.
147 (print_register_list): Use PRIi64 to print the index.
148 (aarch64_print_operand): Likewise.
149
5703197e
TS		 1502016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
151
152 * mcore-opc.h: Remove sentinal.
153 * mcore-dis.c (print_insn_mcore): Adjust.
154
ce440d63
GM		 1552016-06-23 Graham Markall <graham.markall@embecosm.com>
156
157 * arc-opc.c: Correct description of availability of NPS400
158 features.
159
6fd3a02d
PB		 1602016-06-22 Peter Bergner <bergner@vnet.ibm.com>
161
162 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
163 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
164 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
165 xor3>: New mnemonics.
166 <setb>: Change to a VX form instruction.
167 (insert_sh6): Add support for rldixor.
168 (extract_sh6): Likewise.
169
6b477896
TS		 1702016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
171
172 * arc-ext.h: Wrap in extern C.
173
bdd582db
GM		 1742016-06-21 Graham Markall <graham.markall@embecosm.com>
175
176 * arc-dis.c (arc_insn_length): Add comment on instruction length.
177 Use same method for determining instruction length on ARC700 and
178 NPS-400.
179 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
180 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
181 with the NPS400 subclass.
182 * arc-opc.c: Likewise.
183
96074adc
JM		 1842016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
185
186 * sparc-opc.c (rdasr): New macro.
187 (wrasr): Likewise.
188 (rdpr): Likewise.
189 (wrpr): Likewise.
190 (rdhpr): Likewise.
191 (wrhpr): Likewise.
192 (sparc_opcodes): Use the macros above to fix and expand the
193 definition of read/write instructions from/to
194 asr/privileged/hyperprivileged instructions.
195 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
196 %hva_mask_nz. Prefer softint_set and softint_clear over
197 set_softint and clear_softint.
198 (print_insn_sparc): Support %ver in Rd.
199
7a10c22f
JM		 2002016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
201
202 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
203 architecture according to the hardware capabilities they require.
204
4f26fb3a
JM		 2052016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
206
207 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
208 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
209 bfd_mach_sparc_v9{c,d,e,v,m}.
210 * sparc-opc.c (MASK_V9C): Define.
211 (MASK_V9D): Likewise.
212 (MASK_V9E): Likewise.
213 (MASK_V9V): Likewise.
214 (MASK_V9M): Likewise.
215 (v6): Add MASK_V9{C,D,E,V,M}.
216 (v6notlet): Likewise.
217 (v7): Likewise.
218 (v8): Likewise.
219 (v9): Likewise.
220 (v9andleon): Likewise.
221 (v9a): Likewise.
222 (v9b): Likewise.
223 (v9c): Define.
224 (v9d): Likewise.
225 (v9e): Likewise.
226 (v9v): Likewise.
227 (v9m): Likewise.
228 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
229
3ee6e4fb
NC		 2302016-06-15 Nick Clifton <nickc@redhat.com>
231
232 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
233 constants to match expected behaviour.
234 (nds32_parse_opcode): Likewise. Also for whitespace.
235
02f3be19
AB		 2362016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
237
238 * arc-opc.c (extract_rhv1): Extract value from insn.
239
6f9f37ed 2402016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 241
242 * arc-nps400-tbl.h: Add ldbit instruction.
243 * arc-opc.c: Add flag classes required for ldbit.
244
6f9f37ed 2452016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 246
247 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
248 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
249 support the above instructions.
250
6f9f37ed 2512016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 252
253 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
254 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
255 csma, cbba, zncv, and hofs.
256 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
257 support the above instructions.
258
2592016-06-06 Graham Markall <graham.markall@embecosm.com>
260
261 * arc-nps400-tbl.h: Add andab and orab instructions.
262
2632016-06-06 Graham Markall <graham.markall@embecosm.com>
264
265 * arc-nps400-tbl.h: Add addl-like instructions.
266
2672016-06-06 Graham Markall <graham.markall@embecosm.com>
268
269 * arc-nps400-tbl.h: Add mxb and imxb instructions.
270
2712016-06-06 Graham Markall <graham.markall@embecosm.com>
272
273 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
274 instructions.
275
b2cc3f6f
AK		 2762016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
277
278 * s390-dis.c (option_use_insn_len_bits_p): New file scope
279 variable.
280 (init_disasm): Handle new command line option "insnlength".
281 (print_s390_disassembler_options): Mention new option in help
282 output.
283 (print_insn_s390): Use the encoded insn length when dumping
284 unknown instructions.
285
1857fe72
DC		 2862016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
287
288 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
289 to the address and set as symbol address for LDS/ STS immediate operands.
290
14b57c7c
AM		 2912016-06-07 Alan Modra <amodra@gmail.com>
292
293 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
294 cpu for "vle" to e500.
295 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
296 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
297 (PPCNONE): Delete, substitute throughout.
298 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
299 except for major opcode 4 and 31.
300 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
301
4d1464f2
MW		 3022016-06-07 Matthew Wahab <matthew.wahab@arm.com>
303
304 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
305 ARM_EXT_RAS in relevant entries.
306
026122a6
PB		 3072016-06-03 Peter Bergner <bergner@vnet.ibm.com>
308
309 PR binutils/20196
310 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
311 opcodes for E6500.
312
07f5af7d
L		 3132016-06-03 H.J. Lu <hongjiu.lu@intel.com>
314
315 PR binutis/18386
316 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
317 (indir_v_mode): New.
318 Add comments for '&'.
319 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
320 (putop): Handle '&'.
321 (intel_operand_size): Handle indir_v_mode.
322 (OP_E_register): Likewise.
323 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
324 64-bit indirect call/jmp for AMD64.
325 * i386-tbl.h: Regenerated
326
4eb6f892
AB		 3272016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
328
329 * arc-dis.c (struct arc_operand_iterator): New structure.
330 (find_format_from_table): All the old content from find_format,
331 with some minor adjustments, and parameter renaming.
332 (find_format_long_instructions): New function.
333 (find_format): Rewritten.
334 (arc_insn_length): Add LSB parameter.
335 (extract_operand_value): New function.
336 (operand_iterator_next): New function.
337 (print_insn_arc): Use new functions to find opcode, and iterator
338 over operands.
339 * arc-opc.c (insert_nps_3bit_dst_short): New function.
340 (extract_nps_3bit_dst_short): New function.
341 (insert_nps_3bit_src2_short): New function.
342 (extract_nps_3bit_src2_short): New function.
343 (insert_nps_bitop1_size): New function.
344 (extract_nps_bitop1_size): New function.
345 (insert_nps_bitop2_size): New function.
346 (extract_nps_bitop2_size): New function.
347 (insert_nps_bitop_mod4_msb): New function.
348 (extract_nps_bitop_mod4_msb): New function.
349 (insert_nps_bitop_mod4_lsb): New function.
350 (extract_nps_bitop_mod4_lsb): New function.
351 (insert_nps_bitop_dst_pos3_pos4): New function.
352 (extract_nps_bitop_dst_pos3_pos4): New function.
353 (insert_nps_bitop_ins_ext): New function.
354 (extract_nps_bitop_ins_ext): New function.
355 (arc_operands): Add new operands.
356 (arc_long_opcodes): New global array.
357 (arc_num_long_opcodes): New global.
358 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
359
1fe0971e
TS		 3602016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
361
362 * nds32-asm.h: Add extern "C".
363 * sh-opc.h: Likewise.
364
315f180f
GM		 3652016-06-01 Graham Markall <graham.markall@embecosm.com>
366
367 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
368 0,b,limm to the rflt instruction.
369
a2b5fccc
TS		 3702016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
371
372 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
373 constant.
374
0cbd0046
L		 3752016-05-29 H.J. Lu <hongjiu.lu@intel.com>
376
377 PR gas/20145
378 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
379 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
380 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
381 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
382 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
383 * i386-init.h: Regenerated.
384
1848e567
L		 3852016-05-27 H.J. Lu <hongjiu.lu@intel.com>
386
387 PR gas/20145
388 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
389 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
390 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
391 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
392 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
393 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
394 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
395 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
396 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
397 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
398 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
399 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
400 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
401 CpuRegMask for AVX512.
402 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
403 and CpuRegMask.
404 (set_bitfield_from_cpu_flag_init): New function.
405 (set_bitfield): Remove const on f. Call
406 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
407 * i386-opc.h (CpuRegMMX): New.
408 (CpuRegXMM): Likewise.
409 (CpuRegYMM): Likewise.
410 (CpuRegZMM): Likewise.
411 (CpuRegMask): Likewise.
412 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
413 and cpuregmask.
414 * i386-init.h: Regenerated.
415 * i386-tbl.h: Likewise.
416
e92bae62
L		 4172016-05-27 H.J. Lu <hongjiu.lu@intel.com>
418
419 PR gas/20154
420 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
421 (opcode_modifiers): Add AMD64 and Intel64.
422 (main): Properly verify CpuMax.
423 * i386-opc.h (CpuAMD64): Removed.
424 (CpuIntel64): Likewise.
425 (CpuMax): Set to CpuNo64.
426 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
427 (AMD64): New.
428 (Intel64): Likewise.
429 (i386_opcode_modifier): Add amd64 and intel64.
430 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
431 on call and jmp.
432 * i386-init.h: Regenerated.
433 * i386-tbl.h: Likewise.
434
e89c5eaa
L		 4352016-05-27 H.J. Lu <hongjiu.lu@intel.com>
436
437 PR gas/20154
438 * i386-gen.c (main): Fail if CpuMax is incorrect.
439 * i386-opc.h (CpuMax): Set to CpuIntel64.
440 * i386-tbl.h: Regenerated.
441
77d66e7b
NC		 4422016-05-27 Nick Clifton <nickc@redhat.com>
443
444 PR target/20150
445 * msp430-dis.c (msp430dis_read_two_bytes): New function.
446 (msp430dis_opcode_unsigned): New function.
447 (msp430dis_opcode_signed): New function.
448 (msp430_singleoperand): Use the new opcode reading functions.
449 Only disassenmble bytes if they were successfully read.
450 (msp430_doubleoperand): Likewise.
451 (msp430_branchinstr): Likewise.
452 (msp430x_callx_instr): Likewise.
453 (print_insn_msp430): Check that it is safe to read bytes before
454 attempting disassembly. Use the new opcode reading functions.
455
19dfcc89
PB		 4562016-05-26 Peter Bergner <bergner@vnet.ibm.com>
457
458 * ppc-opc.c (CY): New define. Document it.
459 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
460
f3ad7637
L		 4612016-05-25 H.J. Lu <hongjiu.lu@intel.com>
462
463 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
464 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
465 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
466 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
467 CPU_ANY_AVX_FLAGS.
468 * i386-init.h: Regenerated.
469
f1360d58
L		 4702016-05-25 H.J. Lu <hongjiu.lu@intel.com>
471
472 PR gas/20141
473 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
474 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
475 * i386-init.h: Regenerated.
476
293f5f65
L		 4772016-05-25 H.J. Lu <hongjiu.lu@intel.com>
478
479 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
480 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
481 * i386-init.h: Regenerated.
482
d9eca1df
CZ		 4832016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
484
485 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
486 information.
487 (print_insn_arc): Set insn_type information.
488 * arc-opc.c (C_CC): Add F_CLASS_COND.
489 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
490 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
491 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
492 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
493 (brne, brne_s, jeq_s, jne_s): Likewise.
494
87789e08
CZ		 4952016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
496
497 * arc-tbl.h (neg): New instruction variant.
498
c810e0b8
CZ		 4992016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
500
501 * arc-dis.c (find_format, find_format, get_auxreg)
502 (print_insn_arc): Changed.
503 * arc-ext.h (INSERT_XOP): Likewise.
504
3d207518
TS		 5052016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
506
507 * tic54x-dis.c (sprint_mmr): Adjust.
508 * tic54x-opc.c: Likewise.
509
514e58b7
AM		 5102016-05-19 Alan Modra <amodra@gmail.com>
511
512 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
513
e43de63c
AM		 5142016-05-19 Alan Modra <amodra@gmail.com>
515
516 * ppc-opc.c: Formatting.
517 (NSISIGNOPT): Define.
518 (powerpc_opcodes <subis>): Use NSISIGNOPT.
519
1401d2fe
MR		 5202016-05-18 Maciej W. Rozycki <macro@imgtec.com>
521
522 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
523 replacing references to `micromips_ase' throughout.
524 (_print_insn_mips): Don't use file-level microMIPS annotation to
525 determine the disassembly mode with the symbol table.
526
1178da44
PB		 5272016-05-13 Peter Bergner <bergner@vnet.ibm.com>
528
529 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
530
8f4f9071
MF		 5312016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
532
533 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
534 mips64r6.
535 * mips-opc.c (D34): New macro.
536 (mips_builtin_opcodes): Define bposge32c for DSPr3.
537
8bc52696
AF		 5382016-05-10 Alexander Fomin <alexander.fomin@intel.com>
539
540 * i386-dis.c (prefix_table): Add RDPID instruction.
541 * i386-gen.c (cpu_flag_init): Add RDPID flag.
542 (cpu_flags): Add RDPID bitfield.
543 * i386-opc.h (enum): Add RDPID element.
544 (i386_cpu_flags): Add RDPID field.
545 * i386-opc.tbl: Add RDPID instruction.
546 * i386-init.h: Regenerate.
547 * i386-tbl.h: Regenerate.
548
39d911fc
TP		 5492016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
550
551 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
552 branch type of a symbol.
553 (print_insn): Likewise.
554
16a1fa25
TP		 5552016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
556
557 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
558 Mainline Security Extensions instructions.
559 (thumb_opcodes): Add entries for narrow ARMv8-M Security
560 Extensions instructions.
561 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
562 instructions.
563 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
564 special registers.
565
d751b79e
JM		 5662016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
567
568 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
569
945e0f82
CZ		 5702016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
571
572 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
573 (arcExtMap_genOpcode): Likewise.
574 * arc-opc.c (arg_32bit_rc): Define new variable.
575 (arg_32bit_u6): Likewise.
576 (arg_32bit_limm): Likewise.
577
20f55f38
SN		 5782016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
579
580 * aarch64-gen.c (VERIFIER): Define.
581 * aarch64-opc.c (VERIFIER): Define.
582 (verify_ldpsw): Use static linkage.
583 * aarch64-opc.h (verify_ldpsw): Remove.
584 * aarch64-tbl.h: Use VERIFIER for verifiers.
585
4bd13cde
NC		 5862016-04-28 Nick Clifton <nickc@redhat.com>
587
588 PR target/19722
589 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
590 * aarch64-opc.c (verify_ldpsw): New function.
591 * aarch64-opc.h (verify_ldpsw): New prototype.
592 * aarch64-tbl.h: Add initialiser for verifier field.
593 (LDPSW): Set verifier to verify_ldpsw.
594
c0f92bf9
L		 5952016-04-23 H.J. Lu <hongjiu.lu@intel.com>
596
597 PR binutils/19983
598 PR binutils/19984
599 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
600 smaller than address size.
601
e6c7cdec
TS		 6022016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
603
604 * alpha-dis.c: Regenerate.
605 * crx-dis.c: Likewise.
606 * disassemble.c: Likewise.
607 * epiphany-opc.c: Likewise.
608 * fr30-opc.c: Likewise.
609 * frv-opc.c: Likewise.
610 * ip2k-opc.c: Likewise.
611 * iq2000-opc.c: Likewise.
612 * lm32-opc.c: Likewise.
613 * lm32-opinst.c: Likewise.
614 * m32c-opc.c: Likewise.
615 * m32r-opc.c: Likewise.
616 * m32r-opinst.c: Likewise.
617 * mep-opc.c: Likewise.
618 * mt-opc.c: Likewise.
619 * or1k-opc.c: Likewise.
620 * or1k-opinst.c: Likewise.
621 * tic80-opc.c: Likewise.
622 * xc16x-opc.c: Likewise.
623 * xstormy16-opc.c: Likewise.
624
537aefaf
AB		 6252016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
626
627 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
628 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
629 calcsd, and calcxd instructions.
630 * arc-opc.c (insert_nps_bitop_size): Delete.
631 (extract_nps_bitop_size): Delete.
632 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
633 (extract_nps_qcmp_m3): Define.
634 (extract_nps_qcmp_m2): Define.
635 (extract_nps_qcmp_m1): Define.
636 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
637 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
638 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
639 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
640 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
641 NPS_QCMP_M3.
642
c8f785f2
AB		 6432016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
644
645 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
646
6fd8e7c2
L		 6472016-04-15 H.J. Lu <hongjiu.lu@intel.com>
648
649 * Makefile.in: Regenerated with automake 1.11.6.
650 * aclocal.m4: Likewise.
651
4b0c052e
AB		 6522016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
653
654 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
655 instructions.
656 * arc-opc.c (insert_nps_cmem_uimm16): New function.
657 (extract_nps_cmem_uimm16): New function.
658 (arc_operands): Add NPS_XLDST_UIMM16 operand.
659
cb040366
AB		 6602016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
661
662 * arc-dis.c (arc_insn_length): New function.
663 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
664 (find_format): Change insnLen parameter to unsigned.
665
accc0180
NC		 6662016-04-13 Nick Clifton <nickc@redhat.com>
667
668 PR target/19937
669 * v850-opc.c (v850_opcodes): Correct masks for long versions of
670 the LD.B and LD.BU instructions.
671
f36e33da
CZ		 6722016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
673
674 * arc-dis.c (find_format): Check for extension flags.
675 (print_flags): New function.
676 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
677 .extAuxRegister.
678 * arc-ext.c (arcExtMap_coreRegName): Use
679 LAST_EXTENSION_CORE_REGISTER.
680 (arcExtMap_coreReadWrite): Likewise.
681 (dump_ARC_extmap): Update printing.
682 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
683 (arc_aux_regs): Add cpu field.
684 * arc-regs.h: Add cpu field, lower case name aux registers.
685
1c2e355e
CZ		 6862016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
687
688 * arc-tbl.h: Add rtsc, sleep with no arguments.
689
b99747ae
CZ		 6902016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
691
692 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
693 Initialize.
694 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
695 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
696 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
697 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
698 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
699 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
700 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
701 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
702 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
703 (arc_opcode arc_opcodes): Null terminate the array.
704 (arc_num_opcodes): Remove.
705 * arc-ext.h (INSERT_XOP): Define.
706 (extInstruction_t): Likewise.
707 (arcExtMap_instName): Delete.
708 (arcExtMap_insn): New function.
709 (arcExtMap_genOpcode): Likewise.
710 * arc-ext.c (ExtInstruction): Remove.
711 (create_map): Zero initialize instruction fields.
712 (arcExtMap_instName): Remove.
713 (arcExtMap_insn): New function.
714 (dump_ARC_extmap): More info while debuging.
715 (arcExtMap_genOpcode): New function.
716 * arc-dis.c (find_format): New function.
717 (print_insn_arc): Use find_format.
718 (arc_get_disassembler): Enable dump_ARC_extmap only when
719 debugging.
720
92708cec
MR		 7212016-04-11 Maciej W. Rozycki <macro@imgtec.com>
722
723 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
724 instruction bits out.
725
a42a4f84
AB		 7262016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
727
728 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
729 * arc-opc.c (arc_flag_operands): Add new flags.
730 (arc_flag_classes): Add new classes.
731
1328504b
AB		 7322016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
733
734 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
735
820f03ff
AB		 7362016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
737
738 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
739 encode1, rflt, crc16, and crc32 instructions.
740 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
741 (arc_flag_classes): Add C_NPS_R.
742 (insert_nps_bitop_size_2b): New function.
743 (extract_nps_bitop_size_2b): Likewise.
744 (insert_nps_bitop_uimm8): Likewise.
745 (extract_nps_bitop_uimm8): Likewise.
746 (arc_operands): Add new operand entries.
747
8ddf6b2a
CZ		 7482016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
749
b99747ae
CZ		 750 * arc-regs.h: Add a new subclass field. Add double assist
751 accumulator register values.
752 * arc-tbl.h: Use DPA subclass to mark the double assist
753 instructions. Use DPX/SPX subclas to mark the FPX instructions.
754 * arc-opc.c (RSP): Define instead of SP.
755 (arc_aux_regs): Add the subclass field.
8ddf6b2a 756
589a7d88
JW		 7572016-04-05 Jiong Wang <jiong.wang@arm.com>
758
759 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
760
0a191de9 7612016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 762
763 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
764 NPS_R_SRC1.
765
0a106562
AB		 7662016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
767
768 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
769 issues. No functional changes.
770
bd05ac5f
CZ		 7712016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
772
b99747ae
CZ		 773 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
774 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
775 (RTT): Remove duplicate.
776 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
777 (PCT_CONFIG*): Remove.
778 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 779
9885948f
CZ		 7802016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
781
b99747ae 782 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 783
f2dd8838
CZ		 7842016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
785
b99747ae
CZ		 786 * arc-tbl.h (invld07): Remove.
787 * arc-ext-tbl.h: New file.
788 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
789 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 790
0d2f91fe
JK		 7912016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
792
793 Fix -Wstack-usage warnings.
794 * aarch64-dis.c (print_operands): Substitute size.
795 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
796
a6b71f42
JM		 7972016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
798
799 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
800 to get a proper diagnostic when an invalid ASR register is used.
801
9780e045
NC		 8022016-03-22 Nick Clifton <nickc@redhat.com>
803
804 * configure: Regenerate.
805
e23e8ebe
AB		 8062016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
807
808 * arc-nps400-tbl.h: New file.
809 * arc-opc.c: Add top level comment.
810 (insert_nps_3bit_dst): New function.
811 (extract_nps_3bit_dst): New function.
812 (insert_nps_3bit_src2): New function.
813 (extract_nps_3bit_src2): New function.
814 (insert_nps_bitop_size): New function.
815 (extract_nps_bitop_size): New function.
816 (arc_flag_operands): Add nps400 entries.
817 (arc_flag_classes): Add nps400 entries.
818 (arc_operands): Add nps400 entries.
819 (arc_opcodes): Add nps400 include.
820
1ae8ab47
AB		 8212016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
822
823 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
824 the new class enum values.
825
8699fc3e
AB		 8262016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
827
828 * arc-dis.c (print_insn_arc): Handle nps400.
829
24740d83
AB		 8302016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
831
832 * arc-opc.c (BASE): Delete.
833
8678914f
NC		 8342016-03-18 Nick Clifton <nickc@redhat.com>
835
836 PR target/19721
837 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
838 of MOV insn that aliases an ORR insn.
839
cc933301
JW		 8402016-03-16 Jiong Wang <jiong.wang@arm.com>
841
842 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
843
f86f5863
TS		 8442016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
845
846 * mcore-opc.h: Add const qualifiers.
847 * microblaze-opc.h (struct op_code_struct): Likewise.
848 * sh-opc.h: Likewise.
849 * tic4x-dis.c (tic4x_print_indirect): Likewise.
850 (tic4x_print_op): Likewise.
851
62de1c63
AM		 8522016-03-02 Alan Modra <amodra@gmail.com>
853
d11698cd 854 * or1k-desc.h: Regenerate.
62de1c63 855 * fr30-ibld.c: Regenerate.
c697cf0b 856 * rl78-decode.c: Regenerate.
62de1c63 857
020efce5
NC		 8582016-03-01 Nick Clifton <nickc@redhat.com>
859
860 PR target/19747
861 * rl78-dis.c (print_insn_rl78_common): Fix typo.
862
b0c11777
RL		 8632016-02-24 Renlin Li <renlin.li@arm.com>
864
865 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
866 (print_insn_coprocessor): Support fp16 instructions.
867
3e309328
RL		 8682016-02-24 Renlin Li <renlin.li@arm.com>
869
870 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
871 vminnm, vrint(mpna).
872
8afc7bea
RL		 8732016-02-24 Renlin Li <renlin.li@arm.com>
874
875 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
876 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
877
4fd7268a
L		 8782016-02-15 H.J. Lu <hongjiu.lu@intel.com>
879
880 * i386-dis.c (print_insn): Parenthesize expression to prevent
881 truncated addresses.
882 (OP_J): Likewise.
883
4670103e
CZ		 8842016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
885 Janek van Oirschot <jvanoirs@synopsys.com>
886
b99747ae
CZ		 887 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
888 variable.
4670103e 889
c1d9289f
NC		 8902016-02-04 Nick Clifton <nickc@redhat.com>
891
892 PR target/19561
893 * msp430-dis.c (print_insn_msp430): Add a special case for
894 decoding an RRC instruction with the ZC bit set in the extension
895 word.
896
a143b004
AB		 8972016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
898
899 * cgen-ibld.in (insert_normal): Rework calculation of shift.
900 * epiphany-ibld.c: Regenerate.
901 * fr30-ibld.c: Regenerate.
902 * frv-ibld.c: Regenerate.
903 * ip2k-ibld.c: Regenerate.
904 * iq2000-ibld.c: Regenerate.
905 * lm32-ibld.c: Regenerate.
906 * m32c-ibld.c: Regenerate.
907 * m32r-ibld.c: Regenerate.
908 * mep-ibld.c: Regenerate.
909 * mt-ibld.c: Regenerate.
910 * or1k-ibld.c: Regenerate.
911 * xc16x-ibld.c: Regenerate.
912 * xstormy16-ibld.c: Regenerate.
913
b89807c6
AB		 9142016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
915
916 * epiphany-dis.c: Regenerated from latest cpu files.
917
d8c823c8
MM		 9182016-02-01 Michael McConville <mmcco@mykolab.com>
919
920 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
921 test bit.
922
5bc5ae88
RL		 9232016-01-25 Renlin Li <renlin.li@arm.com>
924
925 * arm-dis.c (mapping_symbol_for_insn): New function.
926 (find_ifthen_state): Call mapping_symbol_for_insn().
927
0bff6e2d
MW		 9282016-01-20 Matthew Wahab <matthew.wahab@arm.com>
929
930 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
931 of MSR UAO immediate operand.
932
100b4f2e
MR		 9332016-01-18 Maciej W. Rozycki <macro@imgtec.com>
934
935 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
936 instruction support.
937
5c14705f
AM		 9382016-01-17 Alan Modra <amodra@gmail.com>
939
940 * configure: Regenerate.
941
4d82fe66
NC		 9422016-01-14 Nick Clifton <nickc@redhat.com>
943
944 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
945 instructions that can support stack pointer operations.
946 * rl78-decode.c: Regenerate.
947 * rl78-dis.c: Fix display of stack pointer in MOVW based
948 instructions.
949
651657fa
MW		 9502016-01-14 Matthew Wahab <matthew.wahab@arm.com>
951
952 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
953 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
954 erxtatus_el1 and erxaddr_el1.
955
105bde57
MW		 9562016-01-12 Matthew Wahab <matthew.wahab@arm.com>
957
958 * arm-dis.c (arm_opcodes): Add "esb".
959 (thumb_opcodes): Likewise.
960
afa8d405
PB		 9612016-01-11 Peter Bergner <bergner@vnet.ibm.com>
962
963 * ppc-opc.c <xscmpnedp>: Delete.
964 <xvcmpnedp>: Likewise.
965 <xvcmpnedp.>: Likewise.
966 <xvcmpnesp>: Likewise.
967 <xvcmpnesp.>: Likewise.
968
83c3256e
AS		 9692016-01-08 Andreas Schwab <schwab@linux-m68k.org>
970
971 PR gas/13050
972 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
973 addition to ISA_A.
974
6f2750fe
AM		 9752016-01-01 Alan Modra <amodra@gmail.com>
976
977 Update year range in copyright notice of all files.
978
3499769a
AM		 979For older changes see ChangeLog-2015
980\f
981Copyright (C) 2016 Free Software Foundation, Inc.
982
983Copying and distribution of this file, with or without modification,
984are permitted in any medium without royalty provided the copyright
985notice and this notice are preserved.
986
987Local Variables:
988mode: change-log
989left-margin: 8
990fill-column: 74
991version-control: never
992End:
GDB Binutils - Deliverables
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