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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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6b477896
TS		 12016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
2
3 * arc-ext.h: Wrap in extern C.
4
bdd582db
GM		 52016-06-21 Graham Markall <graham.markall@embecosm.com>
6
7 * arc-dis.c (arc_insn_length): Add comment on instruction length.
8 Use same method for determining instruction length on ARC700 and
9 NPS-400.
10 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
11 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
12 with the NPS400 subclass.
13 * arc-opc.c: Likewise.
14
96074adc
JM		 152016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
16
17 * sparc-opc.c (rdasr): New macro.
18 (wrasr): Likewise.
19 (rdpr): Likewise.
20 (wrpr): Likewise.
21 (rdhpr): Likewise.
22 (wrhpr): Likewise.
23 (sparc_opcodes): Use the macros above to fix and expand the
24 definition of read/write instructions from/to
25 asr/privileged/hyperprivileged instructions.
26 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
27 %hva_mask_nz. Prefer softint_set and softint_clear over
28 set_softint and clear_softint.
29 (print_insn_sparc): Support %ver in Rd.
30
7a10c22f
JM		 312016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
32
33 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
34 architecture according to the hardware capabilities they require.
35
4f26fb3a
JM		 362016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
37
38 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
39 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
40 bfd_mach_sparc_v9{c,d,e,v,m}.
41 * sparc-opc.c (MASK_V9C): Define.
42 (MASK_V9D): Likewise.
43 (MASK_V9E): Likewise.
44 (MASK_V9V): Likewise.
45 (MASK_V9M): Likewise.
46 (v6): Add MASK_V9{C,D,E,V,M}.
47 (v6notlet): Likewise.
48 (v7): Likewise.
49 (v8): Likewise.
50 (v9): Likewise.
51 (v9andleon): Likewise.
52 (v9a): Likewise.
53 (v9b): Likewise.
54 (v9c): Define.
55 (v9d): Likewise.
56 (v9e): Likewise.
57 (v9v): Likewise.
58 (v9m): Likewise.
59 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
60
3ee6e4fb
NC		 612016-06-15 Nick Clifton <nickc@redhat.com>
62
63 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
64 constants to match expected behaviour.
65 (nds32_parse_opcode): Likewise. Also for whitespace.
66
02f3be19
AB		 672016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
68
69 * arc-opc.c (extract_rhv1): Extract value from insn.
70
6f9f37ed 712016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 72
73 * arc-nps400-tbl.h: Add ldbit instruction.
74 * arc-opc.c: Add flag classes required for ldbit.
75
6f9f37ed 762016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 77
78 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
79 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
80 support the above instructions.
81
6f9f37ed 822016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 83
84 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
85 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
86 csma, cbba, zncv, and hofs.
87 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
88 support the above instructions.
89
902016-06-06 Graham Markall <graham.markall@embecosm.com>
91
92 * arc-nps400-tbl.h: Add andab and orab instructions.
93
942016-06-06 Graham Markall <graham.markall@embecosm.com>
95
96 * arc-nps400-tbl.h: Add addl-like instructions.
97
982016-06-06 Graham Markall <graham.markall@embecosm.com>
99
100 * arc-nps400-tbl.h: Add mxb and imxb instructions.
101
1022016-06-06 Graham Markall <graham.markall@embecosm.com>
103
104 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
105 instructions.
106
b2cc3f6f
AK		 1072016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
108
109 * s390-dis.c (option_use_insn_len_bits_p): New file scope
110 variable.
111 (init_disasm): Handle new command line option "insnlength".
112 (print_s390_disassembler_options): Mention new option in help
113 output.
114 (print_insn_s390): Use the encoded insn length when dumping
115 unknown instructions.
116
1857fe72
DC		 1172016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
118
119 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
120 to the address and set as symbol address for LDS/ STS immediate operands.
121
14b57c7c
AM		 1222016-06-07 Alan Modra <amodra@gmail.com>
123
124 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
125 cpu for "vle" to e500.
126 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
127 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
128 (PPCNONE): Delete, substitute throughout.
129 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
130 except for major opcode 4 and 31.
131 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
132
4d1464f2
MW		 1332016-06-07 Matthew Wahab <matthew.wahab@arm.com>
134
135 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
136 ARM_EXT_RAS in relevant entries.
137
026122a6
PB		 1382016-06-03 Peter Bergner <bergner@vnet.ibm.com>
139
140 PR binutils/20196
141 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
142 opcodes for E6500.
143
07f5af7d
L		 1442016-06-03 H.J. Lu <hongjiu.lu@intel.com>
145
146 PR binutis/18386
147 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
148 (indir_v_mode): New.
149 Add comments for '&'.
150 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
151 (putop): Handle '&'.
152 (intel_operand_size): Handle indir_v_mode.
153 (OP_E_register): Likewise.
154 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
155 64-bit indirect call/jmp for AMD64.
156 * i386-tbl.h: Regenerated
157
4eb6f892
AB		 1582016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
159
160 * arc-dis.c (struct arc_operand_iterator): New structure.
161 (find_format_from_table): All the old content from find_format,
162 with some minor adjustments, and parameter renaming.
163 (find_format_long_instructions): New function.
164 (find_format): Rewritten.
165 (arc_insn_length): Add LSB parameter.
166 (extract_operand_value): New function.
167 (operand_iterator_next): New function.
168 (print_insn_arc): Use new functions to find opcode, and iterator
169 over operands.
170 * arc-opc.c (insert_nps_3bit_dst_short): New function.
171 (extract_nps_3bit_dst_short): New function.
172 (insert_nps_3bit_src2_short): New function.
173 (extract_nps_3bit_src2_short): New function.
174 (insert_nps_bitop1_size): New function.
175 (extract_nps_bitop1_size): New function.
176 (insert_nps_bitop2_size): New function.
177 (extract_nps_bitop2_size): New function.
178 (insert_nps_bitop_mod4_msb): New function.
179 (extract_nps_bitop_mod4_msb): New function.
180 (insert_nps_bitop_mod4_lsb): New function.
181 (extract_nps_bitop_mod4_lsb): New function.
182 (insert_nps_bitop_dst_pos3_pos4): New function.
183 (extract_nps_bitop_dst_pos3_pos4): New function.
184 (insert_nps_bitop_ins_ext): New function.
185 (extract_nps_bitop_ins_ext): New function.
186 (arc_operands): Add new operands.
187 (arc_long_opcodes): New global array.
188 (arc_num_long_opcodes): New global.
189 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
190
1fe0971e
TS		 1912016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
192
193 * nds32-asm.h: Add extern "C".
194 * sh-opc.h: Likewise.
195
315f180f
GM		 1962016-06-01 Graham Markall <graham.markall@embecosm.com>
197
198 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
199 0,b,limm to the rflt instruction.
200
a2b5fccc
TS		 2012016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
202
203 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
204 constant.
205
0cbd0046
L		 2062016-05-29 H.J. Lu <hongjiu.lu@intel.com>
207
208 PR gas/20145
209 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
210 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
211 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
212 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
213 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
214 * i386-init.h: Regenerated.
215
1848e567
L		 2162016-05-27 H.J. Lu <hongjiu.lu@intel.com>
217
218 PR gas/20145
219 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
220 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
221 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
222 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
223 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
224 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
225 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
226 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
227 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
228 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
229 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
230 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
231 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
232 CpuRegMask for AVX512.
233 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
234 and CpuRegMask.
235 (set_bitfield_from_cpu_flag_init): New function.
236 (set_bitfield): Remove const on f. Call
237 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
238 * i386-opc.h (CpuRegMMX): New.
239 (CpuRegXMM): Likewise.
240 (CpuRegYMM): Likewise.
241 (CpuRegZMM): Likewise.
242 (CpuRegMask): Likewise.
243 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
244 and cpuregmask.
245 * i386-init.h: Regenerated.
246 * i386-tbl.h: Likewise.
247
e92bae62
L		 2482016-05-27 H.J. Lu <hongjiu.lu@intel.com>
249
250 PR gas/20154
251 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
252 (opcode_modifiers): Add AMD64 and Intel64.
253 (main): Properly verify CpuMax.
254 * i386-opc.h (CpuAMD64): Removed.
255 (CpuIntel64): Likewise.
256 (CpuMax): Set to CpuNo64.
257 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
258 (AMD64): New.
259 (Intel64): Likewise.
260 (i386_opcode_modifier): Add amd64 and intel64.
261 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
262 on call and jmp.
263 * i386-init.h: Regenerated.
264 * i386-tbl.h: Likewise.
265
e89c5eaa
L		 2662016-05-27 H.J. Lu <hongjiu.lu@intel.com>
267
268 PR gas/20154
269 * i386-gen.c (main): Fail if CpuMax is incorrect.
270 * i386-opc.h (CpuMax): Set to CpuIntel64.
271 * i386-tbl.h: Regenerated.
272
77d66e7b
NC		 2732016-05-27 Nick Clifton <nickc@redhat.com>
274
275 PR target/20150
276 * msp430-dis.c (msp430dis_read_two_bytes): New function.
277 (msp430dis_opcode_unsigned): New function.
278 (msp430dis_opcode_signed): New function.
279 (msp430_singleoperand): Use the new opcode reading functions.
280 Only disassenmble bytes if they were successfully read.
281 (msp430_doubleoperand): Likewise.
282 (msp430_branchinstr): Likewise.
283 (msp430x_callx_instr): Likewise.
284 (print_insn_msp430): Check that it is safe to read bytes before
285 attempting disassembly. Use the new opcode reading functions.
286
19dfcc89
PB		 2872016-05-26 Peter Bergner <bergner@vnet.ibm.com>
288
289 * ppc-opc.c (CY): New define. Document it.
290 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
291
f3ad7637
L		 2922016-05-25 H.J. Lu <hongjiu.lu@intel.com>
293
294 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
295 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
296 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
297 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
298 CPU_ANY_AVX_FLAGS.
299 * i386-init.h: Regenerated.
300
f1360d58
L		 3012016-05-25 H.J. Lu <hongjiu.lu@intel.com>
302
303 PR gas/20141
304 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
305 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
306 * i386-init.h: Regenerated.
307
293f5f65
L		 3082016-05-25 H.J. Lu <hongjiu.lu@intel.com>
309
310 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
311 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
312 * i386-init.h: Regenerated.
313
d9eca1df
CZ		 3142016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
315
316 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
317 information.
318 (print_insn_arc): Set insn_type information.
319 * arc-opc.c (C_CC): Add F_CLASS_COND.
320 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
321 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
322 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
323 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
324 (brne, brne_s, jeq_s, jne_s): Likewise.
325
87789e08
CZ		 3262016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
327
328 * arc-tbl.h (neg): New instruction variant.
329
c810e0b8
CZ		 3302016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
331
332 * arc-dis.c (find_format, find_format, get_auxreg)
333 (print_insn_arc): Changed.
334 * arc-ext.h (INSERT_XOP): Likewise.
335
3d207518
TS		 3362016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
337
338 * tic54x-dis.c (sprint_mmr): Adjust.
339 * tic54x-opc.c: Likewise.
340
514e58b7
AM		 3412016-05-19 Alan Modra <amodra@gmail.com>
342
343 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
344
e43de63c
AM		 3452016-05-19 Alan Modra <amodra@gmail.com>
346
347 * ppc-opc.c: Formatting.
348 (NSISIGNOPT): Define.
349 (powerpc_opcodes <subis>): Use NSISIGNOPT.
350
1401d2fe
MR		 3512016-05-18 Maciej W. Rozycki <macro@imgtec.com>
352
353 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
354 replacing references to `micromips_ase' throughout.
355 (_print_insn_mips): Don't use file-level microMIPS annotation to
356 determine the disassembly mode with the symbol table.
357
1178da44
PB		 3582016-05-13 Peter Bergner <bergner@vnet.ibm.com>
359
360 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
361
8f4f9071
MF		 3622016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
363
364 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
365 mips64r6.
366 * mips-opc.c (D34): New macro.
367 (mips_builtin_opcodes): Define bposge32c for DSPr3.
368
8bc52696
AF		 3692016-05-10 Alexander Fomin <alexander.fomin@intel.com>
370
371 * i386-dis.c (prefix_table): Add RDPID instruction.
372 * i386-gen.c (cpu_flag_init): Add RDPID flag.
373 (cpu_flags): Add RDPID bitfield.
374 * i386-opc.h (enum): Add RDPID element.
375 (i386_cpu_flags): Add RDPID field.
376 * i386-opc.tbl: Add RDPID instruction.
377 * i386-init.h: Regenerate.
378 * i386-tbl.h: Regenerate.
379
39d911fc
TP		 3802016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
381
382 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
383 branch type of a symbol.
384 (print_insn): Likewise.
385
16a1fa25
TP		 3862016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
387
388 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
389 Mainline Security Extensions instructions.
390 (thumb_opcodes): Add entries for narrow ARMv8-M Security
391 Extensions instructions.
392 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
393 instructions.
394 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
395 special registers.
396
d751b79e
JM		 3972016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
398
399 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
400
945e0f82
CZ		 4012016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
402
403 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
404 (arcExtMap_genOpcode): Likewise.
405 * arc-opc.c (arg_32bit_rc): Define new variable.
406 (arg_32bit_u6): Likewise.
407 (arg_32bit_limm): Likewise.
408
20f55f38
SN		 4092016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
410
411 * aarch64-gen.c (VERIFIER): Define.
412 * aarch64-opc.c (VERIFIER): Define.
413 (verify_ldpsw): Use static linkage.
414 * aarch64-opc.h (verify_ldpsw): Remove.
415 * aarch64-tbl.h: Use VERIFIER for verifiers.
416
4bd13cde
NC		 4172016-04-28 Nick Clifton <nickc@redhat.com>
418
419 PR target/19722
420 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
421 * aarch64-opc.c (verify_ldpsw): New function.
422 * aarch64-opc.h (verify_ldpsw): New prototype.
423 * aarch64-tbl.h: Add initialiser for verifier field.
424 (LDPSW): Set verifier to verify_ldpsw.
425
c0f92bf9
L		 4262016-04-23 H.J. Lu <hongjiu.lu@intel.com>
427
428 PR binutils/19983
429 PR binutils/19984
430 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
431 smaller than address size.
432
e6c7cdec
TS		 4332016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
434
435 * alpha-dis.c: Regenerate.
436 * crx-dis.c: Likewise.
437 * disassemble.c: Likewise.
438 * epiphany-opc.c: Likewise.
439 * fr30-opc.c: Likewise.
440 * frv-opc.c: Likewise.
441 * ip2k-opc.c: Likewise.
442 * iq2000-opc.c: Likewise.
443 * lm32-opc.c: Likewise.
444 * lm32-opinst.c: Likewise.
445 * m32c-opc.c: Likewise.
446 * m32r-opc.c: Likewise.
447 * m32r-opinst.c: Likewise.
448 * mep-opc.c: Likewise.
449 * mt-opc.c: Likewise.
450 * or1k-opc.c: Likewise.
451 * or1k-opinst.c: Likewise.
452 * tic80-opc.c: Likewise.
453 * xc16x-opc.c: Likewise.
454 * xstormy16-opc.c: Likewise.
455
537aefaf
AB		 4562016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
457
458 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
459 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
460 calcsd, and calcxd instructions.
461 * arc-opc.c (insert_nps_bitop_size): Delete.
462 (extract_nps_bitop_size): Delete.
463 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
464 (extract_nps_qcmp_m3): Define.
465 (extract_nps_qcmp_m2): Define.
466 (extract_nps_qcmp_m1): Define.
467 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
468 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
469 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
470 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
471 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
472 NPS_QCMP_M3.
473
c8f785f2
AB		 4742016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
475
476 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
477
6fd8e7c2
L		 4782016-04-15 H.J. Lu <hongjiu.lu@intel.com>
479
480 * Makefile.in: Regenerated with automake 1.11.6.
481 * aclocal.m4: Likewise.
482
4b0c052e
AB		 4832016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
484
485 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
486 instructions.
487 * arc-opc.c (insert_nps_cmem_uimm16): New function.
488 (extract_nps_cmem_uimm16): New function.
489 (arc_operands): Add NPS_XLDST_UIMM16 operand.
490
cb040366
AB		 4912016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
492
493 * arc-dis.c (arc_insn_length): New function.
494 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
495 (find_format): Change insnLen parameter to unsigned.
496
accc0180
NC		 4972016-04-13 Nick Clifton <nickc@redhat.com>
498
499 PR target/19937
500 * v850-opc.c (v850_opcodes): Correct masks for long versions of
501 the LD.B and LD.BU instructions.
502
f36e33da
CZ		 5032016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
504
505 * arc-dis.c (find_format): Check for extension flags.
506 (print_flags): New function.
507 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
508 .extAuxRegister.
509 * arc-ext.c (arcExtMap_coreRegName): Use
510 LAST_EXTENSION_CORE_REGISTER.
511 (arcExtMap_coreReadWrite): Likewise.
512 (dump_ARC_extmap): Update printing.
513 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
514 (arc_aux_regs): Add cpu field.
515 * arc-regs.h: Add cpu field, lower case name aux registers.
516
1c2e355e
CZ		 5172016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
518
519 * arc-tbl.h: Add rtsc, sleep with no arguments.
520
b99747ae
CZ		 5212016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
522
523 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
524 Initialize.
525 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
526 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
527 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
528 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
529 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
530 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
531 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
532 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
533 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
534 (arc_opcode arc_opcodes): Null terminate the array.
535 (arc_num_opcodes): Remove.
536 * arc-ext.h (INSERT_XOP): Define.
537 (extInstruction_t): Likewise.
538 (arcExtMap_instName): Delete.
539 (arcExtMap_insn): New function.
540 (arcExtMap_genOpcode): Likewise.
541 * arc-ext.c (ExtInstruction): Remove.
542 (create_map): Zero initialize instruction fields.
543 (arcExtMap_instName): Remove.
544 (arcExtMap_insn): New function.
545 (dump_ARC_extmap): More info while debuging.
546 (arcExtMap_genOpcode): New function.
547 * arc-dis.c (find_format): New function.
548 (print_insn_arc): Use find_format.
549 (arc_get_disassembler): Enable dump_ARC_extmap only when
550 debugging.
551
92708cec
MR		 5522016-04-11 Maciej W. Rozycki <macro@imgtec.com>
553
554 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
555 instruction bits out.
556
a42a4f84
AB		 5572016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
558
559 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
560 * arc-opc.c (arc_flag_operands): Add new flags.
561 (arc_flag_classes): Add new classes.
562
1328504b
AB		 5632016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
564
565 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
566
820f03ff
AB		 5672016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
568
569 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
570 encode1, rflt, crc16, and crc32 instructions.
571 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
572 (arc_flag_classes): Add C_NPS_R.
573 (insert_nps_bitop_size_2b): New function.
574 (extract_nps_bitop_size_2b): Likewise.
575 (insert_nps_bitop_uimm8): Likewise.
576 (extract_nps_bitop_uimm8): Likewise.
577 (arc_operands): Add new operand entries.
578
8ddf6b2a
CZ		 5792016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
580
b99747ae
CZ		 581 * arc-regs.h: Add a new subclass field. Add double assist
582 accumulator register values.
583 * arc-tbl.h: Use DPA subclass to mark the double assist
584 instructions. Use DPX/SPX subclas to mark the FPX instructions.
585 * arc-opc.c (RSP): Define instead of SP.
586 (arc_aux_regs): Add the subclass field.
8ddf6b2a 587
589a7d88
JW		 5882016-04-05 Jiong Wang <jiong.wang@arm.com>
589
590 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
591
0a191de9 5922016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 593
594 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
595 NPS_R_SRC1.
596
0a106562
AB		 5972016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
598
599 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
600 issues. No functional changes.
601
bd05ac5f
CZ		 6022016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
603
b99747ae
CZ		 604 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
605 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
606 (RTT): Remove duplicate.
607 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
608 (PCT_CONFIG*): Remove.
609 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 610
9885948f
CZ		 6112016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
612
b99747ae 613 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 614
f2dd8838
CZ		 6152016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
616
b99747ae
CZ		 617 * arc-tbl.h (invld07): Remove.
618 * arc-ext-tbl.h: New file.
619 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
620 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 621
0d2f91fe
JK		 6222016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
623
624 Fix -Wstack-usage warnings.
625 * aarch64-dis.c (print_operands): Substitute size.
626 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
627
a6b71f42
JM		 6282016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
629
630 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
631 to get a proper diagnostic when an invalid ASR register is used.
632
9780e045
NC		 6332016-03-22 Nick Clifton <nickc@redhat.com>
634
635 * configure: Regenerate.
636
e23e8ebe
AB		 6372016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
638
639 * arc-nps400-tbl.h: New file.
640 * arc-opc.c: Add top level comment.
641 (insert_nps_3bit_dst): New function.
642 (extract_nps_3bit_dst): New function.
643 (insert_nps_3bit_src2): New function.
644 (extract_nps_3bit_src2): New function.
645 (insert_nps_bitop_size): New function.
646 (extract_nps_bitop_size): New function.
647 (arc_flag_operands): Add nps400 entries.
648 (arc_flag_classes): Add nps400 entries.
649 (arc_operands): Add nps400 entries.
650 (arc_opcodes): Add nps400 include.
651
1ae8ab47
AB		 6522016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
653
654 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
655 the new class enum values.
656
8699fc3e
AB		 6572016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
658
659 * arc-dis.c (print_insn_arc): Handle nps400.
660
24740d83
AB		 6612016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
662
663 * arc-opc.c (BASE): Delete.
664
8678914f
NC		 6652016-03-18 Nick Clifton <nickc@redhat.com>
666
667 PR target/19721
668 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
669 of MOV insn that aliases an ORR insn.
670
cc933301
JW		 6712016-03-16 Jiong Wang <jiong.wang@arm.com>
672
673 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
674
f86f5863
TS		 6752016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
676
677 * mcore-opc.h: Add const qualifiers.
678 * microblaze-opc.h (struct op_code_struct): Likewise.
679 * sh-opc.h: Likewise.
680 * tic4x-dis.c (tic4x_print_indirect): Likewise.
681 (tic4x_print_op): Likewise.
682
62de1c63
AM		 6832016-03-02 Alan Modra <amodra@gmail.com>
684
d11698cd 685 * or1k-desc.h: Regenerate.
62de1c63 686 * fr30-ibld.c: Regenerate.
c697cf0b 687 * rl78-decode.c: Regenerate.
62de1c63 688
020efce5
NC		 6892016-03-01 Nick Clifton <nickc@redhat.com>
690
691 PR target/19747
692 * rl78-dis.c (print_insn_rl78_common): Fix typo.
693
b0c11777
RL		 6942016-02-24 Renlin Li <renlin.li@arm.com>
695
696 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
697 (print_insn_coprocessor): Support fp16 instructions.
698
3e309328
RL		 6992016-02-24 Renlin Li <renlin.li@arm.com>
700
701 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
702 vminnm, vrint(mpna).
703
8afc7bea
RL		 7042016-02-24 Renlin Li <renlin.li@arm.com>
705
706 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
707 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
708
4fd7268a
L		 7092016-02-15 H.J. Lu <hongjiu.lu@intel.com>
710
711 * i386-dis.c (print_insn): Parenthesize expression to prevent
712 truncated addresses.
713 (OP_J): Likewise.
714
4670103e
CZ		 7152016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
716 Janek van Oirschot <jvanoirs@synopsys.com>
717
b99747ae
CZ		 718 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
719 variable.
4670103e 720
c1d9289f
NC		 7212016-02-04 Nick Clifton <nickc@redhat.com>
722
723 PR target/19561
724 * msp430-dis.c (print_insn_msp430): Add a special case for
725 decoding an RRC instruction with the ZC bit set in the extension
726 word.
727
a143b004
AB		 7282016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
729
730 * cgen-ibld.in (insert_normal): Rework calculation of shift.
731 * epiphany-ibld.c: Regenerate.
732 * fr30-ibld.c: Regenerate.
733 * frv-ibld.c: Regenerate.
734 * ip2k-ibld.c: Regenerate.
735 * iq2000-ibld.c: Regenerate.
736 * lm32-ibld.c: Regenerate.
737 * m32c-ibld.c: Regenerate.
738 * m32r-ibld.c: Regenerate.
739 * mep-ibld.c: Regenerate.
740 * mt-ibld.c: Regenerate.
741 * or1k-ibld.c: Regenerate.
742 * xc16x-ibld.c: Regenerate.
743 * xstormy16-ibld.c: Regenerate.
744
b89807c6
AB		 7452016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
746
747 * epiphany-dis.c: Regenerated from latest cpu files.
748
d8c823c8
MM		 7492016-02-01 Michael McConville <mmcco@mykolab.com>
750
751 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
752 test bit.
753
5bc5ae88
RL		 7542016-01-25 Renlin Li <renlin.li@arm.com>
755
756 * arm-dis.c (mapping_symbol_for_insn): New function.
757 (find_ifthen_state): Call mapping_symbol_for_insn().
758
0bff6e2d
MW		 7592016-01-20 Matthew Wahab <matthew.wahab@arm.com>
760
761 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
762 of MSR UAO immediate operand.
763
100b4f2e
MR		 7642016-01-18 Maciej W. Rozycki <macro@imgtec.com>
765
766 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
767 instruction support.
768
5c14705f
AM		 7692016-01-17 Alan Modra <amodra@gmail.com>
770
771 * configure: Regenerate.
772
4d82fe66
NC		 7732016-01-14 Nick Clifton <nickc@redhat.com>
774
775 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
776 instructions that can support stack pointer operations.
777 * rl78-decode.c: Regenerate.
778 * rl78-dis.c: Fix display of stack pointer in MOVW based
779 instructions.
780
651657fa
MW		 7812016-01-14 Matthew Wahab <matthew.wahab@arm.com>
782
783 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
784 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
785 erxtatus_el1 and erxaddr_el1.
786
105bde57
MW		 7872016-01-12 Matthew Wahab <matthew.wahab@arm.com>
788
789 * arm-dis.c (arm_opcodes): Add "esb".
790 (thumb_opcodes): Likewise.
791
afa8d405
PB		 7922016-01-11 Peter Bergner <bergner@vnet.ibm.com>
793
794 * ppc-opc.c <xscmpnedp>: Delete.
795 <xvcmpnedp>: Likewise.
796 <xvcmpnedp.>: Likewise.
797 <xvcmpnesp>: Likewise.
798 <xvcmpnesp.>: Likewise.
799
83c3256e
AS		 8002016-01-08 Andreas Schwab <schwab@linux-m68k.org>
801
802 PR gas/13050
803 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
804 addition to ISA_A.
805
6f2750fe
AM		 8062016-01-01 Alan Modra <amodra@gmail.com>
807
808 Update year range in copyright notice of all files.
809
3499769a
AM		 810For older changes see ChangeLog-2015
811\f
812Copyright (C) 2016 Free Software Foundation, Inc.
813
814Copying and distribution of this file, with or without modification,
815are permitted in any medium without royalty provided the copyright
816notice and this notice are preserved.
817
818Local Variables:
819mode: change-log
820left-margin: 8
821fill-column: 74
822version-control: never
823End:
GDB Binutils - Deliverables
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