Fix snafu with booleans in readelf patch - lack of a program header is not a reason...
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
7db2c588
JB
12017-02-24 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
4
1e9d41d4
SL
52017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
6
7 Add support for associating SPARC ASIs with an architecture level.
8 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
9 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
10 decoding of SPARC ASIs.
11
53c4d625
JB
122017-02-23 Jan Beulich <jbeulich@suse.com>
13
14 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
15 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
16
11648de5
JB
172017-02-21 Jan Beulich <jbeulich@suse.com>
18
19 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
20 1 (instead of to itself). Correct typo.
21
f98d33be
AW
222017-02-14 Andrew Waterman <andrew@sifive.com>
23
24 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
25 pseudoinstructions.
26
773fb663
RS
272017-02-15 Richard Sandiford <richard.sandiford@arm.com>
28
29 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
30 (aarch64_sys_reg_supported_p): Handle them.
31
cc07cda6
CZ
322017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
33
34 * arc-opc.c (UIMM6_20R): Define.
35 (SIMM12_20): Use above.
36 (SIMM12_20R): Define.
37 (SIMM3_5_S): Use above.
38 (UIMM7_A32_11R_S): Define.
39 (UIMM7_9_S): Use above.
40 (UIMM3_13R_S): Define.
41 (SIMM11_A32_7_S): Use above.
42 (SIMM9_8R): Define.
43 (UIMM10_A32_8_S): Use above.
44 (UIMM8_8R_S): Define.
45 (W6): Use above.
46 (arc_relax_opcodes): Use all above defines.
47
66a5a740
VG
482017-02-15 Vineet Gupta <vgupta@synopsys.com>
49
50 * arc-regs.h: Distinguish some of the registers different on
51 ARC700 and HS38 cpus.
52
7e0de605
AM
532017-02-14 Alan Modra <amodra@gmail.com>
54
55 PR 21118
56 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
57 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
58
54064fdb
AM
592017-02-11 Stafford Horne <shorne@gmail.com>
60 Alan Modra <amodra@gmail.com>
61
62 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
63 Use insn_bytes_value and insn_int_value directly instead. Don't
64 free allocated memory until function exit.
65
dce75bf9
NP
662017-02-10 Nicholas Piggin <npiggin@gmail.com>
67
68 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
69
1b7e3d2f
NC
702017-02-03 Nick Clifton <nickc@redhat.com>
71
72 PR 21096
73 * aarch64-opc.c (print_register_list): Ensure that the register
74 list index will fir into the tb buffer.
75 (print_register_offset_address): Likewise.
76 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
77
8ec5cf65
AD
782017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
79
80 PR 21056
81 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
82 instructions when the previous fetch packet ends with a 32-bit
83 instruction.
84
a1aa5e81
DD
852017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
86
87 * pru-opc.c: Remove vague reference to a future GDB port.
88
add3afb2
NC
892017-01-20 Nick Clifton <nickc@redhat.com>
90
91 * po/ga.po: Updated Irish translation.
92
c13a63b0
SN
932017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
94
95 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
96
9608051a
YQ
972017-01-13 Yao Qi <yao.qi@linaro.org>
98
99 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
100 if FETCH_DATA returns 0.
101 (m68k_scan_mask): Likewise.
102 (print_insn_m68k): Update code to handle -1 return value.
103
f622ea96
YQ
1042017-01-13 Yao Qi <yao.qi@linaro.org>
105
106 * m68k-dis.c (enum print_insn_arg_error): New.
107 (NEXTBYTE): Replace -3 with
108 PRINT_INSN_ARG_MEMORY_ERROR.
109 (NEXTULONG): Likewise.
110 (NEXTSINGLE): Likewise.
111 (NEXTDOUBLE): Likewise.
112 (NEXTDOUBLE): Likewise.
113 (NEXTPACKED): Likewise.
114 (FETCH_ARG): Likewise.
115 (FETCH_DATA): Update comments.
116 (print_insn_arg): Update comments. Replace magic numbers with
117 enum.
118 (match_insn_m68k): Likewise.
119
620214f7
IT
1202017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
121
122 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
123 * i386-dis-evex.h (evex_table): Updated.
124 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
125 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
126 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
127 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
128 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
129 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
130 * i386-init.h: Regenerate.
131 * i386-tbl.h: Ditto.
132
d95014a2
YQ
1332017-01-12 Yao Qi <yao.qi@linaro.org>
134
135 * msp430-dis.c (msp430_singleoperand): Return -1 if
136 msp430dis_opcode_signed returns false.
137 (msp430_doubleoperand): Likewise.
138 (msp430_branchinstr): Return -1 if
139 msp430dis_opcode_unsigned returns false.
140 (msp430x_calla_instr): Likewise.
141 (print_insn_msp430): Likewise.
142
0ae60c3e
NC
1432017-01-05 Nick Clifton <nickc@redhat.com>
144
145 PR 20946
146 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
147 could not be matched.
148 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
149 NULL.
150
d74d4880
SN
1512017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
152
153 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
154 (aarch64_opcode_table): Use RCPC_INSN.
155
cc917fd9
KC
1562017-01-03 Kito Cheng <kito.cheng@gmail.com>
157
158 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
159 extension.
160 * riscv-opcodes/all-opcodes: Likewise.
161
b52d3cfc
DP
1622017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
163
164 * riscv-dis.c (print_insn_args): Add fall through comment.
165
f90c58d5
NC
1662017-01-03 Nick Clifton <nickc@redhat.com>
167
168 * po/sr.po: New Serbian translation.
169 * configure.ac (ALL_LINGUAS): Add sr.
170 * configure: Regenerate.
171
f47b0d4a
AM
1722017-01-02 Alan Modra <amodra@gmail.com>
173
174 * epiphany-desc.h: Regenerate.
175 * epiphany-opc.h: Regenerate.
176 * fr30-desc.h: Regenerate.
177 * fr30-opc.h: Regenerate.
178 * frv-desc.h: Regenerate.
179 * frv-opc.h: Regenerate.
180 * ip2k-desc.h: Regenerate.
181 * ip2k-opc.h: Regenerate.
182 * iq2000-desc.h: Regenerate.
183 * iq2000-opc.h: Regenerate.
184 * lm32-desc.h: Regenerate.
185 * lm32-opc.h: Regenerate.
186 * m32c-desc.h: Regenerate.
187 * m32c-opc.h: Regenerate.
188 * m32r-desc.h: Regenerate.
189 * m32r-opc.h: Regenerate.
190 * mep-desc.h: Regenerate.
191 * mep-opc.h: Regenerate.
192 * mt-desc.h: Regenerate.
193 * mt-opc.h: Regenerate.
194 * or1k-desc.h: Regenerate.
195 * or1k-opc.h: Regenerate.
196 * xc16x-desc.h: Regenerate.
197 * xc16x-opc.h: Regenerate.
198 * xstormy16-desc.h: Regenerate.
199 * xstormy16-opc.h: Regenerate.
200
2571583a
AM
2012017-01-02 Alan Modra <amodra@gmail.com>
202
203 Update year range in copyright notice of all files.
204
5c1ad6b5 205For older changes see ChangeLog-2016
3499769a 206\f
5c1ad6b5 207Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM
208
209Copying and distribution of this file, with or without modification,
210are permitted in any medium without royalty provided the copyright
211notice and this notice are preserved.
212
213Local Variables:
214mode: change-log
215left-margin: 8
216fill-column: 74
217version-control: never
218End:
This page took 0.0809 seconds and 4 git commands to generate.