x86: Add {rex} pseudo prefix
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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6b6b6807
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12018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-opc.tbl: Add {rex},
4 * i386-tbl.h: Regenerated.
5
75f31665
MR
62018-02-20 Maciej W. Rozycki <macro@mips.com>
7
8 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
9 (mips16_opcodes): Replace `M' with `m' for "restore".
10
e207bc53
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112018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
12
13 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
14
87993319
MR
152018-02-13 Maciej W. Rozycki <macro@mips.com>
16
17 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
18 variable to `function_index'.
19
68d20676
NC
202018-02-13 Nick Clifton <nickc@redhat.com>
21
22 PR 22823
23 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
24 about truncation of printing.
25
d2159fdc
HW
262018-02-12 Henry Wong <henry@stuffedcow.net>
27
28 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
29
f174ef9f
NC
302018-02-05 Nick Clifton <nickc@redhat.com>
31
32 * po/pt_BR.po: Updated Brazilian Portuguese translation.
33
be3a8dca
IT
342018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
35
36 * i386-dis.c (enum): Add pconfig.
37 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
38 (cpu_flags): Add CpuPCONFIG.
39 * i386-opc.h (enum): Add CpuPCONFIG.
40 (i386_cpu_flags): Add cpupconfig.
41 * i386-opc.tbl: Add PCONFIG instruction.
42 * i386-init.h: Regenerate.
43 * i386-tbl.h: Likewise.
44
3233d7d0
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452018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
46
47 * i386-dis.c (enum): Add PREFIX_0F09.
48 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
49 (cpu_flags): Add CpuWBNOINVD.
50 * i386-opc.h (enum): Add CpuWBNOINVD.
51 (i386_cpu_flags): Add cpuwbnoinvd.
52 * i386-opc.tbl: Add WBNOINVD instruction.
53 * i386-init.h: Regenerate.
54 * i386-tbl.h: Likewise.
55
e925c834
JW
562018-01-17 Jim Wilson <jimw@sifive.com>
57
58 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
59
d777820b
IT
602018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
61
62 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
63 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
64 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
65 (cpu_flags): Add CpuIBT, CpuSHSTK.
66 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
67 (i386_cpu_flags): Add cpuibt, cpushstk.
68 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
69 * i386-init.h: Regenerate.
70 * i386-tbl.h: Likewise.
71
f6efed01
NC
722018-01-16 Nick Clifton <nickc@redhat.com>
73
74 * po/pt_BR.po: Updated Brazilian Portugese translation.
75 * po/de.po: Updated German translation.
76
2721d702
JW
772018-01-15 Jim Wilson <jimw@sifive.com>
78
79 * riscv-opc.c (match_c_nop): New.
80 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
81
616dcb87
NC
822018-01-15 Nick Clifton <nickc@redhat.com>
83
84 * po/uk.po: Updated Ukranian translation.
85
3957a496
NC
862018-01-13 Nick Clifton <nickc@redhat.com>
87
88 * po/opcodes.pot: Regenerated.
89
769c7ea5
NC
902018-01-13 Nick Clifton <nickc@redhat.com>
91
92 * configure: Regenerate.
93
faf766e3
NC
942018-01-13 Nick Clifton <nickc@redhat.com>
95
96 2.30 branch created.
97
888a89da
IT
982018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
99
100 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
101 * i386-tbl.h: Regenerate.
102
cbda583a
JB
1032018-01-10 Jan Beulich <jbeulich@suse.com>
104
105 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
106 * i386-tbl.h: Re-generate.
107
c9e92278
JB
1082018-01-10 Jan Beulich <jbeulich@suse.com>
109
110 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
111 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
112 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
113 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
114 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
115 Disp8MemShift of AVX512VL forms.
116 * i386-tbl.h: Re-generate.
117
35fd2b2b
JW
1182018-01-09 Jim Wilson <jimw@sifive.com>
119
120 * riscv-dis.c (maybe_print_address): If base_reg is zero,
121 then the hi_addr value is zero.
122
91d8b670
JG
1232018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
124
125 * arm-dis.c (arm_opcodes): Add csdb.
126 (thumb32_opcodes): Add csdb.
127
be2e7d95
JG
1282018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
129
130 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
131 * aarch64-asm-2.c: Regenerate.
132 * aarch64-dis-2.c: Regenerate.
133 * aarch64-opc-2.c: Regenerate.
134
704a705d
L
1352018-01-08 H.J. Lu <hongjiu.lu@intel.com>
136
137 PR gas/22681
138 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
139 Remove AVX512 vmovd with 64-bit operands.
140 * i386-tbl.h: Regenerated.
141
35eeb78f
JW
1422018-01-05 Jim Wilson <jimw@sifive.com>
143
144 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
145 jalr.
146
219d1afa
AM
1472018-01-03 Alan Modra <amodra@gmail.com>
148
149 Update year range in copyright notice of all files.
150
1508bbf5
JB
1512018-01-02 Jan Beulich <jbeulich@suse.com>
152
153 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
154 and OPERAND_TYPE_REGZMM entries.
155
1e563868 156For older changes see ChangeLog-2017
3499769a 157\f
1e563868 158Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
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159
160Copying and distribution of this file, with or without modification,
161are permitted in any medium without royalty provided the copyright
162notice and this notice are preserved.
163
164Local Variables:
165mode: change-log
166left-margin: 8
167fill-column: 74
168version-control: never
169End:
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