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3c374143
L		 12018-09-15 H.J. Lu <hongjiu.lu@intel.com>
2
3 PR gas/23665
4 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
5 VEX_LEN_0FD6_P_2 entries.
6 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
7 * i386-tbl.h: Regenerated.
8
6865c043
L		 92018-09-14 H.J. Lu <hongjiu.lu@intel.com>
10
11 PR gas/23642
12 * i386-opc.h (VEXWIG): New.
13 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
14 * i386-tbl.h: Regenerated.
15
70df6fc9
L		 162018-09-14 H.J. Lu <hongjiu.lu@intel.com>
17
18 PR binutils/23655
19 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
20 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
21 * i386-dis.c (EXxEVexR64): New.
22 (evex_rounding_64_mode): Likewise.
23 (OP_Rounding): Handle evex_rounding_64_mode.
24
d20dee9e
L		 252018-09-14 H.J. Lu <hongjiu.lu@intel.com>
26
27 PR binutils/23655
28 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
29 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
30 * i386-dis.c (Edqa): New.
31 (dqa_mode): Likewise.
32 (intel_operand_size): Handle dqa_mode as m_mode.
33 (OP_E_register): Handle dqa_mode as dq_mode.
34 (OP_E_memory): Set shift for dqa_mode based on address_mode.
35
5074ad8a
L		 362018-09-14 H.J. Lu <hongjiu.lu@intel.com>
37
38 * i386-dis.c (OP_E_memory): Reformat.
39
556059dd
JB		 402018-09-14 Jan Beulich <jbeulich@suse.com>
41
42 * i386-opc.tbl (crc32): Fold byte and word forms.
43 * i386-tbl.h: Re-generate.
44
41d1ab6a
L		 452018-09-13 H.J. Lu <hongjiu.lu@intel.com>
46
47 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
48 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
49 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
50 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
51 * i386-tbl.h: Regenerated.
52
57f6375e
JB		 532018-09-13 Jan Beulich <jbeulich@suse.com>
54
55 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
56 meaningless.
57 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
58 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
59 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
60 * i386-tbl.h: Re-generate.
61
2589a7e5
JB		 622018-09-13 Jan Beulich <jbeulich@suse.com>
63
64 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
65 AVX512_4VNNIW insns.
66 * i386-tbl.h: Re-generate.
67
a760eb41
JB		 682018-09-13 Jan Beulich <jbeulich@suse.com>
69
70 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
71 meaningless.
72 * i386-tbl.h: Re-generate.
73
e9042658
JB		 742018-09-13 Jan Beulich <jbeulich@suse.com>
75
76 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
77 meaningless.
78 * i386-tbl.h: Re-generate.
79
9caa306f
JB		 802018-09-13 Jan Beulich <jbeulich@suse.com>
81
82 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
83 meaningless.
84 * i386-tbl.h: Re-generate.
85
fb6ce599
JB		 862018-09-13 Jan Beulich <jbeulich@suse.com>
87
88 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
89 meaningless.
90 * i386-tbl.h: Re-generate.
91
6a8da886
JB		 922018-09-13 Jan Beulich <jbeulich@suse.com>
93
94 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
95 meaningless.
96 * i386-tbl.h: Re-generate.
97
c7f27919
JB		 982018-09-13 Jan Beulich <jbeulich@suse.com>
99
100 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
101 * i386-tbl.h: Re-generate.
102
0f407ee9
JB		 1032018-09-13 Jan Beulich <jbeulich@suse.com>
104
105 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
106 * i386-tbl.h: Re-generate.
107
2fbbbee5
JB		 1082018-09-13 Jan Beulich <jbeulich@suse.com>
109
110 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
111 meaningless.
112 * i386-tbl.h: Re-generate.
113
2b02b9a2
JB		 1142018-09-13 Jan Beulich <jbeulich@suse.com>
115
116 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
117 meaningless.
118 * i386-tbl.h: Re-generate.
119
963c68aa
JB		 1202018-09-13 Jan Beulich <jbeulich@suse.com>
121
122 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
123 * i386-tbl.h: Re-generate.
124
64e025c3
JB		 1252018-09-13 Jan Beulich <jbeulich@suse.com>
126
127 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
128 * i386-tbl.h: Re-generate.
129
47603f88
JB		 1302018-09-13 Jan Beulich <jbeulich@suse.com>
131
132 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
133 * i386-tbl.h: Re-generate.
134
0001cfd0
JB		 1352018-09-13 Jan Beulich <jbeulich@suse.com>
136
137 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
138 meaningless.
139 * i386-tbl.h: Re-generate.
140
be4b452e
JB		 1412018-09-13 Jan Beulich <jbeulich@suse.com>
142
143 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
144 meaningless.
145 * i386-tbl.h: Re-generate.
146
d09a1394
JB		 1472018-09-13 Jan Beulich <jbeulich@suse.com>
148
149 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
150 meaningless.
151 * i386-tbl.h: Re-generate.
152
07599e13
JB		 1532018-09-13 Jan Beulich <jbeulich@suse.com>
154
155 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
156 * i386-tbl.h: Re-generate.
157
1ee3e487
JB		 1582018-09-13 Jan Beulich <jbeulich@suse.com>
159
160 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
161 * i386-tbl.h: Re-generate.
162
a5f580e5
JB		 1632018-09-13 Jan Beulich <jbeulich@suse.com>
164
165 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
166 * i386-tbl.h: Re-generate.
167
49d5d12d
JB		 1682018-09-13 Jan Beulich <jbeulich@suse.com>
169
170 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
171 (vpbroadcastw, rdpid): Drop NoRex64.
172 * i386-tbl.h: Re-generate.
173
f5eb1d70
JB		 1742018-09-13 Jan Beulich <jbeulich@suse.com>
175
176 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
177 store templates, adding D.
178 * i386-tbl.h: Re-generate.
179
dbbc8b7e
JB		 1802018-09-13 Jan Beulich <jbeulich@suse.com>
181
182 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
183 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
184 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
185 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
186 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
187 Fold load and store templates where possible, adding D. Drop
188 IgnoreSize where it was pointlessly present. Drop redundant
189 *word.
190 * i386-tbl.h: Re-generate.
191
d276ec69
JB		 1922018-09-13 Jan Beulich <jbeulich@suse.com>
193
194 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
195 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
196 (intel_operand_size): Handle v_bndmk_mode.
197 (OP_E_memory): Likewise. Produce (bad) when also riprel.
198
9da4dfd6
JD		 1992018-09-08 John Darrington <john@darrington.wattle.id.au>
200
201 * disassemble.c (ARCH_s12z): Define if ARCH_all.
202
be192bc2
JW		 2032018-08-31 Kito Cheng <kito@andestech.com>
204
205 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
206 compressed floating point instructions.
207
43135d3b
JW		 2082018-08-30 Kito Cheng <kito@andestech.com>
209
210 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
211 riscv_opcode.xlen_requirement.
212 * riscv-opc.c (riscv_opcodes): Update for struct change.
213
df28970f
MA		 2142018-08-29 Martin Aberg <maberg@gaisler.com>
215
216 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
217 psr (PWRPSR) instruction.
218
9108bc33
CX		 2192018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
220
221 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
222
bd782c07
CX		 2232018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
224
225 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
226
ac8cb70f
CX		 2272018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
228
229 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
230 loongson3a as an alias of gs464 for compatibility.
231 * mips-opc.c (mips_opcodes): Change Comments.
232
a693765e
CX		 2332018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
234
235 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
236 option.
237 (print_mips_disassembler_options): Document -M loongson-ext.
238 * mips-opc.c (LEXT2): New macro.
239 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
240
bdc6c06e
CX		 2412018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
242
243 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
244 descriptors.
245 (parse_mips_ase_option): Handle -M loongson-ext option.
246 (print_mips_disassembler_options): Document -M loongson-ext.
247 * mips-opc.c (IL3A): Delete.
248 * mips-opc.c (LEXT): New macro.
249 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
250 instructions.
251
716c08de
CX		 2522018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
253
254 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
255 descriptors.
256 (parse_mips_ase_option): Handle -M loongson-cam option.
257 (print_mips_disassembler_options): Document -M loongson-cam.
258 * mips-opc.c (LCAM): New macro.
259 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
260 instructions.
261
9cf7e568
AM		 2622018-08-21 Alan Modra <amodra@gmail.com>
263
264 * ppc-dis.c (operand_value_powerpc): Init "invalid".
265 (skip_optional_operands): Count optional operands, and update
266 ppc_optional_operand_value call.
267 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
268 (extract_vlensi): Likewise.
269 (extract_fxm): Return default value for missing optional operand.
270 (extract_ls, extract_raq, extract_tbr): Likewise.
271 (insert_sxl, extract_sxl): New functions.
272 (insert_esync, extract_esync): Remove Power9 handling and simplify.
273 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
274 flag and extra entry.
275 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
276 extract_sxl.
277
d203b41a 2782018-08-20 Alan Modra <amodra@gmail.com>
f4107842 279
d203b41a 280 * sh-opc.h (MASK): Simplify.
f4107842 281
08a8fe2f 2822018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 283
d203b41a
AM		 284 * s12z-dis.c (bm_decode): Deal with cases where the mode is
285 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 286 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 287
08a8fe2f 2882018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 289
290 * s12z.h: Delete.
7ba3ba91 291
1bc60e56
L		 2922018-08-14 H.J. Lu <hongjiu.lu@intel.com>
293
294 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
295 address with the addr32 prefix and without base nor index
296 registers.
297
d871f3f4
L		 2982018-08-11 H.J. Lu <hongjiu.lu@intel.com>
299
300 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
301 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
302 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
303 (cpu_flags): Add CpuCMOV and CpuFXSR.
304 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
305 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
306 * i386-init.h: Regenerated.
307 * i386-tbl.h: Likewise.
308
b6523c37 3092018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
310
311 * arc-regs.h: Update auxiliary registers.
312
e968fc9b
JB		 3132018-08-06 Jan Beulich <jbeulich@suse.com>
314
315 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
316 (RegIP, RegIZ): Define.
317 * i386-reg.tbl: Adjust comments.
318 (rip): Use Qword instead of BaseIndex. Use RegIP.
319 (eip): Use Dword instead of BaseIndex. Use RegIP.
320 (riz): Add Qword. Use RegIZ.
321 (eiz): Add Dword. Use RegIZ.
322 * i386-tbl.h: Re-generate.
323
dbf8be89
JB		 3242018-08-03 Jan Beulich <jbeulich@suse.com>
325
326 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
327 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
328 vpmovzxdq, vpmovzxwd): Remove NoRex64.
329 * i386-tbl.h: Re-generate.
330
c48dadc9
JB		 3312018-08-03 Jan Beulich <jbeulich@suse.com>
332
333 * i386-gen.c (operand_types): Remove Mem field.
334 * i386-opc.h (union i386_operand_type): Remove mem field.
335 * i386-init.h, i386-tbl.h: Re-generate.
336
cb86a42a
AM		 3372018-08-01 Alan Modra <amodra@gmail.com>
338
339 * po/POTFILES.in: Regenerate.
340
07cc0450
NC		 3412018-07-31 Nick Clifton <nickc@redhat.com>
342
343 * po/sv.po: Updated Swedish translation.
344
1424ad86
JB		 3452018-07-31 Jan Beulich <jbeulich@suse.com>
346
347 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
348 * i386-init.h, i386-tbl.h: Re-generate.
349
ae2387fe
JB		 3502018-07-31 Jan Beulich <jbeulich@suse.com>
351
352 * i386-opc.h (ZEROING_MASKING) Rename to ...
353 (DYNAMIC_MASKING): ... this. Adjust comment.
354 * i386-opc.tbl (MaskingMorZ): Define.
355 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
356 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
357 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
358 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
359 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
360 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
361 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
362 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
363 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
364
6ff00b5e
JB		 3652018-07-31 Jan Beulich <jbeulich@suse.com>
366
367 * i386-opc.tbl: Use element rather than vector size for AVX512*
368 scatter/gather insns.
369 * i386-tbl.h: Re-generate.
370
e951d5ca
JB		 3712018-07-31 Jan Beulich <jbeulich@suse.com>
372
373 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
374 (cpu_flags): Drop CpuVREX.
375 * i386-opc.h (CpuVREX): Delete.
376 (union i386_cpu_flags): Remove cpuvrex.
377 * i386-init.h, i386-tbl.h: Re-generate.
378
eb41b248
JW		 3792018-07-30 Jim Wilson <jimw@sifive.com>
380
381 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
382 fields.
383 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
384
b8891f8d
AJ		 3852018-07-30 Andrew Jenner <andrew@codesourcery.com>
386
387 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
388 * Makefile.in: Regenerated.
389 * configure.ac: Add C-SKY.
390 * configure: Regenerated.
391 * csky-dis.c: New file.
392 * csky-opc.h: New file.
393 * disassemble.c (ARCH_csky): Define.
394 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
395 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
396
16065af1
AM		 3972018-07-27 Alan Modra <amodra@gmail.com>
398
399 * ppc-opc.c (insert_sprbat): Correct function parameter and
400 return type.
401 (extract_sprbat): Likewise, variable too.
402
fa758a70
AC		 4032018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
404 Alan Modra <amodra@gmail.com>
405
406 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
407 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
408 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
409 support disjointed BAT.
410 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
411 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
412 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
413
4a1b91ea
L		 4142018-07-25 H.J. Lu <hongjiu.lu@intel.com>
415 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
416
417 * i386-gen.c (adjust_broadcast_modifier): New function.
418 (process_i386_opcode_modifier): Add an argument for operands.
419 Adjust the Broadcast value based on operands.
420 (output_i386_opcode): Pass operand_types to
421 process_i386_opcode_modifier.
422 (process_i386_opcodes): Pass NULL as operands to
423 process_i386_opcode_modifier.
424 * i386-opc.h (BYTE_BROADCAST): New.
425 (WORD_BROADCAST): Likewise.
426 (DWORD_BROADCAST): Likewise.
427 (QWORD_BROADCAST): Likewise.
428 (i386_opcode_modifier): Expand broadcast to 3 bits.
429 * i386-tbl.h: Regenerated.
430
67ce483b
AM		 4312018-07-24 Alan Modra <amodra@gmail.com>
432
433 PR 23430
434 * or1k-desc.h: Regenerate.
435
4174bfff
JB		 4362018-07-24 Jan Beulich <jbeulich@suse.com>
437
438 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
439 vcvtusi2ss, and vcvtusi2sd.
440 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
441 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
442 * i386-tbl.h: Re-generate.
443
04e65276
CZ		 4442018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
445
446 * arc-opc.c (extract_w6): Fix extending the sign.
447
47e6f81c
CZ		 4482018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
449
450 * arc-tbl.h (vewt): Allow it for ARC EM family.
451
bb71536f
AM		 4522018-07-23 Alan Modra <amodra@gmail.com>
453
454 PR 23419
455 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
456 opcode variants for mtspr/mfspr encodings.
457
8095d2f7
CX		 4582018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
459 Maciej W. Rozycki <macro@mips.com>
460
461 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
462 loongson3a descriptors.
463 (parse_mips_ase_option): Handle -M loongson-mmi option.
464 (print_mips_disassembler_options): Document -M loongson-mmi.
465 * mips-opc.c (LMMI): New macro.
466 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
467 instructions.
468
5f32791e
JB		 4692018-07-19 Jan Beulich <jbeulich@suse.com>
470
471 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
472 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
473 IgnoreSize and [XYZ]MMword where applicable.
474 * i386-tbl.h: Re-generate.
475
625cbd7a
JB		 4762018-07-19 Jan Beulich <jbeulich@suse.com>
477
478 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
479 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
480 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
481 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
482 * i386-tbl.h: Re-generate.
483
86b15c32
JB		 4842018-07-19 Jan Beulich <jbeulich@suse.com>
485
486 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
487 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
488 VPCLMULQDQ templates into their respective AVX512VL counterparts
489 where possible, using Disp8ShiftVL and CheckRegSize instead of
490 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
491 * i386-tbl.h: Re-generate.
492
cf769ed5
JB		 4932018-07-19 Jan Beulich <jbeulich@suse.com>
494
495 * i386-opc.tbl: Fold AVX512DQ templates into their respective
496 AVX512VL counterparts where possible, using Disp8ShiftVL and
497 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
498 IgnoreSize) as appropriate.
499 * i386-tbl.h: Re-generate.
500
8282b7ad
JB		 5012018-07-19 Jan Beulich <jbeulich@suse.com>
502
503 * i386-opc.tbl: Fold AVX512BW templates into their respective
504 AVX512VL counterparts where possible, using Disp8ShiftVL and
505 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
506 IgnoreSize) as appropriate.
507 * i386-tbl.h: Re-generate.
508
755908cc
JB		 5092018-07-19 Jan Beulich <jbeulich@suse.com>
510
511 * i386-opc.tbl: Fold AVX512CD templates into their respective
512 AVX512VL counterparts where possible, using Disp8ShiftVL and
513 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
514 IgnoreSize) as appropriate.
515 * i386-tbl.h: Re-generate.
516
7091c612
JB		 5172018-07-19 Jan Beulich <jbeulich@suse.com>
518
519 * i386-opc.h (DISP8_SHIFT_VL): New.
520 * i386-opc.tbl (Disp8ShiftVL): Define.
521 (various): Fold AVX512VL templates into their respective
522 AVX512F counterparts where possible, using Disp8ShiftVL and
523 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
524 IgnoreSize) as appropriate.
525 * i386-tbl.h: Re-generate.
526
c30be56e
JB		 5272018-07-19 Jan Beulich <jbeulich@suse.com>
528
529 * Makefile.am: Change dependencies and rule for
530 $(srcdir)/i386-init.h.
531 * Makefile.in: Re-generate.
532 * i386-gen.c (process_i386_opcodes): New local variable
533 "marker". Drop opening of input file. Recognize marker and line
534 number directives.
535 * i386-opc.tbl (OPCODE_I386_H): Define.
536 (i386-opc.h): Include it.
537 (None): Undefine.
538
11a322db
L		 5392018-07-18 H.J. Lu <hongjiu.lu@intel.com>
540
541 PR gas/23418
542 * i386-opc.h (Byte): Update comments.
543 (Word): Likewise.
544 (Dword): Likewise.
545 (Fword): Likewise.
546 (Qword): Likewise.
547 (Tbyte): Likewise.
548 (Xmmword): Likewise.
549 (Ymmword): Likewise.
550 (Zmmword): Likewise.
551 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
552 vcvttps2uqq.
553 * i386-tbl.h: Regenerated.
554
cde3679e
NC		 5552018-07-12 Sudakshina Das <sudi.das@arm.com>
556
557 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
558 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
559 * aarch64-asm-2.c: Regenerate.
560 * aarch64-dis-2.c: Regenerate.
561 * aarch64-opc-2.c: Regenerate.
562
45a28947
TC		 5632018-07-12 Tamar Christina <tamar.christina@arm.com>
564
565 PR binutils/23192
566 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
567 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
568 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
569 sqdmulh, sqrdmulh): Use Em16.
570
c597cc3d
SD		 5712018-07-11 Sudakshina Das <sudi.das@arm.com>
572
573 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
574 csdb together with them.
575 (thumb32_opcodes): Likewise.
576
a79eaed6
JB		 5772018-07-11 Jan Beulich <jbeulich@suse.com>
578
579 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
580 requiring 32-bit registers as operands 2 and 3. Improve
581 comments.
582 (mwait, mwaitx): Fold templates. Improve comments.
583 OPERAND_TYPE_INOUTPORTREG.
584 * i386-tbl.h: Re-generate.
585
2fb5be8d
JB		 5862018-07-11 Jan Beulich <jbeulich@suse.com>
587
588 * i386-gen.c (operand_type_init): Remove
589 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
590 OPERAND_TYPE_INOUTPORTREG.
591 * i386-init.h: Re-generate.
592
7f5cad30
JB		 5932018-07-11 Jan Beulich <jbeulich@suse.com>
594
595 * i386-opc.tbl (wrssd, wrussd): Add Dword.
596 (wrssq, wrussq): Add Qword.
597 * i386-tbl.h: Re-generate.
598
f0a85b07
JB		 5992018-07-11 Jan Beulich <jbeulich@suse.com>
600
601 * i386-opc.h: Rename OTMax to OTNum.
602 (OTNumOfUints): Adjust calculation.
603 (OTUnused): Directly alias to OTNum.
604
9dcb0ba4
MR		 6052018-07-09 Maciej W. Rozycki <macro@mips.com>
606
607 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
608 `reg_xys'.
609 (lea_reg_xys): Likewise.
610 (print_insn_loop_primitive): Rename `reg' local variable to
611 `reg_dxy'.
612
f311ba7e
TC		 6132018-07-06 Tamar Christina <tamar.christina@arm.com>
614
615 PR binutils/23242
616 * aarch64-tbl.h (ldarh): Fix disassembly mask.
617
cba05feb
TC		 6182018-07-06 Tamar Christina <tamar.christina@arm.com>
619
620 PR binutils/23369
621 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
622 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
623
471b9d15
MR		 6242018-07-02 Maciej W. Rozycki <macro@mips.com>
625
626 PR tdep/8282
627 * mips-dis.c (mips_option_arg_t): New enumeration.
628 (mips_options): New variable.
629 (disassembler_options_mips): New function.
630 (print_mips_disassembler_options): Reimplement in terms of
631 `disassembler_options_mips'.
632 * arm-dis.c (disassembler_options_arm): Adapt to using the
633 `disasm_options_and_args_t' structure.
634 * ppc-dis.c (disassembler_options_powerpc): Likewise.
635 * s390-dis.c (disassembler_options_s390): Likewise.
636
c0c468d5
TP		 6372018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
638
639 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
640 expected result.
641 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
642 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
643 * testsuite/ld-arm/tls-longplt.d: Likewise.
644
369c9167
TC		 6452018-06-29 Tamar Christina <tamar.christina@arm.com>
646
647 PR binutils/23192
648 * aarch64-asm-2.c: Regenerate.
649 * aarch64-dis-2.c: Likewise.
650 * aarch64-opc-2.c: Likewise.
651 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
652 * aarch64-opc.c (operand_general_constraint_met_p,
653 aarch64_print_operand): Likewise.
654 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
655 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
656 fmlal2, fmlsl2.
657 (AARCH64_OPERANDS): Add Em2.
658
30aa1306
NC		 6592018-06-26 Nick Clifton <nickc@redhat.com>
660
661 * po/uk.po: Updated Ukranian translation.
662 * po/de.po: Updated German translation.
663 * po/pt_BR.po: Updated Brazilian Portuguese translation.
664
eca4b721
NC		 6652018-06-26 Nick Clifton <nickc@redhat.com>
666
667 * nfp-dis.c: Fix spelling mistake.
668
71300e2c
NC		 6692018-06-24 Nick Clifton <nickc@redhat.com>
670
671 * configure: Regenerate.
672 * po/opcodes.pot: Regenerate.
673
719d8288
NC		 6742018-06-24 Nick Clifton <nickc@redhat.com>
675
676 2.31 branch created.
677
514cd3a0
TC		 6782018-06-19 Tamar Christina <tamar.christina@arm.com>
679
680 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
681 * aarch64-asm-2.c: Regenerate.
682 * aarch64-dis-2.c: Likewise.
683
385e4d0f
MR		 6842018-06-21 Maciej W. Rozycki <macro@mips.com>
685
686 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
687 `-M ginv' option description.
688
160d1b3d
SH		 6892018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
690
691 PR gas/23305
692 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
693 la and lla.
694
d0ac1c44
SM		 6952018-06-19 Simon Marchi <simon.marchi@ericsson.com>
696
697 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
698 * configure.ac: Remove AC_PREREQ.
699 * Makefile.in: Re-generate.
700 * aclocal.m4: Re-generate.
701 * configure: Re-generate.
702
6f20c942
FS		 7032018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
704
705 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
706 mips64r6 descriptors.
707 (parse_mips_ase_option): Handle -Mginv option.
708 (print_mips_disassembler_options): Document -Mginv.
709 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
710 (GINV): New macro.
711 (mips_opcodes): Define ginvi and ginvt.
712
730c3174
SE		 7132018-06-13 Scott Egerton <scott.egerton@imgtec.com>
714 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
715
716 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
717 * mips-opc.c (CRC, CRC64): New macros.
718 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
719 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
720 crc32cd for CRC64.
721
cb366992
EB		 7222018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
723
724 PR 20319
725 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
726 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
727
ce72cd46
AM		 7282018-06-06 Alan Modra <amodra@gmail.com>
729
730 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
731 setjmp. Move init for some other vars later too.
732
4b8e28c7
MF		 7332018-06-04 Max Filippov <jcmvbkbc@gmail.com>
734
735 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
736 (dis_private): Add new fields for property section tracking.
737 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
738 (xtensa_instruction_fits): New functions.
739 (fetch_data): Bump minimal fetch size to 4.
740 (print_insn_xtensa): Make struct dis_private static.
741 Load and prepare property table on section change.
742 Don't disassemble literals. Don't disassemble instructions that
743 cross property table boundaries.
744
55e99962
L		 7452018-06-01 H.J. Lu <hongjiu.lu@intel.com>
746
747 * configure: Regenerated.
748
733bd0ab
JB		 7492018-06-01 Jan Beulich <jbeulich@suse.com>
750
751 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
752 * i386-tbl.h: Re-generate.
753
dfd27d41
JB		 7542018-06-01 Jan Beulich <jbeulich@suse.com>
755
756 * i386-opc.tbl (sldt, str): Add NoRex64.
757 * i386-tbl.h: Re-generate.
758
64795710
JB		 7592018-06-01 Jan Beulich <jbeulich@suse.com>
760
761 * i386-opc.tbl (invpcid): Add Oword.
762 * i386-tbl.h: Re-generate.
763
030157d8
AM		 7642018-06-01 Alan Modra <amodra@gmail.com>
765
766 * sysdep.h (_bfd_error_handler): Don't declare.
767 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
768 * rl78-decode.opc: Likewise.
769 * msp430-decode.c: Regenerate.
770 * rl78-decode.c: Regenerate.
771
a9660a6f
AP		 7722018-05-30 Amit Pawar <Amit.Pawar@amd.com>
773
774 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
775 * i386-init.h : Regenerated.
776
277eb7f6
AM		 7772018-05-25 Alan Modra <amodra@gmail.com>
778
779 * Makefile.in: Regenerate.
780 * po/POTFILES.in: Regenerate.
781
98553ad3
PB		 7822018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
783
784 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
785 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
786 (insert_bab, extract_bab, insert_btab, extract_btab,
787 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
788 (BAT, BBA VBA RBS XB6S): Delete macros.
789 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
790 (BB, BD, RBX, XC6): Update for new macros.
791 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
792 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
793 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
794 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
795
7b4ae824
JD		 7962018-05-18 John Darrington <john@darrington.wattle.id.au>
797
798 * Makefile.am: Add support for s12z architecture.
799 * configure.ac: Likewise.
800 * disassemble.c: Likewise.
801 * disassemble.h: Likewise.
802 * Makefile.in: Regenerate.
803 * configure: Regenerate.
804 * s12z-dis.c: New file.
805 * s12z.h: New file.
806
29e0f0a1
AM		 8072018-05-18 Alan Modra <amodra@gmail.com>
808
809 * nfp-dis.c: Don't #include libbfd.h.
810 (init_nfp3200_priv): Use bfd_get_section_contents.
811 (nit_nfp6000_mecsr_sec): Likewise.
812
809276d2
NC		 8132018-05-17 Nick Clifton <nickc@redhat.com>
814
815 * po/zh_CN.po: Updated simplified Chinese translation.
816
ff329288
TC		 8172018-05-16 Tamar Christina <tamar.christina@arm.com>
818
819 PR binutils/23109
820 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
821 * aarch64-dis-2.c: Regenerate.
822
f9830ec1
TC		 8232018-05-15 Tamar Christina <tamar.christina@arm.com>
824
825 PR binutils/21446
826 * aarch64-asm.c (opintl.h): Include.
827 (aarch64_ins_sysreg): Enforce read/write constraints.
828 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
829 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
830 (F_REG_READ, F_REG_WRITE): New.
831 * aarch64-opc.c (aarch64_print_operand): Generate notes for
832 AARCH64_OPND_SYSREG.
833 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
834 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
835 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
836 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
837 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
838 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
839 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
840 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
841 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
842 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
843 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
844 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
845 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
846 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
847 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
848 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
849 msr (F_SYS_WRITE), mrs (F_SYS_READ).
850
7d02540a
TC		 8512018-05-15 Tamar Christina <tamar.christina@arm.com>
852
853 PR binutils/21446
854 * aarch64-dis.c (no_notes: New.
855 (parse_aarch64_dis_option): Support notes.
856 (aarch64_decode_insn, print_operands): Likewise.
857 (print_aarch64_disassembler_options): Document notes.
858 * aarch64-opc.c (aarch64_print_operand): Support notes.
859
561a72d4
TC		 8602018-05-15 Tamar Christina <tamar.christina@arm.com>
861
862 PR binutils/21446
863 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
864 and take error struct.
865 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
866 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
867 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
868 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
869 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
870 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
871 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
872 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
873 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
874 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
875 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
876 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
877 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
878 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
879 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
880 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
881 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
882 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
883 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
884 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
885 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
886 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
887 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
888 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
889 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
890 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
891 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
892 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
893 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
894 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
895 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
896 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
897 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
898 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
899 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
900 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
901 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
902 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
903 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
904 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
905 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
906 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
907 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
908 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
909 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
910 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
911 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
912 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
913 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
914 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
915 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
916 (determine_disassembling_preference, aarch64_decode_insn,
917 print_insn_aarch64_word, print_insn_data): Take errors struct.
918 (print_insn_aarch64): Use errors.
919 * aarch64-asm-2.c: Regenerate.
920 * aarch64-dis-2.c: Regenerate.
921 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
922 boolean in aarch64_insert_operan.
923 (print_operand_extractor): Likewise.
924 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
925
1678bd35
FT		 9262018-05-15 Francois H. Theron <francois.theron@netronome.com>
927
928 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
929
06cfb1c8
L		 9302018-05-09 H.J. Lu <hongjiu.lu@intel.com>
931
932 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
933
84f9f8c3
AM		 9342018-05-09 Sebastian Rasmussen <sebras@gmail.com>
935
936 * cr16-opc.c (cr16_instruction): Comment typo fix.
937 * hppa-dis.c (print_insn_hppa): Likewise.
938
e6f372ba
JW		 9392018-05-08 Jim Wilson <jimw@sifive.com>
940
941 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
942 (match_c_slli64, match_srxi_as_c_srxi): New.
943 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
944 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
945 <c.slli, c.srli, c.srai>: Use match_s_slli.
946 <c.slli64, c.srli64, c.srai64>: New.
947
f413a913
AM		 9482018-05-08 Alan Modra <amodra@gmail.com>
949
950 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
951 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
952 partition opcode space for index lookup.
953
a87a6478
PB		 9542018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
955
956 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
957 <insn_length>: ...with this. Update usage.
958 Remove duplicate call to *info->memory_error_func.
959
c0a30a9f
L		 9602018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
961 H.J. Lu <hongjiu.lu@intel.com>
962
963 * i386-dis.c (Gva): New.
964 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
965 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
966 (prefix_table): New instructions (see prefix above).
967 (mod_table): New instructions (see prefix above).
968 (OP_G): Handle va_mode.
969 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
970 CPU_MOVDIR64B_FLAGS.
971 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
972 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
973 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
974 * i386-opc.tbl: Add movidir{i,64b}.
975 * i386-init.h: Regenerated.
976 * i386-tbl.h: Likewise.
977
75c0a438
L		 9782018-05-07 H.J. Lu <hongjiu.lu@intel.com>
979
980 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
981 AddrPrefixOpReg.
982 * i386-opc.h (AddrPrefixOp0): Renamed to ...
983 (AddrPrefixOpReg): This.
984 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
985 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
986
2ceb7719
PB		 9872018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
988
989 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
990 (vle_num_opcodes): Likewise.
991 (spe2_num_opcodes): Likewise.
992 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
993 initialization loop.
994 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
995 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
996 only once.
997
b3ac5c6c
TC		 9982018-05-01 Tamar Christina <tamar.christina@arm.com>
999
1000 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1001
fe944acf
FT		 10022018-04-30 Francois H. Theron <francois.theron@netronome.com>
1003
1004 Makefile.am: Added nfp-dis.c.
1005 configure.ac: Added bfd_nfp_arch.
1006 disassemble.h: Added print_insn_nfp prototype.
1007 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1008 nfp-dis.c: New, for NFP support.
1009 po/POTFILES.in: Added nfp-dis.c to the list.
1010 Makefile.in: Regenerate.
1011 configure: Regenerate.
1012
e2195274
JB		 10132018-04-26 Jan Beulich <jbeulich@suse.com>
1014
1015 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1016 templates into their base ones.
1017 * i386-tlb.h: Re-generate.
1018
59ef5df4
JB		 10192018-04-26 Jan Beulich <jbeulich@suse.com>
1020
1021 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1022 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1023 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1024 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1025 * i386-init.h: Re-generate.
1026
6e041cf4
JB		 10272018-04-26 Jan Beulich <jbeulich@suse.com>
1028
1029 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1030 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1031 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1032 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1033 comment.
1034 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1035 and CpuRegMask.
1036 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1037 CpuRegMask: Delete.
1038 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1039 cpuregzmm, and cpuregmask.
1040 * i386-init.h: Re-generate.
1041 * i386-tbl.h: Re-generate.
1042
0e0eea78
JB		 10432018-04-26 Jan Beulich <jbeulich@suse.com>
1044
1045 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1046 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1047 * i386-init.h: Re-generate.
1048
2f1bada2
JB		 10492018-04-26 Jan Beulich <jbeulich@suse.com>
1050
1051 * i386-gen.c (VexImmExt): Delete.
1052 * i386-opc.h (VexImmExt, veximmext): Delete.
1053 * i386-opc.tbl: Drop all VexImmExt uses.
1054 * i386-tlb.h: Re-generate.
1055
bacd1457
JB		 10562018-04-25 Jan Beulich <jbeulich@suse.com>
1057
1058 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1059 register-only forms.
1060 * i386-tlb.h: Re-generate.
1061
10bba94b
TC		 10622018-04-25 Tamar Christina <tamar.christina@arm.com>
1063
1064 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1065
c48935d7
IT		 10662018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1067
1068 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1069 PREFIX_0F1C.
1070 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1071 (cpu_flags): Add CpuCLDEMOTE.
1072 * i386-init.h: Regenerate.
1073 * i386-opc.h (enum): Add CpuCLDEMOTE,
1074 (i386_cpu_flags): Add cpucldemote.
1075 * i386-opc.tbl: Add cldemote.
1076 * i386-tbl.h: Regenerate.
1077
211dc24b
AM		 10782018-04-16 Alan Modra <amodra@gmail.com>
1079
1080 * Makefile.am: Remove sh5 and sh64 support.
1081 * configure.ac: Likewise.
1082 * disassemble.c: Likewise.
1083 * disassemble.h: Likewise.
1084 * sh-dis.c: Likewise.
1085 * sh64-dis.c: Delete.
1086 * sh64-opc.c: Delete.
1087 * sh64-opc.h: Delete.
1088 * Makefile.in: Regenerate.
1089 * configure: Regenerate.
1090 * po/POTFILES.in: Regenerate.
1091
a9a4b302
AM		 10922018-04-16 Alan Modra <amodra@gmail.com>
1093
1094 * Makefile.am: Remove w65 support.
1095 * configure.ac: Likewise.
1096 * disassemble.c: Likewise.
1097 * disassemble.h: Likewise.
1098 * w65-dis.c: Delete.
1099 * w65-opc.h: Delete.
1100 * Makefile.in: Regenerate.
1101 * configure: Regenerate.
1102 * po/POTFILES.in: Regenerate.
1103
04cb01fd
AM		 11042018-04-16 Alan Modra <amodra@gmail.com>
1105
1106 * configure.ac: Remove we32k support.
1107 * configure: Regenerate.
1108
c2bf1eec
AM		 11092018-04-16 Alan Modra <amodra@gmail.com>
1110
1111 * Makefile.am: Remove m88k support.
1112 * configure.ac: Likewise.
1113 * disassemble.c: Likewise.
1114 * disassemble.h: Likewise.
1115 * m88k-dis.c: Delete.
1116 * Makefile.in: Regenerate.
1117 * configure: Regenerate.
1118 * po/POTFILES.in: Regenerate.
1119
6793974d
AM		 11202018-04-16 Alan Modra <amodra@gmail.com>
1121
1122 * Makefile.am: Remove i370 support.
1123 * configure.ac: Likewise.
1124 * disassemble.c: Likewise.
1125 * disassemble.h: Likewise.
1126 * i370-dis.c: Delete.
1127 * i370-opc.c: Delete.
1128 * Makefile.in: Regenerate.
1129 * configure: Regenerate.
1130 * po/POTFILES.in: Regenerate.
1131
e82aa794
AM		 11322018-04-16 Alan Modra <amodra@gmail.com>
1133
1134 * Makefile.am: Remove h8500 support.
1135 * configure.ac: Likewise.
1136 * disassemble.c: Likewise.
1137 * disassemble.h: Likewise.
1138 * h8500-dis.c: Delete.
1139 * h8500-opc.h: Delete.
1140 * Makefile.in: Regenerate.
1141 * configure: Regenerate.
1142 * po/POTFILES.in: Regenerate.
1143
fceadf09
AM		 11442018-04-16 Alan Modra <amodra@gmail.com>
1145
1146 * configure.ac: Remove tahoe support.
1147 * configure: Regenerate.
1148
ae1d3843
L		 11492018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1150
1151 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1152 umwait.
1153 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1154 64-bit mode.
1155 * i386-tbl.h: Regenerated.
1156
de89d0a3
IT		 11572018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1158
1159 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1160 PREFIX_MOD_1_0FAE_REG_6.
1161 (va_mode): New.
1162 (OP_E_register): Use va_mode.
1163 * i386-dis-evex.h (prefix_table):
1164 New instructions (see prefixes above).
1165 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1166 (cpu_flags): Likewise.
1167 * i386-opc.h (enum): Likewise.
1168 (i386_cpu_flags): Likewise.
1169 * i386-opc.tbl: Add umonitor, umwait, tpause.
1170 * i386-init.h: Regenerate.
1171 * i386-tbl.h: Likewise.
1172
a8eb42a8
AM		 11732018-04-11 Alan Modra <amodra@gmail.com>
1174
1175 * opcodes/i860-dis.c: Delete.
1176 * opcodes/i960-dis.c: Delete.
1177 * Makefile.am: Remove i860 and i960 support.
1178 * configure.ac: Likewise.
1179 * disassemble.c: Likewise.
1180 * disassemble.h: Likewise.
1181 * Makefile.in: Regenerate.
1182 * configure: Regenerate.
1183 * po/POTFILES.in: Regenerate.
1184
caf0678c
L		 11852018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1186
1187 PR binutils/23025
1188 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1189 to 0.
1190 (print_insn): Clear vex instead of vex.evex.
1191
4fb0d2b9
NC		 11922018-04-04 Nick Clifton <nickc@redhat.com>
1193
1194 * po/es.po: Updated Spanish translation.
1195
c39e5b26
JB		 11962018-03-28 Jan Beulich <jbeulich@suse.com>
1197
1198 * i386-gen.c (opcode_modifiers): Delete VecESize.
1199 * i386-opc.h (VecESize): Delete.
1200 (struct i386_opcode_modifier): Delete vecesize.
1201 * i386-opc.tbl: Drop VecESize.
1202 * i386-tlb.h: Re-generate.
1203
8e6e0792
JB		 12042018-03-28 Jan Beulich <jbeulich@suse.com>
1205
1206 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1207 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1208 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1209 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1210 * i386-tlb.h: Re-generate.
1211
9f123b91
JB		 12122018-03-28 Jan Beulich <jbeulich@suse.com>
1213
1214 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1215 Fold AVX512 forms
1216 * i386-tlb.h: Re-generate.
1217
9646c87b
JB		 12182018-03-28 Jan Beulich <jbeulich@suse.com>
1219
1220 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1221 (vex_len_table): Drop Y for vcvt*2si.
1222 (putop): Replace plain 'Y' handling by abort().
1223
c8d59609
NC		 12242018-03-28 Nick Clifton <nickc@redhat.com>
1225
1226 PR 22988
1227 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1228 instructions with only a base address register.
1229 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1230 handle AARHC64_OPND_SVE_ADDR_R.
1231 (aarch64_print_operand): Likewise.
1232 * aarch64-asm-2.c: Regenerate.
1233 * aarch64_dis-2.c: Regenerate.
1234 * aarch64-opc-2.c: Regenerate.
1235
b8c169f3
JB		 12362018-03-22 Jan Beulich <jbeulich@suse.com>
1237
1238 * i386-opc.tbl: Drop VecESize from register only insn forms and
1239 memory forms not allowing broadcast.
1240 * i386-tlb.h: Re-generate.
1241
96bc132a
JB		 12422018-03-22 Jan Beulich <jbeulich@suse.com>
1243
1244 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1245 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1246 sha256*): Drop Disp<N>.
1247
9f79e886
JB		 12482018-03-22 Jan Beulich <jbeulich@suse.com>
1249
1250 * i386-dis.c (EbndS, bnd_swap_mode): New.
1251 (prefix_table): Use EbndS.
1252 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1253 * i386-opc.tbl (bndmov): Move misplaced Load.
1254 * i386-tlb.h: Re-generate.
1255
d6793fa1
JB		 12562018-03-22 Jan Beulich <jbeulich@suse.com>
1257
1258 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1259 templates allowing memory operands and folded ones for register
1260 only flavors.
1261 * i386-tlb.h: Re-generate.
1262
f7768225
JB		 12632018-03-22 Jan Beulich <jbeulich@suse.com>
1264
1265 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1266 256-bit templates. Drop redundant leftover Disp<N>.
1267 * i386-tlb.h: Re-generate.
1268
0e35537d
JW		 12692018-03-14 Kito Cheng <kito.cheng@gmail.com>
1270
1271 * riscv-opc.c (riscv_insn_types): New.
1272
b4a3689a
NC		 12732018-03-13 Nick Clifton <nickc@redhat.com>
1274
1275 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1276
d3d50934
L		 12772018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1278
1279 * i386-opc.tbl: Add Optimize to clr.
1280 * i386-tbl.h: Regenerated.
1281
bd5dea88
L		 12822018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1283
1284 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1285 * i386-opc.h (OldGcc): Removed.
1286 (i386_opcode_modifier): Remove oldgcc.
1287 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1288 instructions for old (<= 2.8.1) versions of gcc.
1289 * i386-tbl.h: Regenerated.
1290
e771e7c9
JB		 12912018-03-08 Jan Beulich <jbeulich@suse.com>
1292
1293 * i386-opc.h (EVEXDYN): New.
1294 * i386-opc.tbl: Fold various AVX512VL templates.
1295 * i386-tlb.h: Re-generate.
1296
ed438a93
JB		 12972018-03-08 Jan Beulich <jbeulich@suse.com>
1298
1299 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1300 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1301 vpexpandd, vpexpandq): Fold AFX512VF templates.
1302 * i386-tlb.h: Re-generate.
1303
454172a9
JB		 13042018-03-08 Jan Beulich <jbeulich@suse.com>
1305
1306 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1307 Fold 128- and 256-bit VEX-encoded templates.
1308 * i386-tlb.h: Re-generate.
1309
36824150
JB		 13102018-03-08 Jan Beulich <jbeulich@suse.com>
1311
1312 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1313 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1314 vpexpandd, vpexpandq): Fold AVX512F templates.
1315 * i386-tlb.h: Re-generate.
1316
e7f5c0a9
JB		 13172018-03-08 Jan Beulich <jbeulich@suse.com>
1318
1319 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1320 64-bit templates. Drop Disp<N>.
1321 * i386-tlb.h: Re-generate.
1322
25a4277f
JB		 13232018-03-08 Jan Beulich <jbeulich@suse.com>
1324
1325 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1326 and 256-bit templates.
1327 * i386-tlb.h: Re-generate.
1328
d2224064
JB		 13292018-03-08 Jan Beulich <jbeulich@suse.com>
1330
1331 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1332 * i386-tlb.h: Re-generate.
1333
1b193f0b
JB		 13342018-03-08 Jan Beulich <jbeulich@suse.com>
1335
1336 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1337 Drop NoAVX.
1338 * i386-tlb.h: Re-generate.
1339
f2f6a710
JB		 13402018-03-08 Jan Beulich <jbeulich@suse.com>
1341
1342 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1343 * i386-tlb.h: Re-generate.
1344
38e314eb
JB		 13452018-03-08 Jan Beulich <jbeulich@suse.com>
1346
1347 * i386-gen.c (opcode_modifiers): Delete FloatD.
1348 * i386-opc.h (FloatD): Delete.
1349 (struct i386_opcode_modifier): Delete floatd.
1350 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1351 FloatD by D.
1352 * i386-tlb.h: Re-generate.
1353
d53e6b98
JB		 13542018-03-08 Jan Beulich <jbeulich@suse.com>
1355
1356 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1357
2907c2f5
JB		 13582018-03-08 Jan Beulich <jbeulich@suse.com>
1359
1360 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1361 * i386-tlb.h: Re-generate.
1362
73053c1f
JB		 13632018-03-08 Jan Beulich <jbeulich@suse.com>
1364
1365 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1366 forms.
1367 * i386-tlb.h: Re-generate.
1368
52fe4420
AM		 13692018-03-07 Alan Modra <amodra@gmail.com>
1370
1371 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1372 bfd_arch_rs6000.
1373 * disassemble.h (print_insn_rs6000): Delete.
1374 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1375 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1376 (print_insn_rs6000): Delete.
1377
a6743a54
AM		 13782018-03-03 Alan Modra <amodra@gmail.com>
1379
1380 * sysdep.h (opcodes_error_handler): Define.
1381 (_bfd_error_handler): Declare.
1382 * Makefile.am: Remove stray #.
1383 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1384 EDIT" comment.
1385 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1386 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1387 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1388 opcodes_error_handler to print errors. Standardize error messages.
1389 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1390 and include opintl.h.
1391 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1392 * i386-gen.c: Standardize error messages.
1393 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1394 * Makefile.in: Regenerate.
1395 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1396 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1397 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1398 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1399 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1400 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1401 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1402 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1403 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1404 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1405 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1406 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1407 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1408
8305403a
L		 14092018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1410
1411 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1412 vpsub[bwdq] instructions.
1413 * i386-tbl.h: Regenerated.
1414
e184813f
AM		 14152018-03-01 Alan Modra <amodra@gmail.com>
1416
1417 * configure.ac (ALL_LINGUAS): Sort.
1418 * configure: Regenerate.
1419
5b616bef
TP		 14202018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1421
1422 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1423 macro by assignements.
1424
b6f8c7c4
L		 14252018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1426
1427 PR gas/22871
1428 * i386-gen.c (opcode_modifiers): Add Optimize.
1429 * i386-opc.h (Optimize): New enum.
1430 (i386_opcode_modifier): Add optimize.
1431 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1432 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1433 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1434 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1435 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1436 vpxord and vpxorq.
1437 * i386-tbl.h: Regenerated.
1438
e95b887f
AM		 14392018-02-26 Alan Modra <amodra@gmail.com>
1440
1441 * crx-dis.c (getregliststring): Allocate a large enough buffer
1442 to silence false positive gcc8 warning.
1443
0bccfb29
JW		 14442018-02-22 Shea Levy <shea@shealevy.com>
1445
1446 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1447
6b6b6807
L		 14482018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1449
1450 * i386-opc.tbl: Add {rex},
1451 * i386-tbl.h: Regenerated.
1452
75f31665
MR		 14532018-02-20 Maciej W. Rozycki <macro@mips.com>
1454
1455 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1456 (mips16_opcodes): Replace `M' with `m' for "restore".
1457
e207bc53
TP		 14582018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1459
1460 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1461
87993319
MR		 14622018-02-13 Maciej W. Rozycki <macro@mips.com>
1463
1464 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1465 variable to `function_index'.
1466
68d20676
NC		 14672018-02-13 Nick Clifton <nickc@redhat.com>
1468
1469 PR 22823
1470 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1471 about truncation of printing.
1472
d2159fdc
HW		 14732018-02-12 Henry Wong <henry@stuffedcow.net>
1474
1475 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1476
f174ef9f
NC		 14772018-02-05 Nick Clifton <nickc@redhat.com>
1478
1479 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1480
be3a8dca
IT		 14812018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1482
1483 * i386-dis.c (enum): Add pconfig.
1484 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1485 (cpu_flags): Add CpuPCONFIG.
1486 * i386-opc.h (enum): Add CpuPCONFIG.
1487 (i386_cpu_flags): Add cpupconfig.
1488 * i386-opc.tbl: Add PCONFIG instruction.
1489 * i386-init.h: Regenerate.
1490 * i386-tbl.h: Likewise.
1491
3233d7d0
IT		 14922018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1493
1494 * i386-dis.c (enum): Add PREFIX_0F09.
1495 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1496 (cpu_flags): Add CpuWBNOINVD.
1497 * i386-opc.h (enum): Add CpuWBNOINVD.
1498 (i386_cpu_flags): Add cpuwbnoinvd.
1499 * i386-opc.tbl: Add WBNOINVD instruction.
1500 * i386-init.h: Regenerate.
1501 * i386-tbl.h: Likewise.
1502
e925c834
JW		 15032018-01-17 Jim Wilson <jimw@sifive.com>
1504
1505 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1506
d777820b
IT		 15072018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1508
1509 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1510 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1511 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1512 (cpu_flags): Add CpuIBT, CpuSHSTK.
1513 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1514 (i386_cpu_flags): Add cpuibt, cpushstk.
1515 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1516 * i386-init.h: Regenerate.
1517 * i386-tbl.h: Likewise.
1518
f6efed01
NC		 15192018-01-16 Nick Clifton <nickc@redhat.com>
1520
1521 * po/pt_BR.po: Updated Brazilian Portugese translation.
1522 * po/de.po: Updated German translation.
1523
2721d702
JW		 15242018-01-15 Jim Wilson <jimw@sifive.com>
1525
1526 * riscv-opc.c (match_c_nop): New.
1527 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1528
616dcb87
NC		 15292018-01-15 Nick Clifton <nickc@redhat.com>
1530
1531 * po/uk.po: Updated Ukranian translation.
1532
3957a496
NC		 15332018-01-13 Nick Clifton <nickc@redhat.com>
1534
1535 * po/opcodes.pot: Regenerated.
1536
769c7ea5
NC		 15372018-01-13 Nick Clifton <nickc@redhat.com>
1538
1539 * configure: Regenerate.
1540
faf766e3
NC		 15412018-01-13 Nick Clifton <nickc@redhat.com>
1542
1543 2.30 branch created.
1544
888a89da
IT		 15452018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1546
1547 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1548 * i386-tbl.h: Regenerate.
1549
cbda583a
JB		 15502018-01-10 Jan Beulich <jbeulich@suse.com>
1551
1552 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1553 * i386-tbl.h: Re-generate.
1554
c9e92278
JB		 15552018-01-10 Jan Beulich <jbeulich@suse.com>
1556
1557 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1558 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1559 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1560 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1561 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1562 Disp8MemShift of AVX512VL forms.
1563 * i386-tbl.h: Re-generate.
1564
35fd2b2b
JW		 15652018-01-09 Jim Wilson <jimw@sifive.com>
1566
1567 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1568 then the hi_addr value is zero.
1569
91d8b670
JG		 15702018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1571
1572 * arm-dis.c (arm_opcodes): Add csdb.
1573 (thumb32_opcodes): Add csdb.
1574
be2e7d95
JG		 15752018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1576
1577 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1578 * aarch64-asm-2.c: Regenerate.
1579 * aarch64-dis-2.c: Regenerate.
1580 * aarch64-opc-2.c: Regenerate.
1581
704a705d
L		 15822018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1583
1584 PR gas/22681
1585 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1586 Remove AVX512 vmovd with 64-bit operands.
1587 * i386-tbl.h: Regenerated.
1588
35eeb78f
JW		 15892018-01-05 Jim Wilson <jimw@sifive.com>
1590
1591 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1592 jalr.
1593
219d1afa
AM		 15942018-01-03 Alan Modra <amodra@gmail.com>
1595
1596 Update year range in copyright notice of all files.
1597
1508bbf5
JB		 15982018-01-02 Jan Beulich <jbeulich@suse.com>
1599
1600 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1601 and OPERAND_TYPE_REGZMM entries.
1602
1e563868 1603For older changes see ChangeLog-2017
3499769a 1604\f
1e563868 1605Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1606
1607Copying and distribution of this file, with or without modification,
1608are permitted in any medium without royalty provided the copyright
1609notice and this notice are preserved.
1610
1611Local Variables:
1612mode: change-log
1613left-margin: 8
1614fill-column: 74
1615version-control: never
1616End:
GDB Binutils - Deliverables
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