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Linker: Remove support for -Map= with an empty argument.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
25e1eca8
SL		 12020-05-26 Sandra Loosemore <sandra@codesourcery.com>
2
3 Fix extraction of signed constants in nios2 disassembler (again).
4
5 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
6 extractions of signed fields.
7
57b17940
SSF		 82020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
9
10 * s390-opc.txt: Relocate vector load/store instructions with
11 additional alignment parameter and change architecture level
12 constraint from z14 to z13.
13
d96bf37b
AM		 142020-05-21 Alan Modra <amodra@gmail.com>
15
16 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
17 * sparc-dis.c: Likewise.
18 * tic4x-dis.c: Likewise.
19 * xtensa-dis.c: Likewise.
20 * bpf-desc.c: Regenerate.
21 * epiphany-desc.c: Regenerate.
22 * fr30-desc.c: Regenerate.
23 * frv-desc.c: Regenerate.
24 * ip2k-desc.c: Regenerate.
25 * iq2000-desc.c: Regenerate.
26 * lm32-desc.c: Regenerate.
27 * m32c-desc.c: Regenerate.
28 * m32r-desc.c: Regenerate.
29 * mep-asm.c: Regenerate.
30 * mep-desc.c: Regenerate.
31 * mt-desc.c: Regenerate.
32 * or1k-desc.c: Regenerate.
33 * xc16x-desc.c: Regenerate.
34 * xstormy16-desc.c: Regenerate.
35
8f595e9b
NC		 362020-05-20 Nelson Chu <nelson.chu@sifive.com>
37
38 * riscv-opc.c (riscv_ext_version_table): The table used to store
39 all information about the supported spec and the corresponding ISA
40 versions. Currently, only Zicsr is supported to verify the
41 correctness of Z sub extension settings. Others will be supported
42 in the future patches.
43 (struct isa_spec_t, isa_specs): List for all supported ISA spec
44 classes and the corresponding strings.
45 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
46 spec class by giving a ISA spec string.
47 * riscv-opc.c (struct priv_spec_t): New structure.
48 (struct priv_spec_t priv_specs): List for all supported privilege spec
49 classes and the corresponding strings.
50 (riscv_get_priv_spec_class): New function. Get the corresponding
51 privilege spec class by giving a spec string.
52 (riscv_get_priv_spec_name): New function. Get the corresponding
53 privilege spec string by giving a CSR version class.
54 * riscv-dis.c: Updated since DECLARE_CSR is changed.
55 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
56 according to the chosen version. Build a hash table riscv_csr_hash to
57 store the valid CSR for the chosen pirv verison. Dump the direct
58 CSR address rather than it's name if it is invalid.
59 (parse_riscv_dis_option_without_args): New function. Parse the options
60 without arguments.
61 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
62 parse the options without arguments first, and then handle the options
63 with arguments. Add the new option -Mpriv-spec, which has argument.
64 * riscv-dis.c (print_riscv_disassembler_options): Add description
65 about the new OBJDUMP option.
66
3d205eb4
PB		 672020-05-19 Peter Bergner <bergner@linux.ibm.com>
68
69 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
70 WC values on POWER10 sync, dcbf and wait instructions.
71 (insert_pl, extract_pl): New functions.
72 (L2OPT, LS, WC): Use insert_ls and extract_ls.
73 (LS3): New , 3-bit L for sync.
74 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
75 (SC2, PL): New, 2-bit SC and PL for sync and wait.
76 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
77 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
78 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
79 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
80 <wait>: Enable PL operand on POWER10.
81 <dcbf>: Enable L3OPT operand on POWER10.
82 <sync>: Enable SC2 operand on POWER10.
83
a501eb44
SH		 842020-05-19 Stafford Horne <shorne@gmail.com>
85
86 PR 25184
87 * or1k-asm.c: Regenerate.
88 * or1k-desc.c: Regenerate.
89 * or1k-desc.h: Regenerate.
90 * or1k-dis.c: Regenerate.
91 * or1k-ibld.c: Regenerate.
92 * or1k-opc.c: Regenerate.
93 * or1k-opc.h: Regenerate.
94 * or1k-opinst.c: Regenerate.
95
3b646889
AM		 962020-05-11 Alan Modra <amodra@gmail.com>
97
98 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
99 xsmaxcqp, xsmincqp.
100
9cc4ce88
AM		 1012020-05-11 Alan Modra <amodra@gmail.com>
102
103 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
104 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
105
5d57bc3f
AM		 1062020-05-11 Alan Modra <amodra@gmail.com>
107
108 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
109
66ef5847
AM		 1102020-05-11 Alan Modra <amodra@gmail.com>
111
112 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
113 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
114
4f3e9537
PB		 1152020-05-11 Peter Bergner <bergner@linux.ibm.com>
116
117 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
118 mnemonics.
119
ec40e91c
AM		 1202020-05-11 Alan Modra <amodra@gmail.com>
121
122 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
123 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
124 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
125 (prefix_opcodes): Add xxeval.
126
d7e97a76
AM		 1272020-05-11 Alan Modra <amodra@gmail.com>
128
129 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
130 xxgenpcvwm, xxgenpcvdm.
131
fdefed7c
AM		 1322020-05-11 Alan Modra <amodra@gmail.com>
133
134 * ppc-opc.c (MP, VXVAM_MASK): Define.
135 (VXVAPS_MASK): Use VXVA_MASK.
136 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
137 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
138 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
139 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
140
aa3c112f
AM		 1412020-05-11 Alan Modra <amodra@gmail.com>
142 Peter Bergner <bergner@linux.ibm.com>
143
144 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
145 New functions.
146 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
147 YMSK2, XA6a, XA6ap, XB6a entries.
148 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
149 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
150 (PPCVSX4): Define.
151 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
152 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
153 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
154 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
155 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
156 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
157 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
158 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
159 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
160 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
161 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
162 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
163 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
164 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
165
6edbfd3b
AM		 1662020-05-11 Alan Modra <amodra@gmail.com>
167
168 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
169 (insert_xts, extract_xts): New functions.
170 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
171 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
172 (VXRC_MASK, VXSH_MASK): Define.
173 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
174 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
175 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
176 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
177 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
178 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
179 xxblendvh, xxblendvw, xxblendvd, xxpermx.
180
c7d7aea2
AM		 1812020-05-11 Alan Modra <amodra@gmail.com>
182
183 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
184 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
185 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
186 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
187 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
188
94ba9882
AM		 1892020-05-11 Alan Modra <amodra@gmail.com>
190
191 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
192 (XTP, DQXP, DQXP_MASK): Define.
193 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
194 (prefix_opcodes): Add plxvp and pstxvp.
195
f4791f1a
AM		 1962020-05-11 Alan Modra <amodra@gmail.com>
197
198 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
199 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
200 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
201
3ff0a5ba
PB		 2022020-05-11 Peter Bergner <bergner@linux.ibm.com>
203
204 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
205
afef4fe9
PB		 2062020-05-11 Peter Bergner <bergner@linux.ibm.com>
207
208 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
209 (L1OPT): Define.
210 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
211
1224c05d
PB		 2122020-05-11 Peter Bergner <bergner@linux.ibm.com>
213
214 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
215
6bbb0c05
AM		 2162020-05-11 Alan Modra <amodra@gmail.com>
217
218 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
219
7c1f4227
AM		 2202020-05-11 Alan Modra <amodra@gmail.com>
221
222 * ppc-dis.c (ppc_opts): Add "power10" entry.
223 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
224 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
225
73199c2b
NC		 2262020-05-11 Nick Clifton <nickc@redhat.com>
227
228 * po/fr.po: Updated French translation.
229
09c1e68a
AC		 2302020-04-30 Alex Coplan <alex.coplan@arm.com>
231
232 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
233 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
234 (operand_general_constraint_met_p): validate
235 AARCH64_OPND_UNDEFINED.
236 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
237 for FLD_imm16_2.
238 * aarch64-asm-2.c: Regenerated.
239 * aarch64-dis-2.c: Regenerated.
240 * aarch64-opc-2.c: Regenerated.
241
9654d51a
NC		 2422020-04-29 Nick Clifton <nickc@redhat.com>
243
244 PR 22699
245 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
246 and SETRC insns.
247
c2e71e57
NC		 2482020-04-29 Nick Clifton <nickc@redhat.com>
249
250 * po/sv.po: Updated Swedish translation.
251
5c936ef5
NC		 2522020-04-29 Nick Clifton <nickc@redhat.com>
253
254 PR 22699
255 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
256 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
257 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
258 IMM0_8U case.
259
bb2a1453
AS		 2602020-04-21 Andreas Schwab <schwab@linux-m68k.org>
261
262 PR 25848
263 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
264 cmpi only on m68020up and cpu32.
265
c2e5c986
SD		 2662020-04-20 Sudakshina Das <sudi.das@arm.com>
267
268 * aarch64-asm.c (aarch64_ins_none): New.
269 * aarch64-asm.h (ins_none): New declaration.
270 * aarch64-dis.c (aarch64_ext_none): New.
271 * aarch64-dis.h (ext_none): New declaration.
272 * aarch64-opc.c (aarch64_print_operand): Update case for
273 AARCH64_OPND_BARRIER_PSB.
274 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
275 (AARCH64_OPERANDS): Update inserter/extracter for
276 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
277 * aarch64-asm-2.c: Regenerated.
278 * aarch64-dis-2.c: Regenerated.
279 * aarch64-opc-2.c: Regenerated.
280
8a6e1d1d
SD		 2812020-04-20 Sudakshina Das <sudi.das@arm.com>
282
283 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
284 (aarch64_feature_ras, RAS): Likewise.
285 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
286 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
287 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
288 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
289 * aarch64-asm-2.c: Regenerated.
290 * aarch64-dis-2.c: Regenerated.
291 * aarch64-opc-2.c: Regenerated.
292
e409955d
FS		 2932020-04-17 Fredrik Strupe <fredrik@strupe.net>
294
295 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
296 (print_insn_neon): Support disassembly of conditional
297 instructions.
298
c54a9b56
DF		 2992020-02-16 David Faust <david.faust@oracle.com>
300
301 * bpf-desc.c: Regenerate.
302 * bpf-desc.h: Likewise.
303 * bpf-opc.c: Regenerate.
304 * bpf-opc.h: Likewise.
305
bb651e8b
CL		 3062020-04-07 Lili Cui <lili.cui@intel.com>
307
308 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
309 (prefix_table): New instructions (see prefixes above).
310 (rm_table): Likewise
311 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
312 CPU_ANY_TSXLDTRK_FLAGS.
313 (cpu_flags): Add CpuTSXLDTRK.
314 * i386-opc.h (enum): Add CpuTSXLDTRK.
315 (i386_cpu_flags): Add cputsxldtrk.
316 * i386-opc.tbl: Add XSUSPLDTRK insns.
317 * i386-init.h: Regenerate.
318 * i386-tbl.h: Likewise.
319
4b27d27c
L		 3202020-04-02 Lili Cui <lili.cui@intel.com>
321
322 * i386-dis.c (prefix_table): New instructions serialize.
323 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
324 CPU_ANY_SERIALIZE_FLAGS.
325 (cpu_flags): Add CpuSERIALIZE.
326 * i386-opc.h (enum): Add CpuSERIALIZE.
327 (i386_cpu_flags): Add cpuserialize.
328 * i386-opc.tbl: Add SERIALIZE insns.
329 * i386-init.h: Regenerate.
330 * i386-tbl.h: Likewise.
331
832a5807
AM		 3322020-03-26 Alan Modra <amodra@gmail.com>
333
334 * disassemble.h (opcodes_assert): Declare.
335 (OPCODES_ASSERT): Define.
336 * disassemble.c: Don't include assert.h. Include opintl.h.
337 (opcodes_assert): New function.
338 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
339 (bfd_h8_disassemble): Reduce size of data array. Correctly
340 calculate maxlen. Omit insn decoding when insn length exceeds
341 maxlen. Exit from nibble loop when looking for E, before
342 accessing next data byte. Move processing of E outside loop.
343 Replace tests of maxlen in loop with assertions.
344
4c4addbe
AM		 3452020-03-26 Alan Modra <amodra@gmail.com>
346
347 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
348
a18cd0ca
AM		 3492020-03-25 Alan Modra <amodra@gmail.com>
350
351 * z80-dis.c (suffix): Init mybuf.
352
57cb32b3
AM		 3532020-03-22 Alan Modra <amodra@gmail.com>
354
355 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
356 successflly read from section.
357
beea5cc1
AM		 3582020-03-22 Alan Modra <amodra@gmail.com>
359
360 * arc-dis.c (find_format): Use ISO C string concatenation rather
361 than line continuation within a string. Don't access needs_limm
362 before testing opcode != NULL.
363
03704c77
AM		 3642020-03-22 Alan Modra <amodra@gmail.com>
365
366 * ns32k-dis.c (print_insn_arg): Update comment.
367 (print_insn_ns32k): Reduce size of index_offset array, and
368 initialize, passing -1 to print_insn_arg for args that are not
369 an index. Don't exit arg loop early. Abort on bad arg number.
370
d1023b5d
AM		 3712020-03-22 Alan Modra <amodra@gmail.com>
372
373 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
374 * s12z-opc.c: Formatting.
375 (operands_f): Return an int.
376 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
377 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
378 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
379 (exg_sex_discrim): Likewise.
380 (create_immediate_operand, create_bitfield_operand),
381 (create_register_operand_with_size, create_register_all_operand),
382 (create_register_all16_operand, create_simple_memory_operand),
383 (create_memory_operand, create_memory_auto_operand): Don't
384 segfault on malloc failure.
385 (z_ext24_decode): Return an int status, negative on fail, zero
386 on success.
387 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
388 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
389 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
390 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
391 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
392 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
393 (loop_primitive_decode, shift_decode, psh_pul_decode),
394 (bit_field_decode): Similarly.
395 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
396 to return value, update callers.
397 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
398 Don't segfault on NULL operand.
399 (decode_operation): Return OP_INVALID on first fail.
400 (decode_s12z): Check all reads, returning -1 on fail.
401
340f3ac8
AM		 4022020-03-20 Alan Modra <amodra@gmail.com>
403
404 * metag-dis.c (print_insn_metag): Don't ignore status from
405 read_memory_func.
406
fe90ae8a
AM		 4072020-03-20 Alan Modra <amodra@gmail.com>
408
409 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
410 Initialize parts of buffer not written when handling a possible
411 2-byte insn at end of section. Don't attempt decoding of such
412 an insn by the 4-byte machinery.
413
833d919c
AM		 4142020-03-20 Alan Modra <amodra@gmail.com>
415
416 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
417 partially filled buffer. Prevent lookup of 4-byte insns when
418 only VLE 2-byte insns are possible due to section size. Print
419 ".word" rather than ".long" for 2-byte leftovers.
420
327ef784
NC		 4212020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
422
423 PR 25641
424 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
425
1673df32
JB		 4262020-03-13 Jan Beulich <jbeulich@suse.com>
427
428 * i386-dis.c (X86_64_0D): Rename to ...
429 (X86_64_0E): ... this.
430
384f3689
L		 4312020-03-09 H.J. Lu <hongjiu.lu@intel.com>
432
433 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
434 * Makefile.in: Regenerated.
435
865e2027
JB		 4362020-03-09 Jan Beulich <jbeulich@suse.com>
437
438 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
439 3-operand pseudos.
440 * i386-tbl.h: Re-generate.
441
2f13234b
JB		 4422020-03-09 Jan Beulich <jbeulich@suse.com>
443
444 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
445 vprot*, vpsha*, and vpshl*.
446 * i386-tbl.h: Re-generate.
447
3fabc179
JB		 4482020-03-09 Jan Beulich <jbeulich@suse.com>
449
450 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
451 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
452 * i386-tbl.h: Re-generate.
453
3677e4c1
JB		 4542020-03-09 Jan Beulich <jbeulich@suse.com>
455
456 * i386-gen.c (set_bitfield): Ignore zero-length field names.
457 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
458 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
459 * i386-tbl.h: Re-generate.
460
4c4898e8
JB		 4612020-03-09 Jan Beulich <jbeulich@suse.com>
462
463 * i386-gen.c (struct template_arg, struct template_instance,
464 struct template_param, struct template, templates,
465 parse_template, expand_templates): New.
466 (process_i386_opcodes): Various local variables moved to
467 expand_templates. Call parse_template and expand_templates.
468 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
469 * i386-tbl.h: Re-generate.
470
bc49bfd8
JB		 4712020-03-06 Jan Beulich <jbeulich@suse.com>
472
473 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
474 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
475 register and memory source templates. Replace VexW= by VexW*
476 where applicable.
477 * i386-tbl.h: Re-generate.
478
4873e243
JB		 4792020-03-06 Jan Beulich <jbeulich@suse.com>
480
481 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
482 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
483 * i386-tbl.h: Re-generate.
484
672a349b
JB		 4852020-03-06 Jan Beulich <jbeulich@suse.com>
486
487 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
488 * i386-tbl.h: Re-generate.
489
4ed21b58
JB		 4902020-03-06 Jan Beulich <jbeulich@suse.com>
491
492 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
493 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
494 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
495 VexW0 on SSE2AVX variants.
496 (vmovq): Drop NoRex64 from XMM/XMM variants.
497 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
498 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
499 applicable use VexW0.
500 * i386-tbl.h: Re-generate.
501
643bb870
JB		 5022020-03-06 Jan Beulich <jbeulich@suse.com>
503
504 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
505 * i386-opc.h (Rex64): Delete.
506 (struct i386_opcode_modifier): Remove rex64 field.
507 * i386-opc.tbl (crc32): Drop Rex64.
508 Replace Rex64 with Size64 everywhere else.
509 * i386-tbl.h: Re-generate.
510
a23b33b3
JB		 5112020-03-06 Jan Beulich <jbeulich@suse.com>
512
513 * i386-dis.c (OP_E_memory): Exclude recording of used address
514 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
515 addressed memory operands for MPX insns.
516
a0497384
JB		 5172020-03-06 Jan Beulich <jbeulich@suse.com>
518
519 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
520 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
521 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
522 (ptwrite): Split into non-64-bit and 64-bit forms.
523 * i386-tbl.h: Re-generate.
524
b630c145
JB		 5252020-03-06 Jan Beulich <jbeulich@suse.com>
526
527 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
528 template.
529 * i386-tbl.h: Re-generate.
530
a847e322
JB		 5312020-03-04 Jan Beulich <jbeulich@suse.com>
532
533 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
534 (prefix_table): Move vmmcall here. Add vmgexit.
535 (rm_table): Replace vmmcall entry by prefix_table[] escape.
536 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
537 (cpu_flags): Add CpuSEV_ES entry.
538 * i386-opc.h (CpuSEV_ES): New.
539 (union i386_cpu_flags): Add cpusev_es field.
540 * i386-opc.tbl (vmgexit): New.
541 * i386-init.h, i386-tbl.h: Re-generate.
542
3cd7f3e3
L		 5432020-03-03 H.J. Lu <hongjiu.lu@intel.com>
544
545 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
546 with MnemonicSize.
547 * i386-opc.h (IGNORESIZE): New.
548 (DEFAULTSIZE): Likewise.
549 (IgnoreSize): Removed.
550 (DefaultSize): Likewise.
551 (MnemonicSize): New.
552 (i386_opcode_modifier): Replace ignoresize/defaultsize with
553 mnemonicsize.
554 * i386-opc.tbl (IgnoreSize): New.
555 (DefaultSize): Likewise.
556 * i386-tbl.h: Regenerated.
557
b8ba1385
SB		 5582020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
559
560 PR 25627
561 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
562 instructions.
563
10d97a0f
L		 5642020-03-03 H.J. Lu <hongjiu.lu@intel.com>
565
566 PR gas/25622
567 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
568 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
569 * i386-tbl.h: Regenerated.
570
dc1e8a47
AM		 5712020-02-26 Alan Modra <amodra@gmail.com>
572
573 * aarch64-asm.c: Indent labels correctly.
574 * aarch64-dis.c: Likewise.
575 * aarch64-gen.c: Likewise.
576 * aarch64-opc.c: Likewise.
577 * alpha-dis.c: Likewise.
578 * i386-dis.c: Likewise.
579 * nds32-asm.c: Likewise.
580 * nfp-dis.c: Likewise.
581 * visium-dis.c: Likewise.
582
265b4673
CZ		 5832020-02-25 Claudiu Zissulescu <claziss@gmail.com>
584
585 * arc-regs.h (int_vector_base): Make it available for all ARC
586 CPUs.
587
bd0cf5a6
NC		 5882020-02-20 Nelson Chu <nelson.chu@sifive.com>
589
590 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
591 changed.
592
fa164239
JW		 5932020-02-19 Nelson Chu <nelson.chu@sifive.com>
594
595 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
596 c.mv/c.li if rs1 is zero.
597
272a84b1
L		 5982020-02-17 H.J. Lu <hongjiu.lu@intel.com>
599
600 * i386-gen.c (cpu_flag_init): Replace CpuABM with
601 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
602 CPU_POPCNT_FLAGS.
603 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
604 * i386-opc.h (CpuABM): Removed.
605 (CpuPOPCNT): New.
606 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
607 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
608 popcnt. Remove CpuABM from lzcnt.
609 * i386-init.h: Regenerated.
610 * i386-tbl.h: Likewise.
611
1f730c46
JB		 6122020-02-17 Jan Beulich <jbeulich@suse.com>
613
614 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
615 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
616 VexW1 instead of open-coding them.
617 * i386-tbl.h: Re-generate.
618
c8f8eebc
JB		 6192020-02-17 Jan Beulich <jbeulich@suse.com>
620
621 * i386-opc.tbl (AddrPrefixOpReg): Define.
622 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
623 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
624 templates. Drop NoRex64.
625 * i386-tbl.h: Re-generate.
626
b9915cbc
JB		 6272020-02-17 Jan Beulich <jbeulich@suse.com>
628
629 PR gas/6518
630 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
631 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
632 into Intel syntax instance (with Unpsecified) and AT&T one
633 (without).
634 (vcvtneps2bf16): Likewise, along with folding the two so far
635 separate ones.
636 * i386-tbl.h: Re-generate.
637
ce504911
L		 6382020-02-16 H.J. Lu <hongjiu.lu@intel.com>
639
640 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
641 CPU_ANY_SSE4A_FLAGS.
642
dabec65d
AM		 6432020-02-17 Alan Modra <amodra@gmail.com>
644
645 * i386-gen.c (cpu_flag_init): Correct last change.
646
af5c13b0
L		 6472020-02-16 H.J. Lu <hongjiu.lu@intel.com>
648
649 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
650 CPU_ANY_SSE4_FLAGS.
651
6867aac0
L		 6522020-02-14 H.J. Lu <hongjiu.lu@intel.com>
653
654 * i386-opc.tbl (movsx): Remove Intel syntax comments.
655 (movzx): Likewise.
656
65fca059
JB		 6572020-02-14 Jan Beulich <jbeulich@suse.com>
658
659 PR gas/25438
660 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
661 destination for Cpu64-only variant.
662 (movzx): Fold patterns.
663 * i386-tbl.h: Re-generate.
664
7deea9aa
JB		 6652020-02-13 Jan Beulich <jbeulich@suse.com>
666
667 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
668 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
669 CPU_ANY_SSE4_FLAGS entry.
670 * i386-init.h: Re-generate.
671
6c0946d0
JB		 6722020-02-12 Jan Beulich <jbeulich@suse.com>
673
674 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
675 with Unspecified, making the present one AT&T syntax only.
676 * i386-tbl.h: Re-generate.
677
ddb56fe6
JB		 6782020-02-12 Jan Beulich <jbeulich@suse.com>
679
680 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
681 * i386-tbl.h: Re-generate.
682
5990e377
JB		 6832020-02-12 Jan Beulich <jbeulich@suse.com>
684
685 PR gas/24546
686 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
687 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
688 Amd64 and Intel64 templates.
689 (call, jmp): Likewise for far indirect variants. Dro
690 Unspecified.
691 * i386-tbl.h: Re-generate.
692
50128d0c
JB		 6932020-02-11 Jan Beulich <jbeulich@suse.com>
694
695 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
696 * i386-opc.h (ShortForm): Delete.
697 (struct i386_opcode_modifier): Remove shortform field.
698 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
699 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
700 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
701 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
702 Drop ShortForm.
703 * i386-tbl.h: Re-generate.
704
1e05b5c4
JB		 7052020-02-11 Jan Beulich <jbeulich@suse.com>
706
707 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
708 fucompi): Drop ShortForm from operand-less templates.
709 * i386-tbl.h: Re-generate.
710
2f5dd314
AM		 7112020-02-11 Alan Modra <amodra@gmail.com>
712
713 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
714 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
715 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
716 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
717 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
718
5aae9ae9
MM		 7192020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
720
721 * arm-dis.c (print_insn_cde): Define 'V' parse character.
722 (cde_opcodes): Add VCX* instructions.
723
4934a27c
MM		 7242020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
725 Matthew Malcomson <matthew.malcomson@arm.com>
726
727 * arm-dis.c (struct cdeopcode32): New.
728 (CDE_OPCODE): New macro.
729 (cde_opcodes): New disassembly table.
730 (regnames): New option to table.
731 (cde_coprocs): New global variable.
732 (print_insn_cde): New
733 (print_insn_thumb32): Use print_insn_cde.
734 (parse_arm_disassembler_options): Parse coprocN args.
735
4b5aaf5f
L		 7362020-02-10 H.J. Lu <hongjiu.lu@intel.com>
737
738 PR gas/25516
739 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
740 with ISA64.
741 * i386-opc.h (AMD64): Removed.
742 (Intel64): Likewose.
743 (AMD64): New.
744 (INTEL64): Likewise.
745 (INTEL64ONLY): Likewise.
746 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
747 * i386-opc.tbl (Amd64): New.
748 (Intel64): Likewise.
749 (Intel64Only): Likewise.
750 Replace AMD64 with Amd64. Update sysenter/sysenter with
751 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
752 * i386-tbl.h: Regenerated.
753
9fc0b501
SB		 7542020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
755
756 PR 25469
757 * z80-dis.c: Add support for GBZ80 opcodes.
758
c5d7be0c
AM		 7592020-02-04 Alan Modra <amodra@gmail.com>
760
761 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
762
44e4546f
AM		 7632020-02-03 Alan Modra <amodra@gmail.com>
764
765 * m32c-ibld.c: Regenerate.
766
b2b1453a
AM		 7672020-02-01 Alan Modra <amodra@gmail.com>
768
769 * frv-ibld.c: Regenerate.
770
4102be5c
JB		 7712020-01-31 Jan Beulich <jbeulich@suse.com>
772
773 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
774 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
775 (OP_E_memory): Replace xmm_mdq_mode case label by
776 vex_scalar_w_dq_mode one.
777 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
778
825bd36c
JB		 7792020-01-31 Jan Beulich <jbeulich@suse.com>
780
781 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
782 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
783 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
784 (intel_operand_size): Drop vex_w_dq_mode case label.
785
c3036ed0
RS		 7862020-01-31 Richard Sandiford <richard.sandiford@arm.com>
787
788 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
789 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
790
0c115f84
AM		 7912020-01-30 Alan Modra <amodra@gmail.com>
792
793 * m32c-ibld.c: Regenerate.
794
bd434cc4
JM		 7952020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
796
797 * bpf-opc.c: Regenerate.
798
aeab2b26
JB		 7992020-01-30 Jan Beulich <jbeulich@suse.com>
800
801 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
802 (dis386): Use them to replace C2/C3 table entries.
803 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
804 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
805 ones. Use Size64 instead of DefaultSize on Intel64 ones.
806 * i386-tbl.h: Re-generate.
807
62b3f548
JB		 8082020-01-30 Jan Beulich <jbeulich@suse.com>
809
810 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
811 forms.
812 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
813 DefaultSize.
814 * i386-tbl.h: Re-generate.
815
1bd8ae10
AM		 8162020-01-30 Alan Modra <amodra@gmail.com>
817
818 * tic4x-dis.c (tic4x_dp): Make unsigned.
819
bc31405e
L		 8202020-01-27 H.J. Lu <hongjiu.lu@intel.com>
821 Jan Beulich <jbeulich@suse.com>
822
823 PR binutils/25445
824 * i386-dis.c (MOVSXD_Fixup): New function.
825 (movsxd_mode): New enum.
826 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
827 (intel_operand_size): Handle movsxd_mode.
828 (OP_E_register): Likewise.
829 (OP_G): Likewise.
830 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
831 register on movsxd. Add movsxd with 16-bit destination register
832 for AMD64 and Intel64 ISAs.
833 * i386-tbl.h: Regenerated.
834
7568c93b
TC		 8352020-01-27 Tamar Christina <tamar.christina@arm.com>
836
837 PR 25403
838 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
839 * aarch64-asm-2.c: Regenerate
840 * aarch64-dis-2.c: Likewise.
841 * aarch64-opc-2.c: Likewise.
842
c006a730
JB		 8432020-01-21 Jan Beulich <jbeulich@suse.com>
844
845 * i386-opc.tbl (sysret): Drop DefaultSize.
846 * i386-tbl.h: Re-generate.
847
c906a69a
JB		 8482020-01-21 Jan Beulich <jbeulich@suse.com>
849
850 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
851 Dword.
852 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
853 * i386-tbl.h: Re-generate.
854
26916852
NC		 8552020-01-20 Nick Clifton <nickc@redhat.com>
856
857 * po/de.po: Updated German translation.
858 * po/pt_BR.po: Updated Brazilian Portuguese translation.
859 * po/uk.po: Updated Ukranian translation.
860
4d6cbb64
AM		 8612020-01-20 Alan Modra <amodra@gmail.com>
862
863 * hppa-dis.c (fput_const): Remove useless cast.
864
2bddb71a
AM		 8652020-01-20 Alan Modra <amodra@gmail.com>
866
867 * arm-dis.c (print_insn_arm): Wrap 'T' value.
868
1b1bb2c6
NC		 8692020-01-18 Nick Clifton <nickc@redhat.com>
870
871 * configure: Regenerate.
872 * po/opcodes.pot: Regenerate.
873
ae774686
NC		 8742020-01-18 Nick Clifton <nickc@redhat.com>
875
876 Binutils 2.34 branch created.
877
07f1f3aa
CB		 8782020-01-17 Christian Biesinger <cbiesinger@google.com>
879
880 * opintl.h: Fix spelling error (seperate).
881
42e04b36
L		 8822020-01-17 H.J. Lu <hongjiu.lu@intel.com>
883
884 * i386-opc.tbl: Add {vex} pseudo prefix.
885 * i386-tbl.h: Regenerated.
886
2da2eaf4
AV		 8872020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
888
889 PR 25376
890 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
891 (neon_opcodes): Likewise.
892 (select_arm_features): Make sure we enable MVE bits when selecting
893 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
894 any architecture.
895
d0849eed
JB		 8962020-01-16 Jan Beulich <jbeulich@suse.com>
897
898 * i386-opc.tbl: Drop stale comment from XOP section.
899
9cf70a44
JB		 9002020-01-16 Jan Beulich <jbeulich@suse.com>
901
902 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
903 (extractps): Add VexWIG to SSE2AVX forms.
904 * i386-tbl.h: Re-generate.
905
4814632e
JB		 9062020-01-16 Jan Beulich <jbeulich@suse.com>
907
908 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
909 Size64 from and use VexW1 on SSE2AVX forms.
910 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
911 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
912 * i386-tbl.h: Re-generate.
913
aad09917
AM		 9142020-01-15 Alan Modra <amodra@gmail.com>
915
916 * tic4x-dis.c (tic4x_version): Make unsigned long.
917 (optab, optab_special, registernames): New file scope vars.
918 (tic4x_print_register): Set up registernames rather than
919 malloc'd registertable.
920 (tic4x_disassemble): Delete optable and optable_special. Use
921 optab and optab_special instead. Throw away old optab,
922 optab_special and registernames when info->mach changes.
923
7a6bf3be
SB		 9242020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
925
926 PR 25377
927 * z80-dis.c (suffix): Use .db instruction to generate double
928 prefix.
929
ca1eaac0
AM		 9302020-01-14 Alan Modra <amodra@gmail.com>
931
932 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
933 values to unsigned before shifting.
934
1d67fe3b
TT		 9352020-01-13 Thomas Troeger <tstroege@gmx.de>
936
937 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
938 flow instructions.
939 (print_insn_thumb16, print_insn_thumb32): Likewise.
940 (print_insn): Initialize the insn info.
941 * i386-dis.c (print_insn): Initialize the insn info fields, and
942 detect jumps.
943
5e4f7e05
CZ		 9442012-01-13 Claudiu Zissulescu <claziss@gmail.com>
945
946 * arc-opc.c (C_NE): Make it required.
947
b9fe6b8a
CZ		 9482012-01-13 Claudiu Zissulescu <claziss@gmail.com>
949
950 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
951 reserved register name.
952
90dee485
AM		 9532020-01-13 Alan Modra <amodra@gmail.com>
954
955 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
956 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
957
febda64f
AM		 9582020-01-13 Alan Modra <amodra@gmail.com>
959
960 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
961 result of wasm_read_leb128 in a uint64_t and check that bits
962 are not lost when copying to other locals. Use uint32_t for
963 most locals. Use PRId64 when printing int64_t.
964
df08b588
AM		 9652020-01-13 Alan Modra <amodra@gmail.com>
966
967 * score-dis.c: Formatting.
968 * score7-dis.c: Formatting.
969
b2c759ce
AM		 9702020-01-13 Alan Modra <amodra@gmail.com>
971
972 * score-dis.c (print_insn_score48): Use unsigned variables for
973 unsigned values. Don't left shift negative values.
974 (print_insn_score32): Likewise.
975 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
976
5496abe1
AM		 9772020-01-13 Alan Modra <amodra@gmail.com>
978
979 * tic4x-dis.c (tic4x_print_register): Remove dead code.
980
202e762b
AM		 9812020-01-13 Alan Modra <amodra@gmail.com>
982
983 * fr30-ibld.c: Regenerate.
984
7ef412cf
AM		 9852020-01-13 Alan Modra <amodra@gmail.com>
986
987 * xgate-dis.c (print_insn): Don't left shift signed value.
988 (ripBits): Formatting, use 1u.
989
7f578b95
AM		 9902020-01-10 Alan Modra <amodra@gmail.com>
991
992 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
993 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
994
441af85b
AM		 9952020-01-10 Alan Modra <amodra@gmail.com>
996
997 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
998 and XRREG value earlier to avoid a shift with negative exponent.
999 * m10200-dis.c (disassemble): Similarly.
1000
bce58db4
NC		 10012020-01-09 Nick Clifton <nickc@redhat.com>
1002
1003 PR 25224
1004 * z80-dis.c (ld_ii_ii): Use correct cast.
1005
40c75bc8
SB		 10062020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1007
1008 PR 25224
1009 * z80-dis.c (ld_ii_ii): Use character constant when checking
1010 opcode byte value.
1011
d835a58b
JB		 10122020-01-09 Jan Beulich <jbeulich@suse.com>
1013
1014 * i386-dis.c (SEP_Fixup): New.
1015 (SEP): Define.
1016 (dis386_twobyte): Use it for sysenter/sysexit.
1017 (enum x86_64_isa): Change amd64 enumerator to value 1.
1018 (OP_J): Compare isa64 against intel64 instead of amd64.
1019 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1020 forms.
1021 * i386-tbl.h: Re-generate.
1022
030a2e78
AM		 10232020-01-08 Alan Modra <amodra@gmail.com>
1024
1025 * z8k-dis.c: Include libiberty.h
1026 (instr_data_s): Make max_fetched unsigned.
1027 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1028 Don't exceed byte_info bounds.
1029 (output_instr): Make num_bytes unsigned.
1030 (unpack_instr): Likewise for nibl_count and loop.
1031 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1032 idx unsigned.
1033 * z8k-opc.h: Regenerate.
1034
bb82aefe
SV		 10352020-01-07 Shahab Vahedi <shahab@synopsys.com>
1036
1037 * arc-tbl.h (llock): Use 'LLOCK' as class.
1038 (llockd): Likewise.
1039 (scond): Use 'SCOND' as class.
1040 (scondd): Likewise.
1041 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1042 (scondd): Likewise.
1043
cc6aa1a6
AM		 10442020-01-06 Alan Modra <amodra@gmail.com>
1045
1046 * m32c-ibld.c: Regenerate.
1047
660e62b1
AM		 10482020-01-06 Alan Modra <amodra@gmail.com>
1049
1050 PR 25344
1051 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1052 Peek at next byte to prevent recursion on repeated prefix bytes.
1053 Ensure uninitialised "mybuf" is not accessed.
1054 (print_insn_z80): Don't zero n_fetch and n_used here,..
1055 (print_insn_z80_buf): ..do it here instead.
1056
c9ae58fe
AM		 10572020-01-04 Alan Modra <amodra@gmail.com>
1058
1059 * m32r-ibld.c: Regenerate.
1060
5f57d4ec
AM		 10612020-01-04 Alan Modra <amodra@gmail.com>
1062
1063 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1064
2c5c1196
AM		 10652020-01-04 Alan Modra <amodra@gmail.com>
1066
1067 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1068
2e98c6c5
AM		 10692020-01-04 Alan Modra <amodra@gmail.com>
1070
1071 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1072
567dfba2
JB		 10732020-01-03 Jan Beulich <jbeulich@suse.com>
1074
5437a02a
JB		 1075 * aarch64-tbl.h (aarch64_opcode_table): Use
1076 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1077
10782020-01-03 Jan Beulich <jbeulich@suse.com>
1079
1080 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1081 forms of SUDOT and USDOT.
1082
8c45011a
JB		 10832020-01-03 Jan Beulich <jbeulich@suse.com>
1084
5437a02a 1085 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1086 uzip{1,2}.
1087 * opcodes/aarch64-dis-2.c: Re-generate.
1088
f4950f76
JB		 10892020-01-03 Jan Beulich <jbeulich@suse.com>
1090
5437a02a 1091 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1092 FMMLA encoding.
1093 * opcodes/aarch64-dis-2.c: Re-generate.
1094
6655dba2
SB		 10952020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1096
1097 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1098
b14ce8bf
AM		 10992020-01-01 Alan Modra <amodra@gmail.com>
1100
1101 Update year range in copyright notice of all files.
1102
0b114740 1103For older changes see ChangeLog-2019
3499769a 1104\f
0b114740 1105Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1106
1107Copying and distribution of this file, with or without modification,
1108are permitted in any medium without royalty provided the copyright
1109notice and this notice are preserved.
1110
1111Local Variables:
1112mode: change-log
1113left-margin: 8
1114fill-column: 74
1115version-control: never
1116End:
GDB Binutils - Deliverables
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