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PR 6526
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
7357c5b6
AM		 12008-08-15 Alan Modra <amodra@bigpond.net.au>
2
3 PR 6526
4 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
5 * Makefile.in: Regenerate.
6 * aclocal.m4: Regenerate.
7 * config.in: Regenerate.
8 * configure: Regenerate.
9
899d85be
AM		 102008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
11
12 PR 6825
13 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
14
dfb07592
L		 152008-08-12 H.J. Lu <hongjiu.lu@intel.com>
16
17 * i386-opc.tbl: Add syscall and sysret for Cpu64.
18
19 * i386-tbl.h: Regenerated.
20
323ee3f4
AM		 212008-08-04 Alan Modra <amodra@bigpond.net.au>
22
23 * Makefile.am (POTFILES.in): Set LC_ALL=C.
24 * Makefile.in: Regenerate.
25 * po/POTFILES.in: Regenerate.
26
9b4e5766
PB		 272008-08-01 Peter Bergner <bergner@vnet.ibm.com>
28
29 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
30 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
31 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
32 * ppc-opc.c (insert_xt6): New static function.
33 (extract_xt6): Likewise.
34 (insert_xa6): Likewise.
35 (extract_xa6: Likewise.
36 (insert_xb6): Likewise.
37 (extract_xb6): Likewise.
38 (insert_xb6s): Likewise.
39 (extract_xb6s): Likewise.
40 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
41 XX3DM_MASK, PPCVSX): New.
42 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
43 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
44
20fd6e2e
PA		 452008-08-01 Pedro Alves <pedro@codesourcery.com>
46
47 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
48 * Makefile.in: Regenerate.
49
a656ed5b
L		 502008-08-01 H.J. Lu <hongjiu.lu@intel.com>
51
52 * i386-reg.tbl: Use Dw2Inval on AVX registers.
53 * i386-tbl.h: Regenerated.
54
081ba1b3
AM		 552008-07-30 Michael J. Eager <eager@eagercon.com>
56
57 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
58 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
59 (insert_sprg, PPC405): Use PPC_OPCODE_405.
60 (powerpc_opcodes): Add Xilinx APU related opcodes.
61
0af1713e
AM		 622008-07-30 Alan Modra <amodra@bigpond.net.au>
63
64 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
65
30c09090
RS		 662008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
67
68 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
69
c27e721e
AN		 702008-07-07 Adam Nemet <anemet@caviumnetworks.com>
71
72 * mips-opc.c (CP): New macro.
73 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
74 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
75 dmtc2 Octeon instructions.
76
bd2e2557
SS		 772008-07-07 Stan Shebs <stan@codesourcery.com>
78
79 * dis-init.c (init_disassemble_info): Init endian_code field.
80 * arm-dis.c (print_insn): Disassemble code according to
81 setting of endian_code.
82 (print_insn_big_arm): Detect when BE8 extension flag has been set.
83
6ba2a415
RS		 842008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
85
86 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
87 for ELF symbols.
88
c8187e15
PB		 892008-06-25 Peter Bergner <bergner@vnet.ibm.com>
90
91 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
92 (print_ppc_disassembler_options): Likewise.
93 * ppc-opc.c (PPC464): Define.
94 (powerpc_opcodes): Add mfdcrux and mtdcrux.
95
7a283e07
RW		 962008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
97
98 * configure: Regenerate.
99
fa452fa6
PB		 1002008-06-13 Peter Bergner <bergner@vnet.ibm.com>
101
102 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
103 ppc_cpu_t typedef.
104 (struct dis_private): New.
105 (POWERPC_DIALECT): New define.
106 (powerpc_dialect): Renamed to...
107 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
108 struct dis_private.
109 (print_insn_big_powerpc): Update for using structure in
110 info->private_data.
111 (print_insn_little_powerpc): Likewise.
112 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
113 (skip_optional_operands): Likewise.
114 (print_insn_powerpc): Likewise. Remove initialization of dialect.
115 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
116 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
117 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
118 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
119 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
120 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
121 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
122 param to be of type ppc_cpu_t. Update prototype.
123
bb35fb24
NC		 1242008-06-12 Adam Nemet <anemet@caviumnetworks.com>
125
126 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
127 +s, +S.
128 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
129 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
130 syncw, syncws, vm3mulu, vm0 and vmulu.
131
dd3cbb7e
NC		 132 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
133 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
134 seqi, sne and snei.
135
a5dabbb0
L		 1362008-05-30 H.J. Lu <hongjiu.lu@intel.com>
137
138 * i386-opc.tbl: Add vmovd with 64bit operand.
139 * i386-tbl.h: Regenerated.
140
725a9891
MS		 1412008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
142
143 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
144
cbc80391
L		 1452008-05-22 H.J. Lu <hongjiu.lu@intel.com>
146
147 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
148 * i386-tbl.h: Regenerated.
149
116615c5
L		 1502008-05-22 H.J. Lu <hongjiu.lu@intel.com>
151
152 PR gas/6517
153 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
154 into 32bit and 64bit. Remove Reg64|Qword and add
155 IgnoreSize|No_qSuf on 32bit version.
156 * i386-tbl.h: Regenerated.
157
d9479f2d
L		 1582008-05-21 H.J. Lu <hongjiu.lu@intel.com>
159
160 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
161 * i386-tbl.h: Regenerated.
162
3ce6fddb
NC		 1632008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
164
165 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
166
8944f3c2
AM		 1672008-05-14 Alan Modra <amodra@bigpond.net.au>
168
169 * Makefile.am: Run "make dep-am".
170 * Makefile.in: Regenerate.
171
f1f8f695
L		 1722008-05-02 H.J. Lu <hongjiu.lu@intel.com>
173
174 * i386-dis.c (MOVBE_Fixup): New.
175 (Mo): Likewise.
176 (PREFIX_0F3880): Likewise.
177 (PREFIX_0F3881): Likewise.
178 (PREFIX_0F38F0): Updated.
179 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
180 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
181 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
182
183 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
184 CPU_EPT_FLAGS.
185 (cpu_flags): Add CpuMovbe and CpuEPT.
186
187 * i386-opc.h (CpuMovbe): New.
188 (CpuEPT): Likewise.
189 (CpuLM): Updated.
190 (i386_cpu_flags): Add cpumovbe and cpuept.
191
192 * i386-opc.tbl: Add entries for movbe and EPT instructions.
193 * i386-init.h: Regenerated.
194 * i386-tbl.h: Likewise.
195
89aa3097
AN		 1962008-04-29 Adam Nemet <anemet@caviumnetworks.com>
197
198 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
199 the two drem and the two dremu macros.
200
39c5c168
AN		 2012008-04-28 Adam Nemet <anemet@caviumnetworks.com>
202
203 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
204 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
205 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
206 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
207
f04d18b7
DM		 2082008-04-25 David S. Miller <davem@davemloft.net>
209
210 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
211 instead of %sys_tick_cmpr, as suggested in architecture manuals.
212
6194aaab
L		 2132008-04-23 Paolo Bonzini <bonzini@gnu.org>
214
215 * aclocal.m4: Regenerate.
216 * configure: Regenerate.
217
1a6b486f
DM		 2182008-04-23 David S. Miller <davem@davemloft.net>
219
220 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
221 extended values.
222 (prefetch_table): Add missing values.
223
81f8a913
L		 2242008-04-22 H.J. Lu <hongjiu.lu@intel.com>
225
226 * i386-gen.c (opcode_modifiers): Add NoAVX.
227
228 * i386-opc.h (NoAVX): New.
229 (OldGcc): Updated.
230 (i386_opcode_modifier): Add noavx.
231
232 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
233 instructions which don't have AVX equivalent.
234 * i386-tbl.h: Regenerated.
235
dae39acc
L		 2362008-04-18 H.J. Lu <hongjiu.lu@intel.com>
237
238 * i386-dis.c (OP_VEX_FMA): New.
239 (OP_EX_VexImmW): Likewise.
240 (VexFMA): Likewise.
241 (Vex128FMA): Likewise.
242 (EXVexImmW): Likewise.
243 (get_vex_imm8): Likewise.
244 (OP_EX_VexReg): Likewise.
245 (vex_i4_done): Renamed to ...
246 (vex_w_done): This.
247 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
248 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
249 FMA instructions.
250 (print_insn): Updated.
251 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
252 (OP_REG_VexI4): Check invalid high registers.
253
ce886ab1
DR		 2542008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
255 Michael Meissner <michael.meissner@amd.com>
256
257 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
258 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 259
19a6653c
AM		 2602008-04-14 Edmar Wienskoski <edmar@freescale.com>
261
262 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
263 accept Power E500MC instructions.
264 (print_ppc_disassembler_options): Document -Me500mc.
265 * ppc-opc.c (DUIS, DUI, T): New.
266 (XRT, XRTRA): Likewise.
267 (E500MC): Likewise.
268 (powerpc_opcodes): Add new Power E500MC instructions.
269
112b7c50
AK		 2702008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
271
272 * s390-dis.c (init_disasm): Evaluate disassembler_options.
273 (print_s390_disassembler_options): New function.
274 * disassemble.c (disassembler_usage): Invoke
275 print_s390_disassembler_options.
276
7ff42648
AK		 2772008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
278
279 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
280 of local variables used for mnemonic parsing: prefix, suffix and
281 number.
282
45a5551e
AK		 2832008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
284
285 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
286 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
287 (s390_crb_extensions): New extensions table.
288 (insertExpandedMnemonic): Handle '$' tag.
289 * s390-opc.txt: Remove conditional jump variants which can now
290 be expanded automatically.
291 Replace '*' tag with '$' in the compare and branch instructions.
292
06c8514a
L		 2932008-04-07 H.J. Lu <hongjiu.lu@intel.com>
294
295 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
296 (PREFIX_VEX_3AXX): Likewis.
297
b122c285
L		 2982008-04-07 H.J. Lu <hongjiu.lu@intel.com>
299
300 * i386-opc.tbl: Remove 4 extra blank lines.
301
594ab6a3
L		 3022008-04-04 H.J. Lu <hongjiu.lu@intel.com>
303
304 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
305 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
306 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
307 * i386-opc.tbl: Likewise.
308
309 * i386-opc.h (CpuCLMUL): Renamed to ...
310 (CpuPCLMUL): This.
311 (CpuFMA): Updated.
312 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
313
314 * i386-init.h: Regenerated.
315
c0f3af97
L		 3162008-04-03 H.J. Lu <hongjiu.lu@intel.com>
317
318 * i386-dis.c (OP_E_register): New.
319 (OP_E_memory): Likewise.
320 (OP_VEX): Likewise.
321 (OP_EX_Vex): Likewise.
322 (OP_EX_VexW): Likewise.
323 (OP_XMM_Vex): Likewise.
324 (OP_XMM_VexW): Likewise.
325 (OP_REG_VexI4): Likewise.
326 (PCLMUL_Fixup): Likewise.
327 (VEXI4_Fixup): Likewise.
328 (VZERO_Fixup): Likewise.
329 (VCMP_Fixup): Likewise.
330 (VPERMIL2_Fixup): Likewise.
331 (rex_original): Likewise.
332 (rex_ignored): Likewise.
333 (Mxmm): Likewise.
334 (XMM): Likewise.
335 (EXxmm): Likewise.
336 (EXxmmq): Likewise.
337 (EXymmq): Likewise.
338 (Vex): Likewise.
339 (Vex128): Likewise.
340 (Vex256): Likewise.
341 (VexI4): Likewise.
342 (EXdVex): Likewise.
343 (EXqVex): Likewise.
344 (EXVexW): Likewise.
345 (EXdVexW): Likewise.
346 (EXqVexW): Likewise.
347 (XMVex): Likewise.
348 (XMVexW): Likewise.
349 (XMVexI4): Likewise.
350 (PCLMUL): Likewise.
351 (VZERO): Likewise.
352 (VCMP): Likewise.
353 (VPERMIL2): Likewise.
354 (xmm_mode): Likewise.
355 (xmmq_mode): Likewise.
356 (ymmq_mode): Likewise.
357 (vex_mode): Likewise.
358 (vex128_mode): Likewise.
359 (vex256_mode): Likewise.
360 (USE_VEX_C4_TABLE): Likewise.
361 (USE_VEX_C5_TABLE): Likewise.
362 (USE_VEX_LEN_TABLE): Likewise.
363 (VEX_C4_TABLE): Likewise.
364 (VEX_C5_TABLE): Likewise.
365 (VEX_LEN_TABLE): Likewise.
366 (REG_VEX_XX): Likewise.
367 (MOD_VEX_XXX): Likewise.
368 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
369 (PREFIX_0F3A44): Likewise.
370 (PREFIX_0F3ADF): Likewise.
371 (PREFIX_VEX_XXX): Likewise.
372 (VEX_OF): Likewise.
373 (VEX_OF38): Likewise.
374 (VEX_OF3A): Likewise.
375 (VEX_LEN_XXX): Likewise.
376 (vex): Likewise.
377 (need_vex): Likewise.
378 (need_vex_reg): Likewise.
379 (vex_i4_done): Likewise.
380 (vex_table): Likewise.
381 (vex_len_table): Likewise.
382 (OP_REG_VexI4): Likewise.
383 (vex_cmp_op): Likewise.
384 (pclmul_op): Likewise.
385 (vpermil2_op): Likewise.
386 (m_mode): Updated.
387 (es_reg): Likewise.
388 (PREFIX_0F38F0): Likewise.
389 (PREFIX_0F3A60): Likewise.
390 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
391 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
392 and PREFIX_VEX_XXX entries.
393 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
394 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
395 PREFIX_0F3ADF.
396 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
397 Add MOD_VEX_XXX entries.
398 (ckprefix): Initialize rex_original and rex_ignored. Store the
399 REX byte in rex_original.
400 (get_valid_dis386): Handle the implicit prefix in VEX prefix
401 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
402 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
403 calling get_valid_dis386. Use rex_original and rex_ignored when
404 printing out REX.
405 (putop): Handle "XY".
406 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
407 ymmq_mode.
408 (OP_E_extended): Updated to use OP_E_register and
409 OP_E_memory.
410 (OP_XMM): Handle VEX.
411 (OP_EX): Likewise.
412 (XMM_Fixup): Likewise.
413 (CMP_Fixup): Use ARRAY_SIZE.
414
415 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
416 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
417 (operand_type_init): Add OPERAND_TYPE_REGYMM and
418 OPERAND_TYPE_VEX_IMM4.
419 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
420 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
421 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
422 VexImmExt and SSE2AVX.
423 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
424
425 * i386-opc.h (CpuAVX): New.
426 (CpuAES): Likewise.
427 (CpuCLMUL): Likewise.
428 (CpuFMA): Likewise.
429 (Vex): Likewise.
430 (Vex256): Likewise.
431 (VexNDS): Likewise.
432 (VexNDD): Likewise.
433 (VexW0): Likewise.
434 (VexW1): Likewise.
435 (Vex0F): Likewise.
436 (Vex0F38): Likewise.
437 (Vex0F3A): Likewise.
438 (Vex3Sources): Likewise.
439 (VexImmExt): Likewise.
440 (SSE2AVX): Likewise.
441 (RegYMM): Likewise.
442 (Ymmword): Likewise.
443 (Vex_Imm4): Likewise.
444 (Implicit1stXmm0): Likewise.
445 (CpuXsave): Updated.
446 (CpuLM): Likewise.
447 (ByteOkIntel): Likewise.
448 (OldGcc): Likewise.
449 (Control): Likewise.
450 (Unspecified): Likewise.
451 (OTMax): Likewise.
452 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
453 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
454 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
455 vex3sources, veximmext and sse2avx.
456 (i386_operand_type): Add regymm, ymmword and vex_imm4.
457
458 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
459
460 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
461
462 * i386-init.h: Regenerated.
463 * i386-tbl.h: Likewise.
464
b21c9cb4
BS		 4652008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
466
467 From Robin Getz <robin.getz@analog.com>
468 * bfin-dis.c (bu32): Typedef.
469 (enum const_forms_t): Add c_uimm32 and c_huimm32.
470 (constant_formats[]): Add uimm32 and huimm16.
471 (fmtconst_val): New.
472 (uimm32): Define.
473 (huimm32): Define.
474 (imm16_val): Define.
475 (luimm16_val): Define.
476 (struct saved_state): Define.
477 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
478 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
479 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
480 (get_allreg): New.
481 (decode_LDIMMhalf_0): Print out the whole register value.
482
ee171c8f
BS		 483 From Jie Zhang <jie.zhang@analog.com>
484 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
485 multiply and multiply-accumulate to data register instruction.
486
086134ec
BS		 487 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
488 c_imm32, c_huimm32e): Define.
489 (constant_formats): Add flags for printing decimal, leading spaces, and
490 exact symbols.
491 (comment, parallel): Add global flags in all disassembly.
492 (fmtconst): Take advantage of new flags, and print default in hex.
493 (fmtconst_val): Likewise.
494 (decode_macfunc): Be consistant with spaces, tabs, comments,
495 capitalization in disassembly, fix minor coding style issues.
496 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
497 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
498 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
499 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
500 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
501 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
502 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
503 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
504 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
505 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
506 _print_insn_bfin, print_insn_bfin): Likewise.
507
58c85be7
RW		 5082008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
509
510 * aclocal.m4: Regenerate.
511 * configure: Likewise.
512 * Makefile.in: Likewise.
513
50e7d84b
AM		 5142008-03-13 Alan Modra <amodra@bigpond.net.au>
515
516 * Makefile.am: Run "make dep-am".
517 * Makefile.in: Regenerate.
518 * configure: Regenerate.
519
de866fcc
AM		 5202008-03-07 Alan Modra <amodra@bigpond.net.au>
521
522 * ppc-opc.c (powerpc_opcodes): Order and format.
523
28dbc079
L		 5242008-03-01 H.J. Lu <hongjiu.lu@intel.com>
525
526 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
527 * i386-tbl.h: Regenerated.
528
849830bd
L		 5292008-02-23 H.J. Lu <hongjiu.lu@intel.com>
530
531 * i386-opc.tbl: Disallow 16-bit near indirect branches for
532 x86-64.
533 * i386-tbl.h: Regenerated.
534
743ddb6b
JB		 5352008-02-21 Jan Beulich <jbeulich@novell.com>
536
537 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
538 and Fword for far indirect jmp. Allow Reg16 and Word for near
539 indirect jmp on x86-64. Disallow Fword for lcall.
540 * i386-tbl.h: Re-generate.
541
796d5313
NC		 5422008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
543
544 * cr16-opc.c (cr16_num_optab): Defined
545
65da13b5
L		 5462008-02-16 H.J. Lu <hongjiu.lu@intel.com>
547
548 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
549 * i386-init.h: Regenerated.
550
0e336180
NC		 5512008-02-14 Nick Clifton <nickc@redhat.com>
552
553 PR binutils/5524
554 * configure.in (SHARED_LIBADD): Select the correct host specific
555 file extension for shared libraries.
556 * configure: Regenerate.
557
b7240065
JB		 5582008-02-13 Jan Beulich <jbeulich@novell.com>
559
560 * i386-opc.h (RegFlat): New.
561 * i386-reg.tbl (flat): Add.
562 * i386-tbl.h: Re-generate.
563
34b772a6
JB		 5642008-02-13 Jan Beulich <jbeulich@novell.com>
565
566 * i386-dis.c (a_mode): New.
567 (cond_jump_mode): Adjust.
568 (Ma): Change to a_mode.
569 (intel_operand_size): Handle a_mode.
570 * i386-opc.tbl: Allow Dword and Qword for bound.
571 * i386-tbl.h: Re-generate.
572
a60de03c
JB		 5732008-02-13 Jan Beulich <jbeulich@novell.com>
574
575 * i386-gen.c (process_i386_registers): Process new fields.
576 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
577 unsigned char. Add dw2_regnum and Dw2Inval.
578 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
579 register names.
580 * i386-tbl.h: Re-generate.
581
f03fe4c1
L		 5822008-02-11 H.J. Lu <hongjiu.lu@intel.com>
583
4b6bc8eb 584 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 585 * i386-init.h: Updated.
586
475a2301
L		 5872008-02-11 H.J. Lu <hongjiu.lu@intel.com>
588
589 * i386-gen.c (cpu_flags): Add CpuXsave.
590
591 * i386-opc.h (CpuXsave): New.
4b6bc8eb 592 (CpuLM): Updated.
475a2301
L		 593 (i386_cpu_flags): Add cpuxsave.
594
595 * i386-dis.c (MOD_0FAE_REG_4): New.
596 (RM_0F01_REG_2): Likewise.
597 (MOD_0FAE_REG_5): Updated.
598 (RM_0F01_REG_3): Likewise.
599 (reg_table): Use MOD_0FAE_REG_4.
600 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
601 for xrstor.
602 (rm_table): Add RM_0F01_REG_2.
603
604 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
605 * i386-init.h: Regenerated.
606 * i386-tbl.h: Likewise.
607
595785c6 6082008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 609
595785c6
JB		 610 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
611 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
612 * i386-tbl.h: Re-generate.
613
bb8541b9
L		 6142008-02-04 H.J. Lu <hongjiu.lu@intel.com>
615
616 PR 5715
617 * configure: Regenerated.
618
57b592a3
AN		 6192008-02-04 Adam Nemet <anemet@caviumnetworks.com>
620
621 * mips-dis.c: Update copyright.
622 (mips_arch_choices): Add Octeon.
623 * mips-opc.c: Update copyright.
624 (IOCT): New macro.
625 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
626
930bb4cf
AM		 6272008-01-29 Alan Modra <amodra@bigpond.net.au>
628
629 * ppc-opc.c: Support optional L form mtmsr.
630
82c18208
L		 6312008-01-24 H.J. Lu <hongjiu.lu@intel.com>
632
633 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
634
599121aa
L		 6352008-01-23 H.J. Lu <hongjiu.lu@intel.com>
636
637 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
638 * i386-init.h: Regenerated.
639
80098f51
TG		 6402008-01-23 Tristan Gingold <gingold@adacore.com>
641
642 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
643 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
644
115c7c25
L		 6452008-01-22 H.J. Lu <hongjiu.lu@intel.com>
646
647 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
648 (cpu_flags): Likewise.
649
650 * i386-opc.h (CpuMMX2): Removed.
651 (CpuSSE): Updated.
652
653 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
654 * i386-init.h: Regenerated.
655 * i386-tbl.h: Likewise.
656
6305a203
L		 6572008-01-22 H.J. Lu <hongjiu.lu@intel.com>
658
659 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
660 CPU_SMX_FLAGS.
661 * i386-init.h: Regenerated.
662
fd07a1c8
L		 6632008-01-15 H.J. Lu <hongjiu.lu@intel.com>
664
665 * i386-opc.tbl: Use Qword on movddup.
666 * i386-tbl.h: Regenerated.
667
321fd21e
L		 6682008-01-15 H.J. Lu <hongjiu.lu@intel.com>
669
670 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
671 * i386-tbl.h: Regenerated.
672
4ee52178
L		 6732008-01-15 H.J. Lu <hongjiu.lu@intel.com>
674
675 * i386-dis.c (Mx): New.
676 (PREFIX_0FC3): Likewise.
677 (PREFIX_0FC7_REG_6): Updated.
678 (dis386_twobyte): Use PREFIX_0FC3.
679 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
680 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
681 movntss.
682
5c07affc
L		 6832008-01-14 H.J. Lu <hongjiu.lu@intel.com>
684
685 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
686 (operand_types): Add Mem.
687
688 * i386-opc.h (IntelSyntax): New.
689 * i386-opc.h (Mem): New.
690 (Byte): Updated.
691 (Opcode_Modifier_Max): Updated.
692 (i386_opcode_modifier): Add intelsyntax.
693 (i386_operand_type): Add mem.
694
695 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
696 instructions.
697
698 * i386-reg.tbl: Add size for accumulator.
699
700 * i386-init.h: Regenerated.
701 * i386-tbl.h: Likewise.
702
0d6a2f58
L		 7032008-01-13 H.J. Lu <hongjiu.lu@intel.com>
704
705 * i386-opc.h (Byte): Fix a typo.
706
7d5e4556
L		 7072008-01-12 H.J. Lu <hongjiu.lu@intel.com>
708
709 PR gas/5534
710 * i386-gen.c (operand_type_init): Add Dword to
711 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
712 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
713 Qword and Xmmword.
714 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
715 Xmmword, Unspecified and Anysize.
716 (set_bitfield): Make Mmword an alias of Qword. Make Oword
717 an alias of Xmmword.
718
719 * i386-opc.h (CheckSize): Removed.
720 (Byte): Updated.
721 (Word): Likewise.
722 (Dword): Likewise.
723 (Qword): Likewise.
724 (Xmmword): Likewise.
725 (FWait): Updated.
726 (OTMax): Likewise.
727 (i386_opcode_modifier): Remove checksize, byte, word, dword,
728 qword and xmmword.
729 (Fword): New.
730 (TBYTE): Likewise.
731 (Unspecified): Likewise.
732 (Anysize): Likewise.
733 (i386_operand_type): Add byte, word, dword, fword, qword,
734 tbyte xmmword, unspecified and anysize.
735
736 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
737 Tbyte, Xmmword, Unspecified and Anysize.
738
739 * i386-reg.tbl: Add size for accumulator.
740
741 * i386-init.h: Regenerated.
742 * i386-tbl.h: Likewise.
743
b5b1fc4f
L		 7442008-01-10 H.J. Lu <hongjiu.lu@intel.com>
745
746 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
747 (REG_0F18): Updated.
748 (reg_table): Updated.
749 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
750 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
751
50e8458f
L		 7522008-01-08 H.J. Lu <hongjiu.lu@intel.com>
753
754 * i386-gen.c (set_bitfield): Use fail () on error.
755
3d4d5afa
L		 7562008-01-08 H.J. Lu <hongjiu.lu@intel.com>
757
758 * i386-gen.c (lineno): New.
759 (filename): Likewise.
760 (set_bitfield): Report filename and line numer on error.
761 (process_i386_opcodes): Set filename and update lineno.
762 (process_i386_registers): Likewise.
763
e1d4d893
L		 7642008-01-05 H.J. Lu <hongjiu.lu@intel.com>
765
766 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
767 ATTSyntax.
768
769 * i386-opc.h (IntelMnemonic): Renamed to ..
770 (ATTSyntax): This
771 (Opcode_Modifier_Max): Updated.
772 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
773 and intelsyntax.
774
8944f3c2 775 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 776 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
777 * i386-tbl.h: Regenerated.
778
6f143e4d
L		 7792008-01-04 H.J. Lu <hongjiu.lu@intel.com>
780
781 * i386-gen.c: Update copyright to 2008.
782 * i386-opc.h: Likewise.
783 * i386-opc.tbl: Likewise.
784
785 * i386-init.h: Regenerated.
786 * i386-tbl.h: Likewise.
787
c6add537
L		 7882008-01-04 H.J. Lu <hongjiu.lu@intel.com>
789
790 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
791 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
792 * i386-tbl.h: Regenerated.
793
3629bb00
L		 7942008-01-03 H.J. Lu <hongjiu.lu@intel.com>
795
796 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
797 CpuSSE4_2_Or_ABM.
798 (cpu_flags): Likewise.
799
800 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
801 (CpuSSE4_2_Or_ABM): Likewise.
802 (CpuLM): Updated.
803 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
804
805 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
806 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
807 and CpuPadLock, respectively.
808 * i386-init.h: Regenerated.
809 * i386-tbl.h: Likewise.
810
24995bd6
L		 8112008-01-03 H.J. Lu <hongjiu.lu@intel.com>
812
813 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
814
815 * i386-opc.h (No_xSuf): Removed.
816 (CheckSize): Updated.
817
818 * i386-tbl.h: Regenerated.
819
e0329a22
L		 8202008-01-02 H.J. Lu <hongjiu.lu@intel.com>
821
822 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
823 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
824 CPU_SSE5_FLAGS.
825 (cpu_flags): Add CpuSSE4_2_Or_ABM.
826
827 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
828 (CpuLM): Updated.
829 (i386_cpu_flags): Add cpusse4_2_or_abm.
830
831 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
832 CpuABM|CpuSSE4_2 on popcnt.
833 * i386-init.h: Regenerated.
834 * i386-tbl.h: Likewise.
835
f2a9c676
L		 8362008-01-02 H.J. Lu <hongjiu.lu@intel.com>
837
838 * i386-opc.h: Update comments.
839
d978b5be
L		 8402008-01-02 H.J. Lu <hongjiu.lu@intel.com>
841
842 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
843 * i386-opc.h: Likewise.
844 * i386-opc.tbl: Likewise.
845
582d5edd
L		 8462008-01-02 H.J. Lu <hongjiu.lu@intel.com>
847
848 PR gas/5534
849 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
850 Byte, Word, Dword, QWord and Xmmword.
851
852 * i386-opc.h (No_xSuf): New.
853 (CheckSize): Likewise.
854 (Byte): Likewise.
855 (Word): Likewise.
856 (Dword): Likewise.
857 (QWord): Likewise.
858 (Xmmword): Likewise.
859 (FWait): Updated.
860 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
861 Dword, QWord and Xmmword.
862
863 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
864 used.
865 * i386-tbl.h: Regenerated.
866
3fe15143
MK		 8672008-01-02 Mark Kettenis <kettenis@gnu.org>
868
869 * m88k-dis.c (instructions): Fix fcvt.* instructions.
870 From Miod Vallat.
871
6c7ac64e 872For older changes see ChangeLog-2007
252b5132
RH		 873\f
874Local Variables:
2f6d2f85
NC		 875mode: change-log
876left-margin: 8
877fill-column: 74
252b5132
RH		 878version-control: never
879End:
GDB Binutils - Deliverables
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