Commit | Line | Data |
---|---|---|
73cd51e5 AV |
1 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
2 | Michael Collison <michael.collison@arm.com> | |
3 | ||
4 | * arm-dis.c (enum mve_instructions): New enum. | |
5 | (enum mve_unpredictable): Likewise. | |
6 | (enum mve_undefined): Likewise. | |
7 | (struct mopcode32): New struct. | |
8 | (is_mve_okay_in_it): New function. | |
9 | (is_mve_architecture): Likewise. | |
10 | (arm_decode_field): Likewise. | |
11 | (arm_decode_field_multiple): Likewise. | |
12 | (is_mve_encoding_conflict): Likewise. | |
13 | (is_mve_undefined): Likewise. | |
14 | (is_mve_unpredictable): Likewise. | |
15 | (print_mve_undefined): Likewise. | |
16 | (print_mve_unpredictable): Likewise. | |
17 | (print_insn_coprocessor_1): Use arm_decode_field_multiple. | |
18 | (print_insn_mve): New function. | |
19 | (print_insn_thumb32): Handle MVE architecture. | |
20 | (select_arm_features): Force thumb for Armv8.1-m Mainline. | |
21 | ||
3076e594 NC |
22 | 2019-05-10 Nick Clifton <nickc@redhat.com> |
23 | ||
24 | PR 24538 | |
25 | * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the | |
26 | end of the table prematurely. | |
27 | ||
387e7624 FS |
28 | 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com> |
29 | ||
30 | * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB | |
31 | macros for R6. | |
32 | ||
0067be51 AM |
33 | 2019-05-11 Alan Modra <amodra@gmail.com> |
34 | ||
35 | * ppc-dis.c (print_insn_powerpc) Don't skip optional operands | |
36 | when -Mraw is in effect. | |
37 | ||
42e6288f MM |
38 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
39 | ||
40 | * aarch64-dis-2.c: Regenerate. | |
41 | * aarch64-tbl.h (OP_SVE_BBU): New variant set. | |
42 | (OP_SVE_BBB): New variant set. | |
43 | (OP_SVE_DDDD): New variant set. | |
44 | (OP_SVE_HHH): New variant set. | |
45 | (OP_SVE_HHHU): New variant set. | |
46 | (OP_SVE_SSS): New variant set. | |
47 | (OP_SVE_SSSU): New variant set. | |
48 | (OP_SVE_SHH): New variant set. | |
49 | (OP_SVE_SBBU): New variant set. | |
50 | (OP_SVE_DSS): New variant set. | |
51 | (OP_SVE_DHHU): New variant set. | |
52 | (OP_SVE_VMV_HSD_BHS): New variant set. | |
53 | (OP_SVE_VVU_HSD_BHS): New variant set. | |
54 | (OP_SVE_VVVU_SD_BH): New variant set. | |
55 | (OP_SVE_VVVU_BHSD): New variant set. | |
56 | (OP_SVE_VVV_QHD_DBS): New variant set. | |
57 | (OP_SVE_VVV_HSD_BHS): New variant set. | |
58 | (OP_SVE_VVV_HSD_BHS2): New variant set. | |
59 | (OP_SVE_VVV_BHS_HSD): New variant set. | |
60 | (OP_SVE_VV_BHS_HSD): New variant set. | |
61 | (OP_SVE_VVV_SD): New variant set. | |
62 | (OP_SVE_VVU_BHS_HSD): New variant set. | |
63 | (OP_SVE_VZVV_SD): New variant set. | |
64 | (OP_SVE_VZVV_BH): New variant set. | |
65 | (OP_SVE_VZV_SD): New variant set. | |
66 | (aarch64_opcode_table): Add sve2 instructions. | |
67 | ||
28ed815a MM |
68 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
69 | ||
70 | * aarch64-asm-2.c: Regenerated. | |
71 | * aarch64-dis-2.c: Regenerated. | |
72 | * aarch64-opc-2.c: Regenerated. | |
73 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
74 | for SVE_SHLIMM_UNPRED_22. | |
75 | (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. | |
76 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 | |
77 | operand. | |
78 | ||
fd1dc4a0 MM |
79 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
80 | ||
81 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
82 | sve_size_tsz_bhs iclass encode. | |
83 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
84 | sve_size_tsz_bhs iclass decode. | |
85 | ||
31e36ab3 MM |
86 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
87 | ||
88 | * aarch64-asm-2.c: Regenerated. | |
89 | * aarch64-dis-2.c: Regenerated. | |
90 | * aarch64-opc-2.c: Regenerated. | |
91 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
92 | for SVE_Zm4_11_INDEX. | |
93 | (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. | |
94 | (fields): Handle SVE_i2h field. | |
95 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. | |
96 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand. | |
97 | ||
1be5f94f MM |
98 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
99 | ||
100 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
101 | sve_shift_tsz_bhsd iclass encode. | |
102 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
103 | sve_shift_tsz_bhsd iclass decode. | |
104 | ||
3c17238b MM |
105 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
106 | ||
107 | * aarch64-asm-2.c: Regenerated. | |
108 | * aarch64-dis-2.c: Regenerated. | |
109 | * aarch64-opc-2.c: Regenerated. | |
110 | * aarch64-asm.c (aarch64_ins_sve_shrimm): | |
111 | (aarch64_encode_variant_using_iclass): Handle | |
112 | sve_shift_tsz_hsd iclass encode. | |
113 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
114 | sve_shift_tsz_hsd iclass decode. | |
115 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
116 | for SVE_SHRIMM_UNPRED_22. | |
117 | (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. | |
118 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 | |
119 | operand. | |
120 | ||
cd50a87a MM |
121 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
122 | ||
123 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
124 | sve_size_013 iclass encode. | |
125 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
126 | sve_size_013 iclass decode. | |
127 | ||
3c705960 MM |
128 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
129 | ||
130 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
131 | sve_size_bh iclass encode. | |
132 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
133 | sve_size_bh iclass decode. | |
134 | ||
0a57e14f MM |
135 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
136 | ||
137 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
138 | sve_size_sd2 iclass encode. | |
139 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
140 | sve_size_sd2 iclass decode. | |
141 | * aarch64-opc.c (fields): Handle SVE_sz2 field. | |
142 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field. | |
143 | ||
c469c864 MM |
144 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
145 | ||
146 | * aarch64-asm-2.c: Regenerated. | |
147 | * aarch64-dis-2.c: Regenerated. | |
148 | * aarch64-opc-2.c: Regenerated. | |
149 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
150 | for SVE_ADDR_ZX. | |
151 | (aarch64_print_operand): Add printing for SVE_ADDR_ZX. | |
152 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand. | |
153 | ||
116adc27 MM |
154 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
155 | ||
156 | * aarch64-asm-2.c: Regenerated. | |
157 | * aarch64-dis-2.c: Regenerated. | |
158 | * aarch64-opc-2.c: Regenerated. | |
159 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
160 | for SVE_Zm3_11_INDEX. | |
161 | (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. | |
162 | (fields): Handle SVE_i3l and SVE_i3h2 fields. | |
163 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 | |
164 | fields. | |
165 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand. | |
166 | ||
3bd82c86 MM |
167 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
168 | ||
169 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
170 | sve_size_hsd2 iclass encode. | |
171 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
172 | sve_size_hsd2 iclass decode. | |
173 | * aarch64-opc.c (fields): Handle SVE_size field. | |
174 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field. | |
175 | ||
adccc507 MM |
176 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
177 | ||
178 | * aarch64-asm-2.c: Regenerated. | |
179 | * aarch64-dis-2.c: Regenerated. | |
180 | * aarch64-opc-2.c: Regenerated. | |
181 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
182 | for SVE_IMM_ROT3. | |
183 | (aarch64_print_operand): Add printing for SVE_IMM_ROT3. | |
184 | (fields): Handle SVE_rot3 field. | |
185 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. | |
186 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand. | |
187 | ||
5cd99750 MM |
188 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
189 | ||
190 | * aarch64-opc.c (verify_constraints): Check for movprfx for sve2 | |
191 | instructions. | |
192 | ||
7ce2460a MM |
193 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
194 | ||
195 | * aarch64-tbl.h | |
196 | (aarch64_feature_sve2, aarch64_feature_sve2aes, | |
197 | aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, | |
198 | aarch64_feature_sve2bitperm): New feature sets. | |
199 | (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros | |
200 | for feature set addresses. | |
201 | (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, | |
202 | SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros. | |
203 | ||
41cee089 FS |
204 | 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com> |
205 | Faraz Shahbazker <fshahbazker@wavecomp.com> | |
206 | ||
207 | * mips-dis.c (mips_calculate_combination_ases): Add ISA | |
208 | argument and set ASE_EVA_R6 appropriately. | |
209 | (set_default_mips_dis_options): Pass ISA to above. | |
210 | (parse_mips_dis_option): Likewise. | |
211 | * mips-opc.c (EVAR6): New macro. | |
212 | (mips_builtin_opcodes): Add llwpe, scwpe. | |
213 | ||
b83b4b13 SD |
214 | 2019-05-01 Sudakshina Das <sudi.das@arm.com> |
215 | ||
216 | * aarch64-asm-2.c: Regenerated. | |
217 | * aarch64-dis-2.c: Regenerated. | |
218 | * aarch64-opc-2.c: Regenerated. | |
219 | * aarch64-opc.c (operand_general_constraint_met_p): Add case for | |
220 | AARCH64_OPND_TME_UIMM16. | |
221 | (aarch64_print_operand): Likewise. | |
222 | * aarch64-tbl.h (QL_IMM_NIL): New. | |
223 | (TME): New. | |
224 | (_TME_INSN): New. | |
225 | (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel. | |
226 | ||
4a90ce95 JD |
227 | 2019-04-29 John Darrington <john@darrington.wattle.id.au> |
228 | ||
229 | * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails. | |
230 | ||
a45328b9 AB |
231 | 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com> |
232 | Faraz Shahbazker <fshahbazker@wavecomp.com> | |
233 | ||
234 | * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp. | |
235 | ||
d10be0cb JD |
236 | 2019-04-24 John Darrington <john@darrington.wattle.id.au> |
237 | ||
238 | * s12z-opc.h: Add extern "C" bracketing to help | |
239 | users who wish to use this interface in c++ code. | |
240 | ||
a679f24e JD |
241 | 2019-04-24 John Darrington <john@darrington.wattle.id.au> |
242 | ||
243 | * s12z-opc.c (bm_decode): Handle bit map operations with the | |
244 | "reserved0" mode. | |
245 | ||
32c36c3c AV |
246 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
247 | ||
248 | * arm-dis.c (coprocessor_opcodes): Document new %J and %K format | |
249 | specifier. Add entries for VLDR and VSTR of system registers. | |
250 | (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in | |
251 | coprocessor instructions on Armv8.1-M Mainline targets. Add handling | |
252 | of %J and %K format specifier. | |
253 | ||
efd6b359 AV |
254 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
255 | ||
256 | * arm-dis.c (coprocessor_opcodes): Document new %C format control code. | |
257 | Add new entries for VSCCLRM instruction. | |
258 | (print_insn_coprocessor): Handle new %C format control code. | |
259 | ||
6b0dd094 AV |
260 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
261 | ||
262 | * arm-dis.c (enum isa): New enum. | |
263 | (struct sopcode32): New structure. | |
264 | (coprocessor_opcodes): change type of entries to struct sopcode32 and | |
265 | set isa field of all current entries to ANY. | |
266 | (print_insn_coprocessor): Change type of insn to struct sopcode32. | |
267 | Only match an entry if its isa field allows the current mode. | |
268 | ||
4b5a202f AV |
269 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
270 | ||
271 | * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for | |
272 | CLRM. | |
273 | (print_insn_thumb32): Add logic to print %n CLRM register list. | |
274 | ||
60f993ce AV |
275 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
276 | ||
277 | * arm-dis.c (print_insn_thumb32): Updated to accept new %P | |
278 | and %Q patterns. | |
279 | ||
f6b2b12d AV |
280 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
281 | ||
282 | * arm-dis.c (thumb32_opcodes): New instruction bfcsel. | |
283 | (print_insn_thumb32): Edit the switch case for %Z. | |
284 | ||
1889da70 AV |
285 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
286 | ||
287 | * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern. | |
288 | ||
65d1bc05 AV |
289 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
290 | ||
291 | * arm-dis.c (thumb32_opcodes): New instruction bfl. | |
292 | ||
1caf72a5 AV |
293 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
294 | ||
295 | * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern. | |
296 | ||
f1c7f421 AV |
297 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
298 | ||
299 | * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an | |
300 | Arm register with r13 and r15 unpredictable. | |
301 | (thumb32_opcodes): New instructions for bfx and bflx. | |
302 | ||
4389b29a AV |
303 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
304 | ||
305 | * arm-dis.c (thumb32_opcodes): New instructions for bf. | |
306 | ||
e5d6e09e AV |
307 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
308 | ||
309 | * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern. | |
310 | ||
e12437dc AV |
311 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
312 | ||
313 | * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern. | |
314 | ||
031254f2 AV |
315 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
316 | ||
317 | * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline. | |
318 | ||
e5a557ac JD |
319 | 2019-04-12 John Darrington <john@darrington.wattle.id.au> |
320 | ||
321 | s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with | |
322 | "optr". ("operator" is a reserved word in c++). | |
323 | ||
bd7ceb8d SD |
324 | 2019-04-11 Sudakshina Das <sudi.das@arm.com> |
325 | ||
326 | * aarch64-opc.c (aarch64_print_operand): Add case for | |
327 | AARCH64_OPND_Rt_SP. | |
328 | (verify_constraints): Likewise. | |
329 | * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. | |
330 | (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions | |
331 | to accept Rt|SP as first operand. | |
332 | (AARCH64_OPERANDS): Add new Rt_SP. | |
333 | * aarch64-asm-2.c: Regenerated. | |
334 | * aarch64-dis-2.c: Regenerated. | |
335 | * aarch64-opc-2.c: Regenerated. | |
336 | ||
e54010f1 SD |
337 | 2019-04-11 Sudakshina Das <sudi.das@arm.com> |
338 | ||
339 | * aarch64-asm-2.c: Regenerated. | |
340 | * aarch64-dis-2.c: Likewise. | |
341 | * aarch64-opc-2.c: Likewise. | |
342 | * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm. | |
343 | ||
7e96e219 RS |
344 | 2019-04-09 Robert Suchanek <robert.suchanek@mips.com> |
345 | ||
346 | * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. | |
347 | ||
6f2791d5 L |
348 | 2019-04-08 H.J. Lu <hongjiu.lu@intel.com> |
349 | ||
350 | * i386-opc.tbl: Consolidate AVX512 BF16 entries. | |
351 | * i386-init.h: Regenerated. | |
352 | ||
e392bad3 AM |
353 | 2019-04-07 Alan Modra <amodra@gmail.com> |
354 | ||
355 | * ppc-dis.c (print_insn_powerpc): Use a tiny state machine | |
356 | op_separator to control printing of spaces, comma and parens | |
357 | rather than need_comma, need_paren and spaces vars. | |
358 | ||
dffaa15c AM |
359 | 2019-04-07 Alan Modra <amodra@gmail.com> |
360 | ||
361 | PR 24421 | |
362 | * arm-dis.c (print_insn_coprocessor): Correct bracket placement. | |
363 | (print_insn_neon, print_insn_arm): Likewise. | |
364 | ||
d6aab7a1 XG |
365 | 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> |
366 | ||
367 | * i386-dis-evex.h (evex_table): Updated to support BF16 | |
368 | instructions. | |
369 | * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 | |
370 | and EVEX_W_0F3872_P_3. | |
371 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. | |
372 | (cpu_flags): Add bitfield for CpuAVX512_BF16. | |
373 | * i386-opc.h (enum): Add CpuAVX512_BF16. | |
374 | (i386_cpu_flags): Add bitfield for cpuavx512_bf16. | |
375 | * i386-opc.tbl: Add AVX512 BF16 instructions. | |
376 | * i386-init.h: Regenerated. | |
377 | * i386-tbl.h: Likewise. | |
378 | ||
66e85460 AM |
379 | 2019-04-05 Alan Modra <amodra@gmail.com> |
380 | ||
381 | * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK. | |
382 | (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics | |
383 | to favour printing of "-" branch hint when using the "y" bit. | |
384 | Allow BH field on bc{ctr,lr,tar}{,l}{-,+}. | |
385 | ||
c2b1c275 AM |
386 | 2019-04-05 Alan Modra <amodra@gmail.com> |
387 | ||
388 | * ppc-dis.c (print_insn_powerpc): Delay printing spaces after | |
389 | opcode until first operand is output. | |
390 | ||
aae9718e PB |
391 | 2019-04-04 Peter Bergner <bergner@linux.ibm.com> |
392 | ||
393 | PR gas/24349 | |
394 | * ppc-opc.c (valid_bo_pre_v2): Add comments. | |
395 | (valid_bo_post_v2): Add support for 'at' branch hints. | |
396 | (insert_bo): Only error on branch on ctr. | |
397 | (get_bo_hint_mask): New function. | |
398 | (insert_boe): Add new 'branch_taken' formal argument. Add support | |
399 | for inserting 'at' branch hints. | |
400 | (extract_boe): Add new 'branch_taken' formal argument. Add support | |
401 | for extracting 'at' branch hints. | |
402 | (insert_bom, extract_bom, insert_bop, extract_bop): New functions. | |
403 | (BOE): Delete operand. | |
404 | (BOM, BOP): New operands. | |
405 | (RM): Update value. | |
406 | (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. | |
407 | (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-, | |
408 | bcctrl-, bctar-, bctarl->: Replace BOE with BOM. | |
409 | (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+, | |
410 | bcctrl+, bctar+, bctarl+>: Replace BOE with BOP. | |
411 | <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, | |
412 | bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, | |
413 | bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, | |
414 | bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, | |
415 | bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, | |
416 | bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, | |
417 | bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, | |
418 | bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, | |
419 | beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, | |
420 | bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, | |
421 | buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, | |
422 | bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, | |
423 | bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, | |
424 | bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, | |
425 | bttarl+>: New extended mnemonics. | |
426 | ||
96a86c01 AM |
427 | 2019-03-28 Alan Modra <amodra@gmail.com> |
428 | ||
429 | PR 24390 | |
430 | * ppc-opc.c (BTF): Define. | |
431 | (powerpc_opcodes): Use for mtfsb*. | |
432 | * ppc-dis.c (print_insn_powerpc): Print fields with both | |
433 | PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. | |
434 | ||
796d6298 TC |
435 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
436 | ||
437 | * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols. | |
438 | (mapping_symbol_for_insn): Implement new algorithm. | |
439 | (print_insn): Remove duplicate code. | |
440 | ||
60df3720 TC |
441 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
442 | ||
443 | * aarch64-dis.c (print_insn_aarch64): | |
444 | Implement override. | |
445 | ||
51457761 TC |
446 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
447 | ||
448 | * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search | |
449 | order. | |
450 | ||
53b2f36b TC |
451 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
452 | ||
453 | * aarch64-dis.c (last_stop_offset): New. | |
454 | (print_insn_aarch64): Use stop_offset. | |
455 | ||
89199bb5 L |
456 | 2019-03-19 H.J. Lu <hongjiu.lu@intel.com> |
457 | ||
458 | PR gas/24359 | |
459 | * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to | |
460 | CPU_ANY_AVX2_FLAGS. | |
461 | * i386-init.h: Regenerated. | |
462 | ||
97ed31ae L |
463 | 2019-03-18 H.J. Lu <hongjiu.lu@intel.com> |
464 | ||
465 | PR gas/24348 | |
466 | * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, | |
467 | vmovdqu16, vmovdqu32 and vmovdqu64. | |
468 | * i386-tbl.h: Regenerated. | |
469 | ||
0919bfe9 AK |
470 | 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com> |
471 | ||
472 | * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand | |
473 | from vstrszb, vstrszh, and vstrszf. | |
474 | ||
475 | 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com> | |
476 | ||
477 | * s390-opc.txt: Add instruction descriptions. | |
478 | ||
21820ebe JW |
479 | 2019-02-08 Jim Wilson <jimw@sifive.com> |
480 | ||
481 | * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form. | |
482 | <bne>: Likewise. | |
483 | ||
f7dd2fb2 TC |
484 | 2019-02-07 Tamar Christina <tamar.christina@arm.com> |
485 | ||
486 | * arm-dis.c (arm_opcodes): Redefine hlt to armv1. | |
487 | ||
6456d318 TC |
488 | 2019-02-07 Tamar Christina <tamar.christina@arm.com> |
489 | ||
490 | PR binutils/23212 | |
491 | * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. | |
492 | * aarch64-opc.c (verify_elem_sd): New. | |
493 | (fields): Add FLD_sz entr. | |
494 | * aarch64-tbl.h (_SIMD_INSN): New. | |
495 | (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and | |
496 | fmulx scalar and vector by element isns. | |
497 | ||
4a83b610 NC |
498 | 2019-02-07 Nick Clifton <nickc@redhat.com> |
499 | ||
500 | * po/sv.po: Updated Swedish translation. | |
501 | ||
fc60b8c8 AK |
502 | 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> |
503 | ||
504 | * s390-mkopc.c (main): Accept arch13 as cpu string. | |
505 | * s390-opc.c: Add new instruction formats and instruction opcode | |
506 | masks. | |
507 | * s390-opc.txt: Add new arch13 instructions. | |
508 | ||
e10620d3 TC |
509 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
510 | ||
511 | * aarch64-tbl.h (QL_LDST_AT): Update macro. | |
512 | (aarch64_opcode): Change encoding for stg, stzg | |
513 | st2g and st2zg. | |
514 | * aarch64-asm-2.c: Regenerated. | |
515 | * aarch64-dis-2.c: Regenerated. | |
516 | * aarch64-opc-2.c: Regenerated. | |
517 | ||
20a4ca55 SD |
518 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
519 | ||
520 | * aarch64-asm-2.c: Regenerated. | |
521 | * aarch64-dis-2.c: Likewise. | |
522 | * aarch64-opc-2.c: Likewise. | |
523 | * aarch64-tbl.h (aarch64_opcode): Add new stzgm. | |
524 | ||
550fd7bf SD |
525 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
526 | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | |
527 | ||
528 | * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. | |
529 | * aarch64-asm.h (ins_addr_simple_2): Likeiwse. | |
530 | * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. | |
531 | * aarch64-dis.h (ext_addr_simple_2): Likewise. | |
532 | * aarch64-opc.c (operand_general_constraint_met_p): Remove | |
533 | case for ldstgv_indexed. | |
534 | (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. | |
535 | * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. | |
536 | (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. | |
537 | * aarch64-asm-2.c: Regenerated. | |
538 | * aarch64-dis-2.c: Regenerated. | |
539 | * aarch64-opc-2.c: Regenerated. | |
540 | ||
d9938630 NC |
541 | 2019-01-23 Nick Clifton <nickc@redhat.com> |
542 | ||
543 | * po/pt_BR.po: Updated Brazilian Portuguese translation. | |
544 | ||
375cd423 NC |
545 | 2019-01-21 Nick Clifton <nickc@redhat.com> |
546 | ||
547 | * po/de.po: Updated German translation. | |
548 | * po/uk.po: Updated Ukranian translation. | |
549 | ||
57299f48 CX |
550 | 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com> |
551 | * mips-dis.c (mips_arch_choices): Fix typo in | |
552 | gs464, gs464e and gs264e descriptors. | |
553 | ||
f48dfe41 NC |
554 | 2019-01-19 Nick Clifton <nickc@redhat.com> |
555 | ||
556 | * configure: Regenerate. | |
557 | * po/opcodes.pot: Regenerate. | |
558 | ||
f974f26c NC |
559 | 2018-06-24 Nick Clifton <nickc@redhat.com> |
560 | ||
561 | 2.32 branch created. | |
562 | ||
39f286cd JD |
563 | 2019-01-09 John Darrington <john@darrington.wattle.id.au> |
564 | ||
448b8ca8 JD |
565 | * s12z-dis.c (print_insn_s12z): Do not dereference an operand |
566 | if it is null. | |
567 | -dis.c (opr_emit_disassembly): Do not omit an index if it is | |
39f286cd JD |
568 | zero. |
569 | ||
3107326d AP |
570 | 2019-01-09 Andrew Paprocki <andrew@ishiboo.com> |
571 | ||
572 | * configure: Regenerate. | |
573 | ||
7e9ca91e AM |
574 | 2019-01-07 Alan Modra <amodra@gmail.com> |
575 | ||
576 | * configure: Regenerate. | |
577 | * po/POTFILES.in: Regenerate. | |
578 | ||
ef1ad42b JD |
579 | 2019-01-03 John Darrington <john@darrington.wattle.id.au> |
580 | ||
581 | * s12z-opc.c: New file. | |
582 | * s12z-opc.h: New file. | |
583 | * s12z-dis.c: Removed all code not directly related to display | |
584 | of instructions. Used the interface provided by the new files | |
585 | instead. | |
586 | * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c. | |
7e9ca91e | 587 | * Makefile.in: Regenerate. |
ef1ad42b | 588 | * configure.ac (bfd_s12z_arch): Correct the dependencies. |
7e9ca91e | 589 | * configure: Regenerate. |
ef1ad42b | 590 | |
82704155 AM |
591 | 2019-01-01 Alan Modra <amodra@gmail.com> |
592 | ||
593 | Update year range in copyright notice of all files. | |
594 | ||
d5c04e1b | 595 | For older changes see ChangeLog-2018 |
3499769a | 596 | \f |
d5c04e1b | 597 | Copyright (C) 2019 Free Software Foundation, Inc. |
3499769a AM |
598 | |
599 | Copying and distribution of this file, with or without modification, | |
600 | are permitted in any medium without royalty provided the copyright | |
601 | notice and this notice are preserved. | |
602 | ||
603 | Local Variables: | |
604 | mode: change-log | |
605 | left-margin: 8 | |
606 | fill-column: 74 | |
607 | version-control: never | |
608 | End: |