[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2011-06-29  H.J. Lu  <hongjiu.lu@intel.com>

	* tilegx-opc.c (find_opcode): Replace "index" with "i".
	* tilepro-opc.c (find_opcode): Likewise.

2011-06-29  Richard Sandiford  <rdsandiford@googlemail.com>

	* mips16-opc.c (jalrc, jrc): Move earlier in file.

2011-06-21  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
	PREFIX_VEX_0F388E.

2011-06-17  Andreas Schwab  <schwab@redhat.com>

	* Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
	(MOSTLYCLEANFILES): ... here.
	* Makefile.in: Regenerate.

2011-06-14  Alan Modra  <amodra@gmail.com>

	* Makefile.in: Regenerate.

2011-06-13  Walter Lee  <walt@tilera.com>

	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
	tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
	* Makefile.in: Regenerate.
	* configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
	* configure: Regenerate.
	* disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
	* po/POTFILES.in: Regenerate.
	* tilegx-dis.c: New file.
	* tilegx-opc.c: New file.
	* tilepro-dis.c: New file.
	* tilepro-opc.c: New file.

2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2011)
	* i386-dis.c (XMGatherQ): New.
	* i386-dis.c (EXxmm_mb): New.
	(EXxmm_mb): Likewise.
	(EXxmm_mw): Likewise.
	(EXxmm_md): Likewise.
	(EXxmm_mq): Likewise.
	(EXxmmdw): Likewise.
	(EXxmmqd): Likewise.
	(VexGatherQ): Likewise.
	(MVexVSIBDWpX): Likewise.
	(MVexVSIBQWpX): Likewise.
	(xmm_mb_mode): Likewise.
	(xmm_mw_mode): Likewise.
	(xmm_md_mode): Likewise.
	(xmm_mq_mode): Likewise.
	(xmmdw_mode): Likewise.
	(xmmqd_mode): Likewise.
	(ymmxmm_mode): Likewise.
	(vex_vsib_d_w_dq_mode): Likewise.
	(vex_vsib_q_w_dq_mode): Likewise.
	(MOD_VEX_0F385A_PREFIX_2): Likewise.
	(MOD_VEX_0F388C_PREFIX_2): Likewise.
	(MOD_VEX_0F388E_PREFIX_2): Likewise.
	(PREFIX_0F3882): Likewise.
	(PREFIX_VEX_0F3816): Likewise.
	(PREFIX_VEX_0F3836): Likewise.
	(PREFIX_VEX_0F3845): Likewise.
	(PREFIX_VEX_0F3846): Likewise.
	(PREFIX_VEX_0F3847): Likewise.
	(PREFIX_VEX_0F3858): Likewise.
	(PREFIX_VEX_0F3859): Likewise.
	(PREFIX_VEX_0F385A): Likewise.
	(PREFIX_VEX_0F3878): Likewise.
	(PREFIX_VEX_0F3879): Likewise.
	(PREFIX_VEX_0F388C): Likewise.
	(PREFIX_VEX_0F388E): Likewise.
	(PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
	(PREFIX_VEX_0F38F5): Likewise.
	(PREFIX_VEX_0F38F6): Likewise.
	(PREFIX_VEX_0F3A00): Likewise.
	(PREFIX_VEX_0F3A01): Likewise.
	(PREFIX_VEX_0F3A02): Likewise.
	(PREFIX_VEX_0F3A38): Likewise.
	(PREFIX_VEX_0F3A39): Likewise.
	(PREFIX_VEX_0F3A46): Likewise.
	(PREFIX_VEX_0F3AF0): Likewise.
	(VEX_LEN_0F3816_P_2): Likewise.
	(VEX_LEN_0F3819_P_2): Likewise.
	(VEX_LEN_0F3836_P_2): Likewise.
	(VEX_LEN_0F385A_P_2_M_0): Likewise.
	(VEX_LEN_0F38F5_P_0): Likewise.
	(VEX_LEN_0F38F5_P_1): Likewise.
	(VEX_LEN_0F38F5_P_3): Likewise.
	(VEX_LEN_0F38F6_P_3): Likewise.
	(VEX_LEN_0F38F7_P_1): Likewise.
	(VEX_LEN_0F38F7_P_2): Likewise.
	(VEX_LEN_0F38F7_P_3): Likewise.
	(VEX_LEN_0F3A00_P_2): Likewise.
	(VEX_LEN_0F3A01_P_2): Likewise.
	(VEX_LEN_0F3A38_P_2): Likewise.
	(VEX_LEN_0F3A39_P_2): Likewise.
	(VEX_LEN_0F3A46_P_2): Likewise.
	(VEX_LEN_0F3AF0_P_3): Likewise.
	(VEX_W_0F3816_P_2): Likewise.
	(VEX_W_0F3818_P_2): Likewise.
	(VEX_W_0F3819_P_2): Likewise.
	(VEX_W_0F3836_P_2): Likewise.
	(VEX_W_0F3846_P_2): Likewise.
	(VEX_W_0F3858_P_2): Likewise.
	(VEX_W_0F3859_P_2): Likewise.
	(VEX_W_0F385A_P_2_M_0): Likewise.
	(VEX_W_0F3878_P_2): Likewise.
	(VEX_W_0F3879_P_2): Likewise.
	(VEX_W_0F3A00_P_2): Likewise.
	(VEX_W_0F3A01_P_2): Likewise.
	(VEX_W_0F3A02_P_2): Likewise.
	(VEX_W_0F3A38_P_2): Likewise.
	(VEX_W_0F3A39_P_2): Likewise.
	(VEX_W_0F3A46_P_2): Likewise.
	(MOD_VEX_0F3818_PREFIX_2): Removed.
	(MOD_VEX_0F3819_PREFIX_2): Likewise.
	(VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
	(VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
	(VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
	(VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
	(VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
	(VEX_LEN_0F3A0E_P_2): Likewise.
	(VEX_LEN_0F3A0F_P_2): Likewise.
	(VEX_LEN_0F3A42_P_2): Likewise.
	(VEX_LEN_0F3A4C_P_2): Likewise.
	(VEX_W_0F3818_P_2_M_0): Likewise.
	(VEX_W_0F3819_P_2_M_0): Likewise.
	(prefix_table): Updated.
	(three_byte_table): Likewise.
	(vex_table): Likewise.
	(vex_len_table): Likewise.
	(vex_w_table): Likewise.
	(mod_table): Likewise.
	(putop): Handle "LW".
	(intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
	xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
	vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
	(OP_EX): Likewise.
	(OP_E_memory): Handle vex_vsib_d_w_dq_mode and
	vex_vsib_q_w_dq_mode.
	(OP_XMM): Handle vex_vsib_q_w_dq_mode.
	(OP_VEX): Likewise.

	* i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
	and CPU_ANY_AVX_FLAGS.  Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
	CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
	(cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
	(opcode_modifiers): Add VecSIB.

	* i386-opc.h (CpuAVX2): New.
	(CpuBMI2): Likewise.
	(CpuLZCNT): Likewise.
	(CpuINVPCID): Likewise.
	(VecSIB128): Likewise.
	(VecSIB256): Likewise.
	(VecSIB): Likewise.
	(i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
	(i386_opcode_modifier): Add vecsib.

	* i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2011-06-03  Quentin Neill  <quentin.neill@amd.com>

	* i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
	* i386-init.h: Regenerated.

2011-06-03  Nick Clifton  <nickc@redhat.com>

	PR binutils/12752
	* arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
	computing address offsets.
	(print_arm_address): Likewise.
	(print_insn_arm): Likewise.
	(print_insn_thumb16): Likewise.
	(print_insn_thumb32): Likewise.

2011-06-02  Jie Zhang <jie@codesourcery.com>
	    Nathan Sidwell <nathan@codesourcery.com>
	    Maciej Rozycki <macro@codesourcery.com>

	* arm-dis.c (print_insn_coprocessor): Explicitly print #-0
	as address offset.
	(print_arm_address): Likewise. Elide positive #0 appropriately.
	(print_insn_arm): Likewise.

2011-06-02  Nick Clifton  <nickc@redhat.com>

	PR gas/12752
	* arm-dis.c (print_insn_thumb32): Do not sign extend  addresses
	passed to print_address_func.

2011-06-02  Nick Clifton  <nickc@redhat.com>

	* arm-dis.c: Fix spelling mistakes.
	* op/opcodes.pot: Regenerate.

2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* s390-opc.c: Replace S390_OPERAND_REG_EVEN with
	S390_OPERAND_REG_PAIR.  Fix INSTR_RRF_0UFEF instruction type.
	* s390-opc.txt: Fix cxr instruction type.

2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* s390-opc.c: Add new instruction types marking register pair
	operands.
	* s390-opc.txt: Match instructions having register pair operands
	to the new instruction types.

2011-05-19  Nick Clifton  <nickc@redhat.com>

	* v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
	operands.

2011-05-10  Quentin Neill  <quentin.neill@amd.com>

	* i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
	* i386-init.h: Regenerated.

2011-04-27  Nick Clifton  <nickc@redhat.com>

	* po/da.po: Updated Danish translation.

2011-04-26  Anton Blanchard  <anton@samba.org>

	* ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.

2011-04-21  DJ Delorie  <dj@redhat.com>

	* rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
	* rx-decode.c: Regenerate.

2011-04-20  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-init.h: Regenerated.

2011-04-19  Quentin Neill  <quentin.neill@amd.com>

	* i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
	from bdver1 flags.

2011-04-13  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (disassemble): Always print a closing square brace if
	an opening square brace was printed.

2011-04-12  Nick Clifton  <nickc@redhat.com>

	PR binutils/12534
	* arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
	patterns.
	(print_insn_thumb32): Handle %L.

2011-04-11  Julian Brown  <julian@codesourcery.com>

	* arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
	(print_insn_thumb32): Add APSR bitmask support.

2011-04-07  Paul Carroll<pcarroll@codesourcery.com>

	* arm-dis.c (print_insn): init vars moved into private_data structure.

2011-03-24  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.

2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>

	* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
	post-increment to support LPM Z+ instruction. Add support for 'E'
	constraint for DES instruction.
	(print_insn_avr): Adjust calls to avr_operand. Rename variable.

2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>

	* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.

2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>

	* arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
	Use branch types instead.
	(print_insn): Likewise.

2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-opc.c (mips_builtin_opcodes): Correct register use
	annotation of "alnv.ps".

2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-opc.c (mips_builtin_opcodes): Add "pref" macro.

2011-02-22  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.

2011-02-22  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.

2011-02-19  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (saved_state): Mark static.  Change a[01]x to ax[] and
	a[01]w to aw[].  Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
	av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
	exception, end_of_registers, msize, memory, bfd_mach.
	(CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
	LB0REG, LC1REG, LT1REG, LB1REG): Delete
	(AXREG, AWREG, LCREG, LTREG, LBREG): Define.
	(get_allreg): Change to new defines.  Fallback to abort().

2011-02-14  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c: Add whitespace/parenthesis where needed.

2011-02-14  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
	than 7.

2011-02-13  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>

	* configure: Regenerate.

2011-02-13  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.

2011-02-13  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1.  Output
	dregs only when P is set, and dregs_lo otherwise.

2011-02-13  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.

2011-02-12  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.

2011-02-12  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (machine_registers): Delete REG_GP.
	(reg_names): Delete "GP".
	(decode_allregs): Change REG_GP to REG_LASTREG.

2011-02-12  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
	M_IH, M_IU): Delete.

2011-02-11  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (reg_names): Add const.
	(decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
	decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
	decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
	decode_counters, decode_allregs): Likewise.

2011-02-09  Michael Snyder  <msnyder@vmware.com>

	* i386-dis.c (OP_J): Parenthesize expression to prevent
	truncated addresses.
	(print_insn): Fix indentation off-by-one.

2011-02-01  Nick Clifton  <nickc@redhat.com>

	* po/da.po: Updated Danish translation.

2011-01-21  Dave Murphy  <davem@devkitpro.org>

	* ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.

2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (sIbT): New.
	(b_T_mode): Likewise.
	(dis386): Replace sIb with sIbT on "pushT".
	(x86_64_table): Replace sIb with Ib on "aam" and "aad".
	(OP_sI): Handle b_T_mode.  Properly sign-extend byte.

2011-01-18  Jan Kratochvil  <jan.kratochvil@redhat.com>

	* i386-init.h: Regenerated.
	* i386-tbl.h: Regenerated

2011-01-17  Quentin Neill  <quentin.neill@amd.com>

	* i386-dis.c (REG_XOP_TBM_01): New.
	(REG_XOP_TBM_02): New.
	(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
	(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
	entries, and add bextr instruction.

	* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
	(cpu_flags): Add CpuTBM.

	* i386-opc.h (CpuTBM) New.
	(i386_cpu_flags): Add bit cputbm.

	* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
	blcs, blsfill, blsic, t1mskc, and tzmsk.

2011-01-12  DJ Delorie  <dj@redhat.com>

	* rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.

2011-01-11  Mingjie Xing  <mingjie.xing@gmail.com>

	* mips-dis.c (print_insn_args): Adjust the value to print the real
	offset for "+c" argument.

2011-01-10  Nick Clifton  <nickc@redhat.com>

	* po/da.po: Updated Danish translation.

2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>

	* arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.

2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (REG_VEX_38F3): New.
	(PREFIX_0FBC): Likewise.
	(PREFIX_VEX_38F2): Likewise.
	(PREFIX_VEX_38F3_REG_1): Likewise.
	(PREFIX_VEX_38F3_REG_2): Likewise.
	(PREFIX_VEX_38F3_REG_3): Likewise.
	(PREFIX_VEX_38F7): Likewise.
	(VEX_LEN_38F2_P_0): Likewise.
	(VEX_LEN_38F3_R_1_P_0): Likewise.
	(VEX_LEN_38F3_R_2_P_0): Likewise.
	(VEX_LEN_38F3_R_3_P_0): Likewise.
	(VEX_LEN_38F7_P_0): Likewise.
	(dis386_twobyte): Use PREFIX_0FBC.
	(reg_table): Add REG_VEX_38F3.
	(prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
	PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
	PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
	(vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
	PREFIX_VEX_38F7.
	(vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
	VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
	VEX_LEN_38F7_P_0.

	* i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
	(cpu_flags): Add CpuBMI.

	* i386-opc.h (CpuBMI): New.
	(i386_cpu_flags): Add cpubmi.

	* i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (VexGdq): New.
	(OP_VEX): Handle dq_mode.

2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright to 2011.

For older changes see ChangeLog-2010
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
906efcbc L	1	2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
	2
	3	* tilegx-opc.c (find_opcode): Replace "index" with "i".
	4	* tilepro-opc.c (find_opcode): Likewise.
	5
ceb94aa5 RS	6	2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
	7
	8	* mips16-opc.c (jalrc, jrc): Move earlier in file.
	9
f7002f42 L	10	2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
	11
	12	* i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
	13	PREFIX_VEX_0F388E.
	14
56300268 AS	15	2011-06-17 Andreas Schwab <schwab@redhat.com>
	16
	17	* Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
	18	(MOSTLYCLEANFILES): ... here.
	19	* Makefile.in: Regenerate.
	20
bcf2cf9f AM	21	2011-06-14 Alan Modra <amodra@gmail.com>
	22
	23	* Makefile.in: Regenerate.
	24
aa137e4d NC	25	2011-06-13 Walter Lee <walt@tilera.com>
	26
	27	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
	28	tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
	29	* Makefile.in: Regenerate.
	30	* configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
	31	* configure: Regenerate.
	32	* disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
	33	* po/POTFILES.in: Regenerate.
	34	* tilegx-dis.c: New file.
	35	* tilegx-opc.c: New file.
	36	* tilepro-dis.c: New file.
	37	* tilepro-opc.c: New file.
	38
6c30d220 L	39	2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
	40
	41	AVX Programming Reference (June, 2011)
	42	* i386-dis.c (XMGatherQ): New.
	43	* i386-dis.c (EXxmm_mb): New.
	44	(EXxmm_mb): Likewise.
	45	(EXxmm_mw): Likewise.
	46	(EXxmm_md): Likewise.
	47	(EXxmm_mq): Likewise.
	48	(EXxmmdw): Likewise.
	49	(EXxmmqd): Likewise.
	50	(VexGatherQ): Likewise.
	51	(MVexVSIBDWpX): Likewise.
	52	(MVexVSIBQWpX): Likewise.
	53	(xmm_mb_mode): Likewise.
	54	(xmm_mw_mode): Likewise.
	55	(xmm_md_mode): Likewise.
	56	(xmm_mq_mode): Likewise.
	57	(xmmdw_mode): Likewise.
	58	(xmmqd_mode): Likewise.
	59	(ymmxmm_mode): Likewise.
	60	(vex_vsib_d_w_dq_mode): Likewise.
	61	(vex_vsib_q_w_dq_mode): Likewise.
	62	(MOD_VEX_0F385A_PREFIX_2): Likewise.
	63	(MOD_VEX_0F388C_PREFIX_2): Likewise.
	64	(MOD_VEX_0F388E_PREFIX_2): Likewise.
	65	(PREFIX_0F3882): Likewise.
	66	(PREFIX_VEX_0F3816): Likewise.
	67	(PREFIX_VEX_0F3836): Likewise.
	68	(PREFIX_VEX_0F3845): Likewise.
	69	(PREFIX_VEX_0F3846): Likewise.
	70	(PREFIX_VEX_0F3847): Likewise.
	71	(PREFIX_VEX_0F3858): Likewise.
	72	(PREFIX_VEX_0F3859): Likewise.
	73	(PREFIX_VEX_0F385A): Likewise.
	74	(PREFIX_VEX_0F3878): Likewise.
	75	(PREFIX_VEX_0F3879): Likewise.
	76	(PREFIX_VEX_0F388C): Likewise.
	77	(PREFIX_VEX_0F388E): Likewise.
	78	(PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
	79	(PREFIX_VEX_0F38F5): Likewise.
	80	(PREFIX_VEX_0F38F6): Likewise.
	81	(PREFIX_VEX_0F3A00): Likewise.
	82	(PREFIX_VEX_0F3A01): Likewise.
	83	(PREFIX_VEX_0F3A02): Likewise.
	84	(PREFIX_VEX_0F3A38): Likewise.
	85	(PREFIX_VEX_0F3A39): Likewise.
	86	(PREFIX_VEX_0F3A46): Likewise.
	87	(PREFIX_VEX_0F3AF0): Likewise.
	88	(VEX_LEN_0F3816_P_2): Likewise.
	89	(VEX_LEN_0F3819_P_2): Likewise.
	90	(VEX_LEN_0F3836_P_2): Likewise.
	91	(VEX_LEN_0F385A_P_2_M_0): Likewise.
	92	(VEX_LEN_0F38F5_P_0): Likewise.
	93	(VEX_LEN_0F38F5_P_1): Likewise.
	94	(VEX_LEN_0F38F5_P_3): Likewise.
	95	(VEX_LEN_0F38F6_P_3): Likewise.
	96	(VEX_LEN_0F38F7_P_1): Likewise.
	97	(VEX_LEN_0F38F7_P_2): Likewise.
	98	(VEX_LEN_0F38F7_P_3): Likewise.
	99	(VEX_LEN_0F3A00_P_2): Likewise.
	100	(VEX_LEN_0F3A01_P_2): Likewise.
	101	(VEX_LEN_0F3A38_P_2): Likewise.
	102	(VEX_LEN_0F3A39_P_2): Likewise.
103	(VEX_LEN_0F3A46_P_2): Likewise.
104	(VEX_LEN_0F3AF0_P_3): Likewise.
105	(VEX_W_0F3816_P_2): Likewise.
106	(VEX_W_0F3818_P_2): Likewise.
107	(VEX_W_0F3819_P_2): Likewise.
108	(VEX_W_0F3836_P_2): Likewise.
109	(VEX_W_0F3846_P_2): Likewise.
110	(VEX_W_0F3858_P_2): Likewise.
111	(VEX_W_0F3859_P_2): Likewise.
112	(VEX_W_0F385A_P_2_M_0): Likewise.
113	(VEX_W_0F3878_P_2): Likewise.
114	(VEX_W_0F3879_P_2): Likewise.
115	(VEX_W_0F3A00_P_2): Likewise.
116	(VEX_W_0F3A01_P_2): Likewise.
117	(VEX_W_0F3A02_P_2): Likewise.
118	(VEX_W_0F3A38_P_2): Likewise.
119	(VEX_W_0F3A39_P_2): Likewise.
120	(VEX_W_0F3A46_P_2): Likewise.
121	(MOD_VEX_0F3818_PREFIX_2): Removed.
122	(MOD_VEX_0F3819_PREFIX_2): Likewise.
123	(VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
124	(VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
125	(VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
126	(VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
127	(VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
128	(VEX_LEN_0F3A0E_P_2): Likewise.
129	(VEX_LEN_0F3A0F_P_2): Likewise.
130	(VEX_LEN_0F3A42_P_2): Likewise.
131	(VEX_LEN_0F3A4C_P_2): Likewise.
132	(VEX_W_0F3818_P_2_M_0): Likewise.
133	(VEX_W_0F3819_P_2_M_0): Likewise.
134	(prefix_table): Updated.
135	(three_byte_table): Likewise.
136	(vex_table): Likewise.
137	(vex_len_table): Likewise.
138	(vex_w_table): Likewise.
139	(mod_table): Likewise.
140	(putop): Handle "LW".
141	(intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
142	xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
143	vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
144	(OP_EX): Likewise.
145	(OP_E_memory): Handle vex_vsib_d_w_dq_mode and
146	vex_vsib_q_w_dq_mode.
147	(OP_XMM): Handle vex_vsib_q_w_dq_mode.
148	(OP_VEX): Likewise.
149
150	* i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
151	and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
152	CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
153	(cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
154	(opcode_modifiers): Add VecSIB.
155
156	* i386-opc.h (CpuAVX2): New.
157	(CpuBMI2): Likewise.
158	(CpuLZCNT): Likewise.
159	(CpuINVPCID): Likewise.
160	(VecSIB128): Likewise.
161	(VecSIB256): Likewise.
162	(VecSIB): Likewise.
163	(i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
164	(i386_opcode_modifier): Add vecsib.
165
166	* i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
167	* i386-init.h: Regenerated.
168	* i386-tbl.h: Likewise.
169
d535accd QN	170	2011-06-03 Quentin Neill <quentin.neill@amd.com>
	171
	172	* i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
	173	* i386-init.h: Regenerated.
	174
f8b960bc NC	175	2011-06-03 Nick Clifton <nickc@redhat.com>
	176
	177	PR binutils/12752
	178	* arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
	179	computing address offsets.
	180	(print_arm_address): Likewise.
	181	(print_insn_arm): Likewise.
	182	(print_insn_thumb16): Likewise.
	183	(print_insn_thumb32): Likewise.
	184
26d97720 NS	185	2011-06-02 Jie Zhang <jie@codesourcery.com>
	186	Nathan Sidwell <nathan@codesourcery.com>
	187	Maciej Rozycki <macro@codesourcery.com>
	188
	189	* arm-dis.c (print_insn_coprocessor): Explicitly print #-0
	190	as address offset.
	191	(print_arm_address): Likewise. Elide positive #0 appropriately.
	192	(print_insn_arm): Likewise.
	193
f8b960bc NC	194	2011-06-02 Nick Clifton <nickc@redhat.com>
	195
	196	PR gas/12752
	197	* arm-dis.c (print_insn_thumb32): Do not sign extend addresses
	198	passed to print_address_func.
	199
cc643b88 NC	200	2011-06-02 Nick Clifton <nickc@redhat.com>
	201
	202	* arm-dis.c: Fix spelling mistakes.
	203	* op/opcodes.pot: Regenerate.
	204
c8fa16ed AK	205	2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
	206
	207	* s390-opc.c: Replace S390_OPERAND_REG_EVEN with
	208	S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
	209	* s390-opc.txt: Fix cxr instruction type.
	210
5e4b319c AK	211	2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
	212
	213	* s390-opc.c: Add new instruction types marking register pair
	214	operands.
	215	* s390-opc.txt: Match instructions having register pair operands
	216	to the new instruction types.
	217
fda544a2 NC	218	2011-05-19 Nick Clifton <nickc@redhat.com>
	219
	220	* v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
	221	operands.
	222
4cab4add QN	223	2011-05-10 Quentin Neill <quentin.neill@amd.com>
	224
	225	* i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
	226	* i386-init.h: Regenerated.
	227
b4e7b885 NC	228	2011-04-27 Nick Clifton <nickc@redhat.com>
	229
	230	* po/da.po: Updated Danish translation.
	231
2f7f7710 AM	232	2011-04-26 Anton Blanchard <anton@samba.org>
	233
	234	* ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
	235
9887672f DD	236	2011-04-21 DJ Delorie <dj@redhat.com>
	237
	238	* rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
	239	* rx-decode.c: Regenerate.
	240
3251b375 L	241	2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
	242
	243	* i386-init.h: Regenerated.
	244
b13a3ca6 QN	245	2011-04-19 Quentin Neill <quentin.neill@amd.com>
	246
	247	* i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
	248	from bdver1 flags.
	249
7d063384 NC	250	2011-04-13 Nick Clifton <nickc@redhat.com>
	251
	252	* v850-dis.c (disassemble): Always print a closing square brace if
	253	an opening square brace was printed.
	254
32a94698 NC	255	2011-04-12 Nick Clifton <nickc@redhat.com>
	256
	257	PR binutils/12534
	258	* arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
	259	patterns.
	260	(print_insn_thumb32): Handle %L.
	261
d2cd1205 JB	262	2011-04-11 Julian Brown <julian@codesourcery.com>
	263
	264	* arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
	265	(print_insn_thumb32): Add APSR bitmask support.
	266
1fbaefec PB	267	2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
	268
	269	* arm-dis.c (print_insn): init vars moved into private_data structure.
	270
67171547 MF	271	2011-03-24 Mike Frysinger <vapier@gentoo.org>
	272
	273	* bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
	274
8cc66334 EW	275	2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
	276
	277	* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
	278	post-increment to support LPM Z+ instruction. Add support for 'E'
	279	constraint for DES instruction.
	280	(print_insn_avr): Adjust calls to avr_operand. Rename variable.
	281
34e77a92 RS	282	2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
	283
	284	* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
	285
35fc36a8 RS	286	2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
	287
	288	* arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
	289	Use branch types instead.
	290	(print_insn): Likewise.
	291
0067d8fc MR	292	2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
	293
	294	* mips-opc.c (mips_builtin_opcodes): Correct register use
	295	annotation of "alnv.ps".
	296
3eebd5eb MR	297	2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
	298
	299	* mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
	300
500cccad MF	301	2011-02-22 Mike Frysinger <vapier@gentoo.org>
	302
	303	* bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
	304
f5caf9f4 MF	305	2011-02-22 Mike Frysinger <vapier@gentoo.org>
	306
	307	* bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
	308
e5bc4265 MF	309	2011-02-19 Mike Frysinger <vapier@gentoo.org>
	310
	311	* bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
	312	a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
	313	av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
	314	exception, end_of_registers, msize, memory, bfd_mach.
	315	(CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
	316	LB0REG, LC1REG, LT1REG, LB1REG): Delete
	317	(AXREG, AWREG, LCREG, LTREG, LBREG): Define.
	318	(get_allreg): Change to new defines. Fallback to abort().
	319
602427c4 MF	320	2011-02-14 Mike Frysinger <vapier@gentoo.org>
	321
	322	* bfin-dis.c: Add whitespace/parenthesis where needed.
	323
298c1ec2 MF	324	2011-02-14 Mike Frysinger <vapier@gentoo.org>
	325
	326	* bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
	327	than 7.
	328
822ce8ee RW	329	2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
	330
	331	* configure: Regenerate.
	332
13c02f06 MF	333	2011-02-13 Mike Frysinger <vapier@gentoo.org>
	334
	335	* bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
	336
4db66394 MF	337	2011-02-13 Mike Frysinger <vapier@gentoo.org>
	338
	339	* bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
	340	dregs only when P is set, and dregs_lo otherwise.
	341
36f44611 MF	342	2011-02-13 Mike Frysinger <vapier@gentoo.org>
	343
	344	* bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
	345
9805c0a5 MF	346	2011-02-12 Mike Frysinger <vapier@gentoo.org>
	347
	348	* bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
	349
43a6aa65 MF	350	2011-02-12 Mike Frysinger <vapier@gentoo.org>
	351
	352	* bfin-dis.c (machine_registers): Delete REG_GP.
	353	(reg_names): Delete "GP".
	354	(decode_allregs): Change REG_GP to REG_LASTREG.
	355
26bb3ddd MF	356	2011-02-12 Mike Frysinger <vapier@gentoo.org>
26bb3ddd MF	357
89c0d58c MR	358	* bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
89c0d58c MR	359	M_IH, M_IU): Delete.
26bb3ddd	360
69b8ea4a MF	361	2011-02-11 Mike Frysinger <vapier@gentoo.org>
	362
	363	* bfin-dis.c (reg_names): Add const.
	364	(decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
	365	decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
	366	decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
	367	decode_counters, decode_allregs): Likewise.
	368
42d5f9c6 MS	369	2011-02-09 Michael Snyder <msnyder@vmware.com>
42d5f9c6 MS	370
56300268	371	* i386-dis.c (OP_J): Parenthesize expression to prevent
42d5f9c6 MS	372	truncated addresses.
	373	(print_insn): Fix indentation off-by-one.
	374
4be0c941 NC	375	2011-02-01 Nick Clifton <nickc@redhat.com>
	376
	377	* po/da.po: Updated Danish translation.
	378
6b069ee7 AM	379	2011-01-21 Dave Murphy <davem@devkitpro.org>
	380
	381	* ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
	382
e3949f17 L	383	2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
	384
	385	* i386-dis.c (sIbT): New.
	386	(b_T_mode): Likewise.
	387	(dis386): Replace sIb with sIbT on "pushT".
	388	(x86_64_table): Replace sIb with Ib on "aam" and "aad".
	389	(OP_sI): Handle b_T_mode. Properly sign-extend byte.
	390
752573b2 JK	391	2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
	392
	393	* i386-init.h: Regenerated.
	394	* i386-tbl.h: Regenerated
	395
2a2a0f38 QN	396	2011-01-17 Quentin Neill <quentin.neill@amd.com>
	397
	398	* i386-dis.c (REG_XOP_TBM_01): New.
	399	(REG_XOP_TBM_02): New.
	400	(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
	401	(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
	402	entries, and add bextr instruction.
	403
	404	* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
	405	(cpu_flags): Add CpuTBM.
	406
	407	* i386-opc.h (CpuTBM) New.
	408	(i386_cpu_flags): Add bit cputbm.
	409
	410	* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
	411	blcs, blsfill, blsic, t1mskc, and tzmsk.
	412
90d6ff62 DD	413	2011-01-12 DJ Delorie <dj@redhat.com>
	414
	415	* rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
	416
c95354ed MX	417	2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
	418
	419	* mips-dis.c (print_insn_args): Adjust the value to print the real
	420	offset for "+c" argument.
	421
f7465604 NC	422	2011-01-10 Nick Clifton <nickc@redhat.com>
	423
	424	* po/da.po: Updated Danish translation.
	425
639e30d2 NS	426	2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
	427
	428	* arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
	429
f12dc422 L	430	2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
	431
	432	* i386-dis.c (REG_VEX_38F3): New.
	433	(PREFIX_0FBC): Likewise.
	434	(PREFIX_VEX_38F2): Likewise.
	435	(PREFIX_VEX_38F3_REG_1): Likewise.
	436	(PREFIX_VEX_38F3_REG_2): Likewise.
	437	(PREFIX_VEX_38F3_REG_3): Likewise.
	438	(PREFIX_VEX_38F7): Likewise.
	439	(VEX_LEN_38F2_P_0): Likewise.
	440	(VEX_LEN_38F3_R_1_P_0): Likewise.
	441	(VEX_LEN_38F3_R_2_P_0): Likewise.
	442	(VEX_LEN_38F3_R_3_P_0): Likewise.
	443	(VEX_LEN_38F7_P_0): Likewise.
	444	(dis386_twobyte): Use PREFIX_0FBC.
	445	(reg_table): Add REG_VEX_38F3.
	446	(prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
	447	PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
	448	PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
	449	(vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
	450	PREFIX_VEX_38F7.
	451	(vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
	452	VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
	453	VEX_LEN_38F7_P_0.
	454
	455	* i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
	456	(cpu_flags): Add CpuBMI.
	457
	458	* i386-opc.h (CpuBMI): New.
	459	(i386_cpu_flags): Add cpubmi.
	460
	461	* i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
	462	* i386-init.h: Regenerated.
	463	* i386-tbl.h: Likewise.
	464
cb21baef L	465	2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
	466
	467	* i386-dis.c (VexGdq): New.
	468	(OP_VEX): Handle dq_mode.
	469
0db46eb4 L	470	2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
	471
	472	* i386-gen.c (process_copyright): Update copyright to 2011.
	473
9e9e0820	474	For older changes see ChangeLog-2010
252b5132 RH	475	\f
252b5132 RH	476	Local Variables:
2f6d2f85 NC	477	mode: change-log
	478	left-margin: 8
	479	fill-column: 74
252b5132 RH	480	version-control: never
252b5132 RH	481	End: