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x86: introduce operand type "instance"
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
75e5731b
JB		 12019-11-12 Jan Beulich <jbeulich@suse.com>
2
3 * i386-gen.c (operand_type_init): Adjust
4 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
5 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
6 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
7 (operand_instances): New.
8 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
9 (output_operand_type): New parameter "instance". Process it.
10 (process_i386_operand_type): New local variable "instance".
11 (main): Adjust static assertions.
12 * i386-opc.h (INSTANCE_WIDTH): Define.
13 (enum operand_instance): New.
14 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
15 (union i386_operand_type): Replace acc, inoutportreg, and
16 shiftcount by instance.
17 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
18 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
19 Add Instance=.
20 * i386-init.h, i386-tbl.h: Re-generate.
21
91802f3c
JB		 222019-11-11 Jan Beulich <jbeulich@suse.com>
23
24 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
25 smaxp/sminp entries' "tied_operand" field to 2.
26
4f5fc85d
JB		 272019-11-11 Jan Beulich <jbeulich@suse.com>
28
29 * aarch64-opc.c (operand_general_constraint_met_p): Replace
30 "index" local variable by that of the already existing "num".
31
dc2be329
L		 322019-11-08 H.J. Lu <hongjiu.lu@intel.com>
33
34 PR gas/25167
35 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
36 * i386-tbl.h: Regenerated.
37
f74a6307
JB		 382019-11-08 Jan Beulich <jbeulich@suse.com>
39
40 * i386-gen.c (operand_type_init): Add Class= to
41 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
42 OPERAND_TYPE_REGBND entry.
43 (operand_classes): Add RegMask and RegBND entries.
44 (operand_types): Drop RegMask and RegBND entry.
45 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
46 (RegMask, RegBND): Delete.
47 (union i386_operand_type): Remove regmask and regbnd fields.
48 * i386-opc.tbl (RegMask, RegBND): Define.
49 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
50 Class=RegBND.
51 * i386-init.h, i386-tbl.h: Re-generate.
52
3528c362
JB		 532019-11-08 Jan Beulich <jbeulich@suse.com>
54
55 * i386-gen.c (operand_type_init): Add Class= to
56 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
57 OPERAND_TYPE_REGZMM entries.
58 (operand_classes): Add RegMMX and RegSIMD entries.
59 (operand_types): Drop RegMMX and RegSIMD entries.
60 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
61 (RegMMX, RegSIMD): Delete.
62 (union i386_operand_type): Remove regmmx and regsimd fields.
63 * i386-opc.tbl (RegMMX): Define.
64 (RegXMM, RegYMM, RegZMM): Add Class=.
65 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
66 Class=RegSIMD.
67 * i386-init.h, i386-tbl.h: Re-generate.
68
4a5c67ed
JB		 692019-11-08 Jan Beulich <jbeulich@suse.com>
70
71 * i386-gen.c (operand_type_init): Add Class= to
72 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
73 entries.
74 (operand_classes): Add RegCR, RegDR, and RegTR entries.
75 (operand_types): Drop Control, Debug, and Test entries.
76 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
77 (Control, Debug, Test): Delete.
78 (union i386_operand_type): Remove control, debug, and test
79 fields.
80 * i386-opc.tbl (Control, Debug, Test): Define.
81 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
82 Class=RegDR, and Test by Class=RegTR.
83 * i386-init.h, i386-tbl.h: Re-generate.
84
00cee14f
JB		 852019-11-08 Jan Beulich <jbeulich@suse.com>
86
87 * i386-gen.c (operand_type_init): Add Class= to
88 OPERAND_TYPE_SREG entry.
89 (operand_classes): Add SReg entry.
90 (operand_types): Drop SReg entry.
91 * i386-opc.h (enum operand_class): Add SReg.
92 (SReg): Delete.
93 (union i386_operand_type): Remove sreg field.
94 * i386-opc.tbl (SReg): Define.
95 * i386-reg.tbl: Replace SReg by Class=SReg.
96 * i386-init.h, i386-tbl.h: Re-generate.
97
bab6aec1
JB		 982019-11-08 Jan Beulich <jbeulich@suse.com>
99
100 * i386-gen.c (operand_type_init): Add Class=. New
101 OPERAND_TYPE_ANYIMM entry.
102 (operand_classes): New.
103 (operand_types): Drop Reg entry.
104 (output_operand_type): New parameter "class". Process it.
105 (process_i386_operand_type): New local variable "class".
106 (main): Adjust static assertions.
107 * i386-opc.h (CLASS_WIDTH): Define.
108 (enum operand_class): New.
109 (Reg): Replace by Class. Adjust comment.
110 (union i386_operand_type): Replace reg by class.
111 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
112 Class=.
113 * i386-reg.tbl: Replace Reg by Class=Reg.
114 * i386-init.h: Re-generate.
115
1f4cd317
MM		 1162019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
117
118 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
119 (aarch64_opcode_table): Add data gathering hint mnemonic.
120 * opcodes/aarch64-dis-2.c: Account for new instruction.
121
616ce08e
MM		 1222019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
123
124 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
125
126
8382113f
MM		 1272019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
128
129 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
130 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
131 aarch64_feature_f64mm): New feature sets.
132 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
133 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
134 instructions.
135 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
136 macros.
137 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
138 (OP_SVE_QQQ): New qualifier.
139 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
140 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
141 the movprfx constraint.
142 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
143 (aarch64_opcode_table): Define new instructions smmla,
144 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
145 uzip{1/2}, trn{1/2}.
146 * aarch64-opc.c (operand_general_constraint_met_p): Handle
147 AARCH64_OPND_SVE_ADDR_RI_S4x32.
148 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
149 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
150 Account for new instructions.
151 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
152 S4x32 operand.
153 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
154
aab2c27d
MM		 1552019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
1562019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
157
158 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
159 Armv8.6-A.
160 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
161 (neon_opcodes): Add bfloat SIMD instructions.
162 (print_insn_coprocessor): Add new control character %b to print
163 condition code without checking cp_num.
164 (print_insn_neon): Account for BFloat16 instructions that have no
165 special top-byte handling.
166
33593eaf
MM		 1672019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
1682019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
169
170 * arm-dis.c (print_insn_coprocessor,
171 print_insn_generic_coprocessor): Create wrapper functions around
172 the implementation of the print_insn_coprocessor control codes.
173 (print_insn_coprocessor_1): Original print_insn_coprocessor
174 function that now takes which array to look at as an argument.
175 (print_insn_arm): Use both print_insn_coprocessor and
176 print_insn_generic_coprocessor.
177 (print_insn_thumb32): As above.
178
df678013
MM		 1792019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
1802019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
181
182 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
183 in reglane special case.
184 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
185 aarch64_find_next_opcode): Account for new instructions.
186 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
187 in reglane special case.
188 * aarch64-opc.c (struct operand_qualifier_data): Add data for
189 new AARCH64_OPND_QLF_S_2H qualifier.
190 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
191 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
192 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
193 sets.
194 (BFLOAT_SVE, BFLOAT): New feature set macros.
195 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
196 instructions.
197 (aarch64_opcode_table): Define new instructions bfdot,
198 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
199 bfcvtn2, bfcvt.
200
8ae2d3d9
MM		 2012019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2022019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
203
204 * aarch64-tbl.h (ARMV8_6): New macro.
205
142861df
JB		 2062019-11-07 Jan Beulich <jbeulich@suse.com>
207
208 * i386-dis.c (prefix_table): Add mcommit.
209 (rm_table): Add rdpru.
210 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
211 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
212 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
213 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
214 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
215 * i386-opc.tbl (mcommit, rdpru): New.
216 * i386-init.h, i386-tbl.h: Re-generate.
217
081e283f
JB		 2182019-11-07 Jan Beulich <jbeulich@suse.com>
219
220 * i386-dis.c (OP_Mwait): Drop local variable "names", use
221 "names32" instead.
222 (OP_Monitor): Drop local variable "op1_names", re-purpose
223 "names" for it instead, and replace former "names" uses by
224 "names32" ones.
225
c050c89a
JB		 2262019-11-07 Jan Beulich <jbeulich@suse.com>
227
228 PR/gas 25167
229 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
230 operand-less forms.
231 * opcodes/i386-tbl.h: Re-generate.
232
7abb8d81
JB		 2332019-11-05 Jan Beulich <jbeulich@suse.com>
234
235 * i386-dis.c (OP_Mwaitx): Delete.
236 (prefix_table): Use OP_Mwait for mwaitx entry.
237 (OP_Mwait): Also handle mwaitx.
238
267b8516
JB		 2392019-11-05 Jan Beulich <jbeulich@suse.com>
240
241 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
242 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
243 (prefix_table): Add respective entries.
244 (rm_table): Link to those entries.
245
f8687e93
JB		 2462019-11-05 Jan Beulich <jbeulich@suse.com>
247
248 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
249 (REG_0F1C_P_0_MOD_0): ... this.
250 (REG_0F1E_MOD_3): Rename to ...
251 (REG_0F1E_P_1_MOD_3): ... this.
252 (RM_0F01_REG_5): Rename to ...
253 (RM_0F01_REG_5_MOD_3): ... this.
254 (RM_0F01_REG_7): Rename to ...
255 (RM_0F01_REG_7_MOD_3): ... this.
256 (RM_0F1E_MOD_3_REG_7): Rename to ...
257 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
258 (RM_0FAE_REG_6): Rename to ...
259 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
260 (RM_0FAE_REG_7): Rename to ...
261 (RM_0FAE_REG_7_MOD_3): ... this.
262 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
263 (PREFIX_0F01_REG_5_MOD_0): ... this.
264 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
265 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
266 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
267 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
268 (PREFIX_0FAE_REG_0): Rename to ...
269 (PREFIX_0FAE_REG_0_MOD_3): ... this.
270 (PREFIX_0FAE_REG_1): Rename to ...
271 (PREFIX_0FAE_REG_1_MOD_3): ... this.
272 (PREFIX_0FAE_REG_2): Rename to ...
273 (PREFIX_0FAE_REG_2_MOD_3): ... this.
274 (PREFIX_0FAE_REG_3): Rename to ...
275 (PREFIX_0FAE_REG_3_MOD_3): ... this.
276 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
277 (PREFIX_0FAE_REG_4_MOD_0): ... this.
278 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
279 (PREFIX_0FAE_REG_4_MOD_3): ... this.
280 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
281 (PREFIX_0FAE_REG_5_MOD_0): ... this.
282 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
283 (PREFIX_0FAE_REG_5_MOD_3): ... this.
284 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
285 (PREFIX_0FAE_REG_6_MOD_0): ... this.
286 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
287 (PREFIX_0FAE_REG_6_MOD_3): ... this.
288 (PREFIX_0FAE_REG_7): Rename to ...
289 (PREFIX_0FAE_REG_7_MOD_0): ... this.
290 (PREFIX_MOD_0_0FC3): Rename to ...
291 (PREFIX_0FC3_MOD_0): ... this.
292 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
293 (PREFIX_0FC7_REG_6_MOD_0): ... this.
294 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
295 (PREFIX_0FC7_REG_6_MOD_3): ... this.
296 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
297 (PREFIX_0FC7_REG_7_MOD_3): ... this.
298 (reg_table, prefix_table, mod_table, rm_table): Adjust
299 accordingly.
300
5103274f
NC		 3012019-11-04 Nick Clifton <nickc@redhat.com>
302
303 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
304 of a v850 system register. Move the v850_sreg_names array into
305 this function.
306 (get_v850_reg_name): Likewise for ordinary register names.
307 (get_v850_vreg_name): Likewise for vector register names.
308 (get_v850_cc_name): Likewise for condition codes.
309 * get_v850_float_cc_name): Likewise for floating point condition
310 codes.
311 (get_v850_cacheop_name): Likewise for cache-ops.
312 (get_v850_prefop_name): Likewise for pref-ops.
313 (disassemble): Use the new accessor functions.
314
1820262b
DB		 3152019-10-30 Delia Burduv <delia.burduv@arm.com>
316
317 * aarch64-opc.c (print_immediate_offset_address): Don't print the
318 immediate for the writeback form of ldraa/ldrab if it is 0.
319 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
320 * aarch64-opc-2.c: Regenerated.
321
3cc17af5
JB		 3222019-10-30 Jan Beulich <jbeulich@suse.com>
323
324 * i386-gen.c (operand_type_shorthands): Delete.
325 (operand_type_init): Expand previous shorthands.
326 (set_bitfield_from_shorthand): Rename back to ...
327 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
328 of operand_type_init[].
329 (set_bitfield): Adjust call to the above function.
330 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
331 RegXMM, RegYMM, RegZMM): Define.
332 * i386-reg.tbl: Expand prior shorthands.
333
a2cebd03
JB		 3342019-10-30 Jan Beulich <jbeulich@suse.com>
335
336 * i386-gen.c (output_i386_opcode): Change order of fields
337 emitted to output.
338 * i386-opc.h (struct insn_template): Move operands field.
339 Convert extension_opcode field to unsigned short.
340 * i386-tbl.h: Re-generate.
341
507916b8
JB		 3422019-10-30 Jan Beulich <jbeulich@suse.com>
343
344 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
345 of W.
346 * i386-opc.h (W): Extend comment.
347 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
348 general purpose variants not allowing for byte operands.
349 * i386-tbl.h: Re-generate.
350
efea62b4
NC		 3512019-10-29 Nick Clifton <nickc@redhat.com>
352
353 * tic30-dis.c (print_branch): Correct size of operand array.
354
9adb2591
NC		 3552019-10-29 Nick Clifton <nickc@redhat.com>
356
357 * d30v-dis.c (print_insn): Check that operand index is valid
358 before attempting to access the operands array.
359
993a00a9
NC		 3602019-10-29 Nick Clifton <nickc@redhat.com>
361
362 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
363 locating the bit to be tested.
364
66a66a17
NC		 3652019-10-29 Nick Clifton <nickc@redhat.com>
366
367 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
368 values.
369 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
370 (print_insn_s12z): Check for illegal size values.
371
1ee3542c
NC		 3722019-10-28 Nick Clifton <nickc@redhat.com>
373
374 * csky-dis.c (csky_chars_to_number): Check for a negative
375 count. Use an unsigned integer to construct the return value.
376
bbf9a0b5
NC		 3772019-10-28 Nick Clifton <nickc@redhat.com>
378
379 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
380 operand buffer. Set value to 15 not 13.
381 (get_register_operand): Use OPERAND_BUFFER_LEN.
382 (get_indirect_operand): Likewise.
383 (print_two_operand): Likewise.
384 (print_three_operand): Likewise.
385 (print_oar_insn): Likewise.
386
d1e304bc
NC		 3872019-10-28 Nick Clifton <nickc@redhat.com>
388
389 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
390 (bit_extract_simple): Likewise.
391 (bit_copy): Likewise.
392 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
393 index_offset array are not accessed.
394
dee33451
NC		 3952019-10-28 Nick Clifton <nickc@redhat.com>
396
397 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
398 operand.
399
27cee81d
NC		 4002019-10-25 Nick Clifton <nickc@redhat.com>
401
402 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
403 access to opcodes.op array element.
404
de6d8dc2
NC		 4052019-10-23 Nick Clifton <nickc@redhat.com>
406
407 * rx-dis.c (get_register_name): Fix spelling typo in error
408 message.
409 (get_condition_name, get_flag_name, get_double_register_name)
410 (get_double_register_high_name, get_double_register_low_name)
411 (get_double_control_register_name, get_double_condition_name)
412 (get_opsize_name, get_size_name): Likewise.
413
6207ed28
NC		 4142019-10-22 Nick Clifton <nickc@redhat.com>
415
416 * rx-dis.c (get_size_name): New function. Provides safe
417 access to name array.
418 (get_opsize_name): Likewise.
419 (print_insn_rx): Use the accessor functions.
420
12234dfd
NC		 4212019-10-16 Nick Clifton <nickc@redhat.com>
422
423 * rx-dis.c (get_register_name): New function. Provides safe
424 access to name array.
425 (get_condition_name, get_flag_name, get_double_register_name)
426 (get_double_register_high_name, get_double_register_low_name)
427 (get_double_control_register_name, get_double_condition_name):
428 Likewise.
429 (print_insn_rx): Use the accessor functions.
430
1d378749
NC		 4312019-10-09 Nick Clifton <nickc@redhat.com>
432
433 PR 25041
434 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
435 instructions.
436
d241b910
JB		 4372019-10-07 Jan Beulich <jbeulich@suse.com>
438
439 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
440 (cmpsd): Likewise. Move EsSeg to other operand.
441 * opcodes/i386-tbl.h: Re-generate.
442
f5c5b7c1
AM		 4432019-09-23 Alan Modra <amodra@gmail.com>
444
445 * m68k-dis.c: Include cpu-m68k.h
446
7beeaeb8
AM		 4472019-09-23 Alan Modra <amodra@gmail.com>
448
449 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
450 "elf/mips.h" earlier.
451
3f9aad11
JB		 4522018-09-20 Jan Beulich <jbeulich@suse.com>
453
454 PR gas/25012
455 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
456 with SReg operand.
457 * i386-tbl.h: Re-generate.
458
fd361982
AM		 4592019-09-18 Alan Modra <amodra@gmail.com>
460
461 * arc-ext.c: Update throughout for bfd section macro changes.
462
e0b2a78c
SM		 4632019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
464
465 * Makefile.in: Re-generate.
466 * configure: Re-generate.
467
7e9ad3a3
JW		 4682019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
469
470 * riscv-opc.c (riscv_opcodes): Change subset field
471 to insn_class field for all instructions.
472 (riscv_insn_types): Likewise.
473
bb695960
PB		 4742019-09-16 Phil Blundell <pb@pbcl.net>
475
476 * configure: Regenerated.
477
8063ab7e
MV		 4782019-09-10 Miod Vallat <miod@online.fr>
479
480 PR 24982
481 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
482
60391a25
PB		 4832019-09-09 Phil Blundell <pb@pbcl.net>
484
485 binutils 2.33 branch created.
486
f44b758d
NC		 4872019-09-03 Nick Clifton <nickc@redhat.com>
488
489 PR 24961
490 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
491 greater than zero before indexing via (bufcnt -1).
492
1e4b5e7d
NC		 4932019-09-03 Nick Clifton <nickc@redhat.com>
494
495 PR 24958
496 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
497 (MAX_SPEC_REG_NAME_LEN): Define.
498 (struct mmix_dis_info): Use defined constants for array lengths.
499 (get_reg_name): New function.
500 (get_sprec_reg_name): New function.
501 (print_insn_mmix): Use new functions.
502
c4a23bf8
SP		 5032019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
504
505 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
506 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
507 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
508
a051e2f3
KT		 5092019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
510
511 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
512 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
513 (aarch64_sys_reg_supported_p): Update checks for the above.
514
08132bdd
SP		 5152019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
516
517 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
518 cases MVE_SQRSHRL and MVE_UQRSHLL.
519 (print_insn_mve): Add case for specifier 'k' to check
520 specific bit of the instruction.
521
d88bdcb4
PA		 5222019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
523
524 PR 24854
525 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
526 encountering an unknown machine type.
527 (print_insn_arc): Handle arc_insn_length returning 0. In error
528 cases return -1 rather than calling abort.
529
bc750500
JB		 5302019-08-07 Jan Beulich <jbeulich@suse.com>
531
532 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
533 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
534 IgnoreSize.
535 * i386-tbl.h: Re-generate.
536
23d188c7
BW		 5372019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
538
539 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
540 instructions.
541
c0d6f62f
JW		 5422019-07-30 Mel Chen <mel.chen@sifive.com>
543
544 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
545 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
546
547 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
548 fscsr.
549
0f3f7167
CZ		 5502019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
551
552 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
553 and MPY class instructions.
554 (parse_option): Add nps400 option.
555 (print_arc_disassembler_options): Add nps400 info.
556
7e126ba3
CZ		 5572019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
558
559 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
560 (bspop): Likewise.
561 (modapp): Likewise.
562 * arc-opc.c (RAD_CHK): Add.
563 * arc-tbl.h: Regenerate.
564
a028026d
KT		 5652019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
566
567 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
568 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
569
ac79ff9e
NC		 5702019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
571
572 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
573 instructions as UNPREDICTABLE.
574
231097b0
JM		 5752019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
576
577 * bpf-desc.c: Regenerated.
578
1d942ae9
JB		 5792019-07-17 Jan Beulich <jbeulich@suse.com>
580
581 * i386-gen.c (static_assert): Define.
582 (main): Use it.
583 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
584 (Opcode_Modifier_Num): ... this.
585 (Mem): Delete.
586
dfd69174
JB		 5872019-07-16 Jan Beulich <jbeulich@suse.com>
588
589 * i386-gen.c (operand_types): Move RegMem ...
590 (opcode_modifiers): ... here.
591 * i386-opc.h (RegMem): Move to opcode modifer enum.
592 (union i386_operand_type): Move regmem field ...
593 (struct i386_opcode_modifier): ... here.
594 * i386-opc.tbl (RegMem): Define.
595 (mov, movq): Move RegMem on segment, control, debug, and test
596 register flavors.
597 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
598 to non-SSE2AVX flavor.
599 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
600 Move RegMem on register only flavors. Drop IgnoreSize from
601 legacy encoding flavors.
602 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
603 flavors.
604 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
605 register only flavors.
606 (vmovd): Move RegMem and drop IgnoreSize on register only
607 flavor. Change opcode and operand order to store form.
608 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
609
21df382b
JB		 6102019-07-16 Jan Beulich <jbeulich@suse.com>
611
612 * i386-gen.c (operand_type_init, operand_types): Replace SReg
613 entries.
614 * i386-opc.h (SReg2, SReg3): Replace by ...
615 (SReg): ... this.
616 (union i386_operand_type): Replace sreg fields.
617 * i386-opc.tbl (mov, ): Use SReg.
618 (push, pop): Likewies. Drop i386 and x86-64 specific segment
619 register flavors.
620 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
621 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
622
3719fd55
JM		 6232019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
624
625 * bpf-desc.c: Regenerate.
626 * bpf-opc.c: Likewise.
627 * bpf-opc.h: Likewise.
628
92434a14
JM		 6292019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
630
631 * bpf-desc.c: Regenerate.
632 * bpf-opc.c: Likewise.
633
43dd7626
HPN		 6342019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
635
636 * arm-dis.c (print_insn_coprocessor): Rename index to
637 index_operand.
638
98602811
JW		 6392019-07-05 Kito Cheng <kito.cheng@sifive.com>
640
641 * riscv-opc.c (riscv_insn_types): Add r4 type.
642
643 * riscv-opc.c (riscv_insn_types): Add b and j type.
644
645 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
646 format for sb type and correct s type.
647
01c1ee4a
RS		 6482019-07-02 Richard Sandiford <richard.sandiford@arm.com>
649
650 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
651 SVE FMOV alias of FCPY.
652
83adff69
RS		 6532019-07-02 Richard Sandiford <richard.sandiford@arm.com>
654
655 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
656 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
657
89418844
RS		 6582019-07-02 Richard Sandiford <richard.sandiford@arm.com>
659
660 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
661 registers in an instruction prefixed by MOVPRFX.
662
41be57ca
MM		 6632019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
664
665 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
666 sve_size_13 icode to account for variant behaviour of
667 pmull{t,b}.
668 * aarch64-dis-2.c: Regenerate.
669 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
670 sve_size_13 icode to account for variant behaviour of
671 pmull{t,b}.
672 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
673 (OP_SVE_VVV_Q_D): Add new qualifier.
674 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
675 (struct aarch64_opcode): Split pmull{t,b} into those requiring
676 AES and those not.
677
9d3bf266
JB		 6782019-07-01 Jan Beulich <jbeulich@suse.com>
679
680 * opcodes/i386-gen.c (operand_type_init): Remove
681 OPERAND_TYPE_VEC_IMM4 entry.
682 (operand_types): Remove Vec_Imm4.
683 * opcodes/i386-opc.h (Vec_Imm4): Delete.
684 (union i386_operand_type): Remove vec_imm4.
685 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
686 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
687
c3949f43
JB		 6882019-07-01 Jan Beulich <jbeulich@suse.com>
689
690 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
691 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
692 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
693 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
694 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
695 monitorx, mwaitx): Drop ImmExt from operand-less forms.
696 * i386-tbl.h: Re-generate.
697
5641ec01
JB		 6982019-07-01 Jan Beulich <jbeulich@suse.com>
699
700 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
701 register operands.
702 * i386-tbl.h: Re-generate.
703
79dec6b7
JB		 7042019-07-01 Jan Beulich <jbeulich@suse.com>
705
706 * i386-opc.tbl (C): New.
707 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
708 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
709 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
710 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
711 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
712 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
713 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
714 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
715 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
716 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
717 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
718 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
719 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
720 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
721 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
722 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
723 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
724 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
725 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
726 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
727 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
728 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
729 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
730 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
731 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
732 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
733 flavors.
734 * i386-tbl.h: Re-generate.
735
a0a1771e
JB		 7362019-07-01 Jan Beulich <jbeulich@suse.com>
737
738 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
739 register operands.
740 * i386-tbl.h: Re-generate.
741
cd546e7b
JB		 7422019-07-01 Jan Beulich <jbeulich@suse.com>
743
744 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
745 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
746 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
747 * i386-tbl.h: Re-generate.
748
e3bba3fc
JB		 7492019-07-01 Jan Beulich <jbeulich@suse.com>
750
751 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
752 Disp8MemShift from register only templates.
753 * i386-tbl.h: Re-generate.
754
36cc073e
JB		 7552019-07-01 Jan Beulich <jbeulich@suse.com>
756
757 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
758 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
759 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
760 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
761 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
762 EVEX_W_0F11_P_3_M_1): Delete.
763 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
764 EVEX_W_0F11_P_3): New.
765 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
766 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
767 MOD_EVEX_0F11_PREFIX_3 table entries.
768 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
769 PREFIX_EVEX_0F11 table entries.
770 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
771 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
772 EVEX_W_0F11_P_3_M_{0,1} table entries.
773
219920a7
JB		 7742019-07-01 Jan Beulich <jbeulich@suse.com>
775
776 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
777 Delete.
778
e395f487
L		 7792019-06-27 H.J. Lu <hongjiu.lu@intel.com>
780
781 PR binutils/24719
782 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
783 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
784 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
785 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
786 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
787 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
788 EVEX_LEN_0F38C7_R_6_P_2_W_1.
789 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
790 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
791 PREFIX_EVEX_0F38C6_REG_6 entries.
792 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
793 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
794 EVEX_W_0F38C7_R_6_P_2 entries.
795 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
796 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
797 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
798 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
799 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
800 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
801 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
802
2b7bcc87
JB		 8032019-06-27 Jan Beulich <jbeulich@suse.com>
804
805 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
806 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
807 VEX_LEN_0F2D_P_3): Delete.
808 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
809 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
810 (prefix_table): ... here.
811
c1dc7af5
JB		 8122019-06-27 Jan Beulich <jbeulich@suse.com>
813
814 * i386-dis.c (Iq): Delete.
815 (Id): New.
816 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
817 TBM insns.
818 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
819 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
820 (OP_E_memory): Also honor needindex when deciding whether an
821 address size prefix needs printing.
822 (OP_I): Remove handling of q_mode. Add handling of d_mode.
823
d7560e2d
JW		 8242019-06-26 Jim Wilson <jimw@sifive.com>
825
826 PR binutils/24739
827 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
828 Set info->display_endian to info->endian_code.
829
2c703856
JB		 8302019-06-25 Jan Beulich <jbeulich@suse.com>
831
832 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
833 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
834 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
835 OPERAND_TYPE_ACC64 entries.
836 * i386-init.h: Re-generate.
837
54fbadc0
JB		 8382019-06-25 Jan Beulich <jbeulich@suse.com>
839
840 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
841 Delete.
842 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
843 of dqa_mode.
844 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
845 entries here.
846 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
847 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
848
a280ab8e
JB		 8492019-06-25 Jan Beulich <jbeulich@suse.com>
850
851 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
852 variables.
853
e1a1babd
JB		 8542019-06-25 Jan Beulich <jbeulich@suse.com>
855
856 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
857 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
858 movnti.
d7560e2d 859 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 860 * i386-tbl.h: Re-generate.
861
b8364fa7
JB		 8622019-06-25 Jan Beulich <jbeulich@suse.com>
863
864 * i386-opc.tbl (and): Mark Imm8S form for optimization.
865 * i386-tbl.h: Re-generate.
866
ad692897
L		 8672019-06-21 H.J. Lu <hongjiu.lu@intel.com>
868
869 * i386-dis-evex.h: Break into ...
870 * i386-dis-evex-len.h: New file.
871 * i386-dis-evex-mod.h: Likewise.
872 * i386-dis-evex-prefix.h: Likewise.
873 * i386-dis-evex-reg.h: Likewise.
874 * i386-dis-evex-w.h: Likewise.
875 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
876 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
877 i386-dis-evex-mod.h.
878
f0a6222e
L		 8792019-06-19 H.J. Lu <hongjiu.lu@intel.com>
880
881 PR binutils/24700
882 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
883 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
884 EVEX_W_0F385B_P_2.
885 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
886 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
887 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
888 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
889 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
890 EVEX_LEN_0F385B_P_2_W_1.
891 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
892 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
893 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
894 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
895 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
896 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
897 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
898 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
899 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
900 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
901
6e1c90b7
L		 9022019-06-17 H.J. Lu <hongjiu.lu@intel.com>
903
904 PR binutils/24691
905 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
906 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
907 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
908 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
909 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
910 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
911 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
912 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
913 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
914 EVEX_LEN_0F3A43_P_2_W_1.
915 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
916 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
917 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
918 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
919 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
920 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
921 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
922 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
923 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
924 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
925 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
926 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
927
bcc5a6eb
NC		 9282019-06-14 Nick Clifton <nickc@redhat.com>
929
930 * po/fr.po; Updated French translation.
931
e4c4ac46
SH		 9322019-06-13 Stafford Horne <shorne@gmail.com>
933
934 * or1k-asm.c: Regenerated.
935 * or1k-desc.c: Regenerated.
936 * or1k-desc.h: Regenerated.
937 * or1k-dis.c: Regenerated.
938 * or1k-ibld.c: Regenerated.
939 * or1k-opc.c: Regenerated.
940 * or1k-opc.h: Regenerated.
941 * or1k-opinst.c: Regenerated.
942
a0e44ef5
PB		 9432019-06-12 Peter Bergner <bergner@linux.ibm.com>
944
945 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
946
12efd68d
L		 9472019-06-05 H.J. Lu <hongjiu.lu@intel.com>
948
949 PR binutils/24633
950 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
951 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
952 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
953 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
954 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
955 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
956 EVEX_LEN_0F3A1B_P_2_W_1.
957 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
958 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
959 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
960 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
961 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
962 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
963 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
964 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
965
63c6fc6c
L		 9662019-06-04 H.J. Lu <hongjiu.lu@intel.com>
967
968 PR binutils/24626
969 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
970 EVEX.vvvv when disassembling VEX and EVEX instructions.
971 (OP_VEX): Set vex.register_specifier to 0 after readding
972 vex.register_specifier.
973 (OP_Vex_2src_1): Likewise.
974 (OP_Vex_2src_2): Likewise.
975 (OP_LWP_E): Likewise.
976 (OP_EX_Vex): Don't check vex.register_specifier.
977 (OP_XMM_Vex): Likewise.
978
9186c494
L		 9792019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
980 Lili Cui <lili.cui@intel.com>
981
982 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
983 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
984 instructions.
985 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
986 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
987 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
988 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
989 (i386_cpu_flags): Add cpuavx512_vp2intersect.
990 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
991 * i386-init.h: Regenerated.
992 * i386-tbl.h: Likewise.
993
5d79adc4
L		 9942019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
995 Lili Cui <lili.cui@intel.com>
996
997 * doc/c-i386.texi: Document enqcmd.
998 * testsuite/gas/i386/enqcmd-intel.d: New file.
999 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1000 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1001 * testsuite/gas/i386/enqcmd.d: Likewise.
1002 * testsuite/gas/i386/enqcmd.s: Likewise.
1003 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1004 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1005 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1006 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1007 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1008 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1009 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1010 and x86-64-enqcmd.
1011
a9d96ab9
AH		 10122019-06-04 Alan Hayward <alan.hayward@arm.com>
1013
1014 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1015
4f6d070a
AM		 10162019-06-03 Alan Modra <amodra@gmail.com>
1017
1018 * ppc-dis.c (prefix_opcd_indices): Correct size.
1019
a2f4b66c
L		 10202019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1021
1022 PR gas/24625
1023 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1024 Disp8ShiftVL.
1025 * i386-tbl.h: Regenerated.
1026
405b5bd8
AM		 10272019-05-24 Alan Modra <amodra@gmail.com>
1028
1029 * po/POTFILES.in: Regenerate.
1030
8acf1435
PB		 10312019-05-24 Peter Bergner <bergner@linux.ibm.com>
1032 Alan Modra <amodra@gmail.com>
1033
1034 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1035 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1036 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1037 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1038 XTOP>): Define and add entries.
1039 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1040 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1041 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1042 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1043
dd7efa79
PB		 10442019-05-24 Peter Bergner <bergner@linux.ibm.com>
1045 Alan Modra <amodra@gmail.com>
1046
1047 * ppc-dis.c (ppc_opts): Add "future" entry.
1048 (PREFIX_OPCD_SEGS): Define.
1049 (prefix_opcd_indices): New array.
1050 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1051 (lookup_prefix): New function.
1052 (print_insn_powerpc): Handle 64-bit prefix instructions.
1053 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1054 (PMRR, POWERXX): Define.
1055 (prefix_opcodes): New instruction table.
1056 (prefix_num_opcodes): New constant.
1057
79472b45
JM		 10582019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1059
1060 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1061 * configure: Regenerated.
1062 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1063 and cpu/bpf.opc.
1064 (HFILES): Add bpf-desc.h and bpf-opc.h.
1065 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1066 bpf-ibld.c and bpf-opc.c.
1067 (BPF_DEPS): Define.
1068 * Makefile.in: Regenerated.
1069 * disassemble.c (ARCH_bpf): Define.
1070 (disassembler): Add case for bfd_arch_bpf.
1071 (disassemble_init_for_target): Likewise.
1072 (enum epbf_isa_attr): Define.
1073 * disassemble.h: extern print_insn_bpf.
1074 * bpf-asm.c: Generated.
1075 * bpf-opc.h: Likewise.
1076 * bpf-opc.c: Likewise.
1077 * bpf-ibld.c: Likewise.
1078 * bpf-dis.c: Likewise.
1079 * bpf-desc.h: Likewise.
1080 * bpf-desc.c: Likewise.
1081
ba6cd17f
SD		 10822019-05-21 Sudakshina Das <sudi.das@arm.com>
1083
1084 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1085 and VMSR with the new operands.
1086
e39c1607
SD		 10872019-05-21 Sudakshina Das <sudi.das@arm.com>
1088
1089 * arm-dis.c (enum mve_instructions): New enum
1090 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1091 and cneg.
1092 (mve_opcodes): New instructions as above.
1093 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1094 csneg and csel.
1095 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1096
23d00a41
SD		 10972019-05-21 Sudakshina Das <sudi.das@arm.com>
1098
1099 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1100 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1101 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1102 uqshl, urshrl and urshr.
1103 (is_mve_okay_in_it): Add new instructions to TRUE list.
1104 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1105 (print_insn_mve): Updated to accept new %j,
1106 %<bitfield>m and %<bitfield>n patterns.
1107
cd4797ee
FS		 11082019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1109
1110 * mips-opc.c (mips_builtin_opcodes): Change source register
1111 constraint for DAUI.
1112
999b073b
NC		 11132019-05-20 Nick Clifton <nickc@redhat.com>
1114
1115 * po/fr.po: Updated French translation.
1116
14b456f2
AV		 11172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1118 Michael Collison <michael.collison@arm.com>
1119
1120 * arm-dis.c (thumb32_opcodes): Add new instructions.
1121 (enum mve_instructions): Likewise.
1122 (enum mve_undefined): Add new reasons.
1123 (is_mve_encoding_conflict): Handle new instructions.
1124 (is_mve_undefined): Likewise.
1125 (is_mve_unpredictable): Likewise.
1126 (print_mve_undefined): Likewise.
1127 (print_mve_size): Likewise.
1128
f49bb598
AV		 11292019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1130 Michael Collison <michael.collison@arm.com>
1131
1132 * arm-dis.c (thumb32_opcodes): Add new instructions.
1133 (enum mve_instructions): Likewise.
1134 (is_mve_encoding_conflict): Handle new instructions.
1135 (is_mve_undefined): Likewise.
1136 (is_mve_unpredictable): Likewise.
1137 (print_mve_size): Likewise.
1138
56858bea
AV		 11392019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1140 Michael Collison <michael.collison@arm.com>
1141
1142 * arm-dis.c (thumb32_opcodes): Add new instructions.
1143 (enum mve_instructions): Likewise.
1144 (is_mve_encoding_conflict): Likewise.
1145 (is_mve_unpredictable): Likewise.
1146 (print_mve_size): Likewise.
1147
e523f101
AV		 11482019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1149 Michael Collison <michael.collison@arm.com>
1150
1151 * arm-dis.c (thumb32_opcodes): Add new instructions.
1152 (enum mve_instructions): Likewise.
1153 (is_mve_encoding_conflict): Handle new instructions.
1154 (is_mve_undefined): Likewise.
1155 (is_mve_unpredictable): Likewise.
1156 (print_mve_size): Likewise.
1157
66dcaa5d
AV		 11582019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1159 Michael Collison <michael.collison@arm.com>
1160
1161 * arm-dis.c (thumb32_opcodes): Add new instructions.
1162 (enum mve_instructions): Likewise.
1163 (is_mve_encoding_conflict): Handle new instructions.
1164 (is_mve_undefined): Likewise.
1165 (is_mve_unpredictable): Likewise.
1166 (print_mve_size): Likewise.
1167 (print_insn_mve): Likewise.
1168
d052b9b7
AV		 11692019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1170 Michael Collison <michael.collison@arm.com>
1171
1172 * arm-dis.c (thumb32_opcodes): Add new instructions.
1173 (print_insn_thumb32): Handle new instructions.
1174
ed63aa17
AV		 11752019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1176 Michael Collison <michael.collison@arm.com>
1177
1178 * arm-dis.c (enum mve_instructions): Add new instructions.
1179 (enum mve_undefined): Add new reasons.
1180 (is_mve_encoding_conflict): Handle new instructions.
1181 (is_mve_undefined): Likewise.
1182 (is_mve_unpredictable): Likewise.
1183 (print_mve_undefined): Likewise.
1184 (print_mve_size): Likewise.
1185 (print_mve_shift_n): Likewise.
1186 (print_insn_mve): Likewise.
1187
897b9bbc
AV		 11882019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1189 Michael Collison <michael.collison@arm.com>
1190
1191 * arm-dis.c (enum mve_instructions): Add new instructions.
1192 (is_mve_encoding_conflict): Handle new instructions.
1193 (is_mve_unpredictable): Likewise.
1194 (print_mve_rotate): Likewise.
1195 (print_mve_size): Likewise.
1196 (print_insn_mve): Likewise.
1197
1c8f2df8
AV		 11982019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1199 Michael Collison <michael.collison@arm.com>
1200
1201 * arm-dis.c (enum mve_instructions): Add new instructions.
1202 (is_mve_encoding_conflict): Handle new instructions.
1203 (is_mve_unpredictable): Likewise.
1204 (print_mve_size): Likewise.
1205 (print_insn_mve): Likewise.
1206
d3b63143
AV		 12072019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1208 Michael Collison <michael.collison@arm.com>
1209
1210 * arm-dis.c (enum mve_instructions): Add new instructions.
1211 (enum mve_undefined): Add new reasons.
1212 (is_mve_encoding_conflict): Handle new instructions.
1213 (is_mve_undefined): Likewise.
1214 (is_mve_unpredictable): Likewise.
1215 (print_mve_undefined): Likewise.
1216 (print_mve_size): Likewise.
1217 (print_insn_mve): Likewise.
1218
14925797
AV		 12192019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1220 Michael Collison <michael.collison@arm.com>
1221
1222 * arm-dis.c (enum mve_instructions): Add new instructions.
1223 (is_mve_encoding_conflict): Handle new instructions.
1224 (is_mve_undefined): Likewise.
1225 (is_mve_unpredictable): Likewise.
1226 (print_mve_size): Likewise.
1227 (print_insn_mve): Likewise.
1228
c507f10b
AV		 12292019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1230 Michael Collison <michael.collison@arm.com>
1231
1232 * arm-dis.c (enum mve_instructions): Add new instructions.
1233 (enum mve_unpredictable): Add new reasons.
1234 (enum mve_undefined): Likewise.
1235 (is_mve_okay_in_it): Handle new isntructions.
1236 (is_mve_encoding_conflict): Likewise.
1237 (is_mve_undefined): Likewise.
1238 (is_mve_unpredictable): Likewise.
1239 (print_mve_vmov_index): Likewise.
1240 (print_simd_imm8): Likewise.
1241 (print_mve_undefined): Likewise.
1242 (print_mve_unpredictable): Likewise.
1243 (print_mve_size): Likewise.
1244 (print_insn_mve): Likewise.
1245
bf0b396d
AV		 12462019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1247 Michael Collison <michael.collison@arm.com>
1248
1249 * arm-dis.c (enum mve_instructions): Add new instructions.
1250 (enum mve_unpredictable): Add new reasons.
1251 (enum mve_undefined): Likewise.
1252 (is_mve_encoding_conflict): Handle new instructions.
1253 (is_mve_undefined): Likewise.
1254 (is_mve_unpredictable): Likewise.
1255 (print_mve_undefined): Likewise.
1256 (print_mve_unpredictable): Likewise.
1257 (print_mve_rounding_mode): Likewise.
1258 (print_mve_vcvt_size): Likewise.
1259 (print_mve_size): Likewise.
1260 (print_insn_mve): Likewise.
1261
ef1576a1
AV		 12622019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1263 Michael Collison <michael.collison@arm.com>
1264
1265 * arm-dis.c (enum mve_instructions): Add new instructions.
1266 (enum mve_unpredictable): Add new reasons.
1267 (enum mve_undefined): Likewise.
1268 (is_mve_undefined): Handle new instructions.
1269 (is_mve_unpredictable): Likewise.
1270 (print_mve_undefined): Likewise.
1271 (print_mve_unpredictable): Likewise.
1272 (print_mve_size): Likewise.
1273 (print_insn_mve): Likewise.
1274
aef6d006
AV		 12752019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1276 Michael Collison <michael.collison@arm.com>
1277
1278 * arm-dis.c (enum mve_instructions): Add new instructions.
1279 (enum mve_undefined): Add new reasons.
1280 (insns): Add new instructions.
1281 (is_mve_encoding_conflict):
1282 (print_mve_vld_str_addr): New print function.
1283 (is_mve_undefined): Handle new instructions.
1284 (is_mve_unpredictable): Likewise.
1285 (print_mve_undefined): Likewise.
1286 (print_mve_size): Likewise.
1287 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1288 (print_insn_mve): Handle new operands.
1289
04d54ace
AV		 12902019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1291 Michael Collison <michael.collison@arm.com>
1292
1293 * arm-dis.c (enum mve_instructions): Add new instructions.
1294 (enum mve_unpredictable): Add new reasons.
1295 (is_mve_encoding_conflict): Handle new instructions.
1296 (is_mve_unpredictable): Likewise.
1297 (mve_opcodes): Add new instructions.
1298 (print_mve_unpredictable): Handle new reasons.
1299 (print_mve_register_blocks): New print function.
1300 (print_mve_size): Handle new instructions.
1301 (print_insn_mve): Likewise.
1302
9743db03
AV		 13032019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1304 Michael Collison <michael.collison@arm.com>
1305
1306 * arm-dis.c (enum mve_instructions): Add new instructions.
1307 (enum mve_unpredictable): Add new reasons.
1308 (enum mve_undefined): Likewise.
1309 (is_mve_encoding_conflict): Handle new instructions.
1310 (is_mve_undefined): Likewise.
1311 (is_mve_unpredictable): Likewise.
1312 (coprocessor_opcodes): Move NEON VDUP from here...
1313 (neon_opcodes): ... to here.
1314 (mve_opcodes): Add new instructions.
1315 (print_mve_undefined): Handle new reasons.
1316 (print_mve_unpredictable): Likewise.
1317 (print_mve_size): Handle new instructions.
1318 (print_insn_neon): Handle vdup.
1319 (print_insn_mve): Handle new operands.
1320
143275ea
AV		 13212019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1322 Michael Collison <michael.collison@arm.com>
1323
1324 * arm-dis.c (enum mve_instructions): Add new instructions.
1325 (enum mve_unpredictable): Add new values.
1326 (mve_opcodes): Add new instructions.
1327 (vec_condnames): New array with vector conditions.
1328 (mve_predicatenames): New array with predicate suffixes.
1329 (mve_vec_sizename): New array with vector sizes.
1330 (enum vpt_pred_state): New enum with vector predication states.
1331 (struct vpt_block): New struct type for vpt blocks.
1332 (vpt_block_state): Global struct to keep track of state.
1333 (mve_extract_pred_mask): New helper function.
1334 (num_instructions_vpt_block): Likewise.
1335 (mark_outside_vpt_block): Likewise.
1336 (mark_inside_vpt_block): Likewise.
1337 (invert_next_predicate_state): Likewise.
1338 (update_next_predicate_state): Likewise.
1339 (update_vpt_block_state): Likewise.
1340 (is_vpt_instruction): Likewise.
1341 (is_mve_encoding_conflict): Add entries for new instructions.
1342 (is_mve_unpredictable): Likewise.
1343 (print_mve_unpredictable): Handle new cases.
1344 (print_instruction_predicate): Likewise.
1345 (print_mve_size): New function.
1346 (print_vec_condition): New function.
1347 (print_insn_mve): Handle vpt blocks and new print operands.
1348
f08d8ce3
AV		 13492019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1350
1351 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1352 8, 14 and 15 for Armv8.1-M Mainline.
1353
73cd51e5
AV		 13542019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1355 Michael Collison <michael.collison@arm.com>
1356
1357 * arm-dis.c (enum mve_instructions): New enum.
1358 (enum mve_unpredictable): Likewise.
1359 (enum mve_undefined): Likewise.
1360 (struct mopcode32): New struct.
1361 (is_mve_okay_in_it): New function.
1362 (is_mve_architecture): Likewise.
1363 (arm_decode_field): Likewise.
1364 (arm_decode_field_multiple): Likewise.
1365 (is_mve_encoding_conflict): Likewise.
1366 (is_mve_undefined): Likewise.
1367 (is_mve_unpredictable): Likewise.
1368 (print_mve_undefined): Likewise.
1369 (print_mve_unpredictable): Likewise.
1370 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1371 (print_insn_mve): New function.
1372 (print_insn_thumb32): Handle MVE architecture.
1373 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1374
3076e594
NC		 13752019-05-10 Nick Clifton <nickc@redhat.com>
1376
1377 PR 24538
1378 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1379 end of the table prematurely.
1380
387e7624
FS		 13812019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1382
1383 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1384 macros for R6.
1385
0067be51
AM		 13862019-05-11 Alan Modra <amodra@gmail.com>
1387
1388 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1389 when -Mraw is in effect.
1390
42e6288f
MM		 13912019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1392
1393 * aarch64-dis-2.c: Regenerate.
1394 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1395 (OP_SVE_BBB): New variant set.
1396 (OP_SVE_DDDD): New variant set.
1397 (OP_SVE_HHH): New variant set.
1398 (OP_SVE_HHHU): New variant set.
1399 (OP_SVE_SSS): New variant set.
1400 (OP_SVE_SSSU): New variant set.
1401 (OP_SVE_SHH): New variant set.
1402 (OP_SVE_SBBU): New variant set.
1403 (OP_SVE_DSS): New variant set.
1404 (OP_SVE_DHHU): New variant set.
1405 (OP_SVE_VMV_HSD_BHS): New variant set.
1406 (OP_SVE_VVU_HSD_BHS): New variant set.
1407 (OP_SVE_VVVU_SD_BH): New variant set.
1408 (OP_SVE_VVVU_BHSD): New variant set.
1409 (OP_SVE_VVV_QHD_DBS): New variant set.
1410 (OP_SVE_VVV_HSD_BHS): New variant set.
1411 (OP_SVE_VVV_HSD_BHS2): New variant set.
1412 (OP_SVE_VVV_BHS_HSD): New variant set.
1413 (OP_SVE_VV_BHS_HSD): New variant set.
1414 (OP_SVE_VVV_SD): New variant set.
1415 (OP_SVE_VVU_BHS_HSD): New variant set.
1416 (OP_SVE_VZVV_SD): New variant set.
1417 (OP_SVE_VZVV_BH): New variant set.
1418 (OP_SVE_VZV_SD): New variant set.
1419 (aarch64_opcode_table): Add sve2 instructions.
1420
28ed815a
MM		 14212019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1422
1423 * aarch64-asm-2.c: Regenerated.
1424 * aarch64-dis-2.c: Regenerated.
1425 * aarch64-opc-2.c: Regenerated.
1426 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1427 for SVE_SHLIMM_UNPRED_22.
1428 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1429 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1430 operand.
1431
fd1dc4a0
MM		 14322019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1433
1434 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1435 sve_size_tsz_bhs iclass encode.
1436 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1437 sve_size_tsz_bhs iclass decode.
1438
31e36ab3
MM		 14392019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1440
1441 * aarch64-asm-2.c: Regenerated.
1442 * aarch64-dis-2.c: Regenerated.
1443 * aarch64-opc-2.c: Regenerated.
1444 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1445 for SVE_Zm4_11_INDEX.
1446 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1447 (fields): Handle SVE_i2h field.
1448 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1449 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1450
1be5f94f
MM		 14512019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1452
1453 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1454 sve_shift_tsz_bhsd iclass encode.
1455 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1456 sve_shift_tsz_bhsd iclass decode.
1457
3c17238b
MM		 14582019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1459
1460 * aarch64-asm-2.c: Regenerated.
1461 * aarch64-dis-2.c: Regenerated.
1462 * aarch64-opc-2.c: Regenerated.
1463 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1464 (aarch64_encode_variant_using_iclass): Handle
1465 sve_shift_tsz_hsd iclass encode.
1466 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1467 sve_shift_tsz_hsd iclass decode.
1468 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1469 for SVE_SHRIMM_UNPRED_22.
1470 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1471 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1472 operand.
1473
cd50a87a
MM		 14742019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1475
1476 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1477 sve_size_013 iclass encode.
1478 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1479 sve_size_013 iclass decode.
1480
3c705960
MM		 14812019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1482
1483 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1484 sve_size_bh iclass encode.
1485 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1486 sve_size_bh iclass decode.
1487
0a57e14f
MM		 14882019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1489
1490 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1491 sve_size_sd2 iclass encode.
1492 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1493 sve_size_sd2 iclass decode.
1494 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1495 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1496
c469c864
MM		 14972019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1498
1499 * aarch64-asm-2.c: Regenerated.
1500 * aarch64-dis-2.c: Regenerated.
1501 * aarch64-opc-2.c: Regenerated.
1502 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1503 for SVE_ADDR_ZX.
1504 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1505 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1506
116adc27
MM		 15072019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1508
1509 * aarch64-asm-2.c: Regenerated.
1510 * aarch64-dis-2.c: Regenerated.
1511 * aarch64-opc-2.c: Regenerated.
1512 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1513 for SVE_Zm3_11_INDEX.
1514 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1515 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1516 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1517 fields.
1518 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1519
3bd82c86
MM		 15202019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1521
1522 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1523 sve_size_hsd2 iclass encode.
1524 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1525 sve_size_hsd2 iclass decode.
1526 * aarch64-opc.c (fields): Handle SVE_size field.
1527 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1528
adccc507
MM		 15292019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1530
1531 * aarch64-asm-2.c: Regenerated.
1532 * aarch64-dis-2.c: Regenerated.
1533 * aarch64-opc-2.c: Regenerated.
1534 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1535 for SVE_IMM_ROT3.
1536 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1537 (fields): Handle SVE_rot3 field.
1538 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1539 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1540
5cd99750
MM		 15412019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1542
1543 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1544 instructions.
1545
7ce2460a
MM		 15462019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1547
1548 * aarch64-tbl.h
1549 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1550 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1551 aarch64_feature_sve2bitperm): New feature sets.
1552 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1553 for feature set addresses.
1554 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1555 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1556
41cee089
FS		 15572019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1558 Faraz Shahbazker <fshahbazker@wavecomp.com>
1559
1560 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1561 argument and set ASE_EVA_R6 appropriately.
1562 (set_default_mips_dis_options): Pass ISA to above.
1563 (parse_mips_dis_option): Likewise.
1564 * mips-opc.c (EVAR6): New macro.
1565 (mips_builtin_opcodes): Add llwpe, scwpe.
1566
b83b4b13
SD		 15672019-05-01 Sudakshina Das <sudi.das@arm.com>
1568
1569 * aarch64-asm-2.c: Regenerated.
1570 * aarch64-dis-2.c: Regenerated.
1571 * aarch64-opc-2.c: Regenerated.
1572 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1573 AARCH64_OPND_TME_UIMM16.
1574 (aarch64_print_operand): Likewise.
1575 * aarch64-tbl.h (QL_IMM_NIL): New.
1576 (TME): New.
1577 (_TME_INSN): New.
1578 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1579
4a90ce95
JD		 15802019-04-29 John Darrington <john@darrington.wattle.id.au>
1581
1582 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1583
a45328b9
AB		 15842019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1585 Faraz Shahbazker <fshahbazker@wavecomp.com>
1586
1587 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1588
d10be0cb
JD		 15892019-04-24 John Darrington <john@darrington.wattle.id.au>
1590
1591 * s12z-opc.h: Add extern "C" bracketing to help
1592 users who wish to use this interface in c++ code.
1593
a679f24e
JD		 15942019-04-24 John Darrington <john@darrington.wattle.id.au>
1595
1596 * s12z-opc.c (bm_decode): Handle bit map operations with the
1597 "reserved0" mode.
1598
32c36c3c
AV		 15992019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1600
1601 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1602 specifier. Add entries for VLDR and VSTR of system registers.
1603 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1604 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1605 of %J and %K format specifier.
1606
efd6b359
AV		 16072019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1608
1609 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1610 Add new entries for VSCCLRM instruction.
1611 (print_insn_coprocessor): Handle new %C format control code.
1612
6b0dd094
AV		 16132019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1614
1615 * arm-dis.c (enum isa): New enum.
1616 (struct sopcode32): New structure.
1617 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1618 set isa field of all current entries to ANY.
1619 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1620 Only match an entry if its isa field allows the current mode.
1621
4b5a202f
AV		 16222019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1623
1624 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1625 CLRM.
1626 (print_insn_thumb32): Add logic to print %n CLRM register list.
1627
60f993ce
AV		 16282019-04-15 Sudakshina Das <sudi.das@arm.com>
1629
1630 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1631 and %Q patterns.
1632
f6b2b12d
AV		 16332019-04-15 Sudakshina Das <sudi.das@arm.com>
1634
1635 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1636 (print_insn_thumb32): Edit the switch case for %Z.
1637
1889da70
AV		 16382019-04-15 Sudakshina Das <sudi.das@arm.com>
1639
1640 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1641
65d1bc05
AV		 16422019-04-15 Sudakshina Das <sudi.das@arm.com>
1643
1644 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1645
1caf72a5
AV		 16462019-04-15 Sudakshina Das <sudi.das@arm.com>
1647
1648 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1649
f1c7f421
AV		 16502019-04-15 Sudakshina Das <sudi.das@arm.com>
1651
1652 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1653 Arm register with r13 and r15 unpredictable.
1654 (thumb32_opcodes): New instructions for bfx and bflx.
1655
4389b29a
AV		 16562019-04-15 Sudakshina Das <sudi.das@arm.com>
1657
1658 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1659
e5d6e09e
AV		 16602019-04-15 Sudakshina Das <sudi.das@arm.com>
1661
1662 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1663
e12437dc
AV		 16642019-04-15 Sudakshina Das <sudi.das@arm.com>
1665
1666 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1667
031254f2
AV		 16682019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1669
1670 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1671
e5a557ac
JD		 16722019-04-12 John Darrington <john@darrington.wattle.id.au>
1673
1674 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1675 "optr". ("operator" is a reserved word in c++).
1676
bd7ceb8d
SD		 16772019-04-11 Sudakshina Das <sudi.das@arm.com>
1678
1679 * aarch64-opc.c (aarch64_print_operand): Add case for
1680 AARCH64_OPND_Rt_SP.
1681 (verify_constraints): Likewise.
1682 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1683 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1684 to accept Rt|SP as first operand.
1685 (AARCH64_OPERANDS): Add new Rt_SP.
1686 * aarch64-asm-2.c: Regenerated.
1687 * aarch64-dis-2.c: Regenerated.
1688 * aarch64-opc-2.c: Regenerated.
1689
e54010f1
SD		 16902019-04-11 Sudakshina Das <sudi.das@arm.com>
1691
1692 * aarch64-asm-2.c: Regenerated.
1693 * aarch64-dis-2.c: Likewise.
1694 * aarch64-opc-2.c: Likewise.
1695 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1696
7e96e219
RS		 16972019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1698
1699 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1700
6f2791d5
L		 17012019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1702
1703 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1704 * i386-init.h: Regenerated.
1705
e392bad3
AM		 17062019-04-07 Alan Modra <amodra@gmail.com>
1707
1708 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1709 op_separator to control printing of spaces, comma and parens
1710 rather than need_comma, need_paren and spaces vars.
1711
dffaa15c
AM		 17122019-04-07 Alan Modra <amodra@gmail.com>
1713
1714 PR 24421
1715 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1716 (print_insn_neon, print_insn_arm): Likewise.
1717
d6aab7a1
XG		 17182019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1719
1720 * i386-dis-evex.h (evex_table): Updated to support BF16
1721 instructions.
1722 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1723 and EVEX_W_0F3872_P_3.
1724 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1725 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1726 * i386-opc.h (enum): Add CpuAVX512_BF16.
1727 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1728 * i386-opc.tbl: Add AVX512 BF16 instructions.
1729 * i386-init.h: Regenerated.
1730 * i386-tbl.h: Likewise.
1731
66e85460
AM		 17322019-04-05 Alan Modra <amodra@gmail.com>
1733
1734 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1735 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1736 to favour printing of "-" branch hint when using the "y" bit.
1737 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1738
c2b1c275
AM		 17392019-04-05 Alan Modra <amodra@gmail.com>
1740
1741 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1742 opcode until first operand is output.
1743
aae9718e
PB		 17442019-04-04 Peter Bergner <bergner@linux.ibm.com>
1745
1746 PR gas/24349
1747 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1748 (valid_bo_post_v2): Add support for 'at' branch hints.
1749 (insert_bo): Only error on branch on ctr.
1750 (get_bo_hint_mask): New function.
1751 (insert_boe): Add new 'branch_taken' formal argument. Add support
1752 for inserting 'at' branch hints.
1753 (extract_boe): Add new 'branch_taken' formal argument. Add support
1754 for extracting 'at' branch hints.
1755 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1756 (BOE): Delete operand.
1757 (BOM, BOP): New operands.
1758 (RM): Update value.
1759 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1760 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1761 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1762 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1763 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1764 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1765 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1766 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1767 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1768 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1769 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1770 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1771 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1772 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1773 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1774 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1775 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1776 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1777 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1778 bttarl+>: New extended mnemonics.
1779
96a86c01
AM		 17802019-03-28 Alan Modra <amodra@gmail.com>
1781
1782 PR 24390
1783 * ppc-opc.c (BTF): Define.
1784 (powerpc_opcodes): Use for mtfsb*.
1785 * ppc-dis.c (print_insn_powerpc): Print fields with both
1786 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1787
796d6298
TC		 17882019-03-25 Tamar Christina <tamar.christina@arm.com>
1789
1790 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1791 (mapping_symbol_for_insn): Implement new algorithm.
1792 (print_insn): Remove duplicate code.
1793
60df3720
TC		 17942019-03-25 Tamar Christina <tamar.christina@arm.com>
1795
1796 * aarch64-dis.c (print_insn_aarch64):
1797 Implement override.
1798
51457761
TC		 17992019-03-25 Tamar Christina <tamar.christina@arm.com>
1800
1801 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1802 order.
1803
53b2f36b
TC		 18042019-03-25 Tamar Christina <tamar.christina@arm.com>
1805
1806 * aarch64-dis.c (last_stop_offset): New.
1807 (print_insn_aarch64): Use stop_offset.
1808
89199bb5
L		 18092019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1810
1811 PR gas/24359
1812 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1813 CPU_ANY_AVX2_FLAGS.
1814 * i386-init.h: Regenerated.
1815
97ed31ae
L		 18162019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1817
1818 PR gas/24348
1819 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1820 vmovdqu16, vmovdqu32 and vmovdqu64.
1821 * i386-tbl.h: Regenerated.
1822
0919bfe9
AK		 18232019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1824
1825 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1826 from vstrszb, vstrszh, and vstrszf.
1827
18282019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1829
1830 * s390-opc.txt: Add instruction descriptions.
1831
21820ebe
JW		 18322019-02-08 Jim Wilson <jimw@sifive.com>
1833
1834 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1835 <bne>: Likewise.
1836
f7dd2fb2
TC		 18372019-02-07 Tamar Christina <tamar.christina@arm.com>
1838
1839 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1840
6456d318
TC		 18412019-02-07 Tamar Christina <tamar.christina@arm.com>
1842
1843 PR binutils/23212
1844 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1845 * aarch64-opc.c (verify_elem_sd): New.
1846 (fields): Add FLD_sz entr.
1847 * aarch64-tbl.h (_SIMD_INSN): New.
1848 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1849 fmulx scalar and vector by element isns.
1850
4a83b610
NC		 18512019-02-07 Nick Clifton <nickc@redhat.com>
1852
1853 * po/sv.po: Updated Swedish translation.
1854
fc60b8c8
AK		 18552019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1856
1857 * s390-mkopc.c (main): Accept arch13 as cpu string.
1858 * s390-opc.c: Add new instruction formats and instruction opcode
1859 masks.
1860 * s390-opc.txt: Add new arch13 instructions.
1861
e10620d3
TC		 18622019-01-25 Sudakshina Das <sudi.das@arm.com>
1863
1864 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1865 (aarch64_opcode): Change encoding for stg, stzg
1866 st2g and st2zg.
1867 * aarch64-asm-2.c: Regenerated.
1868 * aarch64-dis-2.c: Regenerated.
1869 * aarch64-opc-2.c: Regenerated.
1870
20a4ca55
SD		 18712019-01-25 Sudakshina Das <sudi.das@arm.com>
1872
1873 * aarch64-asm-2.c: Regenerated.
1874 * aarch64-dis-2.c: Likewise.
1875 * aarch64-opc-2.c: Likewise.
1876 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1877
550fd7bf
SD		 18782019-01-25 Sudakshina Das <sudi.das@arm.com>
1879 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1880
1881 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1882 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1883 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1884 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1885 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1886 case for ldstgv_indexed.
1887 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1888 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1889 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1890 * aarch64-asm-2.c: Regenerated.
1891 * aarch64-dis-2.c: Regenerated.
1892 * aarch64-opc-2.c: Regenerated.
1893
d9938630
NC		 18942019-01-23 Nick Clifton <nickc@redhat.com>
1895
1896 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1897
375cd423
NC		 18982019-01-21 Nick Clifton <nickc@redhat.com>
1899
1900 * po/de.po: Updated German translation.
1901 * po/uk.po: Updated Ukranian translation.
1902
57299f48
CX		 19032019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1904 * mips-dis.c (mips_arch_choices): Fix typo in
1905 gs464, gs464e and gs264e descriptors.
1906
f48dfe41
NC		 19072019-01-19 Nick Clifton <nickc@redhat.com>
1908
1909 * configure: Regenerate.
1910 * po/opcodes.pot: Regenerate.
1911
f974f26c
NC		 19122018-06-24 Nick Clifton <nickc@redhat.com>
1913
1914 2.32 branch created.
1915
39f286cd
JD		 19162019-01-09 John Darrington <john@darrington.wattle.id.au>
1917
448b8ca8
JD		 1918 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1919 if it is null.
1920 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1921 zero.
1922
3107326d
AP		 19232019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1924
1925 * configure: Regenerate.
1926
7e9ca91e
AM		 19272019-01-07 Alan Modra <amodra@gmail.com>
1928
1929 * configure: Regenerate.
1930 * po/POTFILES.in: Regenerate.
1931
ef1ad42b
JD		 19322019-01-03 John Darrington <john@darrington.wattle.id.au>
1933
1934 * s12z-opc.c: New file.
1935 * s12z-opc.h: New file.
1936 * s12z-dis.c: Removed all code not directly related to display
1937 of instructions. Used the interface provided by the new files
1938 instead.
1939 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1940 * Makefile.in: Regenerate.
ef1ad42b 1941 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1942 * configure: Regenerate.
ef1ad42b 1943
82704155
AM		 19442019-01-01 Alan Modra <amodra@gmail.com>
1945
1946 Update year range in copyright notice of all files.
1947
d5c04e1b 1948For older changes see ChangeLog-2018
3499769a 1949\f
d5c04e1b 1950Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1951
1952Copying and distribution of this file, with or without modification,
1953are permitted in any medium without royalty provided the copyright
1954notice and this notice are preserved.
1955
1956Local Variables:
1957mode: change-log
1958left-margin: 8
1959fill-column: 74
1960version-control: never
1961End:
GDB Binutils - Deliverables
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