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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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a5721ba2
AM		 12016-09-29 Alan Modra <amodra@gmail.com>
2
3 * ppc-opc.c (L): Make compulsory.
4 (LOPT): New, optional form of L.
5 (HTM_R): Define as LOPT.
6 (L0, L1): Delete.
7 (L32OPT): New, optional for 32-bit L.
8 (L2OPT): New, 2-bit L for dcbf.
9 (SVC_LEC): Update.
10 (L2): Define.
11 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
12 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
13 <dcbf>: Use L2OPT.
14 <tlbiel, tlbie>: Use LOPT.
15 <wclr, wclrall>: Use L2.
16
c5da1932
VZ		 172016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
18
19 * Makefile.in: Regenerate.
20 * configure: Likewise.
21
2b848ebd
CZ		 222016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
23
24 * arc-ext-tbl.h (EXTINSN2OPF): Define.
25 (EXTINSN2OP): Use EXTINSN2OPF.
26 (bspeekm, bspop, modapp): New extension instructions.
27 * arc-opc.c (F_DNZ_ND): Define.
28 (F_DNZ_D): Likewise.
29 (F_SIZEB1): Changed.
30 (C_DNZ_D): Define.
31 (C_HARD): Changed.
32 * arc-tbl.h (dbnz): New instruction.
33 (prealloc): Allow it for ARC EM.
34 (xbfu): Likewise.
35
ad43e107
RS		 362016-09-21 Richard Sandiford <richard.sandiford@arm.com>
37
38 * aarch64-opc.c (print_immediate_offset_address): Print spaces
39 after commas in addresses.
40 (aarch64_print_operand): Likewise.
41
ab3b8fcf
RS		 422016-09-21 Richard Sandiford <richard.sandiford@arm.com>
43
44 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
45 rather than "should be" or "expected to be" in error messages.
46
bb7eff52
RS		 472016-09-21 Richard Sandiford <richard.sandiford@arm.com>
48
49 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
50 (print_mnemonic_name): ...here.
51 (print_comment): New function.
52 (print_aarch64_insn): Call it.
53 * aarch64-opc.c (aarch64_conds): Add SVE names.
54 (aarch64_print_operand): Print alternative condition names in
55 a comment.
56
c0890d26
RS		 572016-09-21 Richard Sandiford <richard.sandiford@arm.com>
58
59 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
60 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
61 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
62 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
63 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
64 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
65 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
66 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
67 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
68 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
69 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
70 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
71 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
72 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
73 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
74 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
75 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
76 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
77 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
78 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
79 (OP_SVE_XWU, OP_SVE_XXU): New macros.
80 (aarch64_feature_sve): New variable.
81 (SVE): New macro.
82 (_SVE_INSN): Likewise.
83 (aarch64_opcode_table): Add SVE instructions.
84 * aarch64-opc.h (extract_fields): Declare.
85 * aarch64-opc-2.c: Regenerate.
86 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
87 * aarch64-asm-2.c: Regenerate.
88 * aarch64-dis.c (extract_fields): Make global.
89 (do_misc_decoding): Handle the new SVE aarch64_ops.
90 * aarch64-dis-2.c: Regenerate.
91
116b6019
RS		 922016-09-21 Richard Sandiford <richard.sandiford@arm.com>
93
94 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
95 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
96 aarch64_field_kinds.
97 * aarch64-opc.c (fields): Add corresponding entries.
98 * aarch64-asm.c (aarch64_get_variant): New function.
99 (aarch64_encode_variant_using_iclass): Likewise.
100 (aarch64_opcode_encode): Call it.
101 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
102 (aarch64_opcode_decode): Call it.
103
047cd301
RS		 1042016-09-21 Richard Sandiford <richard.sandiford@arm.com>
105
106 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
107 and FP register operands.
108 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
109 (FLD_SVE_Vn): New aarch64_field_kinds.
110 * aarch64-opc.c (fields): Add corresponding entries.
111 (aarch64_print_operand): Handle the new SVE core and FP register
112 operands.
113 * aarch64-opc-2.c: Regenerate.
114 * aarch64-asm-2.c: Likewise.
115 * aarch64-dis-2.c: Likewise.
116
165d4950
RS		 1172016-09-21 Richard Sandiford <richard.sandiford@arm.com>
118
119 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
120 immediate operands.
121 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
122 * aarch64-opc.c (fields): Add corresponding entry.
123 (operand_general_constraint_met_p): Handle the new SVE FP immediate
124 operands.
125 (aarch64_print_operand): Likewise.
126 * aarch64-opc-2.c: Regenerate.
127 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
128 (ins_sve_float_zero_one): New inserters.
129 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
130 (aarch64_ins_sve_float_half_two): Likewise.
131 (aarch64_ins_sve_float_zero_one): Likewise.
132 * aarch64-asm-2.c: Regenerate.
133 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
134 (ext_sve_float_zero_one): New extractors.
135 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
136 (aarch64_ext_sve_float_half_two): Likewise.
137 (aarch64_ext_sve_float_zero_one): Likewise.
138 * aarch64-dis-2.c: Regenerate.
139
e950b345
RS		 1402016-09-21 Richard Sandiford <richard.sandiford@arm.com>
141
142 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
143 integer immediate operands.
144 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
145 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
146 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
147 * aarch64-opc.c (fields): Add corresponding entries.
148 (operand_general_constraint_met_p): Handle the new SVE integer
149 immediate operands.
150 (aarch64_print_operand): Likewise.
151 (aarch64_sve_dupm_mov_immediate_p): New function.
152 * aarch64-opc-2.c: Regenerate.
153 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
154 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
155 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
156 (aarch64_ins_limm): ...here.
157 (aarch64_ins_inv_limm): New function.
158 (aarch64_ins_sve_aimm): Likewise.
159 (aarch64_ins_sve_asimm): Likewise.
160 (aarch64_ins_sve_limm_mov): Likewise.
161 (aarch64_ins_sve_shlimm): Likewise.
162 (aarch64_ins_sve_shrimm): Likewise.
163 * aarch64-asm-2.c: Regenerate.
164 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
165 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
166 * aarch64-dis.c (decode_limm): New function, split out from...
167 (aarch64_ext_limm): ...here.
168 (aarch64_ext_inv_limm): New function.
169 (decode_sve_aimm): Likewise.
170 (aarch64_ext_sve_aimm): Likewise.
171 (aarch64_ext_sve_asimm): Likewise.
172 (aarch64_ext_sve_limm_mov): Likewise.
173 (aarch64_top_bit): Likewise.
174 (aarch64_ext_sve_shlimm): Likewise.
175 (aarch64_ext_sve_shrimm): Likewise.
176 * aarch64-dis-2.c: Regenerate.
177
98907a70
RS		 1782016-09-21 Richard Sandiford <richard.sandiford@arm.com>
179
180 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
181 operands.
182 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
183 the AARCH64_MOD_MUL_VL entry.
184 (value_aligned_p): Cope with non-power-of-two alignments.
185 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
186 (print_immediate_offset_address): Likewise.
187 (aarch64_print_operand): Likewise.
188 * aarch64-opc-2.c: Regenerate.
189 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
190 (ins_sve_addr_ri_s9xvl): New inserters.
191 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
192 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
193 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
194 * aarch64-asm-2.c: Regenerate.
195 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
196 (ext_sve_addr_ri_s9xvl): New extractors.
197 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
198 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
199 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
200 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
201 * aarch64-dis-2.c: Regenerate.
202
4df068de
RS		 2032016-09-21 Richard Sandiford <richard.sandiford@arm.com>
204
205 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
206 address operands.
207 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
208 (FLD_SVE_xs_22): New aarch64_field_kinds.
209 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
210 (get_operand_specific_data): New function.
211 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
212 FLD_SVE_xs_14 and FLD_SVE_xs_22.
213 (operand_general_constraint_met_p): Handle the new SVE address
214 operands.
215 (sve_reg): New array.
216 (get_addr_sve_reg_name): New function.
217 (aarch64_print_operand): Handle the new SVE address operands.
218 * aarch64-opc-2.c: Regenerate.
219 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
220 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
221 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
222 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
223 (aarch64_ins_sve_addr_rr_lsl): Likewise.
224 (aarch64_ins_sve_addr_rz_xtw): Likewise.
225 (aarch64_ins_sve_addr_zi_u5): Likewise.
226 (aarch64_ins_sve_addr_zz): Likewise.
227 (aarch64_ins_sve_addr_zz_lsl): Likewise.
228 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
229 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
230 * aarch64-asm-2.c: Regenerate.
231 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
232 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
233 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
234 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
235 (aarch64_ext_sve_addr_ri_u6): Likewise.
236 (aarch64_ext_sve_addr_rr_lsl): Likewise.
237 (aarch64_ext_sve_addr_rz_xtw): Likewise.
238 (aarch64_ext_sve_addr_zi_u5): Likewise.
239 (aarch64_ext_sve_addr_zz): Likewise.
240 (aarch64_ext_sve_addr_zz_lsl): Likewise.
241 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
242 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
243 * aarch64-dis-2.c: Regenerate.
244
2442d846
RS		 2452016-09-21 Richard Sandiford <richard.sandiford@arm.com>
246
247 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
248 AARCH64_OPND_SVE_PATTERN_SCALED.
249 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
250 * aarch64-opc.c (fields): Add a corresponding entry.
251 (set_multiplier_out_of_range_error): New function.
252 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
253 (operand_general_constraint_met_p): Handle
254 AARCH64_OPND_SVE_PATTERN_SCALED.
255 (print_register_offset_address): Use PRIi64 to print the
256 shift amount.
257 (aarch64_print_operand): Likewise. Handle
258 AARCH64_OPND_SVE_PATTERN_SCALED.
259 * aarch64-opc-2.c: Regenerate.
260 * aarch64-asm.h (ins_sve_scale): New inserter.
261 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
262 * aarch64-asm-2.c: Regenerate.
263 * aarch64-dis.h (ext_sve_scale): New inserter.
264 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
265 * aarch64-dis-2.c: Regenerate.
266
245d2e3f
RS		 2672016-09-21 Richard Sandiford <richard.sandiford@arm.com>
268
269 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
270 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
271 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
272 (FLD_SVE_prfop): Likewise.
273 * aarch64-opc.c: Include libiberty.h.
274 (aarch64_sve_pattern_array): New variable.
275 (aarch64_sve_prfop_array): Likewise.
276 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
277 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
278 AARCH64_OPND_SVE_PRFOP.
279 * aarch64-asm-2.c: Regenerate.
280 * aarch64-dis-2.c: Likewise.
281 * aarch64-opc-2.c: Likewise.
282
d50c751e
RS		 2832016-09-21 Richard Sandiford <richard.sandiford@arm.com>
284
285 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
286 AARCH64_OPND_QLF_P_[ZM].
287 (aarch64_print_operand): Print /z and /m where appropriate.
288
f11ad6bc
RS		 2892016-09-21 Richard Sandiford <richard.sandiford@arm.com>
290
291 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
292 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
293 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
294 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
295 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
296 * aarch64-opc.c (fields): Add corresponding entries here.
297 (operand_general_constraint_met_p): Check that SVE register lists
298 have the correct length. Check the ranges of SVE index registers.
299 Check for cases where p8-p15 are used in 3-bit predicate fields.
300 (aarch64_print_operand): Handle the new SVE operands.
301 * aarch64-opc-2.c: Regenerate.
302 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
303 * aarch64-asm.c (aarch64_ins_sve_index): New function.
304 (aarch64_ins_sve_reglist): Likewise.
305 * aarch64-asm-2.c: Regenerate.
306 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
307 * aarch64-dis.c (aarch64_ext_sve_index): New function.
308 (aarch64_ext_sve_reglist): Likewise.
309 * aarch64-dis-2.c: Regenerate.
310
0c608d6b
RS		 3112016-09-21 Richard Sandiford <richard.sandiford@arm.com>
312
313 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
314 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
315 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
316 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
317 tied operands.
318
01dbfe4c
RS		 3192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
320
321 * aarch64-opc.c (get_offset_int_reg_name): New function.
322 (print_immediate_offset_address): Likewise.
323 (print_register_offset_address): Take the base and offset
324 registers as parameters.
325 (aarch64_print_operand): Update caller accordingly. Use
326 print_immediate_offset_address.
327
72e9f319
RS		 3282016-09-21 Richard Sandiford <richard.sandiford@arm.com>
329
330 * aarch64-opc.c (BANK): New macro.
331 (R32, R64): Take a register number as argument
332 (int_reg): Use BANK.
333
8a7f0c1b
RS		 3342016-09-21 Richard Sandiford <richard.sandiford@arm.com>
335
336 * aarch64-opc.c (print_register_list): Add a prefix parameter.
337 (aarch64_print_operand): Update accordingly.
338
aa2aa4c6
RS		 3392016-09-21 Richard Sandiford <richard.sandiford@arm.com>
340
341 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
342 for FPIMM.
343 * aarch64-asm.h (ins_fpimm): New inserter.
344 * aarch64-asm.c (aarch64_ins_fpimm): New function.
345 * aarch64-asm-2.c: Regenerate.
346 * aarch64-dis.h (ext_fpimm): New extractor.
347 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
348 (aarch64_ext_fpimm): New function.
349 * aarch64-dis-2.c: Regenerate.
350
b5464a68
RS		 3512016-09-21 Richard Sandiford <richard.sandiford@arm.com>
352
353 * aarch64-asm.c: Include libiberty.h.
354 (insert_fields): New function.
355 (aarch64_ins_imm): Use it.
356 * aarch64-dis.c (extract_fields): New function.
357 (aarch64_ext_imm): Use it.
358
42408347
RS		 3592016-09-21 Richard Sandiford <richard.sandiford@arm.com>
360
361 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
362 with an esize parameter.
363 (operand_general_constraint_met_p): Update accordingly.
364 Fix misindented code.
365 * aarch64-asm.c (aarch64_ins_limm): Update call to
366 aarch64_logical_immediate_p.
367
4989adac
RS		 3682016-09-21 Richard Sandiford <richard.sandiford@arm.com>
369
370 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
371
bd11d5d8
RS		 3722016-09-21 Richard Sandiford <richard.sandiford@arm.com>
373
374 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
375
f807f43d
CZ		 3762016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
377
378 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
379
fd486b63
PB		 3802016-09-14 Peter Bergner <bergner@vnet.ibm.com>
381
382 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
383 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
384 xor3>: Delete mnemonics.
385 <cp_abort>: Rename mnemonic from ...
386 <cpabort>: ...to this.
387 <setb>: Change to a X form instruction.
388 <sync>: Change to 1 operand form.
389 <copy>: Delete mnemonic.
390 <copy_first>: Rename mnemonic from ...
391 <copy>: ...to this.
392 <paste, paste.>: Delete mnemonics.
393 <paste_last>: Rename mnemonic from ...
394 <paste.>: ...to this.
395
dce08442
AK		 3962016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
397
398 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
399
952c3f51
AK		 4002016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
401
402 * s390-mkopc.c (main): Support alternate arch strings.
403
8b71537b
PS		 4042016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
405
406 * s390-opc.txt: Fix kmctr instruction type.
407
5b64d091
L		 4082016-09-07 H.J. Lu <hongjiu.lu@intel.com>
409
410 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
411 * i386-init.h: Regenerated.
412
7763838e
CM		 4132016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
414
415 * opcodes/arc-dis.c (print_insn_arc): Changed.
416
1b8b6532
JM		 4172016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
418
419 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
420 camellia_fl.
421
1a336194
TP		 4222016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
423
424 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
425 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
426 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
427
6b40c462
L		 4282016-08-24 H.J. Lu <hongjiu.lu@intel.com>
429
430 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
431 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
432 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
433 PREFIX_MOD_3_0FAE_REG_4.
434 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
435 PREFIX_MOD_3_0FAE_REG_4.
436 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
437 (cpu_flags): Add CpuPTWRITE.
438 * i386-opc.h (CpuPTWRITE): New.
439 (i386_cpu_flags): Add cpuptwrite.
440 * i386-opc.tbl: Add ptwrite instruction.
441 * i386-init.h: Regenerated.
442 * i386-tbl.h: Likewise.
443
ab548d2d
AK		 4442016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
445
446 * arc-dis.h: Wrap around in extern "C".
447
344bde0a
RS		 4482016-08-23 Richard Sandiford <richard.sandiford@arm.com>
449
450 * aarch64-tbl.h (V8_2_INSN): New macro.
451 (aarch64_opcode_table): Use it.
452
5ce912d8
RS		 4532016-08-23 Richard Sandiford <richard.sandiford@arm.com>
454
455 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
456 CORE_INSN, __FP_INSN and SIMD_INSN.
457
9d30b0bd
RS		 4582016-08-23 Richard Sandiford <richard.sandiford@arm.com>
459
460 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
461 (aarch64_opcode_table): Update uses accordingly.
462
dfdaec14
AJ		 4632016-07-25 Andrew Jenner <andrew@codesourcery.com>
464 Kwok Cheung Yeung <kcy@codesourcery.com>
465
466 opcodes/
467 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
468 'e_cmplwi' to 'e_cmpli' instead.
469 (OPVUPRT, OPVUPRT_MASK): Define.
470 (powerpc_opcodes): Add E200Z4 insns.
471 (vle_opcodes): Add context save/restore insns.
472
7bd374a4
MR		 4732016-07-27 Maciej W. Rozycki <macro@imgtec.com>
474
475 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
476 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
477 "j".
478
db18dbab
GM		 4792016-07-27 Graham Markall <graham.markall@embecosm.com>
480
481 * arc-nps400-tbl.h: Change block comments to GNU format.
482 * arc-dis.c: Add new globals addrtypenames,
483 addrtypenames_max, and addtypeunknown.
484 (get_addrtype): New function.
485 (print_insn_arc): Print colons and address types when
486 required.
487 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
488 define insert and extract functions for all address types.
489 (arc_operands): Add operands for colon and all address
490 types.
491 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
492 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
493 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
494 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
495 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
496 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
497
fecd57f9
L		 4982016-07-21 H.J. Lu <hongjiu.lu@intel.com>
499
500 * configure: Regenerated.
501
37fd5ef3
CZ		 5022016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
503
504 * arc-dis.c (skipclass): New structure.
505 (decodelist): New variable.
506 (is_compatible_p): New function.
507 (new_element): Likewise.
508 (skip_class_p): Likewise.
509 (find_format_from_table): Use skip_class_p function.
510 (find_format): Decode first the extension instructions.
511 (print_insn_arc): Select either ARCEM or ARCHS based on elf
512 e_flags.
513 (parse_option): New function.
514 (parse_disassembler_options): Likewise.
515 (print_arc_disassembler_options): Likewise.
516 (print_insn_arc): Use parse_disassembler_options function. Proper
517 select ARCv2 cpu variant.
518 * disassemble.c (disassembler_usage): Add ARC disassembler
519 options.
520
92281a5b
MR		 5212016-07-13 Maciej W. Rozycki <macro@imgtec.com>
522
523 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
524 annotation from the "nal" entry and reorder it beyond "bltzal".
525
6e7ced37
JM		 5262016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
527
528 * sparc-opc.c (ldtxa): New macro.
529 (sparc_opcodes): Use the macro defined above to add entries for
530 the LDTXA instructions.
531 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
532 instruction.
533
2f831b9a 5342016-07-07 James Bowman <james.bowman@ftdichip.com>
535
536 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
537 and "jmpc".
538
c07315e0
JB		 5392016-07-01 Jan Beulich <jbeulich@suse.com>
540
541 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
542 (movzb): Adjust to cover all permitted suffixes.
543 (movzw): New.
544 * i386-tbl.h: Re-generate.
545
9243100a
JB		 5462016-07-01 Jan Beulich <jbeulich@suse.com>
547
548 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
549 (lgdt): Remove Tbyte from non-64-bit variant.
550 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
551 xsaves64, xsavec64): Remove Disp16.
552 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
553 Remove Disp32S from non-64-bit variants. Remove Disp16 from
554 64-bit variants.
555 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
556 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
557 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
558 64-bit variants.
559 * i386-tbl.h: Re-generate.
560
8325cc63
JB		 5612016-07-01 Jan Beulich <jbeulich@suse.com>
562
563 * i386-opc.tbl (xlat): Remove RepPrefixOk.
564 * i386-tbl.h: Re-generate.
565
838441e4
YQ		 5662016-06-30 Yao Qi <yao.qi@linaro.org>
567
568 * arm-dis.c (print_insn): Fix typo in comment.
569
dab26bf4
RS		 5702016-06-28 Richard Sandiford <richard.sandiford@arm.com>
571
572 * aarch64-opc.c (operand_general_constraint_met_p): Check the
573 range of ldst_elemlist operands.
574 (print_register_list): Use PRIi64 to print the index.
575 (aarch64_print_operand): Likewise.
576
5703197e
TS		 5772016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
578
579 * mcore-opc.h: Remove sentinal.
580 * mcore-dis.c (print_insn_mcore): Adjust.
581
ce440d63
GM		 5822016-06-23 Graham Markall <graham.markall@embecosm.com>
583
584 * arc-opc.c: Correct description of availability of NPS400
585 features.
586
6fd3a02d
PB		 5872016-06-22 Peter Bergner <bergner@vnet.ibm.com>
588
589 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
590 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
591 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
592 xor3>: New mnemonics.
593 <setb>: Change to a VX form instruction.
594 (insert_sh6): Add support for rldixor.
595 (extract_sh6): Likewise.
596
6b477896
TS		 5972016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
598
599 * arc-ext.h: Wrap in extern C.
600
bdd582db
GM		 6012016-06-21 Graham Markall <graham.markall@embecosm.com>
602
603 * arc-dis.c (arc_insn_length): Add comment on instruction length.
604 Use same method for determining instruction length on ARC700 and
605 NPS-400.
606 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
607 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
608 with the NPS400 subclass.
609 * arc-opc.c: Likewise.
610
96074adc
JM		 6112016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
612
613 * sparc-opc.c (rdasr): New macro.
614 (wrasr): Likewise.
615 (rdpr): Likewise.
616 (wrpr): Likewise.
617 (rdhpr): Likewise.
618 (wrhpr): Likewise.
619 (sparc_opcodes): Use the macros above to fix and expand the
620 definition of read/write instructions from/to
621 asr/privileged/hyperprivileged instructions.
622 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
623 %hva_mask_nz. Prefer softint_set and softint_clear over
624 set_softint and clear_softint.
625 (print_insn_sparc): Support %ver in Rd.
626
7a10c22f
JM		 6272016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
628
629 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
630 architecture according to the hardware capabilities they require.
631
4f26fb3a
JM		 6322016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
633
634 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
635 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
636 bfd_mach_sparc_v9{c,d,e,v,m}.
637 * sparc-opc.c (MASK_V9C): Define.
638 (MASK_V9D): Likewise.
639 (MASK_V9E): Likewise.
640 (MASK_V9V): Likewise.
641 (MASK_V9M): Likewise.
642 (v6): Add MASK_V9{C,D,E,V,M}.
643 (v6notlet): Likewise.
644 (v7): Likewise.
645 (v8): Likewise.
646 (v9): Likewise.
647 (v9andleon): Likewise.
648 (v9a): Likewise.
649 (v9b): Likewise.
650 (v9c): Define.
651 (v9d): Likewise.
652 (v9e): Likewise.
653 (v9v): Likewise.
654 (v9m): Likewise.
655 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
656
3ee6e4fb
NC		 6572016-06-15 Nick Clifton <nickc@redhat.com>
658
659 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
660 constants to match expected behaviour.
661 (nds32_parse_opcode): Likewise. Also for whitespace.
662
02f3be19
AB		 6632016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
664
665 * arc-opc.c (extract_rhv1): Extract value from insn.
666
6f9f37ed 6672016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 668
669 * arc-nps400-tbl.h: Add ldbit instruction.
670 * arc-opc.c: Add flag classes required for ldbit.
671
6f9f37ed 6722016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 673
674 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
675 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
676 support the above instructions.
677
6f9f37ed 6782016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 679
680 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
681 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
682 csma, cbba, zncv, and hofs.
683 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
684 support the above instructions.
685
6862016-06-06 Graham Markall <graham.markall@embecosm.com>
687
688 * arc-nps400-tbl.h: Add andab and orab instructions.
689
6902016-06-06 Graham Markall <graham.markall@embecosm.com>
691
692 * arc-nps400-tbl.h: Add addl-like instructions.
693
6942016-06-06 Graham Markall <graham.markall@embecosm.com>
695
696 * arc-nps400-tbl.h: Add mxb and imxb instructions.
697
6982016-06-06 Graham Markall <graham.markall@embecosm.com>
699
700 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
701 instructions.
702
b2cc3f6f
AK		 7032016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
704
705 * s390-dis.c (option_use_insn_len_bits_p): New file scope
706 variable.
707 (init_disasm): Handle new command line option "insnlength".
708 (print_s390_disassembler_options): Mention new option in help
709 output.
710 (print_insn_s390): Use the encoded insn length when dumping
711 unknown instructions.
712
1857fe72
DC		 7132016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
714
715 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
716 to the address and set as symbol address for LDS/ STS immediate operands.
717
14b57c7c
AM		 7182016-06-07 Alan Modra <amodra@gmail.com>
719
720 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
721 cpu for "vle" to e500.
722 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
723 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
724 (PPCNONE): Delete, substitute throughout.
725 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
726 except for major opcode 4 and 31.
727 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
728
4d1464f2
MW		 7292016-06-07 Matthew Wahab <matthew.wahab@arm.com>
730
731 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
732 ARM_EXT_RAS in relevant entries.
733
026122a6
PB		 7342016-06-03 Peter Bergner <bergner@vnet.ibm.com>
735
736 PR binutils/20196
737 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
738 opcodes for E6500.
739
07f5af7d
L		 7402016-06-03 H.J. Lu <hongjiu.lu@intel.com>
741
742 PR binutis/18386
743 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
744 (indir_v_mode): New.
745 Add comments for '&'.
746 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
747 (putop): Handle '&'.
748 (intel_operand_size): Handle indir_v_mode.
749 (OP_E_register): Likewise.
750 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
751 64-bit indirect call/jmp for AMD64.
752 * i386-tbl.h: Regenerated
753
4eb6f892
AB		 7542016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
755
756 * arc-dis.c (struct arc_operand_iterator): New structure.
757 (find_format_from_table): All the old content from find_format,
758 with some minor adjustments, and parameter renaming.
759 (find_format_long_instructions): New function.
760 (find_format): Rewritten.
761 (arc_insn_length): Add LSB parameter.
762 (extract_operand_value): New function.
763 (operand_iterator_next): New function.
764 (print_insn_arc): Use new functions to find opcode, and iterator
765 over operands.
766 * arc-opc.c (insert_nps_3bit_dst_short): New function.
767 (extract_nps_3bit_dst_short): New function.
768 (insert_nps_3bit_src2_short): New function.
769 (extract_nps_3bit_src2_short): New function.
770 (insert_nps_bitop1_size): New function.
771 (extract_nps_bitop1_size): New function.
772 (insert_nps_bitop2_size): New function.
773 (extract_nps_bitop2_size): New function.
774 (insert_nps_bitop_mod4_msb): New function.
775 (extract_nps_bitop_mod4_msb): New function.
776 (insert_nps_bitop_mod4_lsb): New function.
777 (extract_nps_bitop_mod4_lsb): New function.
778 (insert_nps_bitop_dst_pos3_pos4): New function.
779 (extract_nps_bitop_dst_pos3_pos4): New function.
780 (insert_nps_bitop_ins_ext): New function.
781 (extract_nps_bitop_ins_ext): New function.
782 (arc_operands): Add new operands.
783 (arc_long_opcodes): New global array.
784 (arc_num_long_opcodes): New global.
785 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
786
1fe0971e
TS		 7872016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
788
789 * nds32-asm.h: Add extern "C".
790 * sh-opc.h: Likewise.
791
315f180f
GM		 7922016-06-01 Graham Markall <graham.markall@embecosm.com>
793
794 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
795 0,b,limm to the rflt instruction.
796
a2b5fccc
TS		 7972016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
798
799 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
800 constant.
801
0cbd0046
L		 8022016-05-29 H.J. Lu <hongjiu.lu@intel.com>
803
804 PR gas/20145
805 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
806 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
807 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
808 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
809 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
810 * i386-init.h: Regenerated.
811
1848e567
L		 8122016-05-27 H.J. Lu <hongjiu.lu@intel.com>
813
814 PR gas/20145
815 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
816 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
817 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
818 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
819 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
820 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
821 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
822 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
823 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
824 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
825 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
826 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
827 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
828 CpuRegMask for AVX512.
829 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
830 and CpuRegMask.
831 (set_bitfield_from_cpu_flag_init): New function.
832 (set_bitfield): Remove const on f. Call
833 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
834 * i386-opc.h (CpuRegMMX): New.
835 (CpuRegXMM): Likewise.
836 (CpuRegYMM): Likewise.
837 (CpuRegZMM): Likewise.
838 (CpuRegMask): Likewise.
839 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
840 and cpuregmask.
841 * i386-init.h: Regenerated.
842 * i386-tbl.h: Likewise.
843
e92bae62
L		 8442016-05-27 H.J. Lu <hongjiu.lu@intel.com>
845
846 PR gas/20154
847 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
848 (opcode_modifiers): Add AMD64 and Intel64.
849 (main): Properly verify CpuMax.
850 * i386-opc.h (CpuAMD64): Removed.
851 (CpuIntel64): Likewise.
852 (CpuMax): Set to CpuNo64.
853 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
854 (AMD64): New.
855 (Intel64): Likewise.
856 (i386_opcode_modifier): Add amd64 and intel64.
857 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
858 on call and jmp.
859 * i386-init.h: Regenerated.
860 * i386-tbl.h: Likewise.
861
e89c5eaa
L		 8622016-05-27 H.J. Lu <hongjiu.lu@intel.com>
863
864 PR gas/20154
865 * i386-gen.c (main): Fail if CpuMax is incorrect.
866 * i386-opc.h (CpuMax): Set to CpuIntel64.
867 * i386-tbl.h: Regenerated.
868
77d66e7b
NC		 8692016-05-27 Nick Clifton <nickc@redhat.com>
870
871 PR target/20150
872 * msp430-dis.c (msp430dis_read_two_bytes): New function.
873 (msp430dis_opcode_unsigned): New function.
874 (msp430dis_opcode_signed): New function.
875 (msp430_singleoperand): Use the new opcode reading functions.
876 Only disassenmble bytes if they were successfully read.
877 (msp430_doubleoperand): Likewise.
878 (msp430_branchinstr): Likewise.
879 (msp430x_callx_instr): Likewise.
880 (print_insn_msp430): Check that it is safe to read bytes before
881 attempting disassembly. Use the new opcode reading functions.
882
19dfcc89
PB		 8832016-05-26 Peter Bergner <bergner@vnet.ibm.com>
884
885 * ppc-opc.c (CY): New define. Document it.
886 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
887
f3ad7637
L		 8882016-05-25 H.J. Lu <hongjiu.lu@intel.com>
889
890 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
891 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
892 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
893 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
894 CPU_ANY_AVX_FLAGS.
895 * i386-init.h: Regenerated.
896
f1360d58
L		 8972016-05-25 H.J. Lu <hongjiu.lu@intel.com>
898
899 PR gas/20141
900 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
901 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
902 * i386-init.h: Regenerated.
903
293f5f65
L		 9042016-05-25 H.J. Lu <hongjiu.lu@intel.com>
905
906 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
907 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
908 * i386-init.h: Regenerated.
909
d9eca1df
CZ		 9102016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
911
912 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
913 information.
914 (print_insn_arc): Set insn_type information.
915 * arc-opc.c (C_CC): Add F_CLASS_COND.
916 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
917 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
918 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
919 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
920 (brne, brne_s, jeq_s, jne_s): Likewise.
921
87789e08
CZ		 9222016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
923
924 * arc-tbl.h (neg): New instruction variant.
925
c810e0b8
CZ		 9262016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
927
928 * arc-dis.c (find_format, find_format, get_auxreg)
929 (print_insn_arc): Changed.
930 * arc-ext.h (INSERT_XOP): Likewise.
931
3d207518
TS		 9322016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
933
934 * tic54x-dis.c (sprint_mmr): Adjust.
935 * tic54x-opc.c: Likewise.
936
514e58b7
AM		 9372016-05-19 Alan Modra <amodra@gmail.com>
938
939 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
940
e43de63c
AM		 9412016-05-19 Alan Modra <amodra@gmail.com>
942
943 * ppc-opc.c: Formatting.
944 (NSISIGNOPT): Define.
945 (powerpc_opcodes <subis>): Use NSISIGNOPT.
946
1401d2fe
MR		 9472016-05-18 Maciej W. Rozycki <macro@imgtec.com>
948
949 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
950 replacing references to `micromips_ase' throughout.
951 (_print_insn_mips): Don't use file-level microMIPS annotation to
952 determine the disassembly mode with the symbol table.
953
1178da44
PB		 9542016-05-13 Peter Bergner <bergner@vnet.ibm.com>
955
956 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
957
8f4f9071
MF		 9582016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
959
960 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
961 mips64r6.
962 * mips-opc.c (D34): New macro.
963 (mips_builtin_opcodes): Define bposge32c for DSPr3.
964
8bc52696
AF		 9652016-05-10 Alexander Fomin <alexander.fomin@intel.com>
966
967 * i386-dis.c (prefix_table): Add RDPID instruction.
968 * i386-gen.c (cpu_flag_init): Add RDPID flag.
969 (cpu_flags): Add RDPID bitfield.
970 * i386-opc.h (enum): Add RDPID element.
971 (i386_cpu_flags): Add RDPID field.
972 * i386-opc.tbl: Add RDPID instruction.
973 * i386-init.h: Regenerate.
974 * i386-tbl.h: Regenerate.
975
39d911fc
TP		 9762016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
977
978 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
979 branch type of a symbol.
980 (print_insn): Likewise.
981
16a1fa25
TP		 9822016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
983
984 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
985 Mainline Security Extensions instructions.
986 (thumb_opcodes): Add entries for narrow ARMv8-M Security
987 Extensions instructions.
988 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
989 instructions.
990 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
991 special registers.
992
d751b79e
JM		 9932016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
994
995 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
996
945e0f82
CZ		 9972016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
998
999 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1000 (arcExtMap_genOpcode): Likewise.
1001 * arc-opc.c (arg_32bit_rc): Define new variable.
1002 (arg_32bit_u6): Likewise.
1003 (arg_32bit_limm): Likewise.
1004
20f55f38
SN		 10052016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1006
1007 * aarch64-gen.c (VERIFIER): Define.
1008 * aarch64-opc.c (VERIFIER): Define.
1009 (verify_ldpsw): Use static linkage.
1010 * aarch64-opc.h (verify_ldpsw): Remove.
1011 * aarch64-tbl.h: Use VERIFIER for verifiers.
1012
4bd13cde
NC		 10132016-04-28 Nick Clifton <nickc@redhat.com>
1014
1015 PR target/19722
1016 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1017 * aarch64-opc.c (verify_ldpsw): New function.
1018 * aarch64-opc.h (verify_ldpsw): New prototype.
1019 * aarch64-tbl.h: Add initialiser for verifier field.
1020 (LDPSW): Set verifier to verify_ldpsw.
1021
c0f92bf9
L		 10222016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1023
1024 PR binutils/19983
1025 PR binutils/19984
1026 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1027 smaller than address size.
1028
e6c7cdec
TS		 10292016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1030
1031 * alpha-dis.c: Regenerate.
1032 * crx-dis.c: Likewise.
1033 * disassemble.c: Likewise.
1034 * epiphany-opc.c: Likewise.
1035 * fr30-opc.c: Likewise.
1036 * frv-opc.c: Likewise.
1037 * ip2k-opc.c: Likewise.
1038 * iq2000-opc.c: Likewise.
1039 * lm32-opc.c: Likewise.
1040 * lm32-opinst.c: Likewise.
1041 * m32c-opc.c: Likewise.
1042 * m32r-opc.c: Likewise.
1043 * m32r-opinst.c: Likewise.
1044 * mep-opc.c: Likewise.
1045 * mt-opc.c: Likewise.
1046 * or1k-opc.c: Likewise.
1047 * or1k-opinst.c: Likewise.
1048 * tic80-opc.c: Likewise.
1049 * xc16x-opc.c: Likewise.
1050 * xstormy16-opc.c: Likewise.
1051
537aefaf
AB		 10522016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1053
1054 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1055 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1056 calcsd, and calcxd instructions.
1057 * arc-opc.c (insert_nps_bitop_size): Delete.
1058 (extract_nps_bitop_size): Delete.
1059 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1060 (extract_nps_qcmp_m3): Define.
1061 (extract_nps_qcmp_m2): Define.
1062 (extract_nps_qcmp_m1): Define.
1063 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1064 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1065 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1066 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1067 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1068 NPS_QCMP_M3.
1069
c8f785f2
AB		 10702016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1071
1072 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1073
6fd8e7c2
L		 10742016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1075
1076 * Makefile.in: Regenerated with automake 1.11.6.
1077 * aclocal.m4: Likewise.
1078
4b0c052e
AB		 10792016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1080
1081 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1082 instructions.
1083 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1084 (extract_nps_cmem_uimm16): New function.
1085 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1086
cb040366
AB		 10872016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1088
1089 * arc-dis.c (arc_insn_length): New function.
1090 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1091 (find_format): Change insnLen parameter to unsigned.
1092
accc0180
NC		 10932016-04-13 Nick Clifton <nickc@redhat.com>
1094
1095 PR target/19937
1096 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1097 the LD.B and LD.BU instructions.
1098
f36e33da
CZ		 10992016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1100
1101 * arc-dis.c (find_format): Check for extension flags.
1102 (print_flags): New function.
1103 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1104 .extAuxRegister.
1105 * arc-ext.c (arcExtMap_coreRegName): Use
1106 LAST_EXTENSION_CORE_REGISTER.
1107 (arcExtMap_coreReadWrite): Likewise.
1108 (dump_ARC_extmap): Update printing.
1109 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1110 (arc_aux_regs): Add cpu field.
1111 * arc-regs.h: Add cpu field, lower case name aux registers.
1112
1c2e355e
CZ		 11132016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1114
1115 * arc-tbl.h: Add rtsc, sleep with no arguments.
1116
b99747ae
CZ		 11172016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1118
1119 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1120 Initialize.
1121 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1122 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1123 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1124 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1125 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1126 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1127 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1128 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1129 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1130 (arc_opcode arc_opcodes): Null terminate the array.
1131 (arc_num_opcodes): Remove.
1132 * arc-ext.h (INSERT_XOP): Define.
1133 (extInstruction_t): Likewise.
1134 (arcExtMap_instName): Delete.
1135 (arcExtMap_insn): New function.
1136 (arcExtMap_genOpcode): Likewise.
1137 * arc-ext.c (ExtInstruction): Remove.
1138 (create_map): Zero initialize instruction fields.
1139 (arcExtMap_instName): Remove.
1140 (arcExtMap_insn): New function.
1141 (dump_ARC_extmap): More info while debuging.
1142 (arcExtMap_genOpcode): New function.
1143 * arc-dis.c (find_format): New function.
1144 (print_insn_arc): Use find_format.
1145 (arc_get_disassembler): Enable dump_ARC_extmap only when
1146 debugging.
1147
92708cec
MR		 11482016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1149
1150 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1151 instruction bits out.
1152
a42a4f84
AB		 11532016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1154
1155 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1156 * arc-opc.c (arc_flag_operands): Add new flags.
1157 (arc_flag_classes): Add new classes.
1158
1328504b
AB		 11592016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1160
1161 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1162
820f03ff
AB		 11632016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1164
1165 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1166 encode1, rflt, crc16, and crc32 instructions.
1167 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1168 (arc_flag_classes): Add C_NPS_R.
1169 (insert_nps_bitop_size_2b): New function.
1170 (extract_nps_bitop_size_2b): Likewise.
1171 (insert_nps_bitop_uimm8): Likewise.
1172 (extract_nps_bitop_uimm8): Likewise.
1173 (arc_operands): Add new operand entries.
1174
8ddf6b2a
CZ		 11752016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1176
b99747ae
CZ		 1177 * arc-regs.h: Add a new subclass field. Add double assist
1178 accumulator register values.
1179 * arc-tbl.h: Use DPA subclass to mark the double assist
1180 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1181 * arc-opc.c (RSP): Define instead of SP.
1182 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1183
589a7d88
JW		 11842016-04-05 Jiong Wang <jiong.wang@arm.com>
1185
1186 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1187
0a191de9 11882016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1189
1190 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1191 NPS_R_SRC1.
1192
0a106562
AB		 11932016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1194
1195 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1196 issues. No functional changes.
1197
bd05ac5f
CZ		 11982016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1199
b99747ae
CZ		 1200 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1201 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1202 (RTT): Remove duplicate.
1203 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1204 (PCT_CONFIG*): Remove.
1205 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1206
9885948f
CZ		 12072016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1208
b99747ae 1209 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1210
f2dd8838
CZ		 12112016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1212
b99747ae
CZ		 1213 * arc-tbl.h (invld07): Remove.
1214 * arc-ext-tbl.h: New file.
1215 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1216 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1217
0d2f91fe
JK		 12182016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1219
1220 Fix -Wstack-usage warnings.
1221 * aarch64-dis.c (print_operands): Substitute size.
1222 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1223
a6b71f42
JM		 12242016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1225
1226 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1227 to get a proper diagnostic when an invalid ASR register is used.
1228
9780e045
NC		 12292016-03-22 Nick Clifton <nickc@redhat.com>
1230
1231 * configure: Regenerate.
1232
e23e8ebe
AB		 12332016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1234
1235 * arc-nps400-tbl.h: New file.
1236 * arc-opc.c: Add top level comment.
1237 (insert_nps_3bit_dst): New function.
1238 (extract_nps_3bit_dst): New function.
1239 (insert_nps_3bit_src2): New function.
1240 (extract_nps_3bit_src2): New function.
1241 (insert_nps_bitop_size): New function.
1242 (extract_nps_bitop_size): New function.
1243 (arc_flag_operands): Add nps400 entries.
1244 (arc_flag_classes): Add nps400 entries.
1245 (arc_operands): Add nps400 entries.
1246 (arc_opcodes): Add nps400 include.
1247
1ae8ab47
AB		 12482016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1249
1250 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1251 the new class enum values.
1252
8699fc3e
AB		 12532016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1254
1255 * arc-dis.c (print_insn_arc): Handle nps400.
1256
24740d83
AB		 12572016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1258
1259 * arc-opc.c (BASE): Delete.
1260
8678914f
NC		 12612016-03-18 Nick Clifton <nickc@redhat.com>
1262
1263 PR target/19721
1264 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1265 of MOV insn that aliases an ORR insn.
1266
cc933301
JW		 12672016-03-16 Jiong Wang <jiong.wang@arm.com>
1268
1269 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1270
f86f5863
TS		 12712016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1272
1273 * mcore-opc.h: Add const qualifiers.
1274 * microblaze-opc.h (struct op_code_struct): Likewise.
1275 * sh-opc.h: Likewise.
1276 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1277 (tic4x_print_op): Likewise.
1278
62de1c63
AM		 12792016-03-02 Alan Modra <amodra@gmail.com>
1280
d11698cd 1281 * or1k-desc.h: Regenerate.
62de1c63 1282 * fr30-ibld.c: Regenerate.
c697cf0b 1283 * rl78-decode.c: Regenerate.
62de1c63 1284
020efce5
NC		 12852016-03-01 Nick Clifton <nickc@redhat.com>
1286
1287 PR target/19747
1288 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1289
b0c11777
RL		 12902016-02-24 Renlin Li <renlin.li@arm.com>
1291
1292 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1293 (print_insn_coprocessor): Support fp16 instructions.
1294
3e309328
RL		 12952016-02-24 Renlin Li <renlin.li@arm.com>
1296
1297 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1298 vminnm, vrint(mpna).
1299
8afc7bea
RL		 13002016-02-24 Renlin Li <renlin.li@arm.com>
1301
1302 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1303 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1304
4fd7268a
L		 13052016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1306
1307 * i386-dis.c (print_insn): Parenthesize expression to prevent
1308 truncated addresses.
1309 (OP_J): Likewise.
1310
4670103e
CZ		 13112016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1312 Janek van Oirschot <jvanoirs@synopsys.com>
1313
b99747ae
CZ		 1314 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1315 variable.
4670103e 1316
c1d9289f
NC		 13172016-02-04 Nick Clifton <nickc@redhat.com>
1318
1319 PR target/19561
1320 * msp430-dis.c (print_insn_msp430): Add a special case for
1321 decoding an RRC instruction with the ZC bit set in the extension
1322 word.
1323
a143b004
AB		 13242016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1325
1326 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1327 * epiphany-ibld.c: Regenerate.
1328 * fr30-ibld.c: Regenerate.
1329 * frv-ibld.c: Regenerate.
1330 * ip2k-ibld.c: Regenerate.
1331 * iq2000-ibld.c: Regenerate.
1332 * lm32-ibld.c: Regenerate.
1333 * m32c-ibld.c: Regenerate.
1334 * m32r-ibld.c: Regenerate.
1335 * mep-ibld.c: Regenerate.
1336 * mt-ibld.c: Regenerate.
1337 * or1k-ibld.c: Regenerate.
1338 * xc16x-ibld.c: Regenerate.
1339 * xstormy16-ibld.c: Regenerate.
1340
b89807c6
AB		 13412016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1342
1343 * epiphany-dis.c: Regenerated from latest cpu files.
1344
d8c823c8
MM		 13452016-02-01 Michael McConville <mmcco@mykolab.com>
1346
1347 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1348 test bit.
1349
5bc5ae88
RL		 13502016-01-25 Renlin Li <renlin.li@arm.com>
1351
1352 * arm-dis.c (mapping_symbol_for_insn): New function.
1353 (find_ifthen_state): Call mapping_symbol_for_insn().
1354
0bff6e2d
MW		 13552016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1356
1357 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1358 of MSR UAO immediate operand.
1359
100b4f2e
MR		 13602016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1361
1362 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1363 instruction support.
1364
5c14705f
AM		 13652016-01-17 Alan Modra <amodra@gmail.com>
1366
1367 * configure: Regenerate.
1368
4d82fe66
NC		 13692016-01-14 Nick Clifton <nickc@redhat.com>
1370
1371 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1372 instructions that can support stack pointer operations.
1373 * rl78-decode.c: Regenerate.
1374 * rl78-dis.c: Fix display of stack pointer in MOVW based
1375 instructions.
1376
651657fa
MW		 13772016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1378
1379 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1380 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1381 erxtatus_el1 and erxaddr_el1.
1382
105bde57
MW		 13832016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1384
1385 * arm-dis.c (arm_opcodes): Add "esb".
1386 (thumb_opcodes): Likewise.
1387
afa8d405
PB		 13882016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1389
1390 * ppc-opc.c <xscmpnedp>: Delete.
1391 <xvcmpnedp>: Likewise.
1392 <xvcmpnedp.>: Likewise.
1393 <xvcmpnesp>: Likewise.
1394 <xvcmpnesp.>: Likewise.
1395
83c3256e
AS		 13962016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1397
1398 PR gas/13050
1399 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1400 addition to ISA_A.
1401
6f2750fe
AM		 14022016-01-01 Alan Modra <amodra@gmail.com>
1403
1404 Update year range in copyright notice of all files.
1405
3499769a
AM		 1406For older changes see ChangeLog-2015
1407\f
1408Copyright (C) 2016 Free Software Foundation, Inc.
1409
1410Copying and distribution of this file, with or without modification,
1411are permitted in any medium without royalty provided the copyright
1412notice and this notice are preserved.
1413
1414Local Variables:
1415mode: change-log
1416left-margin: 8
1417fill-column: 74
1418version-control: never
1419End:
GDB Binutils - Deliverables
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