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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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4b8e28c7
MF		 12018-06-04 Max Filippov <jcmvbkbc@gmail.com>
2
3 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
4 (dis_private): Add new fields for property section tracking.
5 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
6 (xtensa_instruction_fits): New functions.
7 (fetch_data): Bump minimal fetch size to 4.
8 (print_insn_xtensa): Make struct dis_private static.
9 Load and prepare property table on section change.
10 Don't disassemble literals. Don't disassemble instructions that
11 cross property table boundaries.
12
55e99962
L		 132018-06-01 H.J. Lu <hongjiu.lu@intel.com>
14
15 * configure: Regenerated.
16
733bd0ab
JB		 172018-06-01 Jan Beulich <jbeulich@suse.com>
18
19 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
20 * i386-tbl.h: Re-generate.
21
dfd27d41
JB		 222018-06-01 Jan Beulich <jbeulich@suse.com>
23
24 * i386-opc.tbl (sldt, str): Add NoRex64.
25 * i386-tbl.h: Re-generate.
26
64795710
JB		 272018-06-01 Jan Beulich <jbeulich@suse.com>
28
29 * i386-opc.tbl (invpcid): Add Oword.
30 * i386-tbl.h: Re-generate.
31
030157d8
AM		 322018-06-01 Alan Modra <amodra@gmail.com>
33
34 * sysdep.h (_bfd_error_handler): Don't declare.
35 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
36 * rl78-decode.opc: Likewise.
37 * msp430-decode.c: Regenerate.
38 * rl78-decode.c: Regenerate.
39
a9660a6f
AP		 402018-05-30 Amit Pawar <Amit.Pawar@amd.com>
41
42 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
43 * i386-init.h : Regenerated.
44
277eb7f6
AM		 452018-05-25 Alan Modra <amodra@gmail.com>
46
47 * Makefile.in: Regenerate.
48 * po/POTFILES.in: Regenerate.
49
98553ad3
PB		 502018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
51
52 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
53 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
54 (insert_bab, extract_bab, insert_btab, extract_btab,
55 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
56 (BAT, BBA VBA RBS XB6S): Delete macros.
57 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
58 (BB, BD, RBX, XC6): Update for new macros.
59 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
60 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
61 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
62 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
63
7b4ae824
JD		 642018-05-18 John Darrington <john@darrington.wattle.id.au>
65
66 * Makefile.am: Add support for s12z architecture.
67 * configure.ac: Likewise.
68 * disassemble.c: Likewise.
69 * disassemble.h: Likewise.
70 * Makefile.in: Regenerate.
71 * configure: Regenerate.
72 * s12z-dis.c: New file.
73 * s12z.h: New file.
74
29e0f0a1
AM		 752018-05-18 Alan Modra <amodra@gmail.com>
76
77 * nfp-dis.c: Don't #include libbfd.h.
78 (init_nfp3200_priv): Use bfd_get_section_contents.
79 (nit_nfp6000_mecsr_sec): Likewise.
80
809276d2
NC		 812018-05-17 Nick Clifton <nickc@redhat.com>
82
83 * po/zh_CN.po: Updated simplified Chinese translation.
84
ff329288
TC		 852018-05-16 Tamar Christina <tamar.christina@arm.com>
86
87 PR binutils/23109
88 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
89 * aarch64-dis-2.c: Regenerate.
90
f9830ec1
TC		 912018-05-15 Tamar Christina <tamar.christina@arm.com>
92
93 PR binutils/21446
94 * aarch64-asm.c (opintl.h): Include.
95 (aarch64_ins_sysreg): Enforce read/write constraints.
96 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
97 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
98 (F_REG_READ, F_REG_WRITE): New.
99 * aarch64-opc.c (aarch64_print_operand): Generate notes for
100 AARCH64_OPND_SYSREG.
101 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
102 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
103 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
104 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
105 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
106 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
107 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
108 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
109 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
110 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
111 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
112 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
113 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
114 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
115 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
116 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
117 msr (F_SYS_WRITE), mrs (F_SYS_READ).
118
7d02540a
TC		 1192018-05-15 Tamar Christina <tamar.christina@arm.com>
120
121 PR binutils/21446
122 * aarch64-dis.c (no_notes: New.
123 (parse_aarch64_dis_option): Support notes.
124 (aarch64_decode_insn, print_operands): Likewise.
125 (print_aarch64_disassembler_options): Document notes.
126 * aarch64-opc.c (aarch64_print_operand): Support notes.
127
561a72d4
TC		 1282018-05-15 Tamar Christina <tamar.christina@arm.com>
129
130 PR binutils/21446
131 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
132 and take error struct.
133 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
134 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
135 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
136 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
137 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
138 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
139 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
140 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
141 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
142 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
143 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
144 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
145 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
146 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
147 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
148 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
149 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
150 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
151 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
152 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
153 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
154 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
155 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
156 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
157 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
158 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
159 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
160 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
161 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
162 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
163 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
164 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
165 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
166 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
167 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
168 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
169 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
170 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
171 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
172 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
173 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
174 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
175 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
176 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
177 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
178 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
179 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
180 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
181 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
182 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
183 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
184 (determine_disassembling_preference, aarch64_decode_insn,
185 print_insn_aarch64_word, print_insn_data): Take errors struct.
186 (print_insn_aarch64): Use errors.
187 * aarch64-asm-2.c: Regenerate.
188 * aarch64-dis-2.c: Regenerate.
189 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
190 boolean in aarch64_insert_operan.
191 (print_operand_extractor): Likewise.
192 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
193
1678bd35
FT		 1942018-05-15 Francois H. Theron <francois.theron@netronome.com>
195
196 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
197
06cfb1c8
L		 1982018-05-09 H.J. Lu <hongjiu.lu@intel.com>
199
200 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
201
84f9f8c3
AM		 2022018-05-09 Sebastian Rasmussen <sebras@gmail.com>
203
204 * cr16-opc.c (cr16_instruction): Comment typo fix.
205 * hppa-dis.c (print_insn_hppa): Likewise.
206
e6f372ba
JW		 2072018-05-08 Jim Wilson <jimw@sifive.com>
208
209 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
210 (match_c_slli64, match_srxi_as_c_srxi): New.
211 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
212 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
213 <c.slli, c.srli, c.srai>: Use match_s_slli.
214 <c.slli64, c.srli64, c.srai64>: New.
215
f413a913
AM		 2162018-05-08 Alan Modra <amodra@gmail.com>
217
218 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
219 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
220 partition opcode space for index lookup.
221
a87a6478
PB		 2222018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
223
224 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
225 <insn_length>: ...with this. Update usage.
226 Remove duplicate call to *info->memory_error_func.
227
c0a30a9f
L		 2282018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
229 H.J. Lu <hongjiu.lu@intel.com>
230
231 * i386-dis.c (Gva): New.
232 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
233 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
234 (prefix_table): New instructions (see prefix above).
235 (mod_table): New instructions (see prefix above).
236 (OP_G): Handle va_mode.
237 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
238 CPU_MOVDIR64B_FLAGS.
239 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
240 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
241 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
242 * i386-opc.tbl: Add movidir{i,64b}.
243 * i386-init.h: Regenerated.
244 * i386-tbl.h: Likewise.
245
75c0a438
L		 2462018-05-07 H.J. Lu <hongjiu.lu@intel.com>
247
248 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
249 AddrPrefixOpReg.
250 * i386-opc.h (AddrPrefixOp0): Renamed to ...
251 (AddrPrefixOpReg): This.
252 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
253 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
254
2ceb7719
PB		 2552018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
256
257 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
258 (vle_num_opcodes): Likewise.
259 (spe2_num_opcodes): Likewise.
260 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
261 initialization loop.
262 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
263 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
264 only once.
265
b3ac5c6c
TC		 2662018-05-01 Tamar Christina <tamar.christina@arm.com>
267
268 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
269
fe944acf
FT		 2702018-04-30 Francois H. Theron <francois.theron@netronome.com>
271
272 Makefile.am: Added nfp-dis.c.
273 configure.ac: Added bfd_nfp_arch.
274 disassemble.h: Added print_insn_nfp prototype.
275 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
276 nfp-dis.c: New, for NFP support.
277 po/POTFILES.in: Added nfp-dis.c to the list.
278 Makefile.in: Regenerate.
279 configure: Regenerate.
280
e2195274
JB		 2812018-04-26 Jan Beulich <jbeulich@suse.com>
282
283 * i386-opc.tbl: Fold various non-memory operand AVX512VL
284 templates into their base ones.
285 * i386-tlb.h: Re-generate.
286
59ef5df4
JB		 2872018-04-26 Jan Beulich <jbeulich@suse.com>
288
289 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
290 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
291 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
292 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
293 * i386-init.h: Re-generate.
294
6e041cf4
JB		 2952018-04-26 Jan Beulich <jbeulich@suse.com>
296
297 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
298 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
299 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
300 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
301 comment.
302 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
303 and CpuRegMask.
304 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
305 CpuRegMask: Delete.
306 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
307 cpuregzmm, and cpuregmask.
308 * i386-init.h: Re-generate.
309 * i386-tbl.h: Re-generate.
310
0e0eea78
JB		 3112018-04-26 Jan Beulich <jbeulich@suse.com>
312
313 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
314 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
315 * i386-init.h: Re-generate.
316
2f1bada2
JB		 3172018-04-26 Jan Beulich <jbeulich@suse.com>
318
319 * i386-gen.c (VexImmExt): Delete.
320 * i386-opc.h (VexImmExt, veximmext): Delete.
321 * i386-opc.tbl: Drop all VexImmExt uses.
322 * i386-tlb.h: Re-generate.
323
bacd1457
JB		 3242018-04-25 Jan Beulich <jbeulich@suse.com>
325
326 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
327 register-only forms.
328 * i386-tlb.h: Re-generate.
329
10bba94b
TC		 3302018-04-25 Tamar Christina <tamar.christina@arm.com>
331
332 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
333
c48935d7
IT		 3342018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
335
336 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
337 PREFIX_0F1C.
338 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
339 (cpu_flags): Add CpuCLDEMOTE.
340 * i386-init.h: Regenerate.
341 * i386-opc.h (enum): Add CpuCLDEMOTE,
342 (i386_cpu_flags): Add cpucldemote.
343 * i386-opc.tbl: Add cldemote.
344 * i386-tbl.h: Regenerate.
345
211dc24b
AM		 3462018-04-16 Alan Modra <amodra@gmail.com>
347
348 * Makefile.am: Remove sh5 and sh64 support.
349 * configure.ac: Likewise.
350 * disassemble.c: Likewise.
351 * disassemble.h: Likewise.
352 * sh-dis.c: Likewise.
353 * sh64-dis.c: Delete.
354 * sh64-opc.c: Delete.
355 * sh64-opc.h: Delete.
356 * Makefile.in: Regenerate.
357 * configure: Regenerate.
358 * po/POTFILES.in: Regenerate.
359
a9a4b302
AM		 3602018-04-16 Alan Modra <amodra@gmail.com>
361
362 * Makefile.am: Remove w65 support.
363 * configure.ac: Likewise.
364 * disassemble.c: Likewise.
365 * disassemble.h: Likewise.
366 * w65-dis.c: Delete.
367 * w65-opc.h: Delete.
368 * Makefile.in: Regenerate.
369 * configure: Regenerate.
370 * po/POTFILES.in: Regenerate.
371
04cb01fd
AM		 3722018-04-16 Alan Modra <amodra@gmail.com>
373
374 * configure.ac: Remove we32k support.
375 * configure: Regenerate.
376
c2bf1eec
AM		 3772018-04-16 Alan Modra <amodra@gmail.com>
378
379 * Makefile.am: Remove m88k support.
380 * configure.ac: Likewise.
381 * disassemble.c: Likewise.
382 * disassemble.h: Likewise.
383 * m88k-dis.c: Delete.
384 * Makefile.in: Regenerate.
385 * configure: Regenerate.
386 * po/POTFILES.in: Regenerate.
387
6793974d
AM		 3882018-04-16 Alan Modra <amodra@gmail.com>
389
390 * Makefile.am: Remove i370 support.
391 * configure.ac: Likewise.
392 * disassemble.c: Likewise.
393 * disassemble.h: Likewise.
394 * i370-dis.c: Delete.
395 * i370-opc.c: Delete.
396 * Makefile.in: Regenerate.
397 * configure: Regenerate.
398 * po/POTFILES.in: Regenerate.
399
e82aa794
AM		 4002018-04-16 Alan Modra <amodra@gmail.com>
401
402 * Makefile.am: Remove h8500 support.
403 * configure.ac: Likewise.
404 * disassemble.c: Likewise.
405 * disassemble.h: Likewise.
406 * h8500-dis.c: Delete.
407 * h8500-opc.h: Delete.
408 * Makefile.in: Regenerate.
409 * configure: Regenerate.
410 * po/POTFILES.in: Regenerate.
411
fceadf09
AM		 4122018-04-16 Alan Modra <amodra@gmail.com>
413
414 * configure.ac: Remove tahoe support.
415 * configure: Regenerate.
416
ae1d3843
L		 4172018-04-15 H.J. Lu <hongjiu.lu@intel.com>
418
419 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
420 umwait.
421 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
422 64-bit mode.
423 * i386-tbl.h: Regenerated.
424
de89d0a3
IT		 4252018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
426
427 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
428 PREFIX_MOD_1_0FAE_REG_6.
429 (va_mode): New.
430 (OP_E_register): Use va_mode.
431 * i386-dis-evex.h (prefix_table):
432 New instructions (see prefixes above).
433 * i386-gen.c (cpu_flag_init): Add WAITPKG.
434 (cpu_flags): Likewise.
435 * i386-opc.h (enum): Likewise.
436 (i386_cpu_flags): Likewise.
437 * i386-opc.tbl: Add umonitor, umwait, tpause.
438 * i386-init.h: Regenerate.
439 * i386-tbl.h: Likewise.
440
a8eb42a8
AM		 4412018-04-11 Alan Modra <amodra@gmail.com>
442
443 * opcodes/i860-dis.c: Delete.
444 * opcodes/i960-dis.c: Delete.
445 * Makefile.am: Remove i860 and i960 support.
446 * configure.ac: Likewise.
447 * disassemble.c: Likewise.
448 * disassemble.h: Likewise.
449 * Makefile.in: Regenerate.
450 * configure: Regenerate.
451 * po/POTFILES.in: Regenerate.
452
caf0678c
L		 4532018-04-04 H.J. Lu <hongjiu.lu@intel.com>
454
455 PR binutils/23025
456 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
457 to 0.
458 (print_insn): Clear vex instead of vex.evex.
459
4fb0d2b9
NC		 4602018-04-04 Nick Clifton <nickc@redhat.com>
461
462 * po/es.po: Updated Spanish translation.
463
c39e5b26
JB		 4642018-03-28 Jan Beulich <jbeulich@suse.com>
465
466 * i386-gen.c (opcode_modifiers): Delete VecESize.
467 * i386-opc.h (VecESize): Delete.
468 (struct i386_opcode_modifier): Delete vecesize.
469 * i386-opc.tbl: Drop VecESize.
470 * i386-tlb.h: Re-generate.
471
8e6e0792
JB		 4722018-03-28 Jan Beulich <jbeulich@suse.com>
473
474 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
475 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
476 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
477 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
478 * i386-tlb.h: Re-generate.
479
9f123b91
JB		 4802018-03-28 Jan Beulich <jbeulich@suse.com>
481
482 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
483 Fold AVX512 forms
484 * i386-tlb.h: Re-generate.
485
9646c87b
JB		 4862018-03-28 Jan Beulich <jbeulich@suse.com>
487
488 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
489 (vex_len_table): Drop Y for vcvt*2si.
490 (putop): Replace plain 'Y' handling by abort().
491
c8d59609
NC		 4922018-03-28 Nick Clifton <nickc@redhat.com>
493
494 PR 22988
495 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
496 instructions with only a base address register.
497 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
498 handle AARHC64_OPND_SVE_ADDR_R.
499 (aarch64_print_operand): Likewise.
500 * aarch64-asm-2.c: Regenerate.
501 * aarch64_dis-2.c: Regenerate.
502 * aarch64-opc-2.c: Regenerate.
503
b8c169f3
JB		 5042018-03-22 Jan Beulich <jbeulich@suse.com>
505
506 * i386-opc.tbl: Drop VecESize from register only insn forms and
507 memory forms not allowing broadcast.
508 * i386-tlb.h: Re-generate.
509
96bc132a
JB		 5102018-03-22 Jan Beulich <jbeulich@suse.com>
511
512 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
513 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
514 sha256*): Drop Disp<N>.
515
9f79e886
JB		 5162018-03-22 Jan Beulich <jbeulich@suse.com>
517
518 * i386-dis.c (EbndS, bnd_swap_mode): New.
519 (prefix_table): Use EbndS.
520 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
521 * i386-opc.tbl (bndmov): Move misplaced Load.
522 * i386-tlb.h: Re-generate.
523
d6793fa1
JB		 5242018-03-22 Jan Beulich <jbeulich@suse.com>
525
526 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
527 templates allowing memory operands and folded ones for register
528 only flavors.
529 * i386-tlb.h: Re-generate.
530
f7768225
JB		 5312018-03-22 Jan Beulich <jbeulich@suse.com>
532
533 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
534 256-bit templates. Drop redundant leftover Disp<N>.
535 * i386-tlb.h: Re-generate.
536
0e35537d
JW		 5372018-03-14 Kito Cheng <kito.cheng@gmail.com>
538
539 * riscv-opc.c (riscv_insn_types): New.
540
b4a3689a
NC		 5412018-03-13 Nick Clifton <nickc@redhat.com>
542
543 * po/pt_BR.po: Updated Brazilian Portuguese translation.
544
d3d50934
L		 5452018-03-08 H.J. Lu <hongjiu.lu@intel.com>
546
547 * i386-opc.tbl: Add Optimize to clr.
548 * i386-tbl.h: Regenerated.
549
bd5dea88
L		 5502018-03-08 H.J. Lu <hongjiu.lu@intel.com>
551
552 * i386-gen.c (opcode_modifiers): Remove OldGcc.
553 * i386-opc.h (OldGcc): Removed.
554 (i386_opcode_modifier): Remove oldgcc.
555 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
556 instructions for old (<= 2.8.1) versions of gcc.
557 * i386-tbl.h: Regenerated.
558
e771e7c9
JB		 5592018-03-08 Jan Beulich <jbeulich@suse.com>
560
561 * i386-opc.h (EVEXDYN): New.
562 * i386-opc.tbl: Fold various AVX512VL templates.
563 * i386-tlb.h: Re-generate.
564
ed438a93
JB		 5652018-03-08 Jan Beulich <jbeulich@suse.com>
566
567 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
568 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
569 vpexpandd, vpexpandq): Fold AFX512VF templates.
570 * i386-tlb.h: Re-generate.
571
454172a9
JB		 5722018-03-08 Jan Beulich <jbeulich@suse.com>
573
574 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
575 Fold 128- and 256-bit VEX-encoded templates.
576 * i386-tlb.h: Re-generate.
577
36824150
JB		 5782018-03-08 Jan Beulich <jbeulich@suse.com>
579
580 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
581 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
582 vpexpandd, vpexpandq): Fold AVX512F templates.
583 * i386-tlb.h: Re-generate.
584
e7f5c0a9
JB		 5852018-03-08 Jan Beulich <jbeulich@suse.com>
586
587 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
588 64-bit templates. Drop Disp<N>.
589 * i386-tlb.h: Re-generate.
590
25a4277f
JB		 5912018-03-08 Jan Beulich <jbeulich@suse.com>
592
593 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
594 and 256-bit templates.
595 * i386-tlb.h: Re-generate.
596
d2224064
JB		 5972018-03-08 Jan Beulich <jbeulich@suse.com>
598
599 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
600 * i386-tlb.h: Re-generate.
601
1b193f0b
JB		 6022018-03-08 Jan Beulich <jbeulich@suse.com>
603
604 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
605 Drop NoAVX.
606 * i386-tlb.h: Re-generate.
607
f2f6a710
JB		 6082018-03-08 Jan Beulich <jbeulich@suse.com>
609
610 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
611 * i386-tlb.h: Re-generate.
612
38e314eb
JB		 6132018-03-08 Jan Beulich <jbeulich@suse.com>
614
615 * i386-gen.c (opcode_modifiers): Delete FloatD.
616 * i386-opc.h (FloatD): Delete.
617 (struct i386_opcode_modifier): Delete floatd.
618 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
619 FloatD by D.
620 * i386-tlb.h: Re-generate.
621
d53e6b98
JB		 6222018-03-08 Jan Beulich <jbeulich@suse.com>
623
624 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
625
2907c2f5
JB		 6262018-03-08 Jan Beulich <jbeulich@suse.com>
627
628 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
629 * i386-tlb.h: Re-generate.
630
73053c1f
JB		 6312018-03-08 Jan Beulich <jbeulich@suse.com>
632
633 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
634 forms.
635 * i386-tlb.h: Re-generate.
636
52fe4420
AM		 6372018-03-07 Alan Modra <amodra@gmail.com>
638
639 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
640 bfd_arch_rs6000.
641 * disassemble.h (print_insn_rs6000): Delete.
642 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
643 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
644 (print_insn_rs6000): Delete.
645
a6743a54
AM		 6462018-03-03 Alan Modra <amodra@gmail.com>
647
648 * sysdep.h (opcodes_error_handler): Define.
649 (_bfd_error_handler): Declare.
650 * Makefile.am: Remove stray #.
651 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
652 EDIT" comment.
653 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
654 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
655 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
656 opcodes_error_handler to print errors. Standardize error messages.
657 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
658 and include opintl.h.
659 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
660 * i386-gen.c: Standardize error messages.
661 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
662 * Makefile.in: Regenerate.
663 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
664 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
665 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
666 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
667 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
668 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
669 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
670 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
671 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
672 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
673 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
674 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
675 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
676
8305403a
L		 6772018-03-01 H.J. Lu <hongjiu.lu@intel.com>
678
679 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
680 vpsub[bwdq] instructions.
681 * i386-tbl.h: Regenerated.
682
e184813f
AM		 6832018-03-01 Alan Modra <amodra@gmail.com>
684
685 * configure.ac (ALL_LINGUAS): Sort.
686 * configure: Regenerate.
687
5b616bef
TP		 6882018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
689
690 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
691 macro by assignements.
692
b6f8c7c4
L		 6932018-02-27 H.J. Lu <hongjiu.lu@intel.com>
694
695 PR gas/22871
696 * i386-gen.c (opcode_modifiers): Add Optimize.
697 * i386-opc.h (Optimize): New enum.
698 (i386_opcode_modifier): Add optimize.
699 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
700 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
701 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
702 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
703 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
704 vpxord and vpxorq.
705 * i386-tbl.h: Regenerated.
706
e95b887f
AM		 7072018-02-26 Alan Modra <amodra@gmail.com>
708
709 * crx-dis.c (getregliststring): Allocate a large enough buffer
710 to silence false positive gcc8 warning.
711
0bccfb29
JW		 7122018-02-22 Shea Levy <shea@shealevy.com>
713
714 * disassemble.c (ARCH_riscv): Define if ARCH_all.
715
6b6b6807
L		 7162018-02-22 H.J. Lu <hongjiu.lu@intel.com>
717
718 * i386-opc.tbl: Add {rex},
719 * i386-tbl.h: Regenerated.
720
75f31665
MR		 7212018-02-20 Maciej W. Rozycki <macro@mips.com>
722
723 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
724 (mips16_opcodes): Replace `M' with `m' for "restore".
725
e207bc53
TP		 7262018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
727
728 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
729
87993319
MR		 7302018-02-13 Maciej W. Rozycki <macro@mips.com>
731
732 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
733 variable to `function_index'.
734
68d20676
NC		 7352018-02-13 Nick Clifton <nickc@redhat.com>
736
737 PR 22823
738 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
739 about truncation of printing.
740
d2159fdc
HW		 7412018-02-12 Henry Wong <henry@stuffedcow.net>
742
743 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
744
f174ef9f
NC		 7452018-02-05 Nick Clifton <nickc@redhat.com>
746
747 * po/pt_BR.po: Updated Brazilian Portuguese translation.
748
be3a8dca
IT		 7492018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
750
751 * i386-dis.c (enum): Add pconfig.
752 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
753 (cpu_flags): Add CpuPCONFIG.
754 * i386-opc.h (enum): Add CpuPCONFIG.
755 (i386_cpu_flags): Add cpupconfig.
756 * i386-opc.tbl: Add PCONFIG instruction.
757 * i386-init.h: Regenerate.
758 * i386-tbl.h: Likewise.
759
3233d7d0
IT		 7602018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
761
762 * i386-dis.c (enum): Add PREFIX_0F09.
763 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
764 (cpu_flags): Add CpuWBNOINVD.
765 * i386-opc.h (enum): Add CpuWBNOINVD.
766 (i386_cpu_flags): Add cpuwbnoinvd.
767 * i386-opc.tbl: Add WBNOINVD instruction.
768 * i386-init.h: Regenerate.
769 * i386-tbl.h: Likewise.
770
e925c834
JW		 7712018-01-17 Jim Wilson <jimw@sifive.com>
772
773 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
774
d777820b
IT		 7752018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
776
777 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
778 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
779 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
780 (cpu_flags): Add CpuIBT, CpuSHSTK.
781 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
782 (i386_cpu_flags): Add cpuibt, cpushstk.
783 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
784 * i386-init.h: Regenerate.
785 * i386-tbl.h: Likewise.
786
f6efed01
NC		 7872018-01-16 Nick Clifton <nickc@redhat.com>
788
789 * po/pt_BR.po: Updated Brazilian Portugese translation.
790 * po/de.po: Updated German translation.
791
2721d702
JW		 7922018-01-15 Jim Wilson <jimw@sifive.com>
793
794 * riscv-opc.c (match_c_nop): New.
795 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
796
616dcb87
NC		 7972018-01-15 Nick Clifton <nickc@redhat.com>
798
799 * po/uk.po: Updated Ukranian translation.
800
3957a496
NC		 8012018-01-13 Nick Clifton <nickc@redhat.com>
802
803 * po/opcodes.pot: Regenerated.
804
769c7ea5
NC		 8052018-01-13 Nick Clifton <nickc@redhat.com>
806
807 * configure: Regenerate.
808
faf766e3
NC		 8092018-01-13 Nick Clifton <nickc@redhat.com>
810
811 2.30 branch created.
812
888a89da
IT		 8132018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
814
815 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
816 * i386-tbl.h: Regenerate.
817
cbda583a
JB		 8182018-01-10 Jan Beulich <jbeulich@suse.com>
819
820 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
821 * i386-tbl.h: Re-generate.
822
c9e92278
JB		 8232018-01-10 Jan Beulich <jbeulich@suse.com>
824
825 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
826 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
827 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
828 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
829 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
830 Disp8MemShift of AVX512VL forms.
831 * i386-tbl.h: Re-generate.
832
35fd2b2b
JW		 8332018-01-09 Jim Wilson <jimw@sifive.com>
834
835 * riscv-dis.c (maybe_print_address): If base_reg is zero,
836 then the hi_addr value is zero.
837
91d8b670
JG		 8382018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
839
840 * arm-dis.c (arm_opcodes): Add csdb.
841 (thumb32_opcodes): Add csdb.
842
be2e7d95
JG		 8432018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
844
845 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
846 * aarch64-asm-2.c: Regenerate.
847 * aarch64-dis-2.c: Regenerate.
848 * aarch64-opc-2.c: Regenerate.
849
704a705d
L		 8502018-01-08 H.J. Lu <hongjiu.lu@intel.com>
851
852 PR gas/22681
853 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
854 Remove AVX512 vmovd with 64-bit operands.
855 * i386-tbl.h: Regenerated.
856
35eeb78f
JW		 8572018-01-05 Jim Wilson <jimw@sifive.com>
858
859 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
860 jalr.
861
219d1afa
AM		 8622018-01-03 Alan Modra <amodra@gmail.com>
863
864 Update year range in copyright notice of all files.
865
1508bbf5
JB		 8662018-01-02 Jan Beulich <jbeulich@suse.com>
867
868 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
869 and OPERAND_TYPE_REGZMM entries.
870
1e563868 871For older changes see ChangeLog-2017
3499769a 872\f
1e563868 873Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 874
875Copying and distribution of this file, with or without modification,
876are permitted in any medium without royalty provided the copyright
877notice and this notice are preserved.
878
879Local Variables:
880mode: change-log
881left-margin: 8
882fill-column: 74
883version-control: never
884End:
GDB Binutils - Deliverables
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