[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2006-05-04  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
	    David Ung  <davidu@mips.com>

	* mips-dis.c (mips_arch_choices): Add smartmips instruction
	decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
	2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
	MIPS64R2.
	* mips-opc.c: fix random typos in comments.
	(INSN_SMARTMIPS): New defines.
	(mips_builtin_opcodes): Add paired single support for MIPS32R2.
	Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
	flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
	FP_S and FP_D flags to denote single and double register
	accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
	Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
	for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
	variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
	release 2 ISAs.
	* mips16-opc.c (mips16_opcodes): Add sdbbp instruction.

2006-05-03  Thiemo Seufer  <ths@mips.com>

	* mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.

2006-05-02  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
            David Ung  <davidu@mips.com>

	* mips-dis.c (print_insn_args): Force mips16 to odd addresses.
	(print_mips16_insn_arg): Force mips16 to odd addresses.

2006-04-30  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>

	* mips-opc.c (mips_builtin_opcodes): Add udi instructions
	"udi0" to "udi15".
	* mips-dis.c (print_insn_args): Adds udi argument handling.

2006-04-28  James E Wilson  <wilson@specifix.com>

	* m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
	error message.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>
	    Nigel Stephens  <nigel@mips.com>

	* mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
	names.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
            David Ung  <davidu@mips.com>

	* mips-dis.c (print_insn_args): Add mips_opcode argument.
	(print_insn_mips):  Adjust print_insn_args call.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>

	* mips-dis.c (print_insn_args): Print $fcc only for FP
	instructions, use $cc elsewise.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>

	* opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
	Map MIPS16 registers to O32 names.
	(print_mips16_insn_arg): Use mips16_reg_names.

2006-04-26  Julian Brown  <julian@codesourcery.com>

	* arm-dis.c (print_insn_neon): Disassemble floating-point constant
	VMOV.

2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>

	* opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
	%<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
	Add unified load/store instruction names.
	(neon_opcode_table): New.
	(arm_opcodes): Expand meaning of %<bitfield>['`?].
	(arm_decode_bitfield): New.
	(print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
	Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
	(print_insn_neon): New.
	(print_insn_arm): Adjust print_insn_coprocessor call. Call
	print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
	(print_insn_thumb32): Likewise.

2006-04-19  Alan Modra  <amodra@bigpond.net.au>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.

2006-04-19  Alan Modra  <amodra@bigpond.net.au>

	* avr-dis.c (avr_operand): Warning fix.

	* configure: Regenerate.

2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>

	* po/POTFILES.in: Regenerated.

2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>

	PR binutils/2454
	* avr-dis.c (avr_operand): Arrange for a comment to appear before
	the symolic form of an address, so that the output of objdump -d
	can be reassembled.

2006-04-10  DJ Delorie  <dj@redhat.com>

	* m32c-asm.c: Regenerate.

2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>

	* Makefile.am: Add install-html target.
	* Makefile.in: Regenerate.

2006-04-06  Nick Clifton  <nickc@redhat.com>

	* po/vi/po: Updated Vietnamese translation.

2006-03-31  Paul Koning  <ni1d@arrl.net>

	* pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.

2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>

	* bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
	logic to identify halfword shifts.

2006-03-16  Paul Brook  <paul@codesourcery.com>

	* arm-dis.c (arm_opcodes): Rename swi to svc.
	(thumb_opcodes): Ditto.

2006-03-13  DJ Delorie  <dj@redhat.com>

	* m32c-asm.c: Regenerate.
	* m32c-desc.c: Likewise.
	* m32c-desc.h: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-ibld.c: Likewise.
	* m32c-opc.c: Likewise.
	* m32c-opc.h: Likewise.

2006-03-10  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate with mul.l, mulu.l.
	* m32c-opc.c: Likewise.
	* m32c-opc.h: Likewise.


2006-03-09  Nick Clifton  <nickc@redhat.com>

	* po/sv.po: Updated Swedish translation.

2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/2428
	* i386-dis.c (REP_Fixup): New function.
	(AL): Remove duplicate.
	(Xbr): New.
	(Xvr): Likewise.
	(Ybr): Likewise.
	(Yvr): Likewise.
	(indirDXr): Likewise.
	(ALr): Likewise.
	(eAXr): Likewise.
	(dis386): Updated entries of ins, outs, movs, lods and stos.

2006-03-05  Nick Clifton  <nickc@redhat.com>

	* cgen-ibld.in (insert_normal): Cope with attempts to insert a
	signed 32-bit value into an unsigned 32-bit field when the host is
	a 64-bit machine.
	* fr30-ibld.c: Regenerate.
	* frv-ibld.c: Regenerate.
	* ip2k-ibld.c: Regenerate.
	* iq2000-asm.c: Regenerate.
	* iq2000-ibld.c: Regenerate.
	* m32c-ibld.c: Regenerate.
	* m32r-ibld.c: Regenerate.
	* openrisc-ibld.c: Regenerate.
	* xc16x-ibld.c: Regenerate.
	* xstormy16-ibld.c: Regenerate.

2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)

	* xc16x-asm.c: Regenerate.
	* xc16x-dis.c: Regenerate.

2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>

	* po/Make-in: Add html target.

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
	Intel Merom New Instructions.
	(THREE_BYTE_0): Likewise.
	(THREE_BYTE_1): Likewise.
	(three_byte_table): Likewise.
	(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
	THREE_BYTE_1 for entry 0x3a.
	(twobyte_has_modrm): Updated.
	(twobyte_uses_SSE_prefix): Likewise.
	(print_insn): Handle 3-byte opcodes used by Intel Merom New
	Instructions.

2006-02-24  David S. Miller  <davem@sunset.davemloft.net>

	* sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
	(v9_hpriv_reg_names): New table.
	(print_insn_sparc): Allow values up to 16 for '?' and '!'.
	New cases '$' and '%' for read/write hyperprivileged register.
	* sparc-opc.c (sparc_opcodes): Add new entries for UA2005
	window handling and rdhpr/wrhpr instructions.
	
2006-02-24  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate with linker relaxation attributes.
	* m32c-desc.h: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-opc.c: Likewise.

2006-02-24  Paul Brook  <paul@codesourcery.com>

	* arm-dis.c (arm_opcodes): Add V7 instructions.
	(thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
	(print_arm_address): New function.
	(print_insn_arm): Use it.  Add 'P' and 'U' cases.
	(psr_name): New function.
	(print_insn_thumb32): Add 'U', 'C' and 'D' cases.

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-opc-i.c (bXc): New.
	(mXc): Likewise.
	(OpX2TaTbYaXcC): Likewise.
	(TF). Likewise.
	(TFCM). Likewise.
	(ia64_opcodes_i): Add instructions for tf.

	* ia64-opc.h (IMMU5b): New.

	* ia64-asmtab.c: Regenerated.

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-gen.c: Update copyright years.
	* ia64-opc-b.c: Likewise.

2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-gen.c (lookup_regindex): Handle ".vm".
	(print_dependency_table): Handle '\"'.

	* ia64-ic.tbl: Updated from SDM 2.2.
	* ia64-raw.tbl: Likewise.
	* ia64-waw.tbl: Likewise.
	* ia64-asmtab.c: Regenerated.

	* ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.

2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
            Anil Paranjape   <anilp1@kpitcummins.com>
            Shilin Shakti    <shilins@kpitcummins.com>

	* xc16x-desc.h: New file
	* xc16x-desc.c: New file
	* xc16x-opc.h: New file	
	* xc16x-opc.c: New file
	* xc16x-ibld.c: New file
	* xc16x-asm.c: New file
	* xc16x-dis.c: New file
	* Makefile.am: Entries for xc16x 
	* Makefile.in: Regenerate 
	* cofigure.in: Add xc16x target information.
	* configure: Regenerate.
	* disassemble.c: Add xc16x target information.

2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (dis386_twobyte): Use "movZ" for debug register
	moves.

2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c ('Z'): Add a new macro.
	(dis386_twobyte): Use "movZ" for control register moves.

2006-02-10  Nick Clifton  <nickc@redhat.com>

	* iq2000-asm.c: Regenerate.

2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>

	* m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.

2006-01-26  David Ung  <davidu@mips.com>

	* mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
	ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
	floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
	nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
	rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.

2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>

	* z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
	ld_d_r, pref_xd_cb): Use signed char to hold data to be
	disassembled.	
	* z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
	buffer overflows when disassembling instructions like
	ld (ix+123),0x23
	* z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
	operand, if the offset is negative.

2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>

	* z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
	unsigned char to hold data to be disassembled.

2006-01-17  Andreas Schwab  <schwab@suse.de>

	PR binutils/1486
	* disassemble.c (disassemble_init_for_target): Set
	disassembler_needs_relocs for bfd_arch_arm.

2006-01-16  Paul Brook  <paul@codesourcery.com>

	* m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
	f?add?, and f?sub? instructions.

2006-01-16  Nick Clifton  <nickc@redhat.com>

	* po/zh_CN.po: New Chinese (simplified) translation.
	* configure.in (ALL_LINGUAS): Add "zh_CH".
	* configure: Regenerate.

2006-01-05  Paul Brook  <paul@codesourcery.com>

	* m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.

2006-01-06  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate.
	* m32c-opc.c: Regenerate.
	* m32c-opc.h: Regenerate.

2006-01-03  DJ Delorie  <dj@redhat.com>

	* cgen-ibld.in (extract_normal): Avoid memory range errors.
	* m32c-ibld.c: Regenerated.

For older changes see ChangeLog-2005
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
39a7806d TS	1	2006-05-04 Thiemo Seufer <ths@mips.com>
	2	Nigel Stephens <nigel@mips.com>
	3	David Ung <davidu@mips.com>
	4
	5	* mips-dis.c (mips_arch_choices): Add smartmips instruction
	6	decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
	7	2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
	8	MIPS64R2.
	9	* mips-opc.c: fix random typos in comments.
	10	(INSN_SMARTMIPS): New defines.
	11	(mips_builtin_opcodes): Add paired single support for MIPS32R2.
	12	Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
	13	flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
	14	FP_S and FP_D flags to denote single and double register
	15	accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
	16	Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
	17	for MIPS32R2. Add SmartMIPS instructions. Add two-argument
	18	variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
	19	release 2 ISAs.
	20	* mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
	21
104b4fab TS	22	2006-05-03 Thiemo Seufer <ths@mips.com>
	23
	24	* mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
	25
022fac6d TS	26	2006-05-02 Thiemo Seufer <ths@mips.com>
	27	Nigel Stephens <nigel@mips.com>
	28	David Ung <davidu@mips.com>
	29
	30	* mips-dis.c (print_insn_args): Force mips16 to odd addresses.
	31	(print_mips16_insn_arg): Force mips16 to odd addresses.
	32
9bcd4f99 TS	33	2006-04-30 Thiemo Seufer <ths@mips.com>
	34	David Ung <davidu@mips.com>
	35
	36	* mips-opc.c (mips_builtin_opcodes): Add udi instructions
	37	"udi0" to "udi15".
	38	* mips-dis.c (print_insn_args): Adds udi argument handling.
	39
f095b97b JW	40	2006-04-28 James E Wilson <wilson@specifix.com>
	41
	42	* m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
	43	error message.
	44
59c455b3 TS	45	2006-04-28 Thiemo Seufer <ths@mips.com>
59c455b3 TS	46	David Ung <davidu@mips.com>
bdb09db1	47	Nigel Stephens <nigel@mips.com>
59c455b3 TS	48
	49	* mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
	50	names.
	51
cc0ca239	52	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	53	Nigel Stephens <nigel@mips.com>
cc0ca239 TS	54	David Ung <davidu@mips.com>
	55
	56	* mips-dis.c (print_insn_args): Add mips_opcode argument.
	57	(print_insn_mips): Adjust print_insn_args call.
	58
0d09bfe6	59	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	60	Nigel Stephens <nigel@mips.com>
0d09bfe6 TS	61
	62	* mips-dis.c (print_insn_args): Print $fcc only for FP
	63	instructions, use $cc elsewise.
	64
654c225a	65	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	66	Nigel Stephens <nigel@mips.com>
654c225a TS	67
	68	* opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
	69	Map MIPS16 registers to O32 names.
	70	(print_mips16_insn_arg): Use mips16_reg_names.
	71
0dbde4cf JB	72	2006-04-26 Julian Brown <julian@codesourcery.com>
	73
	74	* arm-dis.c (print_insn_neon): Disassemble floating-point constant
	75	VMOV.
	76
16980d0b JB	77	2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
	78	Julian Brown <julian@codesourcery.com>
	79
	80	* opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
	81	%<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
	82	Add unified load/store instruction names.
	83	(neon_opcode_table): New.
	84	(arm_opcodes): Expand meaning of %<bitfield>['`?].
	85	(arm_decode_bitfield): New.
	86	(print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
	87	Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
	88	(print_insn_neon): New.
	89	(print_insn_arm): Adjust print_insn_coprocessor call. Call
	90	print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
	91	(print_insn_thumb32): Likewise.
	92
ec3fcc56 AM	93	2006-04-19 Alan Modra <amodra@bigpond.net.au>
	94
	95	* Makefile.am: Run "make dep-am".
	96	* Makefile.in: Regenerate.
	97
241a6c40 AM	98	2006-04-19 Alan Modra <amodra@bigpond.net.au>
241a6c40 AM	99
7c6646cd AM	100	* avr-dis.c (avr_operand): Warning fix.
7c6646cd AM	101
241a6c40 AM	102	* configure: Regenerate.
241a6c40 AM	103
e7403566 DJ	104	2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
	105
	106	* po/POTFILES.in: Regenerated.
	107
52f16a0e NC	108	2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
	109
	110	PR binutils/2454
	111	* avr-dis.c (avr_operand): Arrange for a comment to appear before
	112	the symolic form of an address, so that the output of objdump -d
	113	can be reassembled.
	114
e78efa90 DD	115	2006-04-10 DJ Delorie <dj@redhat.com>
	116
	117	* m32c-asm.c: Regenerate.
	118
108a6f8e CD	119	2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
	120
	121	* Makefile.am: Add install-html target.
	122	* Makefile.in: Regenerate.
	123
a135cb2c NC	124	2006-04-06 Nick Clifton <nickc@redhat.com>
	125
	126	* po/vi/po: Updated Vietnamese translation.
	127
47426b41 AM	128	2006-03-31 Paul Koning <ni1d@arrl.net>
	129
	130	* pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
	131
331f1cbe BS	132	2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
	133
	134	* bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
	135	logic to identify halfword shifts.
	136
c16d2bf0 PB	137	2006-03-16 Paul Brook <paul@codesourcery.com>
	138
	139	* arm-dis.c (arm_opcodes): Rename swi to svc.
	140	(thumb_opcodes): Ditto.
	141
5348b81e DD	142	2006-03-13 DJ Delorie <dj@redhat.com>
5348b81e DD	143
5398310a DD	144	* m32c-asm.c: Regenerate.
	145	* m32c-desc.c: Likewise.
	146	* m32c-desc.h: Likewise.
	147	* m32c-dis.c: Likewise.
	148	* m32c-ibld.c: Likewise.
5348b81e DD	149	* m32c-opc.c: Likewise.
	150	* m32c-opc.h: Likewise.
	151
253d272c DD	152	2006-03-10 DJ Delorie <dj@redhat.com>
	153
	154	* m32c-desc.c: Regenerate with mul.l, mulu.l.
	155	* m32c-opc.c: Likewise.
	156	* m32c-opc.h: Likewise.
	157
	158
f530741d NC	159	2006-03-09 Nick Clifton <nickc@redhat.com>
	160
	161	* po/sv.po: Updated Swedish translation.
	162
35c52694 L	163	2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
	164
	165	PR binutils/2428
	166	* i386-dis.c (REP_Fixup): New function.
	167	(AL): Remove duplicate.
	168	(Xbr): New.
	169	(Xvr): Likewise.
	170	(Ybr): Likewise.
	171	(Yvr): Likewise.
	172	(indirDXr): Likewise.
	173	(ALr): Likewise.
	174	(eAXr): Likewise.
	175	(dis386): Updated entries of ins, outs, movs, lods and stos.
	176
ed963e2d NC	177	2006-03-05 Nick Clifton <nickc@redhat.com>
	178
	179	* cgen-ibld.in (insert_normal): Cope with attempts to insert a
	180	signed 32-bit value into an unsigned 32-bit field when the host is
	181	a 64-bit machine.
	182	* fr30-ibld.c: Regenerate.
	183	* frv-ibld.c: Regenerate.
	184	* ip2k-ibld.c: Regenerate.
	185	* iq2000-asm.c: Regenerate.
	186	* iq2000-ibld.c: Regenerate.
	187	* m32c-ibld.c: Regenerate.
	188	* m32r-ibld.c: Regenerate.
	189	* openrisc-ibld.c: Regenerate.
	190	* xc16x-ibld.c: Regenerate.
	191	* xstormy16-ibld.c: Regenerate.
	192
c7d41dc5 NC	193	2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
	194
	195	* xc16x-asm.c: Regenerate.
	196	* xc16x-dis.c: Regenerate.
c7d41dc5	197
f7d9e5c3 CD	198	2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
	199
	200	* po/Make-in: Add html target.
	201
331d2d0d L	202	2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
	203
	204	* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
	205	Intel Merom New Instructions.
	206	(THREE_BYTE_0): Likewise.
	207	(THREE_BYTE_1): Likewise.
	208	(three_byte_table): Likewise.
	209	(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
	210	THREE_BYTE_1 for entry 0x3a.
	211	(twobyte_has_modrm): Updated.
	212	(twobyte_uses_SSE_prefix): Likewise.
	213	(print_insn): Handle 3-byte opcodes used by Intel Merom New
	214	Instructions.
	215
ff3f9d5b DM	216	2006-02-24 David S. Miller <davem@sunset.davemloft.net>
	217
	218	* sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
	219	(v9_hpriv_reg_names): New table.
	220	(print_insn_sparc): Allow values up to 16 for '?' and '!'.
	221	New cases '$' and '%' for read/write hyperprivileged register.
	222	* sparc-opc.c (sparc_opcodes): Add new entries for UA2005
	223	window handling and rdhpr/wrhpr instructions.
	224
6772dd07 DD	225	2006-02-24 DJ Delorie <dj@redhat.com>
	226
	227	* m32c-desc.c: Regenerate with linker relaxation attributes.
	228	* m32c-desc.h: Likewise.
	229	* m32c-dis.c: Likewise.
	230	* m32c-opc.c: Likewise.
	231
62b3e311 PB	232	2006-02-24 Paul Brook <paul@codesourcery.com>
	233
	234	* arm-dis.c (arm_opcodes): Add V7 instructions.
	235	(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
	236	(print_arm_address): New function.
	237	(print_insn_arm): Use it. Add 'P' and 'U' cases.
	238	(psr_name): New function.
	239	(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
	240
59cf82fe L	241	2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
	242
	243	* ia64-opc-i.c (bXc): New.
	244	(mXc): Likewise.
	245	(OpX2TaTbYaXcC): Likewise.
	246	(TF). Likewise.
	247	(TFCM). Likewise.
	248	(ia64_opcodes_i): Add instructions for tf.
	249
	250	* ia64-opc.h (IMMU5b): New.
	251
	252	* ia64-asmtab.c: Regenerated.
	253
19a7219f L	254	2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
	255
	256	* ia64-gen.c: Update copyright years.
	257	* ia64-opc-b.c: Likewise.
	258
7f3dfb9c L	259	2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
	260
	261	* ia64-gen.c (lookup_regindex): Handle ".vm".
	262	(print_dependency_table): Handle '\"'.
	263
	264	* ia64-ic.tbl: Updated from SDM 2.2.
	265	* ia64-raw.tbl: Likewise.
	266	* ia64-waw.tbl: Likewise.
	267	* ia64-asmtab.c: Regenerated.
	268
	269	* ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
	270
d70c5fc7 NC	271	2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
	272	Anil Paranjape <anilp1@kpitcummins.com>
	273	Shilin Shakti <shilins@kpitcummins.com>
	274
	275	* xc16x-desc.h: New file
	276	* xc16x-desc.c: New file
	277	* xc16x-opc.h: New file
	278	* xc16x-opc.c: New file
	279	* xc16x-ibld.c: New file
	280	* xc16x-asm.c: New file
	281	* xc16x-dis.c: New file
	282	* Makefile.am: Entries for xc16x
	283	* Makefile.in: Regenerate
	284	* cofigure.in: Add xc16x target information.
	285	* configure: Regenerate.
	286	* disassemble.c: Add xc16x target information.
	287
a1cfb73e L	288	2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
	289
	290	* i386-dis.c (dis386_twobyte): Use "movZ" for debug register
	291	moves.
	292
6dd5059a L	293	2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
	294
	295	* i386-dis.c ('Z'): Add a new macro.
	296	(dis386_twobyte): Use "movZ" for control register moves.
	297
8536c657 NC	298	2006-02-10 Nick Clifton <nickc@redhat.com>
	299
	300	* iq2000-asm.c: Regenerate.
	301
266abb8f NS	302	2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
	303
	304	* m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
	305
f1a64f49 DU	306	2006-01-26 David Ung <davidu@mips.com>
	307
	308	* mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
	309	ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
	310	floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
	311	nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
	312	rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
	313
9e919b5f AM	314	2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
	315
	316	* z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
	317	ld_d_r, pref_xd_cb): Use signed char to hold data to be
	318	disassembled.
	319	* z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
	320	buffer overflows when disassembling instructions like
	321	ld (ix+123),0x23
	322	* z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
	323	operand, if the offset is negative.
	324
c9021189 AM	325	2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
	326
	327	* z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
	328	unsigned char to hold data to be disassembled.
	329
d99b6465 AS	330	2006-01-17 Andreas Schwab <schwab@suse.de>
	331
	332	PR binutils/1486
	333	* disassemble.c (disassemble_init_for_target): Set
	334	disassembler_needs_relocs for bfd_arch_arm.
	335
c2fe9327 PB	336	2006-01-16 Paul Brook <paul@codesourcery.com>
c2fe9327 PB	337
e88d958a	338	* m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
c2fe9327 PB	339	f?add?, and f?sub? instructions.
c2fe9327 PB	340
32fba81d NC	341	2006-01-16 Nick Clifton <nickc@redhat.com>
	342
	343	* po/zh_CN.po: New Chinese (simplified) translation.
	344	* configure.in (ALL_LINGUAS): Add "zh_CH".
	345	* configure: Regenerate.
	346
1b3a26b5 PB	347	2006-01-05 Paul Brook <paul@codesourcery.com>
	348
	349	* m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
	350
db313fa6 DD	351	2006-01-06 DJ Delorie <dj@redhat.com>
	352
	353	* m32c-desc.c: Regenerate.
	354	* m32c-opc.c: Regenerate.
	355	* m32c-opc.h: Regenerate.
	356
54d46aca DD	357	2006-01-03 DJ Delorie <dj@redhat.com>
	358
	359	* cgen-ibld.in (extract_normal): Avoid memory range errors.
	360	* m32c-ibld.c: Regenerated.
	361
e88d958a	362	For older changes see ChangeLog-2005
252b5132 RH	363	\f
252b5132 RH	364	Local Variables:
2f6d2f85 NC	365	mode: change-log
	366	left-margin: 8
	367	fill-column: 74
252b5132 RH	368	version-control: never
252b5132 RH	369	End: