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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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abe9f67d
ME		 12012-11-21 David Holsgrove <david.holsgrove@xilinx.com>
2
3 * microblaze-opc.h (op_code_struct): Add swapb, swaph Increase MAX_OPCODES.
4 * microblaze-opcm.h (microblaze_instr): Likewise
5
0db4b326
ME		 62012-11-21 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7
8 * microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR
9 * microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK
10
9b30cccc
L		 112012-11-20 Kirill Yukhin <kirill.yukhin@intel.com>
12 H.J. Lu <hongjiu.lu@intel.com>
13
14 PR gas/14859
15 * i386-opc.tbl: Fix opcode for 64-bit jecxz.
16 * i386-tbl.h: Regenerated.
17
0b7fe784
AK		 182012-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
19
20 * s390-opc.txt: Fix srstu and strag opcodes.
21
d3da7741
ME		 222012-11-14 David Holsgrove <david.holsgrove@xilinx.com>
23
24 * microblaze-opc.h: Define new instruction type INST_TYPE_IMM5,
25 update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5,
26 and increase MAX_OPCODES.
27 (op_code_struct): add mbar and sleep
28 * microblaze-opcm.h (microblaze_instr): add mbar
29 Define IMM_MBAR and IMM5_MBAR_MASK
30 * microblaze-dis.c: Add get_field_imm5_mbar
31 (print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE
32
ed8ec0ec
ME		 332012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
34
35 * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add clz insn
36 * microblaze-opcm.h (microblaze_instr): add clz
37
e692c217
ME		 382012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
39
40 * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add lbur,
41 lhur, lwr, sbr, shr, swr
42 * microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr,
43 swr
44
de863c74
NC		 452012-11-09 Nick Clifton <nickc@redhat.com>
46
47 * configure.in: Add bfd_v850_rh850_arch.
48 * configure: Regenerate.
49 * disassemble.c (disassembler): Likewise.
50
5bb3703f
L		 512012-11-09 H.J. Lu <hongjiu.lu@intel.com>
52
53 * aarch64-opc.h (gen_mask): Remove trailing redundant `;'.
54 * ia64-gen.c (fetch_insn_class): Likewise.
55
6febeb74
AM		 562012-11-08 Alan Modra <amodra@gmail.com>
57
58 * po/POTFILES.in: Regenerate.
59
d17dce55
AM		 602012-11-05 Alan Modra <amodra@gmail.com>
61
62 * configure.in: Apply 2012-09-10 change to config.in here.
63
aac129d7
AK		 642012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
65
66 * s390-mkopc.c: Accept empty lines in s390-opc.txt.
d17dce55
AM		 67 * s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2
68 and RRF_RMRR.
aac129d7
AK		 69 * s390-opc.txt: Add new instructions. New instruction type for lptea.
70
747a4ac1
CG		 712012-10-26 Christian Groessler <chris@groessler.org>
72
73 * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb,
74 trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb). Remove
75 non-existing opcode trtrb.
76 * z8k-opc.h: Regenerate.
77
62082a42
AM		 782012-10-26 Alan Modra <amodra@gmail.com>
79
80 * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.
81
6c067bbb
RM		 822012-10-24 Roland McGrath <mcgrathr@google.com>
83
84 * i386-dis.c (ckprefix): When bailing out for fwait with prefixes,
85 set rex_used to rex.
86
ab4437c3
PB		 872012-10-22 Peter Bergner <bergner@vnet.ibm.com>
88
89 * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.
90
9a176a4a
TT		 912012-10-18 Tom Tromey <tromey@redhat.com>
92
93 * tic54x-dis.c (print_instruction): Don't use K&R style.
94 (print_parallel_instruction, sprint_dual_address)
95 (sprint_indirect_address, sprint_direct_address, sprint_mmr)
96 (sprint_cc2, sprint_condition): Likewise.
97
4ad3b7ef
KT		 982012-10-18 Kai Tietz <ktietz@redhat.com>
99
100 * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize
101 value with a default.
102 (do_special_encoding): Likewise.
103 (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
104 variables with default.
105 * arc-dis.c (write_comments_): Don't use strncat due
106 size of state->commentBuffer pointer isn't predictable.
107
b7a54b55
YZ		 1082012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
109
110 * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
111 rmr_el3; remove daifset and daifclr.
112
9b61754a
YZ		 1132012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
114
115 * aarch64-opc.c (operand_general_constraint_met_p): Change to check
116 the alignment of addr.offset.imm instead of that of shifter.amount for
117 operand type AARCH64_OPND_ADDR_UIMM12.
118
f8ece37f
RE		 1192012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
120
121 * arm-dis.c: Use preferred form of vrint instruction variants
122 for disassembly.
123
5e5c50d3
NE		 1242012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
125
126 * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
127 * i386-init.h: Regenerated.
128
c7a5aa9c
PB		 1292012-10-05 Peter Bergner <bergner@vnet.ibm.com>
130
131 * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
132 * ppc-opc.c (VBA): New define.
133 (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
134 mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.
135
04ee5257
NC		 1362012-10-04 Nick Clifton <nickc@redhat.com>
137
138 * v850-dis.c (disassemble): Place square parentheses around second
139 register operand of clr1, not1, set1 and tst1 instructions.
140
cfc72779
AK		 1412012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
142
143 * s390-mkopc.c: Support new option zEC12.
144 * s390-opc.c: Add new instruction formats.
145 * s390-opc.txt: Add new instructions for zEC12.
146
1415a2a7
AG		 1472012-09-27 Anthony Green <green@moxielogic.com>
148
149 * moxie-dis.c (print_insn_moxie): Print 'bad' instructions.
150 * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD.
151
160a30bb
L		 1522012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
153
04ee5257
NC		 154 * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
155 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
160a30bb
L		 156 and CPU_BTVER2_FLAGS.
157 * i386-init.h: Regenerated.
158
60aa667e
L		 1592012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
160
161 * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
162 CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
163 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
164 CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
165 (cpu_flags): Add CpuCX16.
166 * i386-opc.h (CpuCX16): New.
167 (i386_cpu_flags): Add cpucx16.
168 * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
169 * i386-tbl.h: Regenerate.
170 * i386-init.h: Likewise.
171
4b8c8c02
RE		 1722012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
173
60aa667e 174 * arm-dis.c: Changed ldra and strl-form mnemonics
4b8c8c02
RE		 175 to lda and stl-form.
176
83ea18d0
MR		 1772012-09-18 Chao-ying Fu <fu@mips.com>
178
179 * micromips-opc.c (micromips_opcodes): Correct the encoding of
180 the "swxc1" instruction.
181
062f38fa
RE		 1822012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
183
184 * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
185 the parameter 'inst'.
186 (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
187 (convert_mov_to_movewide): Change to assert (0) when
188 aarch64_wide_constant_p returns FALSE.
189
b132a67d
DE		 1902012-09-14 David Edelsohn <dje.gcc@gmail.com>
191
192 * configure: Regenerate.
193
1f9b75dd
AG		 1942012-09-14 Anthony Green <green@moxielogic.com>
195
196 * moxie-dis.c (print_insn_moxie): Branch targets are relative to
197 the address after the branch instruction.
198
e202fa84
AG		 1992012-09-13 Anthony Green <green@moxielogic.com>
200
201 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
202
00716ab1
AM		 2032012-09-10 Matthias Klose <doko@ubuntu.com>
204
205 * config.in: Disable sanity check for kfreebsd.
206
6d2920c8
L		 2072012-09-10 H.J. Lu <hongjiu.lu@intel.com>
208
209 * configure: Regenerated.
210
b3e14eda
L		 2112012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
212
213 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
214 * ia64-gen.c: Promote completer index type to longlong.
215 (irf_operand): Add new register recognition.
216 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
217 (lookup_specifier): Add new resource recognition.
218 (insert_bit_table_ent): Relax abort condition according to the
219 changed completer index type.
220 (print_dis_table): Fix printf format for completer index.
221 * ia64-ic.tbl: Add a new instruction class.
222 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
223 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
224 * ia64-opc.h: Define short names for new operand types.
225 * ia64-raw.tbl: Add new RAW resource for DAHR register.
226 * ia64-waw.tbl: Add new WAW resource for DAHR register.
227 * ia64-asmtab.c: Regenerate.
228
382c72e9
PB		 2292012-08-29 Peter Bergner <bergner@vnet.ibm.com>
230
231 * ppc-opc.c (VXASHB_MASK): New define.
232 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
233
fb048c26
PB		 2342012-08-28 Peter Bergner <bergner@vnet.ibm.com>
235
236 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
237 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
238 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
239 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
240 vupklsh>: Use VXVA_MASK.
241 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
242 <mfvscr>: Use VXVAVB_MASK.
243 <mtvscr>: Use VXVDVA_MASK.
244 <vspltb>: Use VXUIMM4_MASK.
245 <vsplth>: Use VXUIMM3_MASK.
246 <vspltw>: Use VXUIMM2_MASK.
247
3c9017d2
MGD		 2482012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
249
250 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
251
48adcd8e
MGD		 2522012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
253
254 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
255
4f51b4bd
MGD		 2562012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
257
258 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
259
91ff7894
MGD		 2602012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
261
262 * arm-dis.c (neon_opcodes): Add support for AES instructions.
263
c70a8987
MGD		 2642012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
265
266 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
267 conversions.
268
30bdf752
MGD		 2692012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
270
271 * arm-dis.c (coprocessor_opcodes): Add VRINT.
272 (neon_opcodes): Likewise.
273
7e8e6784
MGD		 2742012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
275
276 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
277 variants.
278 (neon_opcodes): Likewise.
279
73924fbc
MGD		 2802012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
281
282 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
283 (neon_opcodes): Likewise.
284
33399f07
MGD		 2852012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
286
287 * arm-dis.c (coprocessor_opcodes): Add VSEL.
288 (print_insn_coprocessor): Add new %<>c bitfield format
289 specifier.
290
9eb6c0f1
MGD		 2912012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
292
293 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
294 (thumb32_opcodes): Likewise.
295 (print_arm_insn): Add support for %<>T formatter.
296
8884b720
MGD		 2972012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
298
299 * arm-dis.c (arm_opcodes): Add HLT.
300 (thumb_opcodes): Likewise.
301
b79f7053
MGD		 3022012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
303
304 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
305
53c4b28b
MGD		 3062012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
307
308 * arm-dis.c (arm_opcodes): Add SEVL.
309 (thumb_opcodes): Likewise.
310 (thumb32_opcodes): Likewise.
311
e797f7e0
MGD		 3122012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
313
314 * arm-dis.c (data_barrier_option): New function.
315 (print_insn_arm): Use data_barrier_option.
316 (print_insn_thumb32): Use data_barrier_option.
317
e2efe87d
MGD		 3182012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
319
320 * arm-dis.c (COND_UNCOND): New constant.
321 (print_insn_coprocessor): Add support for %u format specifier.
322 (print_insn_neon): Likewise.
323
2c63854f
DM		 3242012-08-21 David S. Miller <davem@davemloft.net>
325
326 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
327 F3F4 macro.
328
e67ed0e8
AM		 3292012-08-20 Edmar Wienskoski <edmar@freescale.com>
330
331 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
332 vabsduh, vabsduw, mviwsplt.
333
7b458c12
L		 3342012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
335
336 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
337 CPU_BTVER2_FLAGS.
338
e67ed0e8 339 * i386-opc.h: Update CpuPRFCHW comment.
7b458c12
L		 340
341 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
342 * i386-init.h: Regenerated.
343 * i386-tbl.h: Likewise.
344
eb80cb87
NC		 3452012-08-17 Nick Clifton <nickc@redhat.com>
346
347 * po/uk.po: New Ukranian translation.
348 * configure.in (ALL_LINGUAS): Add uk.
349 * configure: Regenerate.
350
8baf7b78
PB		 3512012-08-16 Peter Bergner <bergner@vnet.ibm.com>
352
353 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
354 RBX for the third operand.
355 <"lswi">: Use RAX for second and NBI for the third operand.
356
3d557b4c
DD		 3572012-08-15 DJ Delorie <dj@redhat.com>
358
359 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
360 operands, so that data addresses can be corrected when not
361 ES-overridden.
362 * rl78-decode.c: Regenerate.
363 * rl78-dis.c (print_insn_rl78): Make order of modifiers
364 irrelevent. When the 'e' specifier is used on an operand and no
365 ES prefix is provided, adjust address to make it absolute.
366
588925d0
PB		 3672012-08-15 Peter Bergner <bergner@vnet.ibm.com>
368
369 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
370
9f6a6cc0
PB		 3712012-08-15 Peter Bergner <bergner@vnet.ibm.com>
372
373 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
374
fc8c4fd1
MR		 3752012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
376
377 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
378 macros, use local variables for info struct member accesses,
379 update the type of the variable used to hold the instruction
380 word.
381 (print_insn_mips, print_mips16_insn_arg): Likewise.
382 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
383 local variables for info struct member accesses.
384 (print_insn_micromips): Add GET_OP_S local macro.
385 (_print_insn_mips): Update the type of the variable used to hold
386 the instruction word.
387
a06ea964 3882012-08-13 Ian Bolton <ian.bolton@arm.com>
e67ed0e8
AM		 389 Laurent Desnogues <laurent.desnogues@arm.com>
390 Jim MacArthur <jim.macarthur@arm.com>
391 Marcus Shawcroft <marcus.shawcroft@arm.com>
392 Nigel Stephens <nigel.stephens@arm.com>
393 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
394 Richard Earnshaw <rearnsha@arm.com>
395 Sofiane Naci <sofiane.naci@arm.com>
396 Tejas Belagod <tejas.belagod@arm.com>
397 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 398
399 * Makefile.am: Add AArch64.
400 * Makefile.in: Regenerate.
401 * aarch64-asm.c: New file.
402 * aarch64-asm.h: New file.
403 * aarch64-dis.c: New file.
404 * aarch64-dis.h: New file.
405 * aarch64-gen.c: New file.
406 * aarch64-opc.c: New file.
407 * aarch64-opc.h: New file.
408 * aarch64-tbl.h: New file.
409 * configure.in: Add AArch64.
410 * configure: Regenerate.
411 * disassemble.c: Add AArch64.
412 * aarch64-asm-2.c: New file (automatically generated).
413 * aarch64-dis-2.c: New file (automatically generated).
414 * aarch64-opc-2.c: New file (automatically generated).
415 * po/POTFILES.in: Regenerate.
416
35d0a169
MR		 4172012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
418
419 * micromips-opc.c (micromips_opcodes): Update comment.
420 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
421 instructions for IOCT as appropriate.
422 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
423 opcode_is_member.
424 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
425 the result of a check for the -Wno-missing-field-initializers
426 GCC option.
427 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
428 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
429 compilation.
430 (mips16-opc.lo): Likewise.
431 (micromips-opc.lo): Likewise.
432 * aclocal.m4: Regenerate.
433 * configure: Regenerate.
434 * Makefile.in: Regenerate.
435
5c5acbbd
L		 4362012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
437
438 PR gas/14423
439 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
440 * i386-init.h: Regenerated.
441
3c892704
NC		 4422012-08-09 Nick Clifton <nickc@redhat.com>
443
444 * po/vi.po: Updated Vietnamese translation.
445
d7189fa5
RM		 4462012-08-07 Roland McGrath <mcgrathr@google.com>
447
448 * i386-dis.c (reg_table): Fill out REG_0F0D table with
449 AMD-reserved cases as "prefetch".
450 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
451 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
452 (reg_table): Use those under REG_0F18.
453 (mod_table): Add those cases as "nop/reserved".
454
4c692bc7
JB		 4552012-08-07 Jan Beulich <jbeulich@suse.com>
456
457 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
458
de882298
RM		 4592012-08-06 Roland McGrath <mcgrathr@google.com>
460
461 * i386-dis.c (print_insn): Print spaces between multiple excess
462 prefixes. Return actual number of excess prefixes consumed,
463 not always one.
464
465 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
466
7bb15c6f
RM		 4672012-08-06 Roland McGrath <mcgrathr@google.com>
468 Victor Khimenko <khim@google.com>
469 H.J. Lu <hongjiu.lu@intel.com>
470
471 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
472 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
473 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
474 (OP_E_register): Likewise.
475 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
476
3843081d
JBG		 4772012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
478
479 * configure.in: Formatting.
480 * configure: Regenerate.
481
48891606
AM		 4822012-08-01 Alan Modra <amodra@gmail.com>
483
484 * h8300-dis.c: Fix printf arg warnings.
485 * i960-dis.c: Likewise.
486 * mips-dis.c: Likewise.
487 * pdp11-dis.c: Likewise.
488 * sh-dis.c: Likewise.
489 * v850-dis.c: Likewise.
490 * configure.in: Formatting.
491 * configure: Regenerate.
492 * rl78-decode.c: Regenerate.
493 * po/POTFILES.in: Regenerate.
494
03f66e8a 4952012-07-31 Chao-Ying Fu <fu@mips.com>
e67ed0e8
AM		 496 Catherine Moore <clm@codesourcery.com>
497 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 498
499 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
500 (DSP_VOLA): Likewise.
501 (D32, D33): Likewise.
502 (micromips_opcodes): Add DSP ASE instructions.
48891606 503 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
03f66e8a
MR		 504 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
505
94948e64
JB		 5062012-07-31 Jan Beulich <jbeulich@suse.com>
507
508 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
509 instruction group. Mark as requiring AVX2.
510 * i386-tbl.h: Re-generate.
511
a6dc81d2
NC		 5122012-07-30 Nick Clifton <nickc@redhat.com>
513
514 * po/opcodes.pot: Updated template.
515 * po/es.po: Updated Spanish translation.
516 * po/fi.po: Updated Finnish translation.
517
c4dd807e
MF		 5182012-07-27 Mike Frysinger <vapier@gentoo.org>
519
520 * configure.in (BFD_VERSION): Run bfd/configure --version and
521 parse the output of that.
522 * configure: Regenerate.
523
03edbe3b
JL		 5242012-07-25 James Lemke <jwlemke@codesourcery.com>
525
526 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
527
63d08c68
NC		 5282012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
529 Dr David Alan Gilbert <dave@treblig.org>
d908c8af
NC		 530
531 PR binutils/13135
532 * arm-dis.c: Add necessary casts for printing integer values.
533 Use %s when printing string values.
534 * hppa-dis.c: Likewise.
535 * m68k-dis.c: Likewise.
536 * microblaze-dis.c: Likewise.
537 * mips-dis.c: Likewise.
538 * sparc-dis.c: Likewise.
539
ff688e1f
L		 5402012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
541
542 PR binutils/14355
543 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
544 (VEX_LEN_0FXOP_08_CD): Likewise.
545 (VEX_LEN_0FXOP_08_CE): Likewise.
546 (VEX_LEN_0FXOP_08_CF): Likewise.
547 (VEX_LEN_0FXOP_08_EC): Likewise.
548 (VEX_LEN_0FXOP_08_ED): Likewise.
549 (VEX_LEN_0FXOP_08_EE): Likewise.
550 (VEX_LEN_0FXOP_08_EF): Likewise.
551 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
552 vpcomub, vpcomuw, vpcomud, vpcomuq.
553 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
554 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
555 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
556 VEX_LEN_0FXOP_08_EF.
557
e2e1fcde
L		 5582012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
559
560 * i386-dis.c (PREFIX_0F38F6): New.
561 (prefix_table): Add adcx, adox instructions.
562 (three_byte_table): Use PREFIX_0F38F6.
563 (mod_table): Add rdseed instruction.
564 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
565 (cpu_flags): Likewise.
566 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
567 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
568 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
569 prefetchw.
570 * i386-tbl.h: Regenerate.
571 * i386-init.h: Likewise.
572
8b99bf0b
TS		 5732012-07-05 Thomas Schwinge <thomas@codesourcery.com>
574
f4263ca2 575 * mips-dis.c: Remove gratuitous newline.
8b99bf0b 576
416cf80a
SK		 5772012-07-05 Sean Keys <skeys@ipdatasys.com>
578
579 * xgate-dis.c: Removed an IF statement that will
e67ed0e8
AM		 580 always be false due to overlapping operand masks.
581 * xgate-opc.c: Corrected 'com' opcode entry and
582 fixed spacing.
416cf80a 583
9fa0f14a
RM		 5842012-07-02 Roland McGrath <mcgrathr@google.com>
585
586 * i386-opc.tbl: Add RepPrefixOk to nop.
587 * i386-tbl.h: Regenerate.
588
4c6a93d3
NC		 5892012-06-28 Nick Clifton <nickc@redhat.com>
590
591 * po/vi.po: Updated Vietnamese translation.
592
29c048b6
RM		 5932012-06-22 Roland McGrath <mcgrathr@google.com>
594
fe13e45b
RM		 595 * i386-opc.tbl: Add RepPrefixOk to ret.
596 * i386-tbl.h: Regenerate.
597
29c048b6
RM		 598 * i386-opc.h (RepPrefixOk): New enum constant.
599 (i386_opcode_modifier): New bitfield 'repprefixok'.
600 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
601 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
602 instructions that have IsString.
603 * i386-tbl.h: Regenerate.
604
c7a8dbf9
AS		 6052012-06-11 Andreas Schwab <schwab@linux-m68k.org>
606
607 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
608 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
609 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
610 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
611 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
612 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
613 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
614 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
615 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
616
94caa966
AM		 6172012-05-19 Alan Modra <amodra@gmail.com>
618
619 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
620 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
621
5eb3690e
AM		 6222012-05-18 Alan Modra <amodra@gmail.com>
623
71fe7bab
AM		 624 * ia64-opc.c: Remove #include "ansidecl.h".
625 * z8kgen.c: Include sysdep.h first.
626
5eb3690e
AM		 627 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
628 * bfin-dis.c: Likewise.
629 * i860-dis.c: Likewise.
630 * ia64-dis.c: Likewise.
631 * ia64-gen.c: Likewise.
632 * m68hc11-dis.c: Likewise.
633 * mmix-dis.c: Likewise.
634 * msp430-dis.c: Likewise.
635 * or32-dis.c: Likewise.
636 * rl78-dis.c: Likewise.
637 * rx-dis.c: Likewise.
638 * tic4x-dis.c: Likewise.
639 * tilegx-opc.c: Likewise.
640 * tilepro-opc.c: Likewise.
641 * rx-decode.c: Regenerate.
642
a4ebc835
AM		 6432012-05-17 James Lemke <jwlemke@codesourcery.com>
644
645 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
646
98c76446
AM		 6472012-05-17 James Lemke <jwlemke@codesourcery.com>
648
649 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
650
df7b86aa
NC		 6512012-05-17 Daniel Richard G. <skunk@iskunk.org>
652 Nick Clifton <nickc@redhat.com>
653
654 PR 14072
655 * configure.in: Add check that sysdep.h has been included before
656 any system header files.
657 * configure: Regenerate.
658 * config.in: Regenerate.
659 * sysdep.h: Generate an error if included before config.h.
660 * alpha-opc.c: Include sysdep.h before any other header file.
661 * alpha-dis.c: Likewise.
662 * avr-dis.c: Likewise.
663 * cgen-opc.c: Likewise.
664 * cr16-dis.c: Likewise.
665 * cris-dis.c: Likewise.
666 * crx-dis.c: Likewise.
667 * d10v-dis.c: Likewise.
668 * d10v-opc.c: Likewise.
669 * d30v-dis.c: Likewise.
670 * d30v-opc.c: Likewise.
671 * h8500-dis.c: Likewise.
672 * i370-dis.c: Likewise.
673 * i370-opc.c: Likewise.
674 * m10200-dis.c: Likewise.
675 * m10300-dis.c: Likewise.
676 * micromips-opc.c: Likewise.
677 * mips-opc.c: Likewise.
678 * mips61-opc.c: Likewise.
679 * moxie-dis.c: Likewise.
680 * or32-opc.c: Likewise.
681 * pj-dis.c: Likewise.
682 * ppc-dis.c: Likewise.
683 * ppc-opc.c: Likewise.
684 * s390-dis.c: Likewise.
685 * sh-dis.c: Likewise.
686 * sh64-dis.c: Likewise.
687 * sparc-dis.c: Likewise.
688 * sparc-opc.c: Likewise.
689 * spu-dis.c: Likewise.
690 * tic30-dis.c: Likewise.
691 * tic54x-dis.c: Likewise.
692 * tic80-dis.c: Likewise.
693 * tic80-opc.c: Likewise.
694 * tilegx-dis.c: Likewise.
695 * tilepro-dis.c: Likewise.
696 * v850-dis.c: Likewise.
697 * v850-opc.c: Likewise.
698 * vax-dis.c: Likewise.
699 * w65-dis.c: Likewise.
700 * xgate-dis.c: Likewise.
701 * xtensa-dis.c: Likewise.
702 * rl78-decode.opc: Likewise.
703 * rl78-decode.c: Regenerate.
704 * rx-decode.opc: Likewise.
705 * rx-decode.c: Regenerate.
706
e1dad58d
AM		 7072012-05-17 Alan Modra <amodra@gmail.com>
708
709 * ppc_dis.c: Don't include elf/ppc.h.
710
101af531
NC		 7112012-05-16 Meador Inge <meadori@codesourcery.com>
712
713 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
714 to PUSH/POP {reg}.
715
6927f982
NC		 7162012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
717 Stephane Carrez <stcarrez@nerim.fr>
718
719 * configure.in: Add S12X and XGATE co-processor support to m68hc11
720 target.
721 * disassemble.c: Likewise.
722 * configure: Regenerate.
723 * m68hc11-dis.c: Make objdump output more consistent, use hex
724 instead of decimal and use 0x prefix for hex.
725 * m68hc11-opc.c: Add S12X and XGATE opcodes.
726
b9c361e0
JL		 7272012-05-14 James Lemke <jwlemke@codesourcery.com>
728
729 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
730 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
731 (vle_opcd_indices): New array.
732 (lookup_vle): New function.
733 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
734 (print_insn_powerpc): Likewise.
735 * ppc-opc.c: Likewise.
736
7372012-05-14 Catherine Moore <clm@codesourcery.com>
738 Maciej W. Rozycki <macro@codesourcery.com>
739 Rhonda Wittels <rhonda@codesourcery.com>
740 Nathan Froyd <froydnj@codesourcery.com>
741
742 * ppc-opc.c (insert_arx, extract_arx): New functions.
743 (insert_ary, extract_ary): New functions.
744 (insert_li20, extract_li20): New functions.
745 (insert_rx, extract_rx): New functions.
746 (insert_ry, extract_ry): New functions.
747 (insert_sci8, extract_sci8): New functions.
748 (insert_sci8n, extract_sci8n): New functions.
749 (insert_sd4h, extract_sd4h): New functions.
750 (insert_sd4w, extract_sd4w): New functions.
751 (insert_vlesi, extract_vlesi): New functions.
752 (insert_vlensi, extract_vlensi): New functions.
753 (insert_vleui, extract_vleui): New functions.
754 (insert_vleil, extract_vleil): New functions.
755 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
756 (BI16, BI32, BO32, B8): New.
757 (B15, B24, CRD32, CRS): New.
758 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
759 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
760 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
761 (SH6_MASK): Use PPC_OPSHIFT_INV.
762 (SI8, UI5, OIMM5, UI7, BO16): New.
763 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
764 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
765 (ALLOW8_SPRG): New.
766 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
767 (OPVUP, OPVUP_MASK OPVUP): New
768 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
769 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
770 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
771 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
772 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
773 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
774 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
775 (SE_IM5, SE_IM5_MASK): New.
776 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
777 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
778 (BO32DNZ, BO32DZ): New.
779 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
780 (PPCVLE): New.
781 (powerpc_opcodes): Add new VLE instructions. Update existing
782 instruction to include PPCVLE if supported.
783 * ppc-dis.c (ppc_opts): Add vle entry.
784 (get_powerpc_dialect): New function.
785 (powerpc_init_dialect): VLE support.
786 (print_insn_big_powerpc): Call get_powerpc_dialect.
787 (print_insn_little_powerpc): Likewise.
788 (operand_value_powerpc): Handle negative shift counts.
789 (print_insn_powerpc): Handle 2-byte instruction lengths.
790
208a4923
NC		 7912012-05-11 Daniel Richard G. <skunk@iskunk.org>
792
793 PR binutils/14028
794 * configure.in: Invoke ACX_HEADER_STRING.
795 * configure: Regenerate.
796 * config.in: Regenerate.
797 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
798 string.h and strings.h.
799
6750a3a7
NC		 8002012-05-11 Nick Clifton <nickc@redhat.com>
801
802 PR binutils/14006
803 * arm-dis.c (print_insn): Fix detection of instruction mode in
804 files containing multiple executable sections.
805
f6c1a2d5
NC		 8062012-05-03 Sean Keys <skeys@ipdatasys.com>
807
808 * Makefile.in, configure: regenerate
809 * disassemble.c (disassembler): Recognize ARCH_XGATE.
810 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
811 New functions.
812 * configure.in: Recognize xgate.
813 * xgate-dis.c, xgate-opc.c: New files for support of xgate
814 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
815 and opcode generation for xgate.
816
78e98aab
DD		 8172012-04-30 DJ Delorie <dj@redhat.com>
818
819 * rx-decode.opc (MOV): Do not sign-extend immediates which are
820 already the maximum bit size.
821 * rx-decode.c: Regenerate.
822
ec668d69
DM		 8232012-04-27 David S. Miller <davem@davemloft.net>
824
2e52845b
DM		 825 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
826 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
827
58004e23
DM		 828 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
829 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
830
698544e1
DM		 831 * sparc-opc.c (CBCOND): New define.
832 (CBCOND_XCC): Likewise.
833 (cbcond): New helper macro.
834 (sparc_opcodes): Add compare-and-branch instructions.
835
6cda1326
DM		 836 * sparc-dis.c (print_insn_sparc): Handle ')'.
837 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
838
ec668d69
DM		 839 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
840 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
841
2615994e
DM		 8422012-04-12 David S. Miller <davem@davemloft.net>
843
844 * sparc-dis.c (X_DISP10): Define.
845 (print_insn_sparc): Handle '='.
846
5de10af0
MF		 8472012-04-01 Mike Frysinger <vapier@gentoo.org>
848
849 * bfin-dis.c (fmtconst): Replace decimal handling with a single
850 sprintf call and the '*' field width.
851
55a36193
MK		 8522012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
853
854 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
855
d6688282
AM		 8562012-03-16 Alan Modra <amodra@gmail.com>
857
858 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
859 (powerpc_opcd_indices): Bump array size.
860 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
861 corresponding to unused opcodes to following entry.
862 (lookup_powerpc): New function, extracted and optimised from..
863 (print_insn_powerpc): ..here.
864
b240011a
AM		 8652012-03-15 Alan Modra <amodra@gmail.com>
866 James Lemke <jwlemke@codesourcery.com>
867
868 * disassemble.c (disassemble_init_for_target): Handle ppc init.
869 * ppc-dis.c (private): New var.
870 (powerpc_init_dialect): Don't return calloc failure, instead use
871 private.
872 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
873 (powerpc_opcd_indices): New array.
874 (disassemble_init_powerpc): New function.
875 (print_insn_big_powerpc): Don't init dialect here.
876 (print_insn_little_powerpc): Likewise.
877 (print_insn_powerpc): Start search using powerpc_opcd_indices.
878
aea77599
AM		 8792012-03-10 Edmar Wienskoski <edmar@freescale.com>
880
881 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
882 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
883 (PPCVEC2, PPCTMR, E6500): New short names.
884 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
885 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
886 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
887 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
888 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
889 optional operands on sync instruction for E6500 target.
890
5333187a
AK		 8912012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
892
893 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
894
a597d2d3
AM		 8952012-02-27 Alan Modra <amodra@gmail.com>
896
897 * mt-dis.c: Regenerate.
898
3f26eb3a
AM		 8992012-02-27 Alan Modra <amodra@gmail.com>
900
901 * v850-opc.c (extract_v8): Rearrange to make it obvious this
902 is the inverse of corresponding insert function.
903 (extract_d22, extract_u9, extract_r4): Likewise.
904 (extract_d9): Correct sign extension.
905 (extract_d16_15): Don't assume "long" is 32 bits, and don't
906 rely on implementation defined behaviour for shift right of
907 signed types.
908 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
909 (extract_d23): Likewise, and correct mask.
910
1f42f8b3
AM		 9112012-02-27 Alan Modra <amodra@gmail.com>
912
913 * crx-dis.c (print_arg): Mask constant to 32 bits.
914 * crx-opc.c (cst4_map): Use int array.
915
cdb06235
AM		 9162012-02-27 Alan Modra <amodra@gmail.com>
917
918 * arc-dis.c (BITS): Don't use shifts to mask off bits.
919 (FIELDD): Sign extend with xor,sub.
920
6f7be959
WL		 9212012-02-25 Walter Lee <walt@tilera.com>
922
923 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
924 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
925 TILEPRO_OPC_LW_TLS_SN.
926
82c2def5
L		 9272012-02-21 H.J. Lu <hongjiu.lu@intel.com>
928
929 * i386-opc.h (HLEPrefixNone): New.
930 (HLEPrefixLock): Likewise.
931 (HLEPrefixAny): Likewise.
932 (HLEPrefixRelease): Likewise.
933
42164a71
L		 9342012-02-08 H.J. Lu <hongjiu.lu@intel.com>
935
936 * i386-dis.c (HLE_Fixup1): New.
937 (HLE_Fixup2): Likewise.
938 (HLE_Fixup3): Likewise.
939 (Ebh1): Likewise.
940 (Evh1): Likewise.
941 (Ebh2): Likewise.
942 (Evh2): Likewise.
943 (Ebh3): Likewise.
944 (Evh3): Likewise.
945 (MOD_C6_REG_7): Likewise.
946 (MOD_C7_REG_7): Likewise.
947 (RM_C6_REG_7): Likewise.
948 (RM_C7_REG_7): Likewise.
949 (XACQUIRE_PREFIX): Likewise.
950 (XRELEASE_PREFIX): Likewise.
951 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
952 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
953 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
954 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
955 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
956 MOD_C6_REG_7 and MOD_C7_REG_7.
957 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
958 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
959 xtest.
960 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
961 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
962
963 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
964 CPU_RTM_FLAGS.
965 (cpu_flags): Add CpuHLE and CpuRTM.
966 (opcode_modifiers): Add HLEPrefixOk.
967
968 * i386-opc.h (CpuHLE): New.
969 (CpuRTM): Likewise.
970 (HLEPrefixOk): Likewise.
971 (i386_cpu_flags): Add cpuhle and cpurtm.
972 (i386_opcode_modifier): Add hleprefixok.
973
974 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
975 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
976 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
977 operand. Add xacquire, xrelease, xabort, xbegin, xend and
978 xtest.
979 * i386-init.h: Regenerated.
980 * i386-tbl.h: Likewise.
981
21abe33a
DD		 9822012-01-24 DJ Delorie <dj@redhat.com>
983
984 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
985 * rl78-decode.c: Regenerate.
986
e20cc039
AM		 9872012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
988
989 PR binutils/10173
990 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
991
e143d25c
AS		 9922012-01-17 Andreas Schwab <schwab@linux-m68k.org>
993
994 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
995 register and move them after pmove with PSR/PCSR register.
996
8729a6f6
L		 9972012-01-13 H.J. Lu <hongjiu.lu@intel.com>
998
999 * i386-dis.c (mod_table): Add vmfunc.
1000
1001 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
1002 (cpu_flags): CpuVMFUNC.
1003
1004 * i386-opc.h (CpuVMFUNC): New.
1005 (i386_cpu_flags): Add cpuvmfunc.
1006
1007 * i386-opc.tbl: Add vmfunc.
1008 * i386-init.h: Regenerated.
1009 * i386-tbl.h: Likewise.
5011093d 1010
23e1d329 1011For older changes see ChangeLog-2011
252b5132
RH		 1012\f
1013Local Variables:
2f6d2f85
NC		 1014mode: change-log
1015left-margin: 8
1016fill-column: 74
252b5132
RH		 1017version-control: never
1018End:
GDB Binutils - Deliverables
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