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2007-06-05 Paul Brook <paul@codesourcery.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
79d49516
PB		 12007-06-05 Paul Brook <paul@codesourcery.com>
2
3 * arm-dis.c (thumb32_opcodes): Display writeback ldrd/strd addresses.
4
37ad9514
SE		 52007-05-24 Steve Ellcey <sje@cup.hp.com>
6
7 * Makefile.in: Regnerate.
8 * configure: Regenerate.
9 * aclocal.m4: Regenerate.
10
65b650b4
AM		 112007-05-18 Alan Modra <amodra@bigpond.net.au>
12
13 * ppc-dis.c (print_insn_powerpc): Don't skip all operands
14 after setting skip_optional.
15
ea192fa3
PB		 162007-05-16 Peter Bergner <bergner@vnet.ibm.com>
17
18 * ppc-dis.c (operand_value_powerpc, skip_optional_operands): New.
19 (print_insn_powerpc): Use the new operand_value_powerpc and
20 skip_optional_operands functions to omit or print all optional
21 operands as a group.
22 * ppc-opc.c (BFF, W, XFL_L, XWRA_MASK): New.
23 (XFL_MASK): Delete L and W bits from the mask.
24 (mtfsfi, mtfsfi.): Replace use of BF with BFF. Relpace use of XRA_MASK
25 with XWRA_MASK. Use W.
26 (mtfsf, mtfsf.): Use XFL_L and W.
27
9beff690
L		 282007-05-14 H.J. Lu <hongjiu.lu@intel.com>
29
30 PR binutils/4502
31 * i386-dis.c (Suffix3DNow): Replace "pfmulhrw" with "pmulhrw".
32
4d67a4d3
L		 332007-05-10 H.J. Lu <hongjiu.lu@intel.com>
34
35 * i386-opc.h (ShortForm): Redefined.
36 (Jump): Likewise.
37 (JumpDword): Likewise.
38 (JumpByte): Likewise.
39 (JumpInterSegment): Likewise.
40 (FloatMF): Likewise.
41 (FloatR): Likewise.
42 (FloatD): Likewise.
43 (Size16): Likewise.
44 (Size32): Likewise.
45 (Size64): Likewise.
46 (IgnoreSize): Likewise.
47 (DefaultSize): Likewise.
48 (No_bSuf): Likewise.
49 (No_wSuf): Likewise.
50 (No_lSuf): Likewise.
51 (No_sSuf): Likewise.
52 (No_qSuf): Likewise.
53 (No_xSuf): Likewise.
54 (FWait): Likewise.
55 (IsString): Likewise.
56 (regKludge): Likewise.
57 (IsPrefix): Likewise.
58 (ImmExt): Likewise.
59 (NoRex64): Likewise.
60 (Rex64): Likewise.
61 (Ugh): Likewise.
62
8de28984
L		 632007-05-07 H.J. Lu <hongjiu.lu@intel.com>
64
65 * i386-dis.c (threebyte_0x38_uses_DATA_prefix): Correct entries
66 for some SSE4 instructions.
67 (threebyte_0x3a_uses_DATA_prefix): Likewise.
68
20592a94
L		 692007-05-03 H.J. Lu <hongjiu.lu@intel.com>
70
71 * i386-dis.c (CRC32_Fixup): Don't print suffix in Intel mode.
72
73 * i386-opc.c (i386_optab): Remove IgnoreSize and correct operand
74 type for crc32.
75
9344ff29
L		 762007-05-01 H.J. Lu <hongjiu.lu@intel.com>
77
78 * i386-dis.c (CRC32_Fixup): Properly handle Intel mode and
79 check data size prefix in 16bit mode.
80
81 * i386-opc.c (i386_optab): Default crc32 to non-8bit and
82 support Intel mode.
83
53289dcd 842007-04-30 Mark Salter <msalter@redhat.com>
65b650b4 85
53289dcd
MS		 86 * frv-desc.c: Regenerate.
87 * frv-desc.h: Regenerate.
65b650b4 88
eb42fac1
AM		 892007-04-30 Alan Modra <amodra@bigpond.net.au>
90
91 PR 4436
92 * ppc-opc.c (powerpc_operands): Correct bitm for second entry of MBE.
93
484c222e
L		 942007-04-27 H.J. Lu <hongjiu.lu@intel.com>
95
96 * i386-dis.c (modrm): Put reg before rm.
97
5d669648
L		 982007-04-26 H.J. Lu <hongjiu.lu@intel.com>
99
100 PR binutils/4430
101 * i386-dis.c (print_displacement): New.
102 (OP_E): Call print_displacement instead of print_operand_value
103 to output displacement when either base or index exist. Print
104 the explicit zero displacement in 16bit mode.
105
185b1163
L		 1062007-04-26 H.J. Lu <hongjiu.lu@intel.com>
107
108 PR binutils/4429
109 * i386-dis.c (print_insn): Also swap the order of op_riprel
110 when swapping op_index. Break when the RIP relative address
111 is printed.
112 (OP_E): Properly handle RIP relative addressing and print the
113 explicit zero displacement for Intel mode.
114
eddc20ad
AM		 1152007-04-27 Alan Modra <amodra@bigpond.net.au>
116
117 * Makefile.am: Run "make dep-am".
118 * Makefile.in: Regenerate.
119 * ns32k-dis.c: Include sysdep.h first.
120
dacc8b01
MS		 1212007-04-24 Andreas Krebbel <krebbel1@de.ibm.com>
122
123 * opcodes/s390-opc.c (MASK_SSF_RRDRD): Fourth nybble belongs to the
124 opcode.
eddc20ad
AM		 125 * opcodes/s390-opc.txt (pfpo, ectg, csst): Add new z9-ec instructions.
126
fbb92301
NC		 1272007-04-24 Nick Clifton <nickc@redhat.com>
128
129 * arm-dis.c (print_insn): Initialise type.
130
4c273957
AM		 1312007-04-24 Alan Modra <amodra@bigpond.net.au>
132
133 * cgen-types.h: Include bfd_stdint.h, not stdint.h.
134 * Makefile.am: Run "make dep-am".
135 * Makefile.in: Regenerate.
136
9a2e615a
NS		 1372007-04-23 Nathan Sidwell <nathan@codesourcery.com>
138
139 * m68k-opc.c: Mark mcfisa_c instructions.
140
37b37b2d
RE		 1412007-04-21 Richard Earnshaw <rearnsha@arm.com>
142
143 * arm-dis.c (arm_opcodes): Disassemble to unified syntax.
144 (thumb_opcodes): Add missing white space in adr.
65b650b4 145 (arm_decode_shift): New parameter, print_shift. Only decode the
37b37b2d
RE		 146 shift parameter if set. Adjust callers.
147 (print_insn_arm): Support for operand type q with no shift decode.
148
717bbdf1
AM		 1492007-04-21 Alan Modra <amodra@bigpond.net.au>
150
db557034
AM		 151 * i386-opc.c (i386_float_regtab, i386_float_regtab_size): Delete.
152 Move contents to..
153 (i386_regtab): ..here.
154 * i386-opc.h (i386_float_regtab, i386_float_regtab_size): Delete.
155
717bbdf1
AM		 156 * ppc-opc.c (powerpc_operands): Delete duplicate entries.
157 (BA_MASK, FXM_MASK, STRM_MASK, VA_MASK, VB_MASK, VC_MASK): Delete.
158 (VD_MASK, WS_MASK, MTMSRD_L, XRT_L): Delete.
159 (powerpc_opcodes): Replace uses of MTMSRD_L and XRT_L.
160
78336706
NS		 1612007-04-20 Nathan Sidwell <nathan@codesourcery.com>
162
163 * m68k-dis.c (print_insn_arg): Show c04 as rambar0 and c05 as
164 rambar1.
165
b84bf58a
AM		 1662007-04-20 Alan Modra <amodra@bigpond.net.au>
167
168 * ppc-dis.c (print_insn_powerpc): Adjust for struct powerpc_operand
169 change.
170 * ppc-opc.c (powerpc_operands): Replace bit count with bit mask
171 in all entries. Add PPC_OPERAND_SIGNED to DE entry. Remove
172 references to following deleted functions.
173 (insert_bd, extract_bd, insert_dq, extract_dq): Delete.
174 (insert_ds, extract_ds, insert_de, extract_de): Delete.
175 (insert_des, extract_des, insert_li, extract_li): Delete.
176 (insert_nb, insert_rsq, insert_rtq, insert_ev2, extract_ev2): Delete.
177 (insert_ev4, extract_ev4, insert_ev8, extract_ev8): Delete.
178 (num_powerpc_operands): New constant.
179 (XSPRG_MASK): Remove entire SPRG field.
180 (powerpc_opcodes <bcctre, bcctrel>): Use XLBB_MASK not XLYBB_MASK.
181
0bbdef92
AM		 1822007-04-20 Alan Modra <amodra@bigpond.net.au>
183
184 * ppc-opc.c (DCM, DGM, TE, RMC, R, SP, S): Correct shift.
185 (Z2_MASK): Define.
186 (powerpc_opcodes): Use Z2_MASK in all insns taking RMC operand.
187
86ad2a13
RE		 1882007-04-20 Richard Earnshaw <rearnsha@arm.com>
189
190 * arm-dis.c (print_insn): Only look for a mapping symbol in the section
191 being disassembled.
192
a33e055d
AM		 1932007-04-19 Alan Modra <amodra@bigpond.net.au>
194
195 * Makefile.am: Run "make dep-am".
196 * Makefile.in: Regenerate.
197 * po/POTFILES.in: Regenerate.
198
360b1600
AM		 1992007-04-19 Alan Modra <amodra@bigpond.net.au>
200
201 * ppc-opc.c (powerpc_opcodes): Add cctpl, cctpm, cctph, db8cyc,
202 db10cyc, db12cyc, db16cyc.
203
b20ae55e
AM		 2042007-04-19 Nathan Froyd <froydnj@codesourcery.com>
205
206 * ppc-opc.c (powerpc_opcodes): Recognize three-operand tlbsxe.
207
381d071f
L		 2082007-04-18 H.J. Lu <hongjiu.lu@intel.com>
209
210 * i386-dis.c (CRC32_Fixup): New.
211 (PREGRP85, PREGRP86, PREGRP87, PREGRP88, PREGRP89, PREGRP90,
212 PREGRP91): New.
213 (threebyte_0x38_uses_DATA_prefix): Updated for SSE4.2.
214 (threebyte_0x3a_uses_DATA_prefix): Likewise.
215 (prefix_user_table): Add PREGRP85, PREGRP86, PREGRP87,
216 PREGRP88, PREGRP89, PREGRP90 and PREGRP91.
217 (three_byte_table): Likewise.
218
219 * i386-opc.c (i386_optab): Add SSE4.2 opcodes.
220
f6fdceb7 221 * i386-opc.h (CpuSSE4_2): New.
381d071f
L		 222 (CpuSSE4): Likewise.
223 (CpuUnknownFlags): Add CpuSSE4_2.
224
42903f7f
L		 2252007-04-18 H.J. Lu <hongjiu.lu@intel.com>
226
227 * i386-dis.c (XMM_Fixup): New.
228 (Edqb): New.
229 (Edqd): New.
230 (XMM0): New.
231 (dqb_mode): New.
232 (dqd_mode): New.
233 (PREGRP39 ... PREGRP85): New.
234 (threebyte_0x38_uses_DATA_prefix): Updated for SSE4.
235 (threebyte_0x3a_uses_DATA_prefix): Likewise.
236 (prefix_user_table): Add PREGRP39 ... PREGRP85.
237 (three_byte_table): Likewise.
238 (putop): Handle 'K'.
239 (intel_operand_size): Handle dqb_mode, dqd_mode):
240 (OP_E): Likewise.
241 (OP_G): Likewise.
242
243 * i386-opc.c (i386_optab): Add SSE4.1 opcodes.
244
245 * i386-opc.h (CpuSSE4_1): New.
246 (CpuUnknownFlags): Add CpuSSE4_1.
247 (regKludge): Update comment.
248
ee5c21a0
DJ		 2492007-04-18 Matthias Klose <doko@ubuntu.com>
250
251 * Makefile.am (libopcodes_la_LDFLAGS): Use bfd soversion.
252 * Makefile.in: Regenerate.
253
b7d19ba6
SE		 2542007-04-14 Steve Ellcey <sje@cup.hp.com>
255
256 * Makefile.am: Add ACLOCAL_AMFLAGS.
257 * Makefile.in: Regenerate.
258
246c51aa
L		 2592007-04-13 H.J. Lu <hongjiu.lu@intel.com>
260
261 * i386-dis.c: Remove trailing white spaces.
6e26e51a
L		 262 * i386-opc.c: Likewise.
263 * i386-opc.h: Likewise.
246c51aa 264
7967e09e
L		 2652007-04-11 H.J. Lu <hongjiu.lu@intel.com>
266
267 PR binutils/4333
268 * i386-dis.c (GRP1a): New.
269 (GRP1b ... GRPPADLCK2): Update index.
270 (dis386): Use GRP1a for entry 0x8f.
271 (mod, rm, reg): Removed. Replaced by ...
272 (modrm): This.
273 (grps): Add GRP1a.
274
56dc1f8a
KH		 2752007-04-09 Kazu Hirata <kazu@codesourcery.com>
276
277 * m68k-dis.c (print_insn_m68k): Restore info->fprintf_func and
278 info->print_address_func if longjmp is called.
279
144f4bc6
DD		 2802007-03-29 DJ Delorie <dj@redhat.com>
281
282 * m32c-desc.c: Regenerate.
283 * m32c-dis.c: Regenerate.
284 * m32c-opc.c: Regenerate.
285
e72cf3ec
L		 2862007-03-28 H.J. Lu <hongjiu.lu@intel.com>
287
288 * i386-opc.c (i386_optab): Change InvMem to RegMem for mov and
289 movq. Remove InvMem from sldt, smsw and str.
290
291 * i386-opc.h (InvMem): Renamed to ...
292 (RegMem): Update comments.
293 (AnyMem): Remove InvMem.
294
831480e9 2952007-03-27 Paul Brook <paul@codesourcery.com>
b74ed8f5 296
b74ed8f5
PB		 297 * arm-dis.c (thumb_opcodes): Add entry for undefined insns (0xbe??).
298
4146fd53
PB		 2992007-03-24 Paul Brook <paul@codesourcery.com>
300
301 * arm-dis.c (coprocessor_opcodes): Remove superfluous 0x.
302 (print_insn_coprocessor): Handle %<bitfield>x.
303
b6702015 3042007-03-24 Paul Brook <paul@codesourcery.com>
e72cf3ec 305 Mark Shinwell <shinwell@codesourcery.com>
b6702015
PB		 306
307 * arm-dis.c (arm_opcodes): Print SRS base register.
308
831480e9 3092007-03-23 H.J. Lu <hongjiu.lu@intel.com>
0003779b
L		 310
311 * i386-dis.c (prefix_name): Replace rex64XYZ with rex.WRXB.
312
313 * i386-opc.c (i386_optab): Add rex.wrxb.
314
831480e9 3152007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 316
317 * i386-dis.c (REX_MODE64): Remove definition.
318 (REX_EXTX): Likewise.
319 (REX_EXTY): Likewise.
320 (REX_EXTZ): Likewise.
321 (USED_REX): Use REX_OPCODE instead of 0x40.
322 Replace REX_MODE64, REX_EXTX, REX_EXTY and REX_EXTZ with REX_W,
323 REX_R, REX_X and REX_B respectively.
324
831480e9 3252007-03-21 H.J. Lu <hongjiu.lu@intel.com>
8b38ad71
L		 326
327 PR binutils/4218
328 * i386-dis.c (PREGRP38): New.
329 (dis386): Use PREGRP38 for 0x90.
330 (prefix_user_table): Add PREGRP38.
331 (print_insn): Set uses_REPZ_prefix to 1 for pause.
332 (NOP_Fixup1): Properly handle REX bits.
333 (NOP_Fixup2): Likewise.
334
335 * i386-opc.c (i386_optab): Allow %eax with xchg in 64bit.
336 Allow register with nop.
337
75b06e7b
DD		 3382007-03-20 DJ Delorie <dj@redhat.com>
339
340 * m32c-asm.c: Regenerate.
341 * m32c-desc.c: Regenerate.
342 * m32c-desc.h: Regenerate.
343 * m32c-dis.h: Regenerate.
344 * m32c-ibld.c: Regenerate.
345 * m32c-opc.c: Regenerate.
346 * m32c-opc.h: Regenerate.
347
c3fe08fa
L		 3482007-03-15 H.J. Lu <hongjiu.lu@intel.com>
349
350 * i386-opc.c: Include "libiberty.h".
351 (i386_regtab): Remove the last entry.
352 (i386_regtab_size): New.
353 (i386_float_regtab_size): Likewise.
354
355 * i386-opc.h (i386_regtab_size): New.
356 (i386_float_regtab_size): Likewise.
357
0b1cf022
L		 3582007-03-15 H.J. Lu <hongjiu.lu@intel.com>
359
360 * Makefile.am (CFILES): Add i386-opc.c.
361 (ALL_MACHINES): Add i386-opc.lo.
362 Run "make dep-am".
363 * Makefile.in: Regenerated.
364
365 * configure.in: Add i386-opc.lo for bfd_i386_arch.
366 * configure: Regenerated.
367
368 * i386-dis.c: Include "opcode/i386.h".
369 (MAXLEN): Renamed to MAX_MNEM_SIZE. Remove definition.
370 (FWAIT_OPCODE): Remove definition.
371 (UNIXWARE_COMPAT): Renamed to SYSV386_COMPAT. Remove definition.
372 (MAX_OPERANDS): Remove definition.
373
374 * i386-opc.c: New file.
375 * i386-opc.h: Likewise.
376
56eced12
L		 3772007-03-15 H.J. Lu <hongjiu.lu@intel.com>
378
379 * Makefile.in: Regenerated.
380
6f74c397
L		 3812007-03-09 H.J. Lu <hongjiu.lu@intel.com>
382
383 * i386-dis.c (OP_Rd): Renamed to ...
384 (OP_R): This.
385 (Rd): Updated.
386 (Rm): Likewise.
387
a6d04ec4
AM		 3882007-03-08 Alan Modra <amodra@bigpond.net.au>
389
1620f33d
AM		 390 * fr30-asm.c: Regenerate.
391 * frv-asm.c: Regenerate.
392 * ip2k-asm.c: Regenerate.
393 * iq2000-asm.c: Regenerate.
394 * m32c-asm.c: Regenerate.
395 * m32r-asm.c: Regenerate.
396 * m32r-dis.c: Regenerate.
397 * mt-asm.c: Regenerate.
398 * mt-ibld.c: Regenerate.
399 * mt-opc.c: Regenerate.
400 * openrisc-asm.c: Regenerate.
401 * xc16x-asm.c: Regenerate.
402 * xstormy16-asm.c: Regenerate.
403
a6d04ec4
AM		 404 * Makefile.am: Run "make dep-am".
405 * Makefile.in: Regenerate.
406 * po/POTFILES.in: Regenerate.
407
b5639b37
MS		 4082007-03-06 Andreas Krebbel <krebbel1@de.ibm.com>
409
410 * opcodes/s390-opc.c (INSTR_RRE_FR, INSTR_RRF_F0FF2, INSTR_RRF_F0FR,
411 INSTR_RRF_UUFF, INSTR_RRF_0UFF, INSTR_RRF_FFFU, INSTR_RRR_F0FF): New
412 instruction formats added.
413 (MASK_RRE_FR, MASK_RRF_F0FF2, MASK_RRF_F0FR, MASK_RRF_UUFF,
414 MASK_RRF_0UFF, MASK_RRF_FFFU, MASK_RRR_F0FF): New instruction format
415 masks added.
416 * opcodes/s390-opc.txt (lpdfr - tgxt): Decimal floating point
417 instructions added.
418 * opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added.
419 (main): z9-ec cpu type option added.
420 * include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added.
421
b2e818b7
DD		 4222007-02-22 DJ Delorie <dj@redhat.com>
423
424 * s390-opc.c (INSTR_SS_L2RDRD): New.
425 (MASK_SS_L2RDRD): New.
426 * s390-opc.txt (pka): Use it.
427
8b082fb1
TS		 4282007-02-20 Thiemo Seufer <ths@mips.com>
429 Chao-Ying Fu <fu@mips.com>
430
431 * mips-dis.c (mips_arch_choices): Add DSP R2 support.
432 (print_insn_args): Add support for balign instruction.
433 * mips-opc.c (D33): New shortcut for DSP R2 instructions.
434 (mips_builtin_opcodes): Add DSP R2 instructions.
435
929e4d1a
MS		 4362007-02-19 Andreas Krebbel <krebbel1@de.ibm.com>
437
438 * s390-opc.c (INSTR_RRF_U0FR, MASK_RRF_U0FR): Removed.
439 (INSTR_RRF_U0RF, MASK_RRF_U0RF): Added.
440 * s390-opc.txt (cfxbr, cfdbr, cfebr, cgebr, cgdbr, cgxbr, cger, cgdr,
441 cgxr, cfxr, cfdr, cfer): Instruction type set to INSTR_RRF_U0RF.
442
b8e55848
MS		 4432007-02-19 Andreas Krebbel <krebbel1@de.ibm.com>
444
445 * s390-opc.txt ("efpc", "sfpc"): Set to RRE_RR_OPT instruction type.
446 * s390-opc.c (s390_operands): Add RO_28 as optional gpr.
447 (INSTR_RRE_RR_OPT, MASK_RRE_RR_OPT): New instruction type for efpc
448 and sfpc.
449
af692060
NC		 4502007-02-16 Nick Clifton <nickc@redhat.com>
451
452 PR binutils/4045
453 * avr-dis.c (comment_start): New variable, contains the prefix to
454 use when printing addresses in comments.
455 (print_insn_avr): Set comment_start to an empty space if there is
456 no symbol table available as the generic address printing code
457 will prefix the numeric value of the address with 0x.
458
ce518a5f
L		 4592007-02-13 H.J. Lu <hongjiu.lu@intel.com>
460
461 * i386-dis.c: Updated to use an array of MAX_OPERANDS operands
462 in struct dis386.
463
bd2f2e55 4642007-02-05 Dave Brolley <brolley@redhat.com>
8c9c183d
DB		 465 Richard Sandiford <rsandifo@redhat.com>
466 DJ Delorie <dj@redhat.com>
467 Graydon Hoare <graydon@redhat.com>
468 Frank Ch. Eigler <fche@redhat.com>
469 Ben Elliston <bje@redhat.com>
470
471 * Makefile.am (HFILES): Add mep-desc.h mep-opc.h.
472 (CFILES): Add mep-*.c
473 (ALL_MACHINES): Add mep-*.lo.
474 (CLEANFILES): Add stamp-mep.
475 (CGEN_CPUS): Add mep.
476 (MEP_DEPS): New variable.
477 (mep-*): New targets.
478 * configure.in: Handle bfd_mep_arch.
479 * disassemble.c (ARCH_mep): New macro.
480 (disassembler): Handle bfd_arch_mep.
481 (disassemble_init_for_target): Likewise.
482 * mep-*: New files for Toshiba Media Processor (MeP).
bd2f2e55
DB		 483 * Makefile.in: Regenerated.
484 * configure: Regenerated.
485
eb7834a6 4862007-02-05 H.J. Lu <hongjiu.lu@intel.com>
65ca155d
L		 487
488 * i386-dis.c (OP_J): Undo the last change. Properly handle 64K
489 wrap around within the same segment in 16bit mode.
490
eb7834a6 4912007-02-02 H.J. Lu <hongjiu.lu@intel.com>
206717e8
L		 492
493 * i386-dis.c (OP_J): Mask to 16bit only if there is a data16
494 prefix.
495
c4f5c3d7
L		 4962007-02-02 H.J. Lu <hongjiu.lu@intel.com>
497
498 * avr-dis.c (avr_operand): Correct PR number in comment.
499
fc523535 5002007-02-02 H.J. Lu <hongjiu.lu@intel.com>
f59a29b9
L		 501
502 * disassemble.c (disassembler_usage): Call
503 print_i386_disassembler_options for i386 disassembler.
504
505 * i386-dis.c (print_i386_disassembler_options): New.
506 (print_insn): Support the new addr64 option.
507
64a3a6fc
NC		 5082007-02-02 Hiroki Kaminaga <kaminaga@sm.sony.co.jp>
509
510 * ppc-dis.c (powerpc_dialect): Handle ppc440.
511 * ppc-dis.c (print_ppc_disassembler_options): Note the -M440 can
512 be used.
513
ba4e851b
AM		 5142007-02-02 Alan Modra <amodra@bigpond.net.au>
515
516 * ppc-opc.c (insert_bdm): -Many comment.
517 (valid_bo): Add "extract" param. Accept both powerpc and power4
518 BO fields when disassembling with -Many.
519 (insert_bo, extract_bo, insert_boe, extract_boe): Adjust valid_bo call.
520
3bdcfdf4
KH		 5212007-01-08 Kazu Hirata <kazu@codesourcery.com>
522
523 * m68k-opc.c (m68k_opcodes): Replace cpu32 with
524 cpu32 | fido_a except on tbl instructions.
525
a028a6f5
PB		 5262007-01-04 Paul Brook <paul@codesourcery.com>
527
528 * arm-dis.c (arm_opcodes): Fix cpsie and cpsid entries.
529
baee4c9e
AS		 5302007-01-04 Andreas Schwab <schwab@suse.de>
531
532 * m68k-opc.c: Fix encoding of signed bit in the cpu32 tbls insns.
533
62ac925e
JB		 5342007-01-04 Julian Brown <julian@codesourcery.com>
535
536 * arm-dis.c (neon_opcode): Fix disassembly for vshl, vqshl, vrshl,
537 vqrshl instructions.
538
10a2343e 539For older changes see ChangeLog-2006
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RH		 540\f
541Local Variables:
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NC		 542mode: change-log
543left-margin: 8
544fill-column: 74
252b5132
RH		 545version-control: never
546End:
GDB Binutils - Deliverables
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