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x86: Swap destination/source to encode VEX only if possible
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
57f6375e
JB		 12018-09-13 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
4 meaningless.
5 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
6 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
7 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
8 * i386-tbl.h: Re-generate.
9
2589a7e5
JB		 102018-09-13 Jan Beulich <jbeulich@suse.com>
11
12 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
13 AVX512_4VNNIW insns.
14 * i386-tbl.h: Re-generate.
15
a760eb41
JB		 162018-09-13 Jan Beulich <jbeulich@suse.com>
17
18 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
19 meaningless.
20 * i386-tbl.h: Re-generate.
21
e9042658
JB		 222018-09-13 Jan Beulich <jbeulich@suse.com>
23
24 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
25 meaningless.
26 * i386-tbl.h: Re-generate.
27
9caa306f
JB		 282018-09-13 Jan Beulich <jbeulich@suse.com>
29
30 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
31 meaningless.
32 * i386-tbl.h: Re-generate.
33
fb6ce599
JB		 342018-09-13 Jan Beulich <jbeulich@suse.com>
35
36 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
37 meaningless.
38 * i386-tbl.h: Re-generate.
39
6a8da886
JB		 402018-09-13 Jan Beulich <jbeulich@suse.com>
41
42 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
43 meaningless.
44 * i386-tbl.h: Re-generate.
45
c7f27919
JB		 462018-09-13 Jan Beulich <jbeulich@suse.com>
47
48 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
49 * i386-tbl.h: Re-generate.
50
0f407ee9
JB		 512018-09-13 Jan Beulich <jbeulich@suse.com>
52
53 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
54 * i386-tbl.h: Re-generate.
55
2fbbbee5
JB		 562018-09-13 Jan Beulich <jbeulich@suse.com>
57
58 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
59 meaningless.
60 * i386-tbl.h: Re-generate.
61
2b02b9a2
JB		 622018-09-13 Jan Beulich <jbeulich@suse.com>
63
64 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
65 meaningless.
66 * i386-tbl.h: Re-generate.
67
963c68aa
JB		 682018-09-13 Jan Beulich <jbeulich@suse.com>
69
70 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
71 * i386-tbl.h: Re-generate.
72
64e025c3
JB		 732018-09-13 Jan Beulich <jbeulich@suse.com>
74
75 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
76 * i386-tbl.h: Re-generate.
77
47603f88
JB		 782018-09-13 Jan Beulich <jbeulich@suse.com>
79
80 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
81 * i386-tbl.h: Re-generate.
82
0001cfd0
JB		 832018-09-13 Jan Beulich <jbeulich@suse.com>
84
85 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
86 meaningless.
87 * i386-tbl.h: Re-generate.
88
be4b452e
JB		 892018-09-13 Jan Beulich <jbeulich@suse.com>
90
91 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
92 meaningless.
93 * i386-tbl.h: Re-generate.
94
d09a1394
JB		 952018-09-13 Jan Beulich <jbeulich@suse.com>
96
97 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
98 meaningless.
99 * i386-tbl.h: Re-generate.
100
07599e13
JB		 1012018-09-13 Jan Beulich <jbeulich@suse.com>
102
103 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
104 * i386-tbl.h: Re-generate.
105
1ee3e487
JB		 1062018-09-13 Jan Beulich <jbeulich@suse.com>
107
108 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
109 * i386-tbl.h: Re-generate.
110
a5f580e5
JB		 1112018-09-13 Jan Beulich <jbeulich@suse.com>
112
113 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
114 * i386-tbl.h: Re-generate.
115
49d5d12d
JB		 1162018-09-13 Jan Beulich <jbeulich@suse.com>
117
118 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
119 (vpbroadcastw, rdpid): Drop NoRex64.
120 * i386-tbl.h: Re-generate.
121
f5eb1d70
JB		 1222018-09-13 Jan Beulich <jbeulich@suse.com>
123
124 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
125 store templates, adding D.
126 * i386-tbl.h: Re-generate.
127
dbbc8b7e
JB		 1282018-09-13 Jan Beulich <jbeulich@suse.com>
129
130 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
131 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
132 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
133 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
134 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
135 Fold load and store templates where possible, adding D. Drop
136 IgnoreSize where it was pointlessly present. Drop redundant
137 *word.
138 * i386-tbl.h: Re-generate.
139
d276ec69
JB		 1402018-09-13 Jan Beulich <jbeulich@suse.com>
141
142 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
143 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
144 (intel_operand_size): Handle v_bndmk_mode.
145 (OP_E_memory): Likewise. Produce (bad) when also riprel.
146
9da4dfd6
JD		 1472018-09-08 John Darrington <john@darrington.wattle.id.au>
148
149 * disassemble.c (ARCH_s12z): Define if ARCH_all.
150
be192bc2
JW		 1512018-08-31 Kito Cheng <kito@andestech.com>
152
153 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
154 compressed floating point instructions.
155
43135d3b
JW		 1562018-08-30 Kito Cheng <kito@andestech.com>
157
158 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
159 riscv_opcode.xlen_requirement.
160 * riscv-opc.c (riscv_opcodes): Update for struct change.
161
df28970f
MA		 1622018-08-29 Martin Aberg <maberg@gaisler.com>
163
164 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
165 psr (PWRPSR) instruction.
166
9108bc33
CX		 1672018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
168
169 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
170
bd782c07
CX		 1712018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
172
173 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
174
ac8cb70f
CX		 1752018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
176
177 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
178 loongson3a as an alias of gs464 for compatibility.
179 * mips-opc.c (mips_opcodes): Change Comments.
180
a693765e
CX		 1812018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
182
183 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
184 option.
185 (print_mips_disassembler_options): Document -M loongson-ext.
186 * mips-opc.c (LEXT2): New macro.
187 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
188
bdc6c06e
CX		 1892018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
190
191 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
192 descriptors.
193 (parse_mips_ase_option): Handle -M loongson-ext option.
194 (print_mips_disassembler_options): Document -M loongson-ext.
195 * mips-opc.c (IL3A): Delete.
196 * mips-opc.c (LEXT): New macro.
197 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
198 instructions.
199
716c08de
CX		 2002018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
201
202 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
203 descriptors.
204 (parse_mips_ase_option): Handle -M loongson-cam option.
205 (print_mips_disassembler_options): Document -M loongson-cam.
206 * mips-opc.c (LCAM): New macro.
207 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
208 instructions.
209
9cf7e568
AM		 2102018-08-21 Alan Modra <amodra@gmail.com>
211
212 * ppc-dis.c (operand_value_powerpc): Init "invalid".
213 (skip_optional_operands): Count optional operands, and update
214 ppc_optional_operand_value call.
215 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
216 (extract_vlensi): Likewise.
217 (extract_fxm): Return default value for missing optional operand.
218 (extract_ls, extract_raq, extract_tbr): Likewise.
219 (insert_sxl, extract_sxl): New functions.
220 (insert_esync, extract_esync): Remove Power9 handling and simplify.
221 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
222 flag and extra entry.
223 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
224 extract_sxl.
225
d203b41a 2262018-08-20 Alan Modra <amodra@gmail.com>
f4107842 227
d203b41a 228 * sh-opc.h (MASK): Simplify.
f4107842 229
08a8fe2f 2302018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 231
d203b41a
AM		 232 * s12z-dis.c (bm_decode): Deal with cases where the mode is
233 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 234 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 235
08a8fe2f 2362018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 237
238 * s12z.h: Delete.
7ba3ba91 239
1bc60e56
L		 2402018-08-14 H.J. Lu <hongjiu.lu@intel.com>
241
242 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
243 address with the addr32 prefix and without base nor index
244 registers.
245
d871f3f4
L		 2462018-08-11 H.J. Lu <hongjiu.lu@intel.com>
247
248 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
249 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
250 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
251 (cpu_flags): Add CpuCMOV and CpuFXSR.
252 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
253 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
254 * i386-init.h: Regenerated.
255 * i386-tbl.h: Likewise.
256
b6523c37 2572018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
258
259 * arc-regs.h: Update auxiliary registers.
260
e968fc9b
JB		 2612018-08-06 Jan Beulich <jbeulich@suse.com>
262
263 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
264 (RegIP, RegIZ): Define.
265 * i386-reg.tbl: Adjust comments.
266 (rip): Use Qword instead of BaseIndex. Use RegIP.
267 (eip): Use Dword instead of BaseIndex. Use RegIP.
268 (riz): Add Qword. Use RegIZ.
269 (eiz): Add Dword. Use RegIZ.
270 * i386-tbl.h: Re-generate.
271
dbf8be89
JB		 2722018-08-03 Jan Beulich <jbeulich@suse.com>
273
274 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
275 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
276 vpmovzxdq, vpmovzxwd): Remove NoRex64.
277 * i386-tbl.h: Re-generate.
278
c48dadc9
JB		 2792018-08-03 Jan Beulich <jbeulich@suse.com>
280
281 * i386-gen.c (operand_types): Remove Mem field.
282 * i386-opc.h (union i386_operand_type): Remove mem field.
283 * i386-init.h, i386-tbl.h: Re-generate.
284
cb86a42a
AM		 2852018-08-01 Alan Modra <amodra@gmail.com>
286
287 * po/POTFILES.in: Regenerate.
288
07cc0450
NC		 2892018-07-31 Nick Clifton <nickc@redhat.com>
290
291 * po/sv.po: Updated Swedish translation.
292
1424ad86
JB		 2932018-07-31 Jan Beulich <jbeulich@suse.com>
294
295 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
296 * i386-init.h, i386-tbl.h: Re-generate.
297
ae2387fe
JB		 2982018-07-31 Jan Beulich <jbeulich@suse.com>
299
300 * i386-opc.h (ZEROING_MASKING) Rename to ...
301 (DYNAMIC_MASKING): ... this. Adjust comment.
302 * i386-opc.tbl (MaskingMorZ): Define.
303 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
304 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
305 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
306 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
307 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
308 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
309 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
310 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
311 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
312
6ff00b5e
JB		 3132018-07-31 Jan Beulich <jbeulich@suse.com>
314
315 * i386-opc.tbl: Use element rather than vector size for AVX512*
316 scatter/gather insns.
317 * i386-tbl.h: Re-generate.
318
e951d5ca
JB		 3192018-07-31 Jan Beulich <jbeulich@suse.com>
320
321 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
322 (cpu_flags): Drop CpuVREX.
323 * i386-opc.h (CpuVREX): Delete.
324 (union i386_cpu_flags): Remove cpuvrex.
325 * i386-init.h, i386-tbl.h: Re-generate.
326
eb41b248
JW		 3272018-07-30 Jim Wilson <jimw@sifive.com>
328
329 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
330 fields.
331 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
332
b8891f8d
AJ		 3332018-07-30 Andrew Jenner <andrew@codesourcery.com>
334
335 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
336 * Makefile.in: Regenerated.
337 * configure.ac: Add C-SKY.
338 * configure: Regenerated.
339 * csky-dis.c: New file.
340 * csky-opc.h: New file.
341 * disassemble.c (ARCH_csky): Define.
342 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
343 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
344
16065af1
AM		 3452018-07-27 Alan Modra <amodra@gmail.com>
346
347 * ppc-opc.c (insert_sprbat): Correct function parameter and
348 return type.
349 (extract_sprbat): Likewise, variable too.
350
fa758a70
AC		 3512018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
352 Alan Modra <amodra@gmail.com>
353
354 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
355 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
356 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
357 support disjointed BAT.
358 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
359 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
360 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
361
4a1b91ea
L		 3622018-07-25 H.J. Lu <hongjiu.lu@intel.com>
363 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
364
365 * i386-gen.c (adjust_broadcast_modifier): New function.
366 (process_i386_opcode_modifier): Add an argument for operands.
367 Adjust the Broadcast value based on operands.
368 (output_i386_opcode): Pass operand_types to
369 process_i386_opcode_modifier.
370 (process_i386_opcodes): Pass NULL as operands to
371 process_i386_opcode_modifier.
372 * i386-opc.h (BYTE_BROADCAST): New.
373 (WORD_BROADCAST): Likewise.
374 (DWORD_BROADCAST): Likewise.
375 (QWORD_BROADCAST): Likewise.
376 (i386_opcode_modifier): Expand broadcast to 3 bits.
377 * i386-tbl.h: Regenerated.
378
67ce483b
AM		 3792018-07-24 Alan Modra <amodra@gmail.com>
380
381 PR 23430
382 * or1k-desc.h: Regenerate.
383
4174bfff
JB		 3842018-07-24 Jan Beulich <jbeulich@suse.com>
385
386 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
387 vcvtusi2ss, and vcvtusi2sd.
388 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
389 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
390 * i386-tbl.h: Re-generate.
391
04e65276
CZ		 3922018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
393
394 * arc-opc.c (extract_w6): Fix extending the sign.
395
47e6f81c
CZ		 3962018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
397
398 * arc-tbl.h (vewt): Allow it for ARC EM family.
399
bb71536f
AM		 4002018-07-23 Alan Modra <amodra@gmail.com>
401
402 PR 23419
403 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
404 opcode variants for mtspr/mfspr encodings.
405
8095d2f7
CX		 4062018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
407 Maciej W. Rozycki <macro@mips.com>
408
409 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
410 loongson3a descriptors.
411 (parse_mips_ase_option): Handle -M loongson-mmi option.
412 (print_mips_disassembler_options): Document -M loongson-mmi.
413 * mips-opc.c (LMMI): New macro.
414 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
415 instructions.
416
5f32791e
JB		 4172018-07-19 Jan Beulich <jbeulich@suse.com>
418
419 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
420 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
421 IgnoreSize and [XYZ]MMword where applicable.
422 * i386-tbl.h: Re-generate.
423
625cbd7a
JB		 4242018-07-19 Jan Beulich <jbeulich@suse.com>
425
426 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
427 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
428 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
429 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
430 * i386-tbl.h: Re-generate.
431
86b15c32
JB		 4322018-07-19 Jan Beulich <jbeulich@suse.com>
433
434 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
435 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
436 VPCLMULQDQ templates into their respective AVX512VL counterparts
437 where possible, using Disp8ShiftVL and CheckRegSize instead of
438 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
439 * i386-tbl.h: Re-generate.
440
cf769ed5
JB		 4412018-07-19 Jan Beulich <jbeulich@suse.com>
442
443 * i386-opc.tbl: Fold AVX512DQ templates into their respective
444 AVX512VL counterparts where possible, using Disp8ShiftVL and
445 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
446 IgnoreSize) as appropriate.
447 * i386-tbl.h: Re-generate.
448
8282b7ad
JB		 4492018-07-19 Jan Beulich <jbeulich@suse.com>
450
451 * i386-opc.tbl: Fold AVX512BW templates into their respective
452 AVX512VL counterparts where possible, using Disp8ShiftVL and
453 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
454 IgnoreSize) as appropriate.
455 * i386-tbl.h: Re-generate.
456
755908cc
JB		 4572018-07-19 Jan Beulich <jbeulich@suse.com>
458
459 * i386-opc.tbl: Fold AVX512CD templates into their respective
460 AVX512VL counterparts where possible, using Disp8ShiftVL and
461 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
462 IgnoreSize) as appropriate.
463 * i386-tbl.h: Re-generate.
464
7091c612
JB		 4652018-07-19 Jan Beulich <jbeulich@suse.com>
466
467 * i386-opc.h (DISP8_SHIFT_VL): New.
468 * i386-opc.tbl (Disp8ShiftVL): Define.
469 (various): Fold AVX512VL templates into their respective
470 AVX512F counterparts where possible, using Disp8ShiftVL and
471 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
472 IgnoreSize) as appropriate.
473 * i386-tbl.h: Re-generate.
474
c30be56e
JB		 4752018-07-19 Jan Beulich <jbeulich@suse.com>
476
477 * Makefile.am: Change dependencies and rule for
478 $(srcdir)/i386-init.h.
479 * Makefile.in: Re-generate.
480 * i386-gen.c (process_i386_opcodes): New local variable
481 "marker". Drop opening of input file. Recognize marker and line
482 number directives.
483 * i386-opc.tbl (OPCODE_I386_H): Define.
484 (i386-opc.h): Include it.
485 (None): Undefine.
486
11a322db
L		 4872018-07-18 H.J. Lu <hongjiu.lu@intel.com>
488
489 PR gas/23418
490 * i386-opc.h (Byte): Update comments.
491 (Word): Likewise.
492 (Dword): Likewise.
493 (Fword): Likewise.
494 (Qword): Likewise.
495 (Tbyte): Likewise.
496 (Xmmword): Likewise.
497 (Ymmword): Likewise.
498 (Zmmword): Likewise.
499 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
500 vcvttps2uqq.
501 * i386-tbl.h: Regenerated.
502
cde3679e
NC		 5032018-07-12 Sudakshina Das <sudi.das@arm.com>
504
505 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
506 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
507 * aarch64-asm-2.c: Regenerate.
508 * aarch64-dis-2.c: Regenerate.
509 * aarch64-opc-2.c: Regenerate.
510
45a28947
TC		 5112018-07-12 Tamar Christina <tamar.christina@arm.com>
512
513 PR binutils/23192
514 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
515 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
516 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
517 sqdmulh, sqrdmulh): Use Em16.
518
c597cc3d
SD		 5192018-07-11 Sudakshina Das <sudi.das@arm.com>
520
521 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
522 csdb together with them.
523 (thumb32_opcodes): Likewise.
524
a79eaed6
JB		 5252018-07-11 Jan Beulich <jbeulich@suse.com>
526
527 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
528 requiring 32-bit registers as operands 2 and 3. Improve
529 comments.
530 (mwait, mwaitx): Fold templates. Improve comments.
531 OPERAND_TYPE_INOUTPORTREG.
532 * i386-tbl.h: Re-generate.
533
2fb5be8d
JB		 5342018-07-11 Jan Beulich <jbeulich@suse.com>
535
536 * i386-gen.c (operand_type_init): Remove
537 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
538 OPERAND_TYPE_INOUTPORTREG.
539 * i386-init.h: Re-generate.
540
7f5cad30
JB		 5412018-07-11 Jan Beulich <jbeulich@suse.com>
542
543 * i386-opc.tbl (wrssd, wrussd): Add Dword.
544 (wrssq, wrussq): Add Qword.
545 * i386-tbl.h: Re-generate.
546
f0a85b07
JB		 5472018-07-11 Jan Beulich <jbeulich@suse.com>
548
549 * i386-opc.h: Rename OTMax to OTNum.
550 (OTNumOfUints): Adjust calculation.
551 (OTUnused): Directly alias to OTNum.
552
9dcb0ba4
MR		 5532018-07-09 Maciej W. Rozycki <macro@mips.com>
554
555 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
556 `reg_xys'.
557 (lea_reg_xys): Likewise.
558 (print_insn_loop_primitive): Rename `reg' local variable to
559 `reg_dxy'.
560
f311ba7e
TC		 5612018-07-06 Tamar Christina <tamar.christina@arm.com>
562
563 PR binutils/23242
564 * aarch64-tbl.h (ldarh): Fix disassembly mask.
565
cba05feb
TC		 5662018-07-06 Tamar Christina <tamar.christina@arm.com>
567
568 PR binutils/23369
569 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
570 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
571
471b9d15
MR		 5722018-07-02 Maciej W. Rozycki <macro@mips.com>
573
574 PR tdep/8282
575 * mips-dis.c (mips_option_arg_t): New enumeration.
576 (mips_options): New variable.
577 (disassembler_options_mips): New function.
578 (print_mips_disassembler_options): Reimplement in terms of
579 `disassembler_options_mips'.
580 * arm-dis.c (disassembler_options_arm): Adapt to using the
581 `disasm_options_and_args_t' structure.
582 * ppc-dis.c (disassembler_options_powerpc): Likewise.
583 * s390-dis.c (disassembler_options_s390): Likewise.
584
c0c468d5
TP		 5852018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
586
587 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
588 expected result.
589 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
590 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
591 * testsuite/ld-arm/tls-longplt.d: Likewise.
592
369c9167
TC		 5932018-06-29 Tamar Christina <tamar.christina@arm.com>
594
595 PR binutils/23192
596 * aarch64-asm-2.c: Regenerate.
597 * aarch64-dis-2.c: Likewise.
598 * aarch64-opc-2.c: Likewise.
599 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
600 * aarch64-opc.c (operand_general_constraint_met_p,
601 aarch64_print_operand): Likewise.
602 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
603 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
604 fmlal2, fmlsl2.
605 (AARCH64_OPERANDS): Add Em2.
606
30aa1306
NC		 6072018-06-26 Nick Clifton <nickc@redhat.com>
608
609 * po/uk.po: Updated Ukranian translation.
610 * po/de.po: Updated German translation.
611 * po/pt_BR.po: Updated Brazilian Portuguese translation.
612
eca4b721
NC		 6132018-06-26 Nick Clifton <nickc@redhat.com>
614
615 * nfp-dis.c: Fix spelling mistake.
616
71300e2c
NC		 6172018-06-24 Nick Clifton <nickc@redhat.com>
618
619 * configure: Regenerate.
620 * po/opcodes.pot: Regenerate.
621
719d8288
NC		 6222018-06-24 Nick Clifton <nickc@redhat.com>
623
624 2.31 branch created.
625
514cd3a0
TC		 6262018-06-19 Tamar Christina <tamar.christina@arm.com>
627
628 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
629 * aarch64-asm-2.c: Regenerate.
630 * aarch64-dis-2.c: Likewise.
631
385e4d0f
MR		 6322018-06-21 Maciej W. Rozycki <macro@mips.com>
633
634 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
635 `-M ginv' option description.
636
160d1b3d
SH		 6372018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
638
639 PR gas/23305
640 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
641 la and lla.
642
d0ac1c44
SM		 6432018-06-19 Simon Marchi <simon.marchi@ericsson.com>
644
645 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
646 * configure.ac: Remove AC_PREREQ.
647 * Makefile.in: Re-generate.
648 * aclocal.m4: Re-generate.
649 * configure: Re-generate.
650
6f20c942
FS		 6512018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
652
653 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
654 mips64r6 descriptors.
655 (parse_mips_ase_option): Handle -Mginv option.
656 (print_mips_disassembler_options): Document -Mginv.
657 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
658 (GINV): New macro.
659 (mips_opcodes): Define ginvi and ginvt.
660
730c3174
SE		 6612018-06-13 Scott Egerton <scott.egerton@imgtec.com>
662 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
663
664 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
665 * mips-opc.c (CRC, CRC64): New macros.
666 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
667 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
668 crc32cd for CRC64.
669
cb366992
EB		 6702018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
671
672 PR 20319
673 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
674 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
675
ce72cd46
AM		 6762018-06-06 Alan Modra <amodra@gmail.com>
677
678 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
679 setjmp. Move init for some other vars later too.
680
4b8e28c7
MF		 6812018-06-04 Max Filippov <jcmvbkbc@gmail.com>
682
683 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
684 (dis_private): Add new fields for property section tracking.
685 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
686 (xtensa_instruction_fits): New functions.
687 (fetch_data): Bump minimal fetch size to 4.
688 (print_insn_xtensa): Make struct dis_private static.
689 Load and prepare property table on section change.
690 Don't disassemble literals. Don't disassemble instructions that
691 cross property table boundaries.
692
55e99962
L		 6932018-06-01 H.J. Lu <hongjiu.lu@intel.com>
694
695 * configure: Regenerated.
696
733bd0ab
JB		 6972018-06-01 Jan Beulich <jbeulich@suse.com>
698
699 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
700 * i386-tbl.h: Re-generate.
701
dfd27d41
JB		 7022018-06-01 Jan Beulich <jbeulich@suse.com>
703
704 * i386-opc.tbl (sldt, str): Add NoRex64.
705 * i386-tbl.h: Re-generate.
706
64795710
JB		 7072018-06-01 Jan Beulich <jbeulich@suse.com>
708
709 * i386-opc.tbl (invpcid): Add Oword.
710 * i386-tbl.h: Re-generate.
711
030157d8
AM		 7122018-06-01 Alan Modra <amodra@gmail.com>
713
714 * sysdep.h (_bfd_error_handler): Don't declare.
715 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
716 * rl78-decode.opc: Likewise.
717 * msp430-decode.c: Regenerate.
718 * rl78-decode.c: Regenerate.
719
a9660a6f
AP		 7202018-05-30 Amit Pawar <Amit.Pawar@amd.com>
721
722 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
723 * i386-init.h : Regenerated.
724
277eb7f6
AM		 7252018-05-25 Alan Modra <amodra@gmail.com>
726
727 * Makefile.in: Regenerate.
728 * po/POTFILES.in: Regenerate.
729
98553ad3
PB		 7302018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
731
732 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
733 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
734 (insert_bab, extract_bab, insert_btab, extract_btab,
735 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
736 (BAT, BBA VBA RBS XB6S): Delete macros.
737 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
738 (BB, BD, RBX, XC6): Update for new macros.
739 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
740 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
741 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
742 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
743
7b4ae824
JD		 7442018-05-18 John Darrington <john@darrington.wattle.id.au>
745
746 * Makefile.am: Add support for s12z architecture.
747 * configure.ac: Likewise.
748 * disassemble.c: Likewise.
749 * disassemble.h: Likewise.
750 * Makefile.in: Regenerate.
751 * configure: Regenerate.
752 * s12z-dis.c: New file.
753 * s12z.h: New file.
754
29e0f0a1
AM		 7552018-05-18 Alan Modra <amodra@gmail.com>
756
757 * nfp-dis.c: Don't #include libbfd.h.
758 (init_nfp3200_priv): Use bfd_get_section_contents.
759 (nit_nfp6000_mecsr_sec): Likewise.
760
809276d2
NC		 7612018-05-17 Nick Clifton <nickc@redhat.com>
762
763 * po/zh_CN.po: Updated simplified Chinese translation.
764
ff329288
TC		 7652018-05-16 Tamar Christina <tamar.christina@arm.com>
766
767 PR binutils/23109
768 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
769 * aarch64-dis-2.c: Regenerate.
770
f9830ec1
TC		 7712018-05-15 Tamar Christina <tamar.christina@arm.com>
772
773 PR binutils/21446
774 * aarch64-asm.c (opintl.h): Include.
775 (aarch64_ins_sysreg): Enforce read/write constraints.
776 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
777 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
778 (F_REG_READ, F_REG_WRITE): New.
779 * aarch64-opc.c (aarch64_print_operand): Generate notes for
780 AARCH64_OPND_SYSREG.
781 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
782 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
783 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
784 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
785 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
786 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
787 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
788 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
789 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
790 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
791 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
792 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
793 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
794 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
795 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
796 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
797 msr (F_SYS_WRITE), mrs (F_SYS_READ).
798
7d02540a
TC		 7992018-05-15 Tamar Christina <tamar.christina@arm.com>
800
801 PR binutils/21446
802 * aarch64-dis.c (no_notes: New.
803 (parse_aarch64_dis_option): Support notes.
804 (aarch64_decode_insn, print_operands): Likewise.
805 (print_aarch64_disassembler_options): Document notes.
806 * aarch64-opc.c (aarch64_print_operand): Support notes.
807
561a72d4
TC		 8082018-05-15 Tamar Christina <tamar.christina@arm.com>
809
810 PR binutils/21446
811 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
812 and take error struct.
813 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
814 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
815 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
816 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
817 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
818 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
819 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
820 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
821 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
822 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
823 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
824 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
825 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
826 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
827 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
828 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
829 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
830 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
831 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
832 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
833 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
834 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
835 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
836 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
837 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
838 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
839 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
840 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
841 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
842 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
843 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
844 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
845 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
846 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
847 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
848 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
849 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
850 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
851 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
852 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
853 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
854 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
855 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
856 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
857 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
858 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
859 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
860 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
861 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
862 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
863 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
864 (determine_disassembling_preference, aarch64_decode_insn,
865 print_insn_aarch64_word, print_insn_data): Take errors struct.
866 (print_insn_aarch64): Use errors.
867 * aarch64-asm-2.c: Regenerate.
868 * aarch64-dis-2.c: Regenerate.
869 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
870 boolean in aarch64_insert_operan.
871 (print_operand_extractor): Likewise.
872 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
873
1678bd35
FT		 8742018-05-15 Francois H. Theron <francois.theron@netronome.com>
875
876 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
877
06cfb1c8
L		 8782018-05-09 H.J. Lu <hongjiu.lu@intel.com>
879
880 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
881
84f9f8c3
AM		 8822018-05-09 Sebastian Rasmussen <sebras@gmail.com>
883
884 * cr16-opc.c (cr16_instruction): Comment typo fix.
885 * hppa-dis.c (print_insn_hppa): Likewise.
886
e6f372ba
JW		 8872018-05-08 Jim Wilson <jimw@sifive.com>
888
889 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
890 (match_c_slli64, match_srxi_as_c_srxi): New.
891 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
892 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
893 <c.slli, c.srli, c.srai>: Use match_s_slli.
894 <c.slli64, c.srli64, c.srai64>: New.
895
f413a913
AM		 8962018-05-08 Alan Modra <amodra@gmail.com>
897
898 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
899 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
900 partition opcode space for index lookup.
901
a87a6478
PB		 9022018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
903
904 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
905 <insn_length>: ...with this. Update usage.
906 Remove duplicate call to *info->memory_error_func.
907
c0a30a9f
L		 9082018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
909 H.J. Lu <hongjiu.lu@intel.com>
910
911 * i386-dis.c (Gva): New.
912 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
913 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
914 (prefix_table): New instructions (see prefix above).
915 (mod_table): New instructions (see prefix above).
916 (OP_G): Handle va_mode.
917 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
918 CPU_MOVDIR64B_FLAGS.
919 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
920 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
921 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
922 * i386-opc.tbl: Add movidir{i,64b}.
923 * i386-init.h: Regenerated.
924 * i386-tbl.h: Likewise.
925
75c0a438
L		 9262018-05-07 H.J. Lu <hongjiu.lu@intel.com>
927
928 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
929 AddrPrefixOpReg.
930 * i386-opc.h (AddrPrefixOp0): Renamed to ...
931 (AddrPrefixOpReg): This.
932 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
933 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
934
2ceb7719
PB		 9352018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
936
937 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
938 (vle_num_opcodes): Likewise.
939 (spe2_num_opcodes): Likewise.
940 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
941 initialization loop.
942 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
943 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
944 only once.
945
b3ac5c6c
TC		 9462018-05-01 Tamar Christina <tamar.christina@arm.com>
947
948 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
949
fe944acf
FT		 9502018-04-30 Francois H. Theron <francois.theron@netronome.com>
951
952 Makefile.am: Added nfp-dis.c.
953 configure.ac: Added bfd_nfp_arch.
954 disassemble.h: Added print_insn_nfp prototype.
955 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
956 nfp-dis.c: New, for NFP support.
957 po/POTFILES.in: Added nfp-dis.c to the list.
958 Makefile.in: Regenerate.
959 configure: Regenerate.
960
e2195274
JB		 9612018-04-26 Jan Beulich <jbeulich@suse.com>
962
963 * i386-opc.tbl: Fold various non-memory operand AVX512VL
964 templates into their base ones.
965 * i386-tlb.h: Re-generate.
966
59ef5df4
JB		 9672018-04-26 Jan Beulich <jbeulich@suse.com>
968
969 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
970 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
971 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
972 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
973 * i386-init.h: Re-generate.
974
6e041cf4
JB		 9752018-04-26 Jan Beulich <jbeulich@suse.com>
976
977 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
978 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
979 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
980 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
981 comment.
982 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
983 and CpuRegMask.
984 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
985 CpuRegMask: Delete.
986 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
987 cpuregzmm, and cpuregmask.
988 * i386-init.h: Re-generate.
989 * i386-tbl.h: Re-generate.
990
0e0eea78
JB		 9912018-04-26 Jan Beulich <jbeulich@suse.com>
992
993 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
994 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
995 * i386-init.h: Re-generate.
996
2f1bada2
JB		 9972018-04-26 Jan Beulich <jbeulich@suse.com>
998
999 * i386-gen.c (VexImmExt): Delete.
1000 * i386-opc.h (VexImmExt, veximmext): Delete.
1001 * i386-opc.tbl: Drop all VexImmExt uses.
1002 * i386-tlb.h: Re-generate.
1003
bacd1457
JB		 10042018-04-25 Jan Beulich <jbeulich@suse.com>
1005
1006 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1007 register-only forms.
1008 * i386-tlb.h: Re-generate.
1009
10bba94b
TC		 10102018-04-25 Tamar Christina <tamar.christina@arm.com>
1011
1012 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1013
c48935d7
IT		 10142018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1015
1016 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1017 PREFIX_0F1C.
1018 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1019 (cpu_flags): Add CpuCLDEMOTE.
1020 * i386-init.h: Regenerate.
1021 * i386-opc.h (enum): Add CpuCLDEMOTE,
1022 (i386_cpu_flags): Add cpucldemote.
1023 * i386-opc.tbl: Add cldemote.
1024 * i386-tbl.h: Regenerate.
1025
211dc24b
AM		 10262018-04-16 Alan Modra <amodra@gmail.com>
1027
1028 * Makefile.am: Remove sh5 and sh64 support.
1029 * configure.ac: Likewise.
1030 * disassemble.c: Likewise.
1031 * disassemble.h: Likewise.
1032 * sh-dis.c: Likewise.
1033 * sh64-dis.c: Delete.
1034 * sh64-opc.c: Delete.
1035 * sh64-opc.h: Delete.
1036 * Makefile.in: Regenerate.
1037 * configure: Regenerate.
1038 * po/POTFILES.in: Regenerate.
1039
a9a4b302
AM		 10402018-04-16 Alan Modra <amodra@gmail.com>
1041
1042 * Makefile.am: Remove w65 support.
1043 * configure.ac: Likewise.
1044 * disassemble.c: Likewise.
1045 * disassemble.h: Likewise.
1046 * w65-dis.c: Delete.
1047 * w65-opc.h: Delete.
1048 * Makefile.in: Regenerate.
1049 * configure: Regenerate.
1050 * po/POTFILES.in: Regenerate.
1051
04cb01fd
AM		 10522018-04-16 Alan Modra <amodra@gmail.com>
1053
1054 * configure.ac: Remove we32k support.
1055 * configure: Regenerate.
1056
c2bf1eec
AM		 10572018-04-16 Alan Modra <amodra@gmail.com>
1058
1059 * Makefile.am: Remove m88k support.
1060 * configure.ac: Likewise.
1061 * disassemble.c: Likewise.
1062 * disassemble.h: Likewise.
1063 * m88k-dis.c: Delete.
1064 * Makefile.in: Regenerate.
1065 * configure: Regenerate.
1066 * po/POTFILES.in: Regenerate.
1067
6793974d
AM		 10682018-04-16 Alan Modra <amodra@gmail.com>
1069
1070 * Makefile.am: Remove i370 support.
1071 * configure.ac: Likewise.
1072 * disassemble.c: Likewise.
1073 * disassemble.h: Likewise.
1074 * i370-dis.c: Delete.
1075 * i370-opc.c: Delete.
1076 * Makefile.in: Regenerate.
1077 * configure: Regenerate.
1078 * po/POTFILES.in: Regenerate.
1079
e82aa794
AM		 10802018-04-16 Alan Modra <amodra@gmail.com>
1081
1082 * Makefile.am: Remove h8500 support.
1083 * configure.ac: Likewise.
1084 * disassemble.c: Likewise.
1085 * disassemble.h: Likewise.
1086 * h8500-dis.c: Delete.
1087 * h8500-opc.h: Delete.
1088 * Makefile.in: Regenerate.
1089 * configure: Regenerate.
1090 * po/POTFILES.in: Regenerate.
1091
fceadf09
AM		 10922018-04-16 Alan Modra <amodra@gmail.com>
1093
1094 * configure.ac: Remove tahoe support.
1095 * configure: Regenerate.
1096
ae1d3843
L		 10972018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1098
1099 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1100 umwait.
1101 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1102 64-bit mode.
1103 * i386-tbl.h: Regenerated.
1104
de89d0a3
IT		 11052018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1106
1107 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1108 PREFIX_MOD_1_0FAE_REG_6.
1109 (va_mode): New.
1110 (OP_E_register): Use va_mode.
1111 * i386-dis-evex.h (prefix_table):
1112 New instructions (see prefixes above).
1113 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1114 (cpu_flags): Likewise.
1115 * i386-opc.h (enum): Likewise.
1116 (i386_cpu_flags): Likewise.
1117 * i386-opc.tbl: Add umonitor, umwait, tpause.
1118 * i386-init.h: Regenerate.
1119 * i386-tbl.h: Likewise.
1120
a8eb42a8
AM		 11212018-04-11 Alan Modra <amodra@gmail.com>
1122
1123 * opcodes/i860-dis.c: Delete.
1124 * opcodes/i960-dis.c: Delete.
1125 * Makefile.am: Remove i860 and i960 support.
1126 * configure.ac: Likewise.
1127 * disassemble.c: Likewise.
1128 * disassemble.h: Likewise.
1129 * Makefile.in: Regenerate.
1130 * configure: Regenerate.
1131 * po/POTFILES.in: Regenerate.
1132
caf0678c
L		 11332018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1134
1135 PR binutils/23025
1136 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1137 to 0.
1138 (print_insn): Clear vex instead of vex.evex.
1139
4fb0d2b9
NC		 11402018-04-04 Nick Clifton <nickc@redhat.com>
1141
1142 * po/es.po: Updated Spanish translation.
1143
c39e5b26
JB		 11442018-03-28 Jan Beulich <jbeulich@suse.com>
1145
1146 * i386-gen.c (opcode_modifiers): Delete VecESize.
1147 * i386-opc.h (VecESize): Delete.
1148 (struct i386_opcode_modifier): Delete vecesize.
1149 * i386-opc.tbl: Drop VecESize.
1150 * i386-tlb.h: Re-generate.
1151
8e6e0792
JB		 11522018-03-28 Jan Beulich <jbeulich@suse.com>
1153
1154 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1155 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1156 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1157 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1158 * i386-tlb.h: Re-generate.
1159
9f123b91
JB		 11602018-03-28 Jan Beulich <jbeulich@suse.com>
1161
1162 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1163 Fold AVX512 forms
1164 * i386-tlb.h: Re-generate.
1165
9646c87b
JB		 11662018-03-28 Jan Beulich <jbeulich@suse.com>
1167
1168 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1169 (vex_len_table): Drop Y for vcvt*2si.
1170 (putop): Replace plain 'Y' handling by abort().
1171
c8d59609
NC		 11722018-03-28 Nick Clifton <nickc@redhat.com>
1173
1174 PR 22988
1175 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1176 instructions with only a base address register.
1177 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1178 handle AARHC64_OPND_SVE_ADDR_R.
1179 (aarch64_print_operand): Likewise.
1180 * aarch64-asm-2.c: Regenerate.
1181 * aarch64_dis-2.c: Regenerate.
1182 * aarch64-opc-2.c: Regenerate.
1183
b8c169f3
JB		 11842018-03-22 Jan Beulich <jbeulich@suse.com>
1185
1186 * i386-opc.tbl: Drop VecESize from register only insn forms and
1187 memory forms not allowing broadcast.
1188 * i386-tlb.h: Re-generate.
1189
96bc132a
JB		 11902018-03-22 Jan Beulich <jbeulich@suse.com>
1191
1192 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1193 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1194 sha256*): Drop Disp<N>.
1195
9f79e886
JB		 11962018-03-22 Jan Beulich <jbeulich@suse.com>
1197
1198 * i386-dis.c (EbndS, bnd_swap_mode): New.
1199 (prefix_table): Use EbndS.
1200 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1201 * i386-opc.tbl (bndmov): Move misplaced Load.
1202 * i386-tlb.h: Re-generate.
1203
d6793fa1
JB		 12042018-03-22 Jan Beulich <jbeulich@suse.com>
1205
1206 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1207 templates allowing memory operands and folded ones for register
1208 only flavors.
1209 * i386-tlb.h: Re-generate.
1210
f7768225
JB		 12112018-03-22 Jan Beulich <jbeulich@suse.com>
1212
1213 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1214 256-bit templates. Drop redundant leftover Disp<N>.
1215 * i386-tlb.h: Re-generate.
1216
0e35537d
JW		 12172018-03-14 Kito Cheng <kito.cheng@gmail.com>
1218
1219 * riscv-opc.c (riscv_insn_types): New.
1220
b4a3689a
NC		 12212018-03-13 Nick Clifton <nickc@redhat.com>
1222
1223 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1224
d3d50934
L		 12252018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1226
1227 * i386-opc.tbl: Add Optimize to clr.
1228 * i386-tbl.h: Regenerated.
1229
bd5dea88
L		 12302018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1231
1232 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1233 * i386-opc.h (OldGcc): Removed.
1234 (i386_opcode_modifier): Remove oldgcc.
1235 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1236 instructions for old (<= 2.8.1) versions of gcc.
1237 * i386-tbl.h: Regenerated.
1238
e771e7c9
JB		 12392018-03-08 Jan Beulich <jbeulich@suse.com>
1240
1241 * i386-opc.h (EVEXDYN): New.
1242 * i386-opc.tbl: Fold various AVX512VL templates.
1243 * i386-tlb.h: Re-generate.
1244
ed438a93
JB		 12452018-03-08 Jan Beulich <jbeulich@suse.com>
1246
1247 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1248 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1249 vpexpandd, vpexpandq): Fold AFX512VF templates.
1250 * i386-tlb.h: Re-generate.
1251
454172a9
JB		 12522018-03-08 Jan Beulich <jbeulich@suse.com>
1253
1254 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1255 Fold 128- and 256-bit VEX-encoded templates.
1256 * i386-tlb.h: Re-generate.
1257
36824150
JB		 12582018-03-08 Jan Beulich <jbeulich@suse.com>
1259
1260 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1261 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1262 vpexpandd, vpexpandq): Fold AVX512F templates.
1263 * i386-tlb.h: Re-generate.
1264
e7f5c0a9
JB		 12652018-03-08 Jan Beulich <jbeulich@suse.com>
1266
1267 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1268 64-bit templates. Drop Disp<N>.
1269 * i386-tlb.h: Re-generate.
1270
25a4277f
JB		 12712018-03-08 Jan Beulich <jbeulich@suse.com>
1272
1273 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1274 and 256-bit templates.
1275 * i386-tlb.h: Re-generate.
1276
d2224064
JB		 12772018-03-08 Jan Beulich <jbeulich@suse.com>
1278
1279 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1280 * i386-tlb.h: Re-generate.
1281
1b193f0b
JB		 12822018-03-08 Jan Beulich <jbeulich@suse.com>
1283
1284 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1285 Drop NoAVX.
1286 * i386-tlb.h: Re-generate.
1287
f2f6a710
JB		 12882018-03-08 Jan Beulich <jbeulich@suse.com>
1289
1290 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1291 * i386-tlb.h: Re-generate.
1292
38e314eb
JB		 12932018-03-08 Jan Beulich <jbeulich@suse.com>
1294
1295 * i386-gen.c (opcode_modifiers): Delete FloatD.
1296 * i386-opc.h (FloatD): Delete.
1297 (struct i386_opcode_modifier): Delete floatd.
1298 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1299 FloatD by D.
1300 * i386-tlb.h: Re-generate.
1301
d53e6b98
JB		 13022018-03-08 Jan Beulich <jbeulich@suse.com>
1303
1304 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1305
2907c2f5
JB		 13062018-03-08 Jan Beulich <jbeulich@suse.com>
1307
1308 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1309 * i386-tlb.h: Re-generate.
1310
73053c1f
JB		 13112018-03-08 Jan Beulich <jbeulich@suse.com>
1312
1313 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1314 forms.
1315 * i386-tlb.h: Re-generate.
1316
52fe4420
AM		 13172018-03-07 Alan Modra <amodra@gmail.com>
1318
1319 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1320 bfd_arch_rs6000.
1321 * disassemble.h (print_insn_rs6000): Delete.
1322 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1323 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1324 (print_insn_rs6000): Delete.
1325
a6743a54
AM		 13262018-03-03 Alan Modra <amodra@gmail.com>
1327
1328 * sysdep.h (opcodes_error_handler): Define.
1329 (_bfd_error_handler): Declare.
1330 * Makefile.am: Remove stray #.
1331 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1332 EDIT" comment.
1333 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1334 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1335 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1336 opcodes_error_handler to print errors. Standardize error messages.
1337 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1338 and include opintl.h.
1339 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1340 * i386-gen.c: Standardize error messages.
1341 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1342 * Makefile.in: Regenerate.
1343 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1344 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1345 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1346 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1347 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1348 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1349 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1350 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1351 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1352 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1353 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1354 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1355 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1356
8305403a
L		 13572018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1358
1359 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1360 vpsub[bwdq] instructions.
1361 * i386-tbl.h: Regenerated.
1362
e184813f
AM		 13632018-03-01 Alan Modra <amodra@gmail.com>
1364
1365 * configure.ac (ALL_LINGUAS): Sort.
1366 * configure: Regenerate.
1367
5b616bef
TP		 13682018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1369
1370 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1371 macro by assignements.
1372
b6f8c7c4
L		 13732018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1374
1375 PR gas/22871
1376 * i386-gen.c (opcode_modifiers): Add Optimize.
1377 * i386-opc.h (Optimize): New enum.
1378 (i386_opcode_modifier): Add optimize.
1379 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1380 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1381 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1382 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1383 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1384 vpxord and vpxorq.
1385 * i386-tbl.h: Regenerated.
1386
e95b887f
AM		 13872018-02-26 Alan Modra <amodra@gmail.com>
1388
1389 * crx-dis.c (getregliststring): Allocate a large enough buffer
1390 to silence false positive gcc8 warning.
1391
0bccfb29
JW		 13922018-02-22 Shea Levy <shea@shealevy.com>
1393
1394 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1395
6b6b6807
L		 13962018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1397
1398 * i386-opc.tbl: Add {rex},
1399 * i386-tbl.h: Regenerated.
1400
75f31665
MR		 14012018-02-20 Maciej W. Rozycki <macro@mips.com>
1402
1403 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1404 (mips16_opcodes): Replace `M' with `m' for "restore".
1405
e207bc53
TP		 14062018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1407
1408 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1409
87993319
MR		 14102018-02-13 Maciej W. Rozycki <macro@mips.com>
1411
1412 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1413 variable to `function_index'.
1414
68d20676
NC		 14152018-02-13 Nick Clifton <nickc@redhat.com>
1416
1417 PR 22823
1418 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1419 about truncation of printing.
1420
d2159fdc
HW		 14212018-02-12 Henry Wong <henry@stuffedcow.net>
1422
1423 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1424
f174ef9f
NC		 14252018-02-05 Nick Clifton <nickc@redhat.com>
1426
1427 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1428
be3a8dca
IT		 14292018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1430
1431 * i386-dis.c (enum): Add pconfig.
1432 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1433 (cpu_flags): Add CpuPCONFIG.
1434 * i386-opc.h (enum): Add CpuPCONFIG.
1435 (i386_cpu_flags): Add cpupconfig.
1436 * i386-opc.tbl: Add PCONFIG instruction.
1437 * i386-init.h: Regenerate.
1438 * i386-tbl.h: Likewise.
1439
3233d7d0
IT		 14402018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1441
1442 * i386-dis.c (enum): Add PREFIX_0F09.
1443 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1444 (cpu_flags): Add CpuWBNOINVD.
1445 * i386-opc.h (enum): Add CpuWBNOINVD.
1446 (i386_cpu_flags): Add cpuwbnoinvd.
1447 * i386-opc.tbl: Add WBNOINVD instruction.
1448 * i386-init.h: Regenerate.
1449 * i386-tbl.h: Likewise.
1450
e925c834
JW		 14512018-01-17 Jim Wilson <jimw@sifive.com>
1452
1453 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1454
d777820b
IT		 14552018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1456
1457 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1458 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1459 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1460 (cpu_flags): Add CpuIBT, CpuSHSTK.
1461 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1462 (i386_cpu_flags): Add cpuibt, cpushstk.
1463 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1464 * i386-init.h: Regenerate.
1465 * i386-tbl.h: Likewise.
1466
f6efed01
NC		 14672018-01-16 Nick Clifton <nickc@redhat.com>
1468
1469 * po/pt_BR.po: Updated Brazilian Portugese translation.
1470 * po/de.po: Updated German translation.
1471
2721d702
JW		 14722018-01-15 Jim Wilson <jimw@sifive.com>
1473
1474 * riscv-opc.c (match_c_nop): New.
1475 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1476
616dcb87
NC		 14772018-01-15 Nick Clifton <nickc@redhat.com>
1478
1479 * po/uk.po: Updated Ukranian translation.
1480
3957a496
NC		 14812018-01-13 Nick Clifton <nickc@redhat.com>
1482
1483 * po/opcodes.pot: Regenerated.
1484
769c7ea5
NC		 14852018-01-13 Nick Clifton <nickc@redhat.com>
1486
1487 * configure: Regenerate.
1488
faf766e3
NC		 14892018-01-13 Nick Clifton <nickc@redhat.com>
1490
1491 2.30 branch created.
1492
888a89da
IT		 14932018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1494
1495 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1496 * i386-tbl.h: Regenerate.
1497
cbda583a
JB		 14982018-01-10 Jan Beulich <jbeulich@suse.com>
1499
1500 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1501 * i386-tbl.h: Re-generate.
1502
c9e92278
JB		 15032018-01-10 Jan Beulich <jbeulich@suse.com>
1504
1505 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1506 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1507 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1508 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1509 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1510 Disp8MemShift of AVX512VL forms.
1511 * i386-tbl.h: Re-generate.
1512
35fd2b2b
JW		 15132018-01-09 Jim Wilson <jimw@sifive.com>
1514
1515 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1516 then the hi_addr value is zero.
1517
91d8b670
JG		 15182018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1519
1520 * arm-dis.c (arm_opcodes): Add csdb.
1521 (thumb32_opcodes): Add csdb.
1522
be2e7d95
JG		 15232018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1524
1525 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1526 * aarch64-asm-2.c: Regenerate.
1527 * aarch64-dis-2.c: Regenerate.
1528 * aarch64-opc-2.c: Regenerate.
1529
704a705d
L		 15302018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1531
1532 PR gas/22681
1533 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1534 Remove AVX512 vmovd with 64-bit operands.
1535 * i386-tbl.h: Regenerated.
1536
35eeb78f
JW		 15372018-01-05 Jim Wilson <jimw@sifive.com>
1538
1539 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1540 jalr.
1541
219d1afa
AM		 15422018-01-03 Alan Modra <amodra@gmail.com>
1543
1544 Update year range in copyright notice of all files.
1545
1508bbf5
JB		 15462018-01-02 Jan Beulich <jbeulich@suse.com>
1547
1548 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1549 and OPERAND_TYPE_REGZMM entries.
1550
1e563868 1551For older changes see ChangeLog-2017
3499769a 1552\f
1e563868 1553Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1554
1555Copying and distribution of this file, with or without modification,
1556are permitted in any medium without royalty provided the copyright
1557notice and this notice are preserved.
1558
1559Local Variables:
1560mode: change-log
1561left-margin: 8
1562fill-column: 74
1563version-control: never
1564End:
GDB Binutils - Deliverables
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