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opcodes,gas: adjust sparc insns and make GAS aware of it
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
7a10c22f
JM		 12016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
2
3 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
4 architecture according to the hardware capabilities they require.
5
4f26fb3a
JM		 62016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
7
8 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
9 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
10 bfd_mach_sparc_v9{c,d,e,v,m}.
11 * sparc-opc.c (MASK_V9C): Define.
12 (MASK_V9D): Likewise.
13 (MASK_V9E): Likewise.
14 (MASK_V9V): Likewise.
15 (MASK_V9M): Likewise.
16 (v6): Add MASK_V9{C,D,E,V,M}.
17 (v6notlet): Likewise.
18 (v7): Likewise.
19 (v8): Likewise.
20 (v9): Likewise.
21 (v9andleon): Likewise.
22 (v9a): Likewise.
23 (v9b): Likewise.
24 (v9c): Define.
25 (v9d): Likewise.
26 (v9e): Likewise.
27 (v9v): Likewise.
28 (v9m): Likewise.
29 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
30
3ee6e4fb
NC		 312016-06-15 Nick Clifton <nickc@redhat.com>
32
33 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
34 constants to match expected behaviour.
35 (nds32_parse_opcode): Likewise. Also for whitespace.
36
02f3be19
AB		 372016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
38
39 * arc-opc.c (extract_rhv1): Extract value from insn.
40
6f9f37ed 412016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 42
43 * arc-nps400-tbl.h: Add ldbit instruction.
44 * arc-opc.c: Add flag classes required for ldbit.
45
6f9f37ed 462016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 47
48 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
49 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
50 support the above instructions.
51
6f9f37ed 522016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 53
54 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
55 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
56 csma, cbba, zncv, and hofs.
57 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
58 support the above instructions.
59
602016-06-06 Graham Markall <graham.markall@embecosm.com>
61
62 * arc-nps400-tbl.h: Add andab and orab instructions.
63
642016-06-06 Graham Markall <graham.markall@embecosm.com>
65
66 * arc-nps400-tbl.h: Add addl-like instructions.
67
682016-06-06 Graham Markall <graham.markall@embecosm.com>
69
70 * arc-nps400-tbl.h: Add mxb and imxb instructions.
71
722016-06-06 Graham Markall <graham.markall@embecosm.com>
73
74 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
75 instructions.
76
b2cc3f6f
AK		 772016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
78
79 * s390-dis.c (option_use_insn_len_bits_p): New file scope
80 variable.
81 (init_disasm): Handle new command line option "insnlength".
82 (print_s390_disassembler_options): Mention new option in help
83 output.
84 (print_insn_s390): Use the encoded insn length when dumping
85 unknown instructions.
86
1857fe72
DC		 872016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
88
89 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
90 to the address and set as symbol address for LDS/ STS immediate operands.
91
14b57c7c
AM		 922016-06-07 Alan Modra <amodra@gmail.com>
93
94 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
95 cpu for "vle" to e500.
96 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
97 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
98 (PPCNONE): Delete, substitute throughout.
99 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
100 except for major opcode 4 and 31.
101 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
102
4d1464f2
MW		 1032016-06-07 Matthew Wahab <matthew.wahab@arm.com>
104
105 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
106 ARM_EXT_RAS in relevant entries.
107
026122a6
PB		 1082016-06-03 Peter Bergner <bergner@vnet.ibm.com>
109
110 PR binutils/20196
111 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
112 opcodes for E6500.
113
07f5af7d
L		 1142016-06-03 H.J. Lu <hongjiu.lu@intel.com>
115
116 PR binutis/18386
117 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
118 (indir_v_mode): New.
119 Add comments for '&'.
120 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
121 (putop): Handle '&'.
122 (intel_operand_size): Handle indir_v_mode.
123 (OP_E_register): Likewise.
124 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
125 64-bit indirect call/jmp for AMD64.
126 * i386-tbl.h: Regenerated
127
4eb6f892
AB		 1282016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
129
130 * arc-dis.c (struct arc_operand_iterator): New structure.
131 (find_format_from_table): All the old content from find_format,
132 with some minor adjustments, and parameter renaming.
133 (find_format_long_instructions): New function.
134 (find_format): Rewritten.
135 (arc_insn_length): Add LSB parameter.
136 (extract_operand_value): New function.
137 (operand_iterator_next): New function.
138 (print_insn_arc): Use new functions to find opcode, and iterator
139 over operands.
140 * arc-opc.c (insert_nps_3bit_dst_short): New function.
141 (extract_nps_3bit_dst_short): New function.
142 (insert_nps_3bit_src2_short): New function.
143 (extract_nps_3bit_src2_short): New function.
144 (insert_nps_bitop1_size): New function.
145 (extract_nps_bitop1_size): New function.
146 (insert_nps_bitop2_size): New function.
147 (extract_nps_bitop2_size): New function.
148 (insert_nps_bitop_mod4_msb): New function.
149 (extract_nps_bitop_mod4_msb): New function.
150 (insert_nps_bitop_mod4_lsb): New function.
151 (extract_nps_bitop_mod4_lsb): New function.
152 (insert_nps_bitop_dst_pos3_pos4): New function.
153 (extract_nps_bitop_dst_pos3_pos4): New function.
154 (insert_nps_bitop_ins_ext): New function.
155 (extract_nps_bitop_ins_ext): New function.
156 (arc_operands): Add new operands.
157 (arc_long_opcodes): New global array.
158 (arc_num_long_opcodes): New global.
159 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
160
1fe0971e
TS		 1612016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
162
163 * nds32-asm.h: Add extern "C".
164 * sh-opc.h: Likewise.
165
315f180f
GM		 1662016-06-01 Graham Markall <graham.markall@embecosm.com>
167
168 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
169 0,b,limm to the rflt instruction.
170
a2b5fccc
TS		 1712016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
172
173 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
174 constant.
175
0cbd0046
L		 1762016-05-29 H.J. Lu <hongjiu.lu@intel.com>
177
178 PR gas/20145
179 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
180 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
181 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
182 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
183 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
184 * i386-init.h: Regenerated.
185
1848e567
L		 1862016-05-27 H.J. Lu <hongjiu.lu@intel.com>
187
188 PR gas/20145
189 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
190 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
191 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
192 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
193 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
194 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
195 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
196 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
197 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
198 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
199 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
200 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
201 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
202 CpuRegMask for AVX512.
203 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
204 and CpuRegMask.
205 (set_bitfield_from_cpu_flag_init): New function.
206 (set_bitfield): Remove const on f. Call
207 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
208 * i386-opc.h (CpuRegMMX): New.
209 (CpuRegXMM): Likewise.
210 (CpuRegYMM): Likewise.
211 (CpuRegZMM): Likewise.
212 (CpuRegMask): Likewise.
213 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
214 and cpuregmask.
215 * i386-init.h: Regenerated.
216 * i386-tbl.h: Likewise.
217
e92bae62
L		 2182016-05-27 H.J. Lu <hongjiu.lu@intel.com>
219
220 PR gas/20154
221 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
222 (opcode_modifiers): Add AMD64 and Intel64.
223 (main): Properly verify CpuMax.
224 * i386-opc.h (CpuAMD64): Removed.
225 (CpuIntel64): Likewise.
226 (CpuMax): Set to CpuNo64.
227 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
228 (AMD64): New.
229 (Intel64): Likewise.
230 (i386_opcode_modifier): Add amd64 and intel64.
231 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
232 on call and jmp.
233 * i386-init.h: Regenerated.
234 * i386-tbl.h: Likewise.
235
e89c5eaa
L		 2362016-05-27 H.J. Lu <hongjiu.lu@intel.com>
237
238 PR gas/20154
239 * i386-gen.c (main): Fail if CpuMax is incorrect.
240 * i386-opc.h (CpuMax): Set to CpuIntel64.
241 * i386-tbl.h: Regenerated.
242
77d66e7b
NC		 2432016-05-27 Nick Clifton <nickc@redhat.com>
244
245 PR target/20150
246 * msp430-dis.c (msp430dis_read_two_bytes): New function.
247 (msp430dis_opcode_unsigned): New function.
248 (msp430dis_opcode_signed): New function.
249 (msp430_singleoperand): Use the new opcode reading functions.
250 Only disassenmble bytes if they were successfully read.
251 (msp430_doubleoperand): Likewise.
252 (msp430_branchinstr): Likewise.
253 (msp430x_callx_instr): Likewise.
254 (print_insn_msp430): Check that it is safe to read bytes before
255 attempting disassembly. Use the new opcode reading functions.
256
19dfcc89
PB		 2572016-05-26 Peter Bergner <bergner@vnet.ibm.com>
258
259 * ppc-opc.c (CY): New define. Document it.
260 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
261
f3ad7637
L		 2622016-05-25 H.J. Lu <hongjiu.lu@intel.com>
263
264 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
265 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
266 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
267 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
268 CPU_ANY_AVX_FLAGS.
269 * i386-init.h: Regenerated.
270
f1360d58
L		 2712016-05-25 H.J. Lu <hongjiu.lu@intel.com>
272
273 PR gas/20141
274 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
275 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
276 * i386-init.h: Regenerated.
277
293f5f65
L		 2782016-05-25 H.J. Lu <hongjiu.lu@intel.com>
279
280 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
281 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
282 * i386-init.h: Regenerated.
283
d9eca1df
CZ		 2842016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
285
286 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
287 information.
288 (print_insn_arc): Set insn_type information.
289 * arc-opc.c (C_CC): Add F_CLASS_COND.
290 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
291 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
292 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
293 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
294 (brne, brne_s, jeq_s, jne_s): Likewise.
295
87789e08
CZ		 2962016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
297
298 * arc-tbl.h (neg): New instruction variant.
299
c810e0b8
CZ		 3002016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
301
302 * arc-dis.c (find_format, find_format, get_auxreg)
303 (print_insn_arc): Changed.
304 * arc-ext.h (INSERT_XOP): Likewise.
305
3d207518
TS		 3062016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
307
308 * tic54x-dis.c (sprint_mmr): Adjust.
309 * tic54x-opc.c: Likewise.
310
514e58b7
AM		 3112016-05-19 Alan Modra <amodra@gmail.com>
312
313 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
314
e43de63c
AM		 3152016-05-19 Alan Modra <amodra@gmail.com>
316
317 * ppc-opc.c: Formatting.
318 (NSISIGNOPT): Define.
319 (powerpc_opcodes <subis>): Use NSISIGNOPT.
320
1401d2fe
MR		 3212016-05-18 Maciej W. Rozycki <macro@imgtec.com>
322
323 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
324 replacing references to `micromips_ase' throughout.
325 (_print_insn_mips): Don't use file-level microMIPS annotation to
326 determine the disassembly mode with the symbol table.
327
1178da44
PB		 3282016-05-13 Peter Bergner <bergner@vnet.ibm.com>
329
330 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
331
8f4f9071
MF		 3322016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
333
334 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
335 mips64r6.
336 * mips-opc.c (D34): New macro.
337 (mips_builtin_opcodes): Define bposge32c for DSPr3.
338
8bc52696
AF		 3392016-05-10 Alexander Fomin <alexander.fomin@intel.com>
340
341 * i386-dis.c (prefix_table): Add RDPID instruction.
342 * i386-gen.c (cpu_flag_init): Add RDPID flag.
343 (cpu_flags): Add RDPID bitfield.
344 * i386-opc.h (enum): Add RDPID element.
345 (i386_cpu_flags): Add RDPID field.
346 * i386-opc.tbl: Add RDPID instruction.
347 * i386-init.h: Regenerate.
348 * i386-tbl.h: Regenerate.
349
39d911fc
TP		 3502016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
351
352 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
353 branch type of a symbol.
354 (print_insn): Likewise.
355
16a1fa25
TP		 3562016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
357
358 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
359 Mainline Security Extensions instructions.
360 (thumb_opcodes): Add entries for narrow ARMv8-M Security
361 Extensions instructions.
362 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
363 instructions.
364 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
365 special registers.
366
d751b79e
JM		 3672016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
368
369 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
370
945e0f82
CZ		 3712016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
372
373 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
374 (arcExtMap_genOpcode): Likewise.
375 * arc-opc.c (arg_32bit_rc): Define new variable.
376 (arg_32bit_u6): Likewise.
377 (arg_32bit_limm): Likewise.
378
20f55f38
SN		 3792016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
380
381 * aarch64-gen.c (VERIFIER): Define.
382 * aarch64-opc.c (VERIFIER): Define.
383 (verify_ldpsw): Use static linkage.
384 * aarch64-opc.h (verify_ldpsw): Remove.
385 * aarch64-tbl.h: Use VERIFIER for verifiers.
386
4bd13cde
NC		 3872016-04-28 Nick Clifton <nickc@redhat.com>
388
389 PR target/19722
390 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
391 * aarch64-opc.c (verify_ldpsw): New function.
392 * aarch64-opc.h (verify_ldpsw): New prototype.
393 * aarch64-tbl.h: Add initialiser for verifier field.
394 (LDPSW): Set verifier to verify_ldpsw.
395
c0f92bf9
L		 3962016-04-23 H.J. Lu <hongjiu.lu@intel.com>
397
398 PR binutils/19983
399 PR binutils/19984
400 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
401 smaller than address size.
402
e6c7cdec
TS		 4032016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
404
405 * alpha-dis.c: Regenerate.
406 * crx-dis.c: Likewise.
407 * disassemble.c: Likewise.
408 * epiphany-opc.c: Likewise.
409 * fr30-opc.c: Likewise.
410 * frv-opc.c: Likewise.
411 * ip2k-opc.c: Likewise.
412 * iq2000-opc.c: Likewise.
413 * lm32-opc.c: Likewise.
414 * lm32-opinst.c: Likewise.
415 * m32c-opc.c: Likewise.
416 * m32r-opc.c: Likewise.
417 * m32r-opinst.c: Likewise.
418 * mep-opc.c: Likewise.
419 * mt-opc.c: Likewise.
420 * or1k-opc.c: Likewise.
421 * or1k-opinst.c: Likewise.
422 * tic80-opc.c: Likewise.
423 * xc16x-opc.c: Likewise.
424 * xstormy16-opc.c: Likewise.
425
537aefaf
AB		 4262016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
427
428 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
429 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
430 calcsd, and calcxd instructions.
431 * arc-opc.c (insert_nps_bitop_size): Delete.
432 (extract_nps_bitop_size): Delete.
433 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
434 (extract_nps_qcmp_m3): Define.
435 (extract_nps_qcmp_m2): Define.
436 (extract_nps_qcmp_m1): Define.
437 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
438 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
439 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
440 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
441 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
442 NPS_QCMP_M3.
443
c8f785f2
AB		 4442016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
445
446 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
447
6fd8e7c2
L		 4482016-04-15 H.J. Lu <hongjiu.lu@intel.com>
449
450 * Makefile.in: Regenerated with automake 1.11.6.
451 * aclocal.m4: Likewise.
452
4b0c052e
AB		 4532016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
454
455 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
456 instructions.
457 * arc-opc.c (insert_nps_cmem_uimm16): New function.
458 (extract_nps_cmem_uimm16): New function.
459 (arc_operands): Add NPS_XLDST_UIMM16 operand.
460
cb040366
AB		 4612016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
462
463 * arc-dis.c (arc_insn_length): New function.
464 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
465 (find_format): Change insnLen parameter to unsigned.
466
accc0180
NC		 4672016-04-13 Nick Clifton <nickc@redhat.com>
468
469 PR target/19937
470 * v850-opc.c (v850_opcodes): Correct masks for long versions of
471 the LD.B and LD.BU instructions.
472
f36e33da
CZ		 4732016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
474
475 * arc-dis.c (find_format): Check for extension flags.
476 (print_flags): New function.
477 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
478 .extAuxRegister.
479 * arc-ext.c (arcExtMap_coreRegName): Use
480 LAST_EXTENSION_CORE_REGISTER.
481 (arcExtMap_coreReadWrite): Likewise.
482 (dump_ARC_extmap): Update printing.
483 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
484 (arc_aux_regs): Add cpu field.
485 * arc-regs.h: Add cpu field, lower case name aux registers.
486
1c2e355e
CZ		 4872016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
488
489 * arc-tbl.h: Add rtsc, sleep with no arguments.
490
b99747ae
CZ		 4912016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
492
493 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
494 Initialize.
495 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
496 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
497 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
498 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
499 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
500 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
501 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
502 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
503 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
504 (arc_opcode arc_opcodes): Null terminate the array.
505 (arc_num_opcodes): Remove.
506 * arc-ext.h (INSERT_XOP): Define.
507 (extInstruction_t): Likewise.
508 (arcExtMap_instName): Delete.
509 (arcExtMap_insn): New function.
510 (arcExtMap_genOpcode): Likewise.
511 * arc-ext.c (ExtInstruction): Remove.
512 (create_map): Zero initialize instruction fields.
513 (arcExtMap_instName): Remove.
514 (arcExtMap_insn): New function.
515 (dump_ARC_extmap): More info while debuging.
516 (arcExtMap_genOpcode): New function.
517 * arc-dis.c (find_format): New function.
518 (print_insn_arc): Use find_format.
519 (arc_get_disassembler): Enable dump_ARC_extmap only when
520 debugging.
521
92708cec
MR		 5222016-04-11 Maciej W. Rozycki <macro@imgtec.com>
523
524 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
525 instruction bits out.
526
a42a4f84
AB		 5272016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
528
529 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
530 * arc-opc.c (arc_flag_operands): Add new flags.
531 (arc_flag_classes): Add new classes.
532
1328504b
AB		 5332016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
534
535 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
536
820f03ff
AB		 5372016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
538
539 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
540 encode1, rflt, crc16, and crc32 instructions.
541 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
542 (arc_flag_classes): Add C_NPS_R.
543 (insert_nps_bitop_size_2b): New function.
544 (extract_nps_bitop_size_2b): Likewise.
545 (insert_nps_bitop_uimm8): Likewise.
546 (extract_nps_bitop_uimm8): Likewise.
547 (arc_operands): Add new operand entries.
548
8ddf6b2a
CZ		 5492016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
550
b99747ae
CZ		 551 * arc-regs.h: Add a new subclass field. Add double assist
552 accumulator register values.
553 * arc-tbl.h: Use DPA subclass to mark the double assist
554 instructions. Use DPX/SPX subclas to mark the FPX instructions.
555 * arc-opc.c (RSP): Define instead of SP.
556 (arc_aux_regs): Add the subclass field.
8ddf6b2a 557
589a7d88
JW		 5582016-04-05 Jiong Wang <jiong.wang@arm.com>
559
560 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
561
0a191de9 5622016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 563
564 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
565 NPS_R_SRC1.
566
0a106562
AB		 5672016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
568
569 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
570 issues. No functional changes.
571
bd05ac5f
CZ		 5722016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
573
b99747ae
CZ		 574 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
575 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
576 (RTT): Remove duplicate.
577 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
578 (PCT_CONFIG*): Remove.
579 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 580
9885948f
CZ		 5812016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
582
b99747ae 583 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 584
f2dd8838
CZ		 5852016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
586
b99747ae
CZ		 587 * arc-tbl.h (invld07): Remove.
588 * arc-ext-tbl.h: New file.
589 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
590 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 591
0d2f91fe
JK		 5922016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
593
594 Fix -Wstack-usage warnings.
595 * aarch64-dis.c (print_operands): Substitute size.
596 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
597
a6b71f42
JM		 5982016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
599
600 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
601 to get a proper diagnostic when an invalid ASR register is used.
602
9780e045
NC		 6032016-03-22 Nick Clifton <nickc@redhat.com>
604
605 * configure: Regenerate.
606
e23e8ebe
AB		 6072016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
608
609 * arc-nps400-tbl.h: New file.
610 * arc-opc.c: Add top level comment.
611 (insert_nps_3bit_dst): New function.
612 (extract_nps_3bit_dst): New function.
613 (insert_nps_3bit_src2): New function.
614 (extract_nps_3bit_src2): New function.
615 (insert_nps_bitop_size): New function.
616 (extract_nps_bitop_size): New function.
617 (arc_flag_operands): Add nps400 entries.
618 (arc_flag_classes): Add nps400 entries.
619 (arc_operands): Add nps400 entries.
620 (arc_opcodes): Add nps400 include.
621
1ae8ab47
AB		 6222016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
623
624 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
625 the new class enum values.
626
8699fc3e
AB		 6272016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
628
629 * arc-dis.c (print_insn_arc): Handle nps400.
630
24740d83
AB		 6312016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
632
633 * arc-opc.c (BASE): Delete.
634
8678914f
NC		 6352016-03-18 Nick Clifton <nickc@redhat.com>
636
637 PR target/19721
638 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
639 of MOV insn that aliases an ORR insn.
640
cc933301
JW		 6412016-03-16 Jiong Wang <jiong.wang@arm.com>
642
643 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
644
f86f5863
TS		 6452016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
646
647 * mcore-opc.h: Add const qualifiers.
648 * microblaze-opc.h (struct op_code_struct): Likewise.
649 * sh-opc.h: Likewise.
650 * tic4x-dis.c (tic4x_print_indirect): Likewise.
651 (tic4x_print_op): Likewise.
652
62de1c63
AM		 6532016-03-02 Alan Modra <amodra@gmail.com>
654
d11698cd 655 * or1k-desc.h: Regenerate.
62de1c63 656 * fr30-ibld.c: Regenerate.
c697cf0b 657 * rl78-decode.c: Regenerate.
62de1c63 658
020efce5
NC		 6592016-03-01 Nick Clifton <nickc@redhat.com>
660
661 PR target/19747
662 * rl78-dis.c (print_insn_rl78_common): Fix typo.
663
b0c11777
RL		 6642016-02-24 Renlin Li <renlin.li@arm.com>
665
666 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
667 (print_insn_coprocessor): Support fp16 instructions.
668
3e309328
RL		 6692016-02-24 Renlin Li <renlin.li@arm.com>
670
671 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
672 vminnm, vrint(mpna).
673
8afc7bea
RL		 6742016-02-24 Renlin Li <renlin.li@arm.com>
675
676 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
677 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
678
4fd7268a
L		 6792016-02-15 H.J. Lu <hongjiu.lu@intel.com>
680
681 * i386-dis.c (print_insn): Parenthesize expression to prevent
682 truncated addresses.
683 (OP_J): Likewise.
684
4670103e
CZ		 6852016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
686 Janek van Oirschot <jvanoirs@synopsys.com>
687
b99747ae
CZ		 688 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
689 variable.
4670103e 690
c1d9289f
NC		 6912016-02-04 Nick Clifton <nickc@redhat.com>
692
693 PR target/19561
694 * msp430-dis.c (print_insn_msp430): Add a special case for
695 decoding an RRC instruction with the ZC bit set in the extension
696 word.
697
a143b004
AB		 6982016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
699
700 * cgen-ibld.in (insert_normal): Rework calculation of shift.
701 * epiphany-ibld.c: Regenerate.
702 * fr30-ibld.c: Regenerate.
703 * frv-ibld.c: Regenerate.
704 * ip2k-ibld.c: Regenerate.
705 * iq2000-ibld.c: Regenerate.
706 * lm32-ibld.c: Regenerate.
707 * m32c-ibld.c: Regenerate.
708 * m32r-ibld.c: Regenerate.
709 * mep-ibld.c: Regenerate.
710 * mt-ibld.c: Regenerate.
711 * or1k-ibld.c: Regenerate.
712 * xc16x-ibld.c: Regenerate.
713 * xstormy16-ibld.c: Regenerate.
714
b89807c6
AB		 7152016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
716
717 * epiphany-dis.c: Regenerated from latest cpu files.
718
d8c823c8
MM		 7192016-02-01 Michael McConville <mmcco@mykolab.com>
720
721 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
722 test bit.
723
5bc5ae88
RL		 7242016-01-25 Renlin Li <renlin.li@arm.com>
725
726 * arm-dis.c (mapping_symbol_for_insn): New function.
727 (find_ifthen_state): Call mapping_symbol_for_insn().
728
0bff6e2d
MW		 7292016-01-20 Matthew Wahab <matthew.wahab@arm.com>
730
731 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
732 of MSR UAO immediate operand.
733
100b4f2e
MR		 7342016-01-18 Maciej W. Rozycki <macro@imgtec.com>
735
736 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
737 instruction support.
738
5c14705f
AM		 7392016-01-17 Alan Modra <amodra@gmail.com>
740
741 * configure: Regenerate.
742
4d82fe66
NC		 7432016-01-14 Nick Clifton <nickc@redhat.com>
744
745 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
746 instructions that can support stack pointer operations.
747 * rl78-decode.c: Regenerate.
748 * rl78-dis.c: Fix display of stack pointer in MOVW based
749 instructions.
750
651657fa
MW		 7512016-01-14 Matthew Wahab <matthew.wahab@arm.com>
752
753 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
754 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
755 erxtatus_el1 and erxaddr_el1.
756
105bde57
MW		 7572016-01-12 Matthew Wahab <matthew.wahab@arm.com>
758
759 * arm-dis.c (arm_opcodes): Add "esb".
760 (thumb_opcodes): Likewise.
761
afa8d405
PB		 7622016-01-11 Peter Bergner <bergner@vnet.ibm.com>
763
764 * ppc-opc.c <xscmpnedp>: Delete.
765 <xvcmpnedp>: Likewise.
766 <xvcmpnedp.>: Likewise.
767 <xvcmpnesp>: Likewise.
768 <xvcmpnesp.>: Likewise.
769
83c3256e
AS		 7702016-01-08 Andreas Schwab <schwab@linux-m68k.org>
771
772 PR gas/13050
773 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
774 addition to ISA_A.
775
6f2750fe
AM		 7762016-01-01 Alan Modra <amodra@gmail.com>
777
778 Update year range in copyright notice of all files.
779
3499769a
AM		 780For older changes see ChangeLog-2015
781\f
782Copyright (C) 2016 Free Software Foundation, Inc.
783
784Copying and distribution of this file, with or without modification,
785are permitted in any medium without royalty provided the copyright
786notice and this notice are preserved.
787
788Local Variables:
789mode: change-log
790left-margin: 8
791fill-column: 74
792version-control: never
793End:
GDB Binutils - Deliverables
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