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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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12011-04-26 Anton Blanchard <anton@samba.org>
2
3 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
4
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52011-04-21 DJ Delorie <dj@redhat.com>
6
7 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
8 * rx-decode.c: Regenerate.
9
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102011-04-20 H.J. Lu <hongjiu.lu@intel.com>
11
12 * i386-init.h: Regenerated.
13
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142011-04-19 Quentin Neill <quentin.neill@amd.com>
15
16 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
17 from bdver1 flags.
18
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192011-04-13 Nick Clifton <nickc@redhat.com>
20
21 * v850-dis.c (disassemble): Always print a closing square brace if
22 an opening square brace was printed.
23
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242011-04-12 Nick Clifton <nickc@redhat.com>
25
26 PR binutils/12534
27 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
28 patterns.
29 (print_insn_thumb32): Handle %L.
30
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312011-04-11 Julian Brown <julian@codesourcery.com>
32
33 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
34 (print_insn_thumb32): Add APSR bitmask support.
35
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362011-04-07 Paul Carroll<pcarroll@codesourcery.com>
37
38 * arm-dis.c (print_insn): init vars moved into private_data structure.
39
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402011-03-24 Mike Frysinger <vapier@gentoo.org>
41
42 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
43
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442011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
45
46 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
47 post-increment to support LPM Z+ instruction. Add support for 'E'
48 constraint for DES instruction.
49 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
50
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512011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
52
53 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
54
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552011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
56
57 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
58 Use branch types instead.
59 (print_insn): Likewise.
60
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612011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
62
63 * mips-opc.c (mips_builtin_opcodes): Correct register use
64 annotation of "alnv.ps".
65
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662011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
67
68 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
69
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702011-02-22 Mike Frysinger <vapier@gentoo.org>
71
72 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
73
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742011-02-22 Mike Frysinger <vapier@gentoo.org>
75
76 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
77
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782011-02-19 Mike Frysinger <vapier@gentoo.org>
79
80 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
81 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
82 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
83 exception, end_of_registers, msize, memory, bfd_mach.
84 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
85 LB0REG, LC1REG, LT1REG, LB1REG): Delete
86 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
87 (get_allreg): Change to new defines. Fallback to abort().
88
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892011-02-14 Mike Frysinger <vapier@gentoo.org>
90
91 * bfin-dis.c: Add whitespace/parenthesis where needed.
92
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932011-02-14 Mike Frysinger <vapier@gentoo.org>
94
95 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
96 than 7.
97
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982011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
99
100 * configure: Regenerate.
101
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1022011-02-13 Mike Frysinger <vapier@gentoo.org>
103
104 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
105
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1062011-02-13 Mike Frysinger <vapier@gentoo.org>
107
108 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
109 dregs only when P is set, and dregs_lo otherwise.
110
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1112011-02-13 Mike Frysinger <vapier@gentoo.org>
112
113 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
114
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1152011-02-12 Mike Frysinger <vapier@gentoo.org>
116
117 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
118
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1192011-02-12 Mike Frysinger <vapier@gentoo.org>
120
121 * bfin-dis.c (machine_registers): Delete REG_GP.
122 (reg_names): Delete "GP".
123 (decode_allregs): Change REG_GP to REG_LASTREG.
124
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1252011-02-12 Mike Frysinger <vapier@gentoo.org>
126
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127 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
128 M_IH, M_IU): Delete.
26bb3ddd 129
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1302011-02-11 Mike Frysinger <vapier@gentoo.org>
131
132 * bfin-dis.c (reg_names): Add const.
133 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
134 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
135 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
136 decode_counters, decode_allregs): Likewise.
137
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1382011-02-09 Michael Snyder <msnyder@vmware.com>
139
140 * i386-dis.c (OP_J): Parenthesize expression to prevent
141 truncated addresses.
142 (print_insn): Fix indentation off-by-one.
143
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1442011-02-01 Nick Clifton <nickc@redhat.com>
145
146 * po/da.po: Updated Danish translation.
147
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1482011-01-21 Dave Murphy <davem@devkitpro.org>
149
150 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
151
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1522011-01-18 H.J. Lu <hongjiu.lu@intel.com>
153
154 * i386-dis.c (sIbT): New.
155 (b_T_mode): Likewise.
156 (dis386): Replace sIb with sIbT on "pushT".
157 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
158 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
159
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1602011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
161
162 * i386-init.h: Regenerated.
163 * i386-tbl.h: Regenerated
164
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1652011-01-17 Quentin Neill <quentin.neill@amd.com>
166
167 * i386-dis.c (REG_XOP_TBM_01): New.
168 (REG_XOP_TBM_02): New.
169 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
170 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
171 entries, and add bextr instruction.
172
173 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
174 (cpu_flags): Add CpuTBM.
175
176 * i386-opc.h (CpuTBM) New.
177 (i386_cpu_flags): Add bit cputbm.
178
179 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
180 blcs, blsfill, blsic, t1mskc, and tzmsk.
181
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1822011-01-12 DJ Delorie <dj@redhat.com>
183
184 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
185
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1862011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
187
188 * mips-dis.c (print_insn_args): Adjust the value to print the real
189 offset for "+c" argument.
190
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1912011-01-10 Nick Clifton <nickc@redhat.com>
192
193 * po/da.po: Updated Danish translation.
194
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1952011-01-05 Nathan Sidwell <nathan@codesourcery.com>
196
197 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
198
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1992011-01-04 H.J. Lu <hongjiu.lu@intel.com>
200
201 * i386-dis.c (REG_VEX_38F3): New.
202 (PREFIX_0FBC): Likewise.
203 (PREFIX_VEX_38F2): Likewise.
204 (PREFIX_VEX_38F3_REG_1): Likewise.
205 (PREFIX_VEX_38F3_REG_2): Likewise.
206 (PREFIX_VEX_38F3_REG_3): Likewise.
207 (PREFIX_VEX_38F7): Likewise.
208 (VEX_LEN_38F2_P_0): Likewise.
209 (VEX_LEN_38F3_R_1_P_0): Likewise.
210 (VEX_LEN_38F3_R_2_P_0): Likewise.
211 (VEX_LEN_38F3_R_3_P_0): Likewise.
212 (VEX_LEN_38F7_P_0): Likewise.
213 (dis386_twobyte): Use PREFIX_0FBC.
214 (reg_table): Add REG_VEX_38F3.
215 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
216 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
217 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
218 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
219 PREFIX_VEX_38F7.
220 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
221 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
222 VEX_LEN_38F7_P_0.
223
224 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
225 (cpu_flags): Add CpuBMI.
226
227 * i386-opc.h (CpuBMI): New.
228 (i386_cpu_flags): Add cpubmi.
229
230 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
231 * i386-init.h: Regenerated.
232 * i386-tbl.h: Likewise.
233
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2342011-01-04 H.J. Lu <hongjiu.lu@intel.com>
235
236 * i386-dis.c (VexGdq): New.
237 (OP_VEX): Handle dq_mode.
238
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2392011-01-01 H.J. Lu <hongjiu.lu@intel.com>
240
241 * i386-gen.c (process_copyright): Update copyright to 2011.
242
9e9e0820 243For older changes see ChangeLog-2010
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244\f
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