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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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7a5f87ce
RS		 12013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
4 ADDA.S, MULA.S and SUBA.S.
5
41741fa4
L		 62013-07-08 H.J. Lu <hongjiu.lu@intel.com>
7
8 PR gas/13572
9 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
10 * i386-tbl.h: Regenerated.
11
f2ae14a1
RS		 122013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
13
14 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
15 and SD A(B) macros up.
16 * micromips-opc.c (micromips_opcodes): Likewise.
17
04c9d415
RS		 182013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
19
20 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
21 instructions.
22
5c324c16
RS		 232013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
24
25 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
26 MDMX-like instructions.
27 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
28 printing "Q" operands for INSN_5400 instructions.
29
23e69e47
RS		 302013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
31
32 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
33 "+S" for "cins".
34 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
35 Combine cases.
36
27c5c572
RS		 372013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
38
39 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
40 "jalx".
41 * mips16-opc.c (mips16_opcodes): Likewise.
42 * micromips-opc.c (micromips_opcodes): Likewise.
43 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
44 (print_insn_mips16): Handle "+i".
45 (print_insn_micromips): Likewise. Conditionally preserve the
46 ISA bit for "a" but not for "+i".
47
e76ff5ab
RS		 482013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
49
50 * micromips-opc.c (WR_mhi): Rename to..
51 (WR_mh): ...this.
52 (micromips_opcodes): Update "movep" entry accordingly. Replace
53 "mh,mi" with "mh".
54 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
55 (micromips_to_32_reg_h_map1): ...this.
56 (micromips_to_32_reg_i_map): Rename to...
57 (micromips_to_32_reg_h_map2): ...this.
58 (print_micromips_insn): Remove "mi" case. Print both registers
59 in the pair for "mh".
60
fa7616a4
RS		 612013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
62
63 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
64 * micromips-opc.c (micromips_opcodes): Likewise.
65 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
66 and "+T" handling. Check for a "0" suffix when deciding whether to
67 use coprocessor 0 names. In that case, also check for ",H" selectors.
68
fb798c50
AK		 692013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
70
71 * s390-opc.c (J12_12, J24_24): New macros.
72 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
73 (MASK_MII_UPI): Rename to MASK_MII_UPP.
74 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
75
58ae08f2
AM		 762013-07-04 Alan Modra <amodra@gmail.com>
77
78 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
79
b5e04c2b
NC		 802013-06-26 Nick Clifton <nickc@redhat.com>
81
82 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
83 field when checking for type 2 nop.
84 * rx-decode.c: Regenerate.
85
833794fc
MR		 862013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
87
88 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
89 and "movep" macros.
90
1bbce132
MR		 912013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
92
93 * mips-dis.c (is_mips16_plt_tail): New function.
94 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
95 word.
96 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
97
34c911a4
NC		 982013-06-21 DJ Delorie <dj@redhat.com>
99
100 * msp430-decode.opc: New.
101 * msp430-decode.c: New/generated.
102 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
103 (MAINTAINER_CLEANFILES): Likewise.
104 Add rule to build msp430-decode.c frommsp430decode.opc
105 using the opc2c program.
106 * Makefile.in: Regenerate.
107 * configure.in: Add msp430-decode.lo to msp430 architecture files.
108 * configure: Regenerate.
109
b9eead84
YZ		 1102013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
111
112 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
113 (SYMTAB_AVAILABLE): Removed.
114 (#include "elf/aarch64.h): Ditto.
115
7f3c4072
CM		 1162013-06-17 Catherine Moore <clm@codesourcery.com>
117 Maciej W. Rozycki <macro@codesourcery.com>
118 Chao-Ying Fu <fu@mips.com>
119
120 * micromips-opc.c (EVA): Define.
121 (TLBINV): Define.
122 (micromips_opcodes): Add EVA opcodes.
123 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
124 (print_insn_args): Handle EVA offsets.
125 (print_insn_micromips): Likewise.
126 * mips-opc.c (EVA): Define.
127 (TLBINV): Define.
128 (mips_builtin_opcodes): Add EVA opcodes.
129
de40ceb6
AM		 1302013-06-17 Alan Modra <amodra@gmail.com>
131
132 * Makefile.am (mips-opc.lo): Add rules to create automatic
133 dependency files. Pass archdefs.
134 (micromips-opc.lo, mips16-opc.lo): Likewise.
135 * Makefile.in: Regenerate.
136
3531d549
DD		 1372013-06-14 DJ Delorie <dj@redhat.com>
138
139 * rx-decode.opc (rx_decode_opcode): Bit operations on
140 registers are 32-bit operations, not 8-bit operations.
141 * rx-decode.c: Regenerate.
142
ba92f7fb
CF		 1432013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
144
145 * micromips-opc.c (IVIRT): New define.
146 (IVIRT64): New define.
147 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
148 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
149
150 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
151 dmtgc0 to print cp0 names.
152
9daf7bab
SL		 1532013-06-09 Sandra Loosemore <sandra@codesourcery.com>
154
155 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
156 argument.
157
d301a56b
RS		 1582013-06-08 Catherine Moore <clm@codesourcery.com>
159 Richard Sandiford <rdsandiford@googlemail.com>
160
161 * micromips-opc.c (D32, D33, MC): Update definitions.
162 (micromips_opcodes): Initialize ase field.
163 * mips-dis.c (mips_arch_choice): Add ase field.
164 (mips_arch_choices): Initialize ase field.
165 (set_default_mips_dis_options): Declare and setup mips_ase.
166 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
167 MT32, MC): Update definitions.
168 (mips_builtin_opcodes): Initialize ase field.
169
a3dcb6c5
RS		 1702013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
171
172 * s390-opc.txt (flogr): Require a register pair destination.
173
6cf1d90c
AK		 1742013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
175
176 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
177 instruction format.
178
c77c0862
RS		 1792013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
180
181 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
182
c0637f3a
PB		 1832013-05-20 Peter Bergner <bergner@vnet.ibm.com>
184
185 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
186 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
187 XLS_MASK, PPCVSX2): New defines.
188 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
189 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
190 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
191 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
192 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
193 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
194 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
195 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
196 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
197 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
198 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
199 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
200 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
201 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
202 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
203 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
204 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
205 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
206 <lxvx, stxvx>: New extended mnemonics.
207
4934fdaf
AM		 2082013-05-17 Alan Modra <amodra@gmail.com>
209
210 * ia64-raw.tbl: Replace non-ASCII char.
211 * ia64-waw.tbl: Likewise.
212 * ia64-asmtab.c: Regenerate.
213
6091d651
SE		 2142013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
215
216 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
217 * i386-init.h: Regenerated.
218
d2865ed3
YZ		 2192013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
220
221 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
222 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
223 check from [0, 255] to [-128, 255].
224
b015e599
AP		 2252013-05-09 Andrew Pinski <apinski@cavium.com>
226
227 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
228 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
229 (parse_mips_dis_option): Handle the virt option.
230 (print_insn_args): Handle "+J".
231 (print_mips_disassembler_options): Print out message about virt64.
232 * mips-opc.c (IVIRT): New define.
233 (IVIRT64): New define.
234 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
235 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
236 Move rfe to the bottom as it conflicts with tlbgp.
237
9f0682fe
AM		 2382013-05-09 Alan Modra <amodra@gmail.com>
239
240 * ppc-opc.c (extract_vlesi): Properly sign extend.
241 (extract_vlensi): Likewise. Comment reason for setting invalid.
242
13761a11
NC		 2432013-05-02 Nick Clifton <nickc@redhat.com>
244
245 * msp430-dis.c: Add support for MSP430X instructions.
246
e3031850
SL		 2472013-04-24 Sandra Loosemore <sandra@codesourcery.com>
248
249 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
250 to "eccinj".
251
17310e56
NC		 2522013-04-17 Wei-chen Wang <cole945@gmail.com>
253
254 PR binutils/15369
255 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
256 of CGEN_CPU_ENDIAN.
257 (hash_insns_list): Likewise.
258
731df338
JK		 2592013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
260
261 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
262 warning workaround.
263
5f77db52
JB		 2642013-04-08 Jan Beulich <jbeulich@suse.com>
265
266 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
267 * i386-tbl.h: Re-generate.
268
0afd1215
DM		 2692013-04-06 David S. Miller <davem@davemloft.net>
270
271 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
272 of an opcode, prefer the one with F_PREFERRED set.
273 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
274 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
275 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
276 mark existing mnenomics as aliases. Add "cc" suffix to edge
277 instructions generating condition codes, mark existing mnenomics
278 as aliases. Add "fp" prefix to VIS compare instructions, mark
279 existing mnenomics as aliases.
280
41702d50
NC		 2812013-04-03 Nick Clifton <nickc@redhat.com>
282
283 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
284 destination address by subtracting the operand from the current
285 address.
286 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
287 a positive value in the insn.
288 (extract_u16_loop): Do not negate the returned value.
289 (D16_LOOP): Add V850_INVERSE_PCREL flag.
290
291 (ceilf.sw): Remove duplicate entry.
292 (cvtf.hs): New entry.
293 (cvtf.sh): Likewise.
294 (fmaf.s): Likewise.
295 (fmsf.s): Likewise.
296 (fnmaf.s): Likewise.
297 (fnmsf.s): Likewise.
298 (maddf.s): Restrict to E3V5 architectures.
299 (msubf.s): Likewise.
300 (nmaddf.s): Likewise.
301 (nmsubf.s): Likewise.
302
55cf16e1
L		 3032013-03-27 H.J. Lu <hongjiu.lu@intel.com>
304
305 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
306 check address mode.
307 (print_insn): Pass sizeflag to get_sib.
308
51dcdd4d
NC		 3092013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
310
311 PR binutils/15068
312 * tic6x-dis.c: Add support for displaying 16-bit insns.
313
795b8e6b
NC		 3142013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
315
316 PR gas/15095
317 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
318 individual msb and lsb halves in src1 & src2 fields. Discard the
319 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
320 follow what Ti SDK does in that case as any value in the src1
321 field yields the same output with SDK disassembler.
322
314d60dd
ME		 3232013-03-12 Michael Eager <eager@eagercon.com>
324
795b8e6b 325 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 326
dad60f8e
SL		 3272013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
328
329 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
330
f5cb796a
SL		 3312013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
332
333 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
334
21fde85c
SL		 3352013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
336
337 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
338
dd5181d5
KT		 3392013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
340
341 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
342 (thumb32_opcodes): Likewise.
343 (print_insn_thumb32): Handle 'S' control char.
344
87a8d6cb
NC		 3452013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
346
347 * lm32-desc.c: Regenerate.
348
99dce992
L		 3492013-03-01 H.J. Lu <hongjiu.lu@intel.com>
350
351 * i386-reg.tbl (riz): Add RegRex64.
352 * i386-tbl.h: Regenerated.
353
e60bb1dd
YZ		 3542013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
355
356 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
357 (aarch64_feature_crc): New static.
358 (CRC): New macro.
359 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
360 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
361 * aarch64-asm-2.c: Re-generate.
362 * aarch64-dis-2.c: Ditto.
363 * aarch64-opc-2.c: Ditto.
364
c7570fcd
AM		 3652013-02-27 Alan Modra <amodra@gmail.com>
366
367 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
368 * rl78-decode.c: Regenerate.
369
151fa98f
NC		 3702013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
371
372 * rl78-decode.opc: Fix encoding of DIVWU insn.
373 * rl78-decode.c: Regenerate.
374
5c111e37
L		 3752013-02-19 H.J. Lu <hongjiu.lu@intel.com>
376
377 PR gas/15159
378 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
379
380 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
381 (cpu_flags): Add CpuSMAP.
382
383 * i386-opc.h (CpuSMAP): New.
384 (i386_cpu_flags): Add cpusmap.
385
386 * i386-opc.tbl: Add clac and stac.
387
388 * i386-init.h: Regenerated.
389 * i386-tbl.h: Likewise.
390
9d1df426
NC		 3912013-02-15 Markos Chandras <markos.chandras@imgtec.com>
392
393 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
394 which also makes the disassembler output be in little
395 endian like it should be.
396
a1ccaec9
YZ		 3972013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
398
399 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
400 fields to NULL.
401 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
402
ef068ef4 4032013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 404
405 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
406 section disassembled.
407
6fe6ded9
RE		 4082013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
409
410 * arm-dis.c: Update strht pattern.
411
0aa27725
RS		 4122013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
413
414 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
415 single-float. Disable ll, lld, sc and scd for EE. Disable the
416 trunc.w.s macro for EE.
417
36591ba1
SL		 4182013-02-06 Sandra Loosemore <sandra@codesourcery.com>
419 Andrew Jenner <andrew@codesourcery.com>
420
421 Based on patches from Altera Corporation.
422
423 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
424 nios2-opc.c.
425 * Makefile.in: Regenerated.
426 * configure.in: Add case for bfd_nios2_arch.
427 * configure: Regenerated.
428 * disassemble.c (ARCH_nios2): Define.
429 (disassembler): Add case for bfd_arch_nios2.
430 * nios2-dis.c: New file.
431 * nios2-opc.c: New file.
432
545093a4
AM		 4332013-02-04 Alan Modra <amodra@gmail.com>
434
435 * po/POTFILES.in: Regenerate.
436 * rl78-decode.c: Regenerate.
437 * rx-decode.c: Regenerate.
438
e30181a5
YZ		 4392013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
440
441 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
442 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
443 * aarch64-asm.c (convert_xtl_to_shll): New function.
444 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
445 calling convert_xtl_to_shll.
446 * aarch64-dis.c (convert_shll_to_xtl): New function.
447 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
448 calling convert_shll_to_xtl.
449 * aarch64-gen.c: Update copyright year.
450 * aarch64-asm-2.c: Re-generate.
451 * aarch64-dis-2.c: Re-generate.
452 * aarch64-opc-2.c: Re-generate.
453
78c8d46c
NC		 4542013-01-24 Nick Clifton <nickc@redhat.com>
455
456 * v850-dis.c: Add support for e3v5 architecture.
457 * v850-opc.c: Likewise.
458
f5555712
YZ		 4592013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
460
461 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
462 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
463 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 464 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 465 alignment check; change to call set_sft_amount_out_of_range_error
466 instead of set_imm_out_of_range_error.
467 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
468 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
469 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
470 SIMD_IMM_SFT.
471
2f81ff92
L		 4722013-01-16 H.J. Lu <hongjiu.lu@intel.com>
473
474 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
475
476 * i386-init.h: Regenerated.
477 * i386-tbl.h: Likewise.
478
dd42f060
NC		 4792013-01-15 Nick Clifton <nickc@redhat.com>
480
481 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
482 values.
483 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
484
a4533ed8
NC		 4852013-01-14 Will Newton <will.newton@imgtec.com>
486
487 * metag-dis.c (REG_WIDTH): Increase to 64.
488
5817ffd1
PB		 4892013-01-10 Peter Bergner <bergner@vnet.ibm.com>
490
491 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
492 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
493 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
494 (SH6): Update.
495 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
496 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
497 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
498 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
499
a3c62988
NC		 5002013-01-10 Will Newton <will.newton@imgtec.com>
501
502 * Makefile.am: Add Meta.
503 * configure.in: Add Meta.
504 * disassemble.c: Add Meta support.
505 * metag-dis.c: New file.
506 * Makefile.in: Regenerate.
507 * configure: Regenerate.
508
73335eae
NC		 5092013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
510
511 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
512 (match_opcode): Rename to cr16_match_opcode.
513
e407c74b
NC		 5142013-01-04 Juergen Urban <JuergenUrban@gmx.de>
515
516 * mips-dis.c: Add names for CP0 registers of r5900.
517 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
518 instructions sq and lq.
519 Add support for MIPS r5900 CPU.
520 Add support for 128 bit MMI (Multimedia Instructions).
521 Add support for EE instructions (Emotion Engine).
522 Disable unsupported floating point instructions (64 bit and
523 undefined compare operations).
524 Enable instructions of MIPS ISA IV which are supported by r5900.
525 Disable 64 bit co processor instructions.
526 Disable 64 bit multiplication and division instructions.
527 Disable instructions for co-processor 2 and 3, because these are
528 not supported (preparation for later VU0 support (Vector Unit)).
529 Disable cvt.w.s because this behaves like trunc.w.s and the
530 correct execution can't be ensured on r5900.
531 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
532 will confuse less developers and compilers.
533
a32c3ff8
NC		 5342013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
535
fb098a1e
YZ		 536 * aarch64-opc.c (aarch64_print_operand): Change to print
537 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
538 in comment.
539 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
540 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
541 OP_MOV_IMM_WIDE.
542
5432013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
544
545 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
546 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 547
62658407
L		 5482013-01-02 H.J. Lu <hongjiu.lu@intel.com>
549
550 * i386-gen.c (process_copyright): Update copyright year to 2013.
551
bab4becb 5522013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 553
bab4becb
NC		 554 * cr16-dis.c (match_opcode,make_instruction): Remove static
555 declaration.
556 (dwordU,wordU): Moved typedefs to opcode/cr16.h
557 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 558
bab4becb 559For older changes see ChangeLog-2012
252b5132 560\f
bab4becb 561Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 562
563Copying and distribution of this file, with or without modification,
564are permitted in any medium without royalty provided the copyright
565notice and this notice are preserved.
566
252b5132 567Local Variables:
2f6d2f85
NC		 568mode: change-log
569left-margin: 8
570fill-column: 74
252b5132
RH		 571version-control: never
572End:
GDB Binutils - Deliverables
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