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Add support for the Freescale s12z processor.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
7b4ae824
JD		 12018-05-18 John Darrington <john@darrington.wattle.id.au>
2
3 * Makefile.am: Add support for s12z architecture.
4 * configure.ac: Likewise.
5 * disassemble.c: Likewise.
6 * disassemble.h: Likewise.
7 * Makefile.in: Regenerate.
8 * configure: Regenerate.
9 * s12z-dis.c: New file.
10 * s12z.h: New file.
11
29e0f0a1
AM		 122018-05-18 Alan Modra <amodra@gmail.com>
13
14 * nfp-dis.c: Don't #include libbfd.h.
15 (init_nfp3200_priv): Use bfd_get_section_contents.
16 (nit_nfp6000_mecsr_sec): Likewise.
17
809276d2
NC		 182018-05-17 Nick Clifton <nickc@redhat.com>
19
20 * po/zh_CN.po: Updated simplified Chinese translation.
21
ff329288
TC		 222018-05-16 Tamar Christina <tamar.christina@arm.com>
23
24 PR binutils/23109
25 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
26 * aarch64-dis-2.c: Regenerate.
27
f9830ec1
TC		 282018-05-15 Tamar Christina <tamar.christina@arm.com>
29
30 PR binutils/21446
31 * aarch64-asm.c (opintl.h): Include.
32 (aarch64_ins_sysreg): Enforce read/write constraints.
33 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
34 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
35 (F_REG_READ, F_REG_WRITE): New.
36 * aarch64-opc.c (aarch64_print_operand): Generate notes for
37 AARCH64_OPND_SYSREG.
38 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
39 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
40 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
41 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
42 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
43 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
44 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
45 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
46 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
47 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
48 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
49 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
50 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
51 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
52 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
53 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
54 msr (F_SYS_WRITE), mrs (F_SYS_READ).
55
7d02540a
TC		 562018-05-15 Tamar Christina <tamar.christina@arm.com>
57
58 PR binutils/21446
59 * aarch64-dis.c (no_notes: New.
60 (parse_aarch64_dis_option): Support notes.
61 (aarch64_decode_insn, print_operands): Likewise.
62 (print_aarch64_disassembler_options): Document notes.
63 * aarch64-opc.c (aarch64_print_operand): Support notes.
64
561a72d4
TC		 652018-05-15 Tamar Christina <tamar.christina@arm.com>
66
67 PR binutils/21446
68 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
69 and take error struct.
70 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
71 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
72 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
73 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
74 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
75 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
76 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
77 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
78 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
79 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
80 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
81 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
82 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
83 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
84 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
85 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
86 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
87 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
88 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
89 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
90 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
91 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
92 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
93 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
94 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
95 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
96 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
97 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
98 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
99 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
100 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
101 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
102 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
103 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
104 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
105 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
106 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
107 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
108 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
109 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
110 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
111 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
112 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
113 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
114 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
115 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
116 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
117 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
118 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
119 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
120 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
121 (determine_disassembling_preference, aarch64_decode_insn,
122 print_insn_aarch64_word, print_insn_data): Take errors struct.
123 (print_insn_aarch64): Use errors.
124 * aarch64-asm-2.c: Regenerate.
125 * aarch64-dis-2.c: Regenerate.
126 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
127 boolean in aarch64_insert_operan.
128 (print_operand_extractor): Likewise.
129 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
130
1678bd35
FT		 1312018-05-15 Francois H. Theron <francois.theron@netronome.com>
132
133 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
134
06cfb1c8
L		 1352018-05-09 H.J. Lu <hongjiu.lu@intel.com>
136
137 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
138
84f9f8c3
AM		 1392018-05-09 Sebastian Rasmussen <sebras@gmail.com>
140
141 * cr16-opc.c (cr16_instruction): Comment typo fix.
142 * hppa-dis.c (print_insn_hppa): Likewise.
143
e6f372ba
JW		 1442018-05-08 Jim Wilson <jimw@sifive.com>
145
146 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
147 (match_c_slli64, match_srxi_as_c_srxi): New.
148 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
149 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
150 <c.slli, c.srli, c.srai>: Use match_s_slli.
151 <c.slli64, c.srli64, c.srai64>: New.
152
f413a913
AM		 1532018-05-08 Alan Modra <amodra@gmail.com>
154
155 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
156 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
157 partition opcode space for index lookup.
158
a87a6478
PB		 1592018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
160
161 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
162 <insn_length>: ...with this. Update usage.
163 Remove duplicate call to *info->memory_error_func.
164
c0a30a9f
L		 1652018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
166 H.J. Lu <hongjiu.lu@intel.com>
167
168 * i386-dis.c (Gva): New.
169 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
170 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
171 (prefix_table): New instructions (see prefix above).
172 (mod_table): New instructions (see prefix above).
173 (OP_G): Handle va_mode.
174 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
175 CPU_MOVDIR64B_FLAGS.
176 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
177 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
178 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
179 * i386-opc.tbl: Add movidir{i,64b}.
180 * i386-init.h: Regenerated.
181 * i386-tbl.h: Likewise.
182
75c0a438
L		 1832018-05-07 H.J. Lu <hongjiu.lu@intel.com>
184
185 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
186 AddrPrefixOpReg.
187 * i386-opc.h (AddrPrefixOp0): Renamed to ...
188 (AddrPrefixOpReg): This.
189 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
190 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
191
2ceb7719
PB		 1922018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
193
194 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
195 (vle_num_opcodes): Likewise.
196 (spe2_num_opcodes): Likewise.
197 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
198 initialization loop.
199 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
200 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
201 only once.
202
b3ac5c6c
TC		 2032018-05-01 Tamar Christina <tamar.christina@arm.com>
204
205 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
206
fe944acf
FT		 2072018-04-30 Francois H. Theron <francois.theron@netronome.com>
208
209 Makefile.am: Added nfp-dis.c.
210 configure.ac: Added bfd_nfp_arch.
211 disassemble.h: Added print_insn_nfp prototype.
212 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
213 nfp-dis.c: New, for NFP support.
214 po/POTFILES.in: Added nfp-dis.c to the list.
215 Makefile.in: Regenerate.
216 configure: Regenerate.
217
e2195274
JB		 2182018-04-26 Jan Beulich <jbeulich@suse.com>
219
220 * i386-opc.tbl: Fold various non-memory operand AVX512VL
221 templates into their base ones.
222 * i386-tlb.h: Re-generate.
223
59ef5df4
JB		 2242018-04-26 Jan Beulich <jbeulich@suse.com>
225
226 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
227 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
228 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
229 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
230 * i386-init.h: Re-generate.
231
6e041cf4
JB		 2322018-04-26 Jan Beulich <jbeulich@suse.com>
233
234 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
235 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
236 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
237 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
238 comment.
239 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
240 and CpuRegMask.
241 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
242 CpuRegMask: Delete.
243 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
244 cpuregzmm, and cpuregmask.
245 * i386-init.h: Re-generate.
246 * i386-tbl.h: Re-generate.
247
0e0eea78
JB		 2482018-04-26 Jan Beulich <jbeulich@suse.com>
249
250 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
251 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
252 * i386-init.h: Re-generate.
253
2f1bada2
JB		 2542018-04-26 Jan Beulich <jbeulich@suse.com>
255
256 * i386-gen.c (VexImmExt): Delete.
257 * i386-opc.h (VexImmExt, veximmext): Delete.
258 * i386-opc.tbl: Drop all VexImmExt uses.
259 * i386-tlb.h: Re-generate.
260
bacd1457
JB		 2612018-04-25 Jan Beulich <jbeulich@suse.com>
262
263 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
264 register-only forms.
265 * i386-tlb.h: Re-generate.
266
10bba94b
TC		 2672018-04-25 Tamar Christina <tamar.christina@arm.com>
268
269 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
270
c48935d7
IT		 2712018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
272
273 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
274 PREFIX_0F1C.
275 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
276 (cpu_flags): Add CpuCLDEMOTE.
277 * i386-init.h: Regenerate.
278 * i386-opc.h (enum): Add CpuCLDEMOTE,
279 (i386_cpu_flags): Add cpucldemote.
280 * i386-opc.tbl: Add cldemote.
281 * i386-tbl.h: Regenerate.
282
211dc24b
AM		 2832018-04-16 Alan Modra <amodra@gmail.com>
284
285 * Makefile.am: Remove sh5 and sh64 support.
286 * configure.ac: Likewise.
287 * disassemble.c: Likewise.
288 * disassemble.h: Likewise.
289 * sh-dis.c: Likewise.
290 * sh64-dis.c: Delete.
291 * sh64-opc.c: Delete.
292 * sh64-opc.h: Delete.
293 * Makefile.in: Regenerate.
294 * configure: Regenerate.
295 * po/POTFILES.in: Regenerate.
296
a9a4b302
AM		 2972018-04-16 Alan Modra <amodra@gmail.com>
298
299 * Makefile.am: Remove w65 support.
300 * configure.ac: Likewise.
301 * disassemble.c: Likewise.
302 * disassemble.h: Likewise.
303 * w65-dis.c: Delete.
304 * w65-opc.h: Delete.
305 * Makefile.in: Regenerate.
306 * configure: Regenerate.
307 * po/POTFILES.in: Regenerate.
308
04cb01fd
AM		 3092018-04-16 Alan Modra <amodra@gmail.com>
310
311 * configure.ac: Remove we32k support.
312 * configure: Regenerate.
313
c2bf1eec
AM		 3142018-04-16 Alan Modra <amodra@gmail.com>
315
316 * Makefile.am: Remove m88k support.
317 * configure.ac: Likewise.
318 * disassemble.c: Likewise.
319 * disassemble.h: Likewise.
320 * m88k-dis.c: Delete.
321 * Makefile.in: Regenerate.
322 * configure: Regenerate.
323 * po/POTFILES.in: Regenerate.
324
6793974d
AM		 3252018-04-16 Alan Modra <amodra@gmail.com>
326
327 * Makefile.am: Remove i370 support.
328 * configure.ac: Likewise.
329 * disassemble.c: Likewise.
330 * disassemble.h: Likewise.
331 * i370-dis.c: Delete.
332 * i370-opc.c: Delete.
333 * Makefile.in: Regenerate.
334 * configure: Regenerate.
335 * po/POTFILES.in: Regenerate.
336
e82aa794
AM		 3372018-04-16 Alan Modra <amodra@gmail.com>
338
339 * Makefile.am: Remove h8500 support.
340 * configure.ac: Likewise.
341 * disassemble.c: Likewise.
342 * disassemble.h: Likewise.
343 * h8500-dis.c: Delete.
344 * h8500-opc.h: Delete.
345 * Makefile.in: Regenerate.
346 * configure: Regenerate.
347 * po/POTFILES.in: Regenerate.
348
fceadf09
AM		 3492018-04-16 Alan Modra <amodra@gmail.com>
350
351 * configure.ac: Remove tahoe support.
352 * configure: Regenerate.
353
ae1d3843
L		 3542018-04-15 H.J. Lu <hongjiu.lu@intel.com>
355
356 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
357 umwait.
358 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
359 64-bit mode.
360 * i386-tbl.h: Regenerated.
361
de89d0a3
IT		 3622018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
363
364 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
365 PREFIX_MOD_1_0FAE_REG_6.
366 (va_mode): New.
367 (OP_E_register): Use va_mode.
368 * i386-dis-evex.h (prefix_table):
369 New instructions (see prefixes above).
370 * i386-gen.c (cpu_flag_init): Add WAITPKG.
371 (cpu_flags): Likewise.
372 * i386-opc.h (enum): Likewise.
373 (i386_cpu_flags): Likewise.
374 * i386-opc.tbl: Add umonitor, umwait, tpause.
375 * i386-init.h: Regenerate.
376 * i386-tbl.h: Likewise.
377
a8eb42a8
AM		 3782018-04-11 Alan Modra <amodra@gmail.com>
379
380 * opcodes/i860-dis.c: Delete.
381 * opcodes/i960-dis.c: Delete.
382 * Makefile.am: Remove i860 and i960 support.
383 * configure.ac: Likewise.
384 * disassemble.c: Likewise.
385 * disassemble.h: Likewise.
386 * Makefile.in: Regenerate.
387 * configure: Regenerate.
388 * po/POTFILES.in: Regenerate.
389
caf0678c
L		 3902018-04-04 H.J. Lu <hongjiu.lu@intel.com>
391
392 PR binutils/23025
393 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
394 to 0.
395 (print_insn): Clear vex instead of vex.evex.
396
4fb0d2b9
NC		 3972018-04-04 Nick Clifton <nickc@redhat.com>
398
399 * po/es.po: Updated Spanish translation.
400
c39e5b26
JB		 4012018-03-28 Jan Beulich <jbeulich@suse.com>
402
403 * i386-gen.c (opcode_modifiers): Delete VecESize.
404 * i386-opc.h (VecESize): Delete.
405 (struct i386_opcode_modifier): Delete vecesize.
406 * i386-opc.tbl: Drop VecESize.
407 * i386-tlb.h: Re-generate.
408
8e6e0792
JB		 4092018-03-28 Jan Beulich <jbeulich@suse.com>
410
411 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
412 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
413 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
414 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
415 * i386-tlb.h: Re-generate.
416
9f123b91
JB		 4172018-03-28 Jan Beulich <jbeulich@suse.com>
418
419 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
420 Fold AVX512 forms
421 * i386-tlb.h: Re-generate.
422
9646c87b
JB		 4232018-03-28 Jan Beulich <jbeulich@suse.com>
424
425 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
426 (vex_len_table): Drop Y for vcvt*2si.
427 (putop): Replace plain 'Y' handling by abort().
428
c8d59609
NC		 4292018-03-28 Nick Clifton <nickc@redhat.com>
430
431 PR 22988
432 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
433 instructions with only a base address register.
434 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
435 handle AARHC64_OPND_SVE_ADDR_R.
436 (aarch64_print_operand): Likewise.
437 * aarch64-asm-2.c: Regenerate.
438 * aarch64_dis-2.c: Regenerate.
439 * aarch64-opc-2.c: Regenerate.
440
b8c169f3
JB		 4412018-03-22 Jan Beulich <jbeulich@suse.com>
442
443 * i386-opc.tbl: Drop VecESize from register only insn forms and
444 memory forms not allowing broadcast.
445 * i386-tlb.h: Re-generate.
446
96bc132a
JB		 4472018-03-22 Jan Beulich <jbeulich@suse.com>
448
449 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
450 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
451 sha256*): Drop Disp<N>.
452
9f79e886
JB		 4532018-03-22 Jan Beulich <jbeulich@suse.com>
454
455 * i386-dis.c (EbndS, bnd_swap_mode): New.
456 (prefix_table): Use EbndS.
457 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
458 * i386-opc.tbl (bndmov): Move misplaced Load.
459 * i386-tlb.h: Re-generate.
460
d6793fa1
JB		 4612018-03-22 Jan Beulich <jbeulich@suse.com>
462
463 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
464 templates allowing memory operands and folded ones for register
465 only flavors.
466 * i386-tlb.h: Re-generate.
467
f7768225
JB		 4682018-03-22 Jan Beulich <jbeulich@suse.com>
469
470 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
471 256-bit templates. Drop redundant leftover Disp<N>.
472 * i386-tlb.h: Re-generate.
473
0e35537d
JW		 4742018-03-14 Kito Cheng <kito.cheng@gmail.com>
475
476 * riscv-opc.c (riscv_insn_types): New.
477
b4a3689a
NC		 4782018-03-13 Nick Clifton <nickc@redhat.com>
479
480 * po/pt_BR.po: Updated Brazilian Portuguese translation.
481
d3d50934
L		 4822018-03-08 H.J. Lu <hongjiu.lu@intel.com>
483
484 * i386-opc.tbl: Add Optimize to clr.
485 * i386-tbl.h: Regenerated.
486
bd5dea88
L		 4872018-03-08 H.J. Lu <hongjiu.lu@intel.com>
488
489 * i386-gen.c (opcode_modifiers): Remove OldGcc.
490 * i386-opc.h (OldGcc): Removed.
491 (i386_opcode_modifier): Remove oldgcc.
492 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
493 instructions for old (<= 2.8.1) versions of gcc.
494 * i386-tbl.h: Regenerated.
495
e771e7c9
JB		 4962018-03-08 Jan Beulich <jbeulich@suse.com>
497
498 * i386-opc.h (EVEXDYN): New.
499 * i386-opc.tbl: Fold various AVX512VL templates.
500 * i386-tlb.h: Re-generate.
501
ed438a93
JB		 5022018-03-08 Jan Beulich <jbeulich@suse.com>
503
504 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
505 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
506 vpexpandd, vpexpandq): Fold AFX512VF templates.
507 * i386-tlb.h: Re-generate.
508
454172a9
JB		 5092018-03-08 Jan Beulich <jbeulich@suse.com>
510
511 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
512 Fold 128- and 256-bit VEX-encoded templates.
513 * i386-tlb.h: Re-generate.
514
36824150
JB		 5152018-03-08 Jan Beulich <jbeulich@suse.com>
516
517 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
518 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
519 vpexpandd, vpexpandq): Fold AVX512F templates.
520 * i386-tlb.h: Re-generate.
521
e7f5c0a9
JB		 5222018-03-08 Jan Beulich <jbeulich@suse.com>
523
524 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
525 64-bit templates. Drop Disp<N>.
526 * i386-tlb.h: Re-generate.
527
25a4277f
JB		 5282018-03-08 Jan Beulich <jbeulich@suse.com>
529
530 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
531 and 256-bit templates.
532 * i386-tlb.h: Re-generate.
533
d2224064
JB		 5342018-03-08 Jan Beulich <jbeulich@suse.com>
535
536 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
537 * i386-tlb.h: Re-generate.
538
1b193f0b
JB		 5392018-03-08 Jan Beulich <jbeulich@suse.com>
540
541 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
542 Drop NoAVX.
543 * i386-tlb.h: Re-generate.
544
f2f6a710
JB		 5452018-03-08 Jan Beulich <jbeulich@suse.com>
546
547 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
548 * i386-tlb.h: Re-generate.
549
38e314eb
JB		 5502018-03-08 Jan Beulich <jbeulich@suse.com>
551
552 * i386-gen.c (opcode_modifiers): Delete FloatD.
553 * i386-opc.h (FloatD): Delete.
554 (struct i386_opcode_modifier): Delete floatd.
555 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
556 FloatD by D.
557 * i386-tlb.h: Re-generate.
558
d53e6b98
JB		 5592018-03-08 Jan Beulich <jbeulich@suse.com>
560
561 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
562
2907c2f5
JB		 5632018-03-08 Jan Beulich <jbeulich@suse.com>
564
565 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
566 * i386-tlb.h: Re-generate.
567
73053c1f
JB		 5682018-03-08 Jan Beulich <jbeulich@suse.com>
569
570 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
571 forms.
572 * i386-tlb.h: Re-generate.
573
52fe4420
AM		 5742018-03-07 Alan Modra <amodra@gmail.com>
575
576 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
577 bfd_arch_rs6000.
578 * disassemble.h (print_insn_rs6000): Delete.
579 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
580 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
581 (print_insn_rs6000): Delete.
582
a6743a54
AM		 5832018-03-03 Alan Modra <amodra@gmail.com>
584
585 * sysdep.h (opcodes_error_handler): Define.
586 (_bfd_error_handler): Declare.
587 * Makefile.am: Remove stray #.
588 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
589 EDIT" comment.
590 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
591 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
592 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
593 opcodes_error_handler to print errors. Standardize error messages.
594 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
595 and include opintl.h.
596 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
597 * i386-gen.c: Standardize error messages.
598 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
599 * Makefile.in: Regenerate.
600 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
601 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
602 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
603 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
604 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
605 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
606 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
607 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
608 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
609 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
610 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
611 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
612 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
613
8305403a
L		 6142018-03-01 H.J. Lu <hongjiu.lu@intel.com>
615
616 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
617 vpsub[bwdq] instructions.
618 * i386-tbl.h: Regenerated.
619
e184813f
AM		 6202018-03-01 Alan Modra <amodra@gmail.com>
621
622 * configure.ac (ALL_LINGUAS): Sort.
623 * configure: Regenerate.
624
5b616bef
TP		 6252018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
626
627 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
628 macro by assignements.
629
b6f8c7c4
L		 6302018-02-27 H.J. Lu <hongjiu.lu@intel.com>
631
632 PR gas/22871
633 * i386-gen.c (opcode_modifiers): Add Optimize.
634 * i386-opc.h (Optimize): New enum.
635 (i386_opcode_modifier): Add optimize.
636 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
637 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
638 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
639 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
640 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
641 vpxord and vpxorq.
642 * i386-tbl.h: Regenerated.
643
e95b887f
AM		 6442018-02-26 Alan Modra <amodra@gmail.com>
645
646 * crx-dis.c (getregliststring): Allocate a large enough buffer
647 to silence false positive gcc8 warning.
648
0bccfb29
JW		 6492018-02-22 Shea Levy <shea@shealevy.com>
650
651 * disassemble.c (ARCH_riscv): Define if ARCH_all.
652
6b6b6807
L		 6532018-02-22 H.J. Lu <hongjiu.lu@intel.com>
654
655 * i386-opc.tbl: Add {rex},
656 * i386-tbl.h: Regenerated.
657
75f31665
MR		 6582018-02-20 Maciej W. Rozycki <macro@mips.com>
659
660 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
661 (mips16_opcodes): Replace `M' with `m' for "restore".
662
e207bc53
TP		 6632018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
664
665 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
666
87993319
MR		 6672018-02-13 Maciej W. Rozycki <macro@mips.com>
668
669 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
670 variable to `function_index'.
671
68d20676
NC		 6722018-02-13 Nick Clifton <nickc@redhat.com>
673
674 PR 22823
675 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
676 about truncation of printing.
677
d2159fdc
HW		 6782018-02-12 Henry Wong <henry@stuffedcow.net>
679
680 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
681
f174ef9f
NC		 6822018-02-05 Nick Clifton <nickc@redhat.com>
683
684 * po/pt_BR.po: Updated Brazilian Portuguese translation.
685
be3a8dca
IT		 6862018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
687
688 * i386-dis.c (enum): Add pconfig.
689 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
690 (cpu_flags): Add CpuPCONFIG.
691 * i386-opc.h (enum): Add CpuPCONFIG.
692 (i386_cpu_flags): Add cpupconfig.
693 * i386-opc.tbl: Add PCONFIG instruction.
694 * i386-init.h: Regenerate.
695 * i386-tbl.h: Likewise.
696
3233d7d0
IT		 6972018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
698
699 * i386-dis.c (enum): Add PREFIX_0F09.
700 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
701 (cpu_flags): Add CpuWBNOINVD.
702 * i386-opc.h (enum): Add CpuWBNOINVD.
703 (i386_cpu_flags): Add cpuwbnoinvd.
704 * i386-opc.tbl: Add WBNOINVD instruction.
705 * i386-init.h: Regenerate.
706 * i386-tbl.h: Likewise.
707
e925c834
JW		 7082018-01-17 Jim Wilson <jimw@sifive.com>
709
710 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
711
d777820b
IT		 7122018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
713
714 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
715 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
716 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
717 (cpu_flags): Add CpuIBT, CpuSHSTK.
718 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
719 (i386_cpu_flags): Add cpuibt, cpushstk.
720 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
721 * i386-init.h: Regenerate.
722 * i386-tbl.h: Likewise.
723
f6efed01
NC		 7242018-01-16 Nick Clifton <nickc@redhat.com>
725
726 * po/pt_BR.po: Updated Brazilian Portugese translation.
727 * po/de.po: Updated German translation.
728
2721d702
JW		 7292018-01-15 Jim Wilson <jimw@sifive.com>
730
731 * riscv-opc.c (match_c_nop): New.
732 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
733
616dcb87
NC		 7342018-01-15 Nick Clifton <nickc@redhat.com>
735
736 * po/uk.po: Updated Ukranian translation.
737
3957a496
NC		 7382018-01-13 Nick Clifton <nickc@redhat.com>
739
740 * po/opcodes.pot: Regenerated.
741
769c7ea5
NC		 7422018-01-13 Nick Clifton <nickc@redhat.com>
743
744 * configure: Regenerate.
745
faf766e3
NC		 7462018-01-13 Nick Clifton <nickc@redhat.com>
747
748 2.30 branch created.
749
888a89da
IT		 7502018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
751
752 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
753 * i386-tbl.h: Regenerate.
754
cbda583a
JB		 7552018-01-10 Jan Beulich <jbeulich@suse.com>
756
757 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
758 * i386-tbl.h: Re-generate.
759
c9e92278
JB		 7602018-01-10 Jan Beulich <jbeulich@suse.com>
761
762 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
763 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
764 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
765 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
766 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
767 Disp8MemShift of AVX512VL forms.
768 * i386-tbl.h: Re-generate.
769
35fd2b2b
JW		 7702018-01-09 Jim Wilson <jimw@sifive.com>
771
772 * riscv-dis.c (maybe_print_address): If base_reg is zero,
773 then the hi_addr value is zero.
774
91d8b670
JG		 7752018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
776
777 * arm-dis.c (arm_opcodes): Add csdb.
778 (thumb32_opcodes): Add csdb.
779
be2e7d95
JG		 7802018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
781
782 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
783 * aarch64-asm-2.c: Regenerate.
784 * aarch64-dis-2.c: Regenerate.
785 * aarch64-opc-2.c: Regenerate.
786
704a705d
L		 7872018-01-08 H.J. Lu <hongjiu.lu@intel.com>
788
789 PR gas/22681
790 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
791 Remove AVX512 vmovd with 64-bit operands.
792 * i386-tbl.h: Regenerated.
793
35eeb78f
JW		 7942018-01-05 Jim Wilson <jimw@sifive.com>
795
796 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
797 jalr.
798
219d1afa
AM		 7992018-01-03 Alan Modra <amodra@gmail.com>
800
801 Update year range in copyright notice of all files.
802
1508bbf5
JB		 8032018-01-02 Jan Beulich <jbeulich@suse.com>
804
805 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
806 and OPERAND_TYPE_REGZMM entries.
807
1e563868 808For older changes see ChangeLog-2017
3499769a 809\f
1e563868 810Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 811
812Copying and distribution of this file, with or without modification,
813are permitted in any medium without royalty provided the copyright
814notice and this notice are preserved.
815
816Local Variables:
817mode: change-log
818left-margin: 8
819fill-column: 74
820version-control: never
821End:
GDB Binutils - Deliverables
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