[binutils][aarch64] SVE2 feature extension flags.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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12019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2
3 * aarch64-tbl.h
4 (aarch64_feature_sve2, aarch64_feature_sve2aes,
5 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
6 aarch64_feature_sve2bitperm): New feature sets.
7 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
8 for feature set addresses.
9 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
10 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
11
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122019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
13 Faraz Shahbazker <fshahbazker@wavecomp.com>
14
15 * mips-dis.c (mips_calculate_combination_ases): Add ISA
16 argument and set ASE_EVA_R6 appropriately.
17 (set_default_mips_dis_options): Pass ISA to above.
18 (parse_mips_dis_option): Likewise.
19 * mips-opc.c (EVAR6): New macro.
20 (mips_builtin_opcodes): Add llwpe, scwpe.
21
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222019-05-01 Sudakshina Das <sudi.das@arm.com>
23
24 * aarch64-asm-2.c: Regenerated.
25 * aarch64-dis-2.c: Regenerated.
26 * aarch64-opc-2.c: Regenerated.
27 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
28 AARCH64_OPND_TME_UIMM16.
29 (aarch64_print_operand): Likewise.
30 * aarch64-tbl.h (QL_IMM_NIL): New.
31 (TME): New.
32 (_TME_INSN): New.
33 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
34
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352019-04-29 John Darrington <john@darrington.wattle.id.au>
36
37 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
38
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392019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
40 Faraz Shahbazker <fshahbazker@wavecomp.com>
41
42 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
43
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442019-04-24 John Darrington <john@darrington.wattle.id.au>
45
46 * s12z-opc.h: Add extern "C" bracketing to help
47 users who wish to use this interface in c++ code.
48
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492019-04-24 John Darrington <john@darrington.wattle.id.au>
50
51 * s12z-opc.c (bm_decode): Handle bit map operations with the
52 "reserved0" mode.
53
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542019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
55
56 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
57 specifier. Add entries for VLDR and VSTR of system registers.
58 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
59 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
60 of %J and %K format specifier.
61
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622019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
63
64 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
65 Add new entries for VSCCLRM instruction.
66 (print_insn_coprocessor): Handle new %C format control code.
67
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682019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
69
70 * arm-dis.c (enum isa): New enum.
71 (struct sopcode32): New structure.
72 (coprocessor_opcodes): change type of entries to struct sopcode32 and
73 set isa field of all current entries to ANY.
74 (print_insn_coprocessor): Change type of insn to struct sopcode32.
75 Only match an entry if its isa field allows the current mode.
76
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772019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
78
79 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
80 CLRM.
81 (print_insn_thumb32): Add logic to print %n CLRM register list.
82
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832019-04-15 Sudakshina Das <sudi.das@arm.com>
84
85 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
86 and %Q patterns.
87
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882019-04-15 Sudakshina Das <sudi.das@arm.com>
89
90 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
91 (print_insn_thumb32): Edit the switch case for %Z.
92
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932019-04-15 Sudakshina Das <sudi.das@arm.com>
94
95 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
96
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972019-04-15 Sudakshina Das <sudi.das@arm.com>
98
99 * arm-dis.c (thumb32_opcodes): New instruction bfl.
100
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1012019-04-15 Sudakshina Das <sudi.das@arm.com>
102
103 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
104
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1052019-04-15 Sudakshina Das <sudi.das@arm.com>
106
107 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
108 Arm register with r13 and r15 unpredictable.
109 (thumb32_opcodes): New instructions for bfx and bflx.
110
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1112019-04-15 Sudakshina Das <sudi.das@arm.com>
112
113 * arm-dis.c (thumb32_opcodes): New instructions for bf.
114
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1152019-04-15 Sudakshina Das <sudi.das@arm.com>
116
117 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
118
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1192019-04-15 Sudakshina Das <sudi.das@arm.com>
120
121 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
122
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1232019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
124
125 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
126
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1272019-04-12 John Darrington <john@darrington.wattle.id.au>
128
129 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
130 "optr". ("operator" is a reserved word in c++).
131
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1322019-04-11 Sudakshina Das <sudi.das@arm.com>
133
134 * aarch64-opc.c (aarch64_print_operand): Add case for
135 AARCH64_OPND_Rt_SP.
136 (verify_constraints): Likewise.
137 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
138 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
139 to accept Rt|SP as first operand.
140 (AARCH64_OPERANDS): Add new Rt_SP.
141 * aarch64-asm-2.c: Regenerated.
142 * aarch64-dis-2.c: Regenerated.
143 * aarch64-opc-2.c: Regenerated.
144
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1452019-04-11 Sudakshina Das <sudi.das@arm.com>
146
147 * aarch64-asm-2.c: Regenerated.
148 * aarch64-dis-2.c: Likewise.
149 * aarch64-opc-2.c: Likewise.
150 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
151
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1522019-04-09 Robert Suchanek <robert.suchanek@mips.com>
153
154 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
155
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1562019-04-08 H.J. Lu <hongjiu.lu@intel.com>
157
158 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
159 * i386-init.h: Regenerated.
160
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1612019-04-07 Alan Modra <amodra@gmail.com>
162
163 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
164 op_separator to control printing of spaces, comma and parens
165 rather than need_comma, need_paren and spaces vars.
166
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1672019-04-07 Alan Modra <amodra@gmail.com>
168
169 PR 24421
170 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
171 (print_insn_neon, print_insn_arm): Likewise.
172
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1732019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
174
175 * i386-dis-evex.h (evex_table): Updated to support BF16
176 instructions.
177 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
178 and EVEX_W_0F3872_P_3.
179 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
180 (cpu_flags): Add bitfield for CpuAVX512_BF16.
181 * i386-opc.h (enum): Add CpuAVX512_BF16.
182 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
183 * i386-opc.tbl: Add AVX512 BF16 instructions.
184 * i386-init.h: Regenerated.
185 * i386-tbl.h: Likewise.
186
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1872019-04-05 Alan Modra <amodra@gmail.com>
188
189 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
190 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
191 to favour printing of "-" branch hint when using the "y" bit.
192 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
193
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1942019-04-05 Alan Modra <amodra@gmail.com>
195
196 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
197 opcode until first operand is output.
198
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1992019-04-04 Peter Bergner <bergner@linux.ibm.com>
200
201 PR gas/24349
202 * ppc-opc.c (valid_bo_pre_v2): Add comments.
203 (valid_bo_post_v2): Add support for 'at' branch hints.
204 (insert_bo): Only error on branch on ctr.
205 (get_bo_hint_mask): New function.
206 (insert_boe): Add new 'branch_taken' formal argument. Add support
207 for inserting 'at' branch hints.
208 (extract_boe): Add new 'branch_taken' formal argument. Add support
209 for extracting 'at' branch hints.
210 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
211 (BOE): Delete operand.
212 (BOM, BOP): New operands.
213 (RM): Update value.
214 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
215 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
216 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
217 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
218 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
219 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
220 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
221 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
222 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
223 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
224 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
225 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
226 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
227 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
228 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
229 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
230 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
231 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
232 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
233 bttarl+>: New extended mnemonics.
234
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2352019-03-28 Alan Modra <amodra@gmail.com>
236
237 PR 24390
238 * ppc-opc.c (BTF): Define.
239 (powerpc_opcodes): Use for mtfsb*.
240 * ppc-dis.c (print_insn_powerpc): Print fields with both
241 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
242
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2432019-03-25 Tamar Christina <tamar.christina@arm.com>
244
245 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
246 (mapping_symbol_for_insn): Implement new algorithm.
247 (print_insn): Remove duplicate code.
248
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2492019-03-25 Tamar Christina <tamar.christina@arm.com>
250
251 * aarch64-dis.c (print_insn_aarch64):
252 Implement override.
253
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2542019-03-25 Tamar Christina <tamar.christina@arm.com>
255
256 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
257 order.
258
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2592019-03-25 Tamar Christina <tamar.christina@arm.com>
260
261 * aarch64-dis.c (last_stop_offset): New.
262 (print_insn_aarch64): Use stop_offset.
263
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2642019-03-19 H.J. Lu <hongjiu.lu@intel.com>
265
266 PR gas/24359
267 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
268 CPU_ANY_AVX2_FLAGS.
269 * i386-init.h: Regenerated.
270
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2712019-03-18 H.J. Lu <hongjiu.lu@intel.com>
272
273 PR gas/24348
274 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
275 vmovdqu16, vmovdqu32 and vmovdqu64.
276 * i386-tbl.h: Regenerated.
277
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2782019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
279
280 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
281 from vstrszb, vstrszh, and vstrszf.
282
2832019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
284
285 * s390-opc.txt: Add instruction descriptions.
286
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2872019-02-08 Jim Wilson <jimw@sifive.com>
288
289 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
290 <bne>: Likewise.
291
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2922019-02-07 Tamar Christina <tamar.christina@arm.com>
293
294 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
295
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2962019-02-07 Tamar Christina <tamar.christina@arm.com>
297
298 PR binutils/23212
299 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
300 * aarch64-opc.c (verify_elem_sd): New.
301 (fields): Add FLD_sz entr.
302 * aarch64-tbl.h (_SIMD_INSN): New.
303 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
304 fmulx scalar and vector by element isns.
305
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3062019-02-07 Nick Clifton <nickc@redhat.com>
307
308 * po/sv.po: Updated Swedish translation.
309
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3102019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
311
312 * s390-mkopc.c (main): Accept arch13 as cpu string.
313 * s390-opc.c: Add new instruction formats and instruction opcode
314 masks.
315 * s390-opc.txt: Add new arch13 instructions.
316
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3172019-01-25 Sudakshina Das <sudi.das@arm.com>
318
319 * aarch64-tbl.h (QL_LDST_AT): Update macro.
320 (aarch64_opcode): Change encoding for stg, stzg
321 st2g and st2zg.
322 * aarch64-asm-2.c: Regenerated.
323 * aarch64-dis-2.c: Regenerated.
324 * aarch64-opc-2.c: Regenerated.
325
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3262019-01-25 Sudakshina Das <sudi.das@arm.com>
327
328 * aarch64-asm-2.c: Regenerated.
329 * aarch64-dis-2.c: Likewise.
330 * aarch64-opc-2.c: Likewise.
331 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
332
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3332019-01-25 Sudakshina Das <sudi.das@arm.com>
334 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
335
336 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
337 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
338 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
339 * aarch64-dis.h (ext_addr_simple_2): Likewise.
340 * aarch64-opc.c (operand_general_constraint_met_p): Remove
341 case for ldstgv_indexed.
342 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
343 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
344 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
345 * aarch64-asm-2.c: Regenerated.
346 * aarch64-dis-2.c: Regenerated.
347 * aarch64-opc-2.c: Regenerated.
348
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3492019-01-23 Nick Clifton <nickc@redhat.com>
350
351 * po/pt_BR.po: Updated Brazilian Portuguese translation.
352
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3532019-01-21 Nick Clifton <nickc@redhat.com>
354
355 * po/de.po: Updated German translation.
356 * po/uk.po: Updated Ukranian translation.
357
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3582019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
359 * mips-dis.c (mips_arch_choices): Fix typo in
360 gs464, gs464e and gs264e descriptors.
361
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3622019-01-19 Nick Clifton <nickc@redhat.com>
363
364 * configure: Regenerate.
365 * po/opcodes.pot: Regenerate.
366
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3672018-06-24 Nick Clifton <nickc@redhat.com>
368
369 2.32 branch created.
370
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3712019-01-09 John Darrington <john@darrington.wattle.id.au>
372
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373 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
374 if it is null.
375 -dis.c (opr_emit_disassembly): Do not omit an index if it is
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376 zero.
377
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3782019-01-09 Andrew Paprocki <andrew@ishiboo.com>
379
380 * configure: Regenerate.
381
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3822019-01-07 Alan Modra <amodra@gmail.com>
383
384 * configure: Regenerate.
385 * po/POTFILES.in: Regenerate.
386
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3872019-01-03 John Darrington <john@darrington.wattle.id.au>
388
389 * s12z-opc.c: New file.
390 * s12z-opc.h: New file.
391 * s12z-dis.c: Removed all code not directly related to display
392 of instructions. Used the interface provided by the new files
393 instead.
394 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 395 * Makefile.in: Regenerate.
ef1ad42b 396 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 397 * configure: Regenerate.
ef1ad42b 398
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3992019-01-01 Alan Modra <amodra@gmail.com>
400
401 Update year range in copyright notice of all files.
402
d5c04e1b 403For older changes see ChangeLog-2018
3499769a 404\f
d5c04e1b 405Copyright (C) 2019 Free Software Foundation, Inc.
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406
407Copying and distribution of this file, with or without modification,
408are permitted in any medium without royalty provided the copyright
409notice and this notice are preserved.
410
411Local Variables:
412mode: change-log
413left-margin: 8
414fill-column: 74
415version-control: never
416End:
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