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fork-child.c: Avoid unnecessary heap-allocation / string copying
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
9a85b496
AM		 12017-04-11 Alan Modra <amodra@gmail.com>
2
ef85eab0 3 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 4 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
5 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 6 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
7 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 8 (PPCVSX2): Define as PPC_OPCODE_POWER8.
9 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 10 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 11 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 12
62adc510
AM		 132017-04-10 Alan Modra <amodra@gmail.com>
14
15 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
16 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
17 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
18 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
19
aa808707
PC		 202017-04-09 Pip Cet <pipcet@gmail.com>
21
22 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
23 appropriate floating-point precision directly.
24
ac8f0f72
AM		 252017-04-07 Alan Modra <amodra@gmail.com>
26
27 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
28 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
29 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
30 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
31 vector instructions with E6500 not PPCVEC2.
32
62ecb94c
PC		 332017-04-06 Pip Cet <pipcet@gmail.com>
34
35 * Makefile.am: Add wasm32-dis.c.
36 * configure.ac: Add wasm32-dis.c to wasm32 target.
37 * disassemble.c: Add wasm32 disassembler code.
38 * wasm32-dis.c: New file.
39 * Makefile.in: Regenerate.
40 * configure: Regenerate.
41 * po/POTFILES.in: Regenerate.
42 * po/opcodes.pot: Regenerate.
43
f995bbe8
PA		 442017-04-05 Pedro Alves <palves@redhat.com>
45
46 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
47 * arm-dis.c (parse_arm_disassembler_options): Constify.
48 * ppc-dis.c (powerpc_init_dialect): Constify local.
49 * vax-dis.c (parse_disassembler_options): Constify.
50
b5292032
PD		 512017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
52
53 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
54 RISCV_GP_SYMBOL.
55
f96bd6c2
PC		 562017-03-30 Pip Cet <pipcet@gmail.com>
57
58 * configure.ac: Add (empty) bfd_wasm32_arch target.
59 * configure: Regenerate
60 * po/opcodes.pot: Regenerate.
61
f7c514a3
JM		 622017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
63
64 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
65 OSA2015.
66 * opcodes/sparc-opc.c (asi_table): New ASIs.
67
52be03fd
AM		 682017-03-29 Alan Modra <amodra@gmail.com>
69
70 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
71 "raw" option.
72 (lookup_powerpc): Don't special case -1 dialect. Handle
73 PPC_OPCODE_RAW.
74 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
75 lookup_powerpc call, pass it on second.
76
9b753937
AM		 772017-03-27 Alan Modra <amodra@gmail.com>
78
79 PR 21303
80 * ppc-dis.c (struct ppc_mopt): Comment.
81 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
82
c0c31e91
RZ		 832017-03-27 Rinat Zelig <rinat@mellanox.com>
84
85 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
86 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
87 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
88 (insert_nps_misc_imm_offset): New function.
89 (extract_nps_misc imm_offset): New function.
90 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
91 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
92
2253c8f0
AK		 932017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
94
95 * s390-mkopc.c (main): Remove vx2 check.
96 * s390-opc.txt: Remove vx2 instruction flags.
97
645d3342
RZ		 982017-03-21 Rinat Zelig <rinat@mellanox.com>
99
100 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
101 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
102 (insert_nps_imm_offset): New function.
103 (extract_nps_imm_offset): New function.
104 (insert_nps_imm_entry): New function.
105 (extract_nps_imm_entry): New function.
106
4b94dd2d
AM		 1072017-03-17 Alan Modra <amodra@gmail.com>
108
109 PR 21248
110 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
111 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
112 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
113
b416fe87
KC		 1142017-03-14 Kito Cheng <kito.cheng@gmail.com>
115
116 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
117 <c.andi>: Likewise.
118 <c.addiw> Likewise.
119
03b039a5
KC		 1202017-03-14 Kito Cheng <kito.cheng@gmail.com>
121
122 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
123
2c232b83
AW		 1242017-03-13 Andrew Waterman <andrew@sifive.com>
125
126 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
127 <srl> Likewise.
128 <srai> Likewise.
129 <sra> Likewise.
130
86fa6981
L		 1312017-03-09 H.J. Lu <hongjiu.lu@intel.com>
132
133 * i386-gen.c (opcode_modifiers): Replace S with Load.
134 * i386-opc.h (S): Removed.
135 (Load): New.
136 (i386_opcode_modifier): Replace s with load.
137 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
138 and {evex}. Replace S with Load.
139 * i386-tbl.h: Regenerated.
140
c1fe188b
L		 1412017-03-09 H.J. Lu <hongjiu.lu@intel.com>
142
143 * i386-opc.tbl: Use CpuCET on rdsspq.
144 * i386-tbl.h: Regenerated.
145
4b8b687e
PB		 1462017-03-08 Peter Bergner <bergner@vnet.ibm.com>
147
148 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
149 <vsx>: Do not use PPC_OPCODE_VSX3;
150
1437d063
PB		 1512017-03-08 Peter Bergner <bergner@vnet.ibm.com>
152
153 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
154
603555e5
L		 1552017-03-06 H.J. Lu <hongjiu.lu@intel.com>
156
157 * i386-dis.c (REG_0F1E_MOD_3): New enum.
158 (MOD_0F1E_PREFIX_1): Likewise.
159 (MOD_0F38F5_PREFIX_2): Likewise.
160 (MOD_0F38F6_PREFIX_0): Likewise.
161 (RM_0F1E_MOD_3_REG_7): Likewise.
162 (PREFIX_MOD_0_0F01_REG_5): Likewise.
163 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
164 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
165 (PREFIX_0F1E): Likewise.
166 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
167 (PREFIX_0F38F5): Likewise.
168 (dis386_twobyte): Use PREFIX_0F1E.
169 (reg_table): Add REG_0F1E_MOD_3.
170 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
171 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
172 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
173 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
174 (three_byte_table): Use PREFIX_0F38F5.
175 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
176 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
177 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
178 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
179 PREFIX_MOD_3_0F01_REG_5_RM_2.
180 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
181 (cpu_flags): Add CpuCET.
182 * i386-opc.h (CpuCET): New enum.
183 (CpuUnused): Commented out.
184 (i386_cpu_flags): Add cpucet.
185 * i386-opc.tbl: Add Intel CET instructions.
186 * i386-init.h: Regenerated.
187 * i386-tbl.h: Likewise.
188
73f07bff
AM		 1892017-03-06 Alan Modra <amodra@gmail.com>
190
191 PR 21124
192 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
193 (extract_raq, extract_ras, extract_rbx): New functions.
194 (powerpc_operands): Use opposite corresponding insert function.
195 (Q_MASK): Define.
196 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
197 register restriction.
198
65b48a81
PB		 1992017-02-28 Peter Bergner <bergner@vnet.ibm.com>
200
201 * disassemble.c Include "safe-ctype.h".
202 (disassemble_init_for_target): Handle s390 init.
203 (remove_whitespace_and_extra_commas): New function.
204 (disassembler_options_cmp): Likewise.
205 * arm-dis.c: Include "libiberty.h".
206 (NUM_ELEM): Delete.
207 (regnames): Use long disassembler style names.
208 Add force-thumb and no-force-thumb options.
209 (NUM_ARM_REGNAMES): Rename from this...
210 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
211 (get_arm_regname_num_options): Delete.
212 (set_arm_regname_option): Likewise.
213 (get_arm_regnames): Likewise.
214 (parse_disassembler_options): Likewise.
215 (parse_arm_disassembler_option): Rename from this...
216 (parse_arm_disassembler_options): ...to this. Make static.
217 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
218 (print_insn): Use parse_arm_disassembler_options.
219 (disassembler_options_arm): New function.
220 (print_arm_disassembler_options): Handle updated regnames.
221 * ppc-dis.c: Include "libiberty.h".
222 (ppc_opts): Add "32" and "64" entries.
223 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
224 (powerpc_init_dialect): Add break to switch statement.
225 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
226 (disassembler_options_powerpc): New function.
227 (print_ppc_disassembler_options): Use ARRAY_SIZE.
228 Remove printing of "32" and "64".
229 * s390-dis.c: Include "libiberty.h".
230 (init_flag): Remove unneeded variable.
231 (struct s390_options_t): New structure type.
232 (options): New structure.
233 (init_disasm): Rename from this...
234 (disassemble_init_s390): ...to this. Add initializations for
235 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
236 (print_insn_s390): Delete call to init_disasm.
237 (disassembler_options_s390): New function.
238 (print_s390_disassembler_options): Print using information from
239 struct 'options'.
240 * po/opcodes.pot: Regenerate.
241
15c7c1d8
JB		 2422017-02-28 Jan Beulich <jbeulich@suse.com>
243
244 * i386-dis.c (PCMPESTR_Fixup): New.
245 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
246 (prefix_table): Use PCMPESTR_Fixup.
247 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
248 PCMPESTR_Fixup.
249 (vex_w_table): Delete VPCMPESTR{I,M} entries.
250 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
251 Split 64-bit and non-64-bit variants.
252 * opcodes/i386-tbl.h: Re-generate.
253
582e12bf
RS		 2542017-02-24 Richard Sandiford <richard.sandiford@arm.com>
255
256 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
257 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
258 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
259 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
260 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
261 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
262 (OP_SVE_V_HSD): New macros.
263 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
264 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
265 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
266 (aarch64_opcode_table): Add new SVE instructions.
267 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
268 for rotation operands. Add new SVE operands.
269 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
270 (ins_sve_quad_index): Likewise.
271 (ins_imm_rotate): Split into...
272 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
273 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
274 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
275 functions.
276 (aarch64_ins_sve_addr_ri_s4): New function.
277 (aarch64_ins_sve_quad_index): Likewise.
278 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
279 * aarch64-asm-2.c: Regenerate.
280 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
281 (ext_sve_quad_index): Likewise.
282 (ext_imm_rotate): Split into...
283 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
284 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
285 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
286 functions.
287 (aarch64_ext_sve_addr_ri_s4): New function.
288 (aarch64_ext_sve_quad_index): Likewise.
289 (aarch64_ext_sve_index): Allow quad indices.
290 (do_misc_decoding): Likewise.
291 * aarch64-dis-2.c: Regenerate.
292 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
293 aarch64_field_kinds.
294 (OPD_F_OD_MASK): Widen by one bit.
295 (OPD_F_NO_ZR): Bump accordingly.
296 (get_operand_field_width): New function.
297 * aarch64-opc.c (fields): Add new SVE fields.
298 (operand_general_constraint_met_p): Handle new SVE operands.
299 (aarch64_print_operand): Likewise.
300 * aarch64-opc-2.c: Regenerate.
301
f482d304
RS		 3022017-02-24 Richard Sandiford <richard.sandiford@arm.com>
303
304 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
305 (aarch64_feature_compnum): ...this.
306 (SIMD_V8_3): Replace with...
307 (COMPNUM): ...this.
308 (CNUM_INSN): New macro.
309 (aarch64_opcode_table): Use it for the complex number instructions.
310
7db2c588
JB		 3112017-02-24 Jan Beulich <jbeulich@suse.com>
312
313 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
314
1e9d41d4
SL		 3152017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
316
317 Add support for associating SPARC ASIs with an architecture level.
318 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
319 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
320 decoding of SPARC ASIs.
321
53c4d625
JB		 3222017-02-23 Jan Beulich <jbeulich@suse.com>
323
324 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
325 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
326
11648de5
JB		 3272017-02-21 Jan Beulich <jbeulich@suse.com>
328
329 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
330 1 (instead of to itself). Correct typo.
331
f98d33be
AW		 3322017-02-14 Andrew Waterman <andrew@sifive.com>
333
334 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
335 pseudoinstructions.
336
773fb663
RS		 3372017-02-15 Richard Sandiford <richard.sandiford@arm.com>
338
339 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
340 (aarch64_sys_reg_supported_p): Handle them.
341
cc07cda6
CZ		 3422017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
343
344 * arc-opc.c (UIMM6_20R): Define.
345 (SIMM12_20): Use above.
346 (SIMM12_20R): Define.
347 (SIMM3_5_S): Use above.
348 (UIMM7_A32_11R_S): Define.
349 (UIMM7_9_S): Use above.
350 (UIMM3_13R_S): Define.
351 (SIMM11_A32_7_S): Use above.
352 (SIMM9_8R): Define.
353 (UIMM10_A32_8_S): Use above.
354 (UIMM8_8R_S): Define.
355 (W6): Use above.
356 (arc_relax_opcodes): Use all above defines.
357
66a5a740
VG		 3582017-02-15 Vineet Gupta <vgupta@synopsys.com>
359
360 * arc-regs.h: Distinguish some of the registers different on
361 ARC700 and HS38 cpus.
362
7e0de605
AM		 3632017-02-14 Alan Modra <amodra@gmail.com>
364
365 PR 21118
366 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
367 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
368
54064fdb
AM		 3692017-02-11 Stafford Horne <shorne@gmail.com>
370 Alan Modra <amodra@gmail.com>
371
372 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
373 Use insn_bytes_value and insn_int_value directly instead. Don't
374 free allocated memory until function exit.
375
dce75bf9
NP		 3762017-02-10 Nicholas Piggin <npiggin@gmail.com>
377
378 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
379
1b7e3d2f
NC		 3802017-02-03 Nick Clifton <nickc@redhat.com>
381
382 PR 21096
383 * aarch64-opc.c (print_register_list): Ensure that the register
384 list index will fir into the tb buffer.
385 (print_register_offset_address): Likewise.
386 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
387
8ec5cf65
AD		 3882017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
389
390 PR 21056
391 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
392 instructions when the previous fetch packet ends with a 32-bit
393 instruction.
394
a1aa5e81
DD		 3952017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
396
397 * pru-opc.c: Remove vague reference to a future GDB port.
398
add3afb2
NC		 3992017-01-20 Nick Clifton <nickc@redhat.com>
400
401 * po/ga.po: Updated Irish translation.
402
c13a63b0
SN		 4032017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
404
405 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
406
9608051a
YQ		 4072017-01-13 Yao Qi <yao.qi@linaro.org>
408
409 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
410 if FETCH_DATA returns 0.
411 (m68k_scan_mask): Likewise.
412 (print_insn_m68k): Update code to handle -1 return value.
413
f622ea96
YQ		 4142017-01-13 Yao Qi <yao.qi@linaro.org>
415
416 * m68k-dis.c (enum print_insn_arg_error): New.
417 (NEXTBYTE): Replace -3 with
418 PRINT_INSN_ARG_MEMORY_ERROR.
419 (NEXTULONG): Likewise.
420 (NEXTSINGLE): Likewise.
421 (NEXTDOUBLE): Likewise.
422 (NEXTDOUBLE): Likewise.
423 (NEXTPACKED): Likewise.
424 (FETCH_ARG): Likewise.
425 (FETCH_DATA): Update comments.
426 (print_insn_arg): Update comments. Replace magic numbers with
427 enum.
428 (match_insn_m68k): Likewise.
429
620214f7
IT		 4302017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
431
432 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
433 * i386-dis-evex.h (evex_table): Updated.
434 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
435 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
436 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
437 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
438 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
439 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
440 * i386-init.h: Regenerate.
441 * i386-tbl.h: Ditto.
442
d95014a2
YQ		 4432017-01-12 Yao Qi <yao.qi@linaro.org>
444
445 * msp430-dis.c (msp430_singleoperand): Return -1 if
446 msp430dis_opcode_signed returns false.
447 (msp430_doubleoperand): Likewise.
448 (msp430_branchinstr): Return -1 if
449 msp430dis_opcode_unsigned returns false.
450 (msp430x_calla_instr): Likewise.
451 (print_insn_msp430): Likewise.
452
0ae60c3e
NC		 4532017-01-05 Nick Clifton <nickc@redhat.com>
454
455 PR 20946
456 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
457 could not be matched.
458 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
459 NULL.
460
d74d4880
SN		 4612017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
462
463 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
464 (aarch64_opcode_table): Use RCPC_INSN.
465
cc917fd9
KC		 4662017-01-03 Kito Cheng <kito.cheng@gmail.com>
467
468 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
469 extension.
470 * riscv-opcodes/all-opcodes: Likewise.
471
b52d3cfc
DP		 4722017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
473
474 * riscv-dis.c (print_insn_args): Add fall through comment.
475
f90c58d5
NC		 4762017-01-03 Nick Clifton <nickc@redhat.com>
477
478 * po/sr.po: New Serbian translation.
479 * configure.ac (ALL_LINGUAS): Add sr.
480 * configure: Regenerate.
481
f47b0d4a
AM		 4822017-01-02 Alan Modra <amodra@gmail.com>
483
484 * epiphany-desc.h: Regenerate.
485 * epiphany-opc.h: Regenerate.
486 * fr30-desc.h: Regenerate.
487 * fr30-opc.h: Regenerate.
488 * frv-desc.h: Regenerate.
489 * frv-opc.h: Regenerate.
490 * ip2k-desc.h: Regenerate.
491 * ip2k-opc.h: Regenerate.
492 * iq2000-desc.h: Regenerate.
493 * iq2000-opc.h: Regenerate.
494 * lm32-desc.h: Regenerate.
495 * lm32-opc.h: Regenerate.
496 * m32c-desc.h: Regenerate.
497 * m32c-opc.h: Regenerate.
498 * m32r-desc.h: Regenerate.
499 * m32r-opc.h: Regenerate.
500 * mep-desc.h: Regenerate.
501 * mep-opc.h: Regenerate.
502 * mt-desc.h: Regenerate.
503 * mt-opc.h: Regenerate.
504 * or1k-desc.h: Regenerate.
505 * or1k-opc.h: Regenerate.
506 * xc16x-desc.h: Regenerate.
507 * xc16x-opc.h: Regenerate.
508 * xstormy16-desc.h: Regenerate.
509 * xstormy16-opc.h: Regenerate.
510
2571583a
AM		 5112017-01-02 Alan Modra <amodra@gmail.com>
512
513 Update year range in copyright notice of all files.
514
5c1ad6b5 515For older changes see ChangeLog-2016
3499769a 516\f
5c1ad6b5 517Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 518
519Copying and distribution of this file, with or without modification,
520are permitted in any medium without royalty provided the copyright
521notice and this notice are preserved.
522
523Local Variables:
524mode: change-log
525left-margin: 8
526fill-column: 74
527version-control: never
528End:
GDB Binutils - Deliverables
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