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MIPS/opcodes: Reorder ELF file header flag handling in disassembler
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
8184783a
MR		 12016-12-14 Maciej W. Rozycki <macro@imgtec.com>
2
3 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
4 header flag interpretation code.
5
353abf7c
MR		 62016-12-14 Maciej W. Rozycki <macro@imgtec.com>
7
8 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
9 `pinfo2' with SP-relative "sd" entries.
10
63e014fc
MR		 112016-12-14 Maciej W. Rozycki <macro@imgtec.com>
12
13 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
14 compact jumps.
15
a6a51754
RL		 162016-12-13 Renlin Li <renlin.li@arm.com>
17
18 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
19 qualifier.
20 (operand_general_constraint_met_p): Remove case for CP_REG.
21 (aarch64_print_operand): Print CRn, CRm operand using imm field.
22 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
23 (QL_SYSL): Likewise.
24 (aarch64_opcode_table): Change CRn, CRm operand class and type.
25 * aarch64-opc-2.c : Regenerate.
26 * aarch64-asm-2.c : Likewise.
27 * aarch64-dis-2.c : Likewise.
28
029e9d52
YQ		 292016-12-12 Yao Qi <yao.qi@linaro.org>
30
31 * rx-dis.c: Include <setjmp.h>
32 (struct private): New.
33 (rx_get_byte): Check return value of read_memory_func, and
34 call memory_error_func and OPCODES_SIGLONGJMP on error.
35 (print_insn_rx): Call OPCODES_SIGSETJMP.
36
3a0b8f7d
YQ		 372016-12-12 Yao Qi <yao.qi@linaro.org>
38
39 * rl78-dis.c: Include <setjmp.h>.
40 (struct private): New.
41 (rl78_get_byte): Check return value of read_memory_func, and
42 call memory_error_func and OPCODES_SIGLONGJMP on error.
43 (print_insn_rl78_common): Call OPCODES_SIGJMP.
44
64c11183
MR		 452016-12-09 Maciej W. Rozycki <macro@imgtec.com>
46
47 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
48
f17ecb4b
MR		 492016-12-09 Maciej W. Rozycki <macro@imgtec.com>
50
51 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
52 than UINT.
53
55af4784
MR		 542016-12-09 Maciej W. Rozycki <macro@imgtec.com>
55
56 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
57 to separate `extend' and its uninterpreted argument output.
58 Separate hexadecimal halves of undecoded extended instructions
59 output.
60
39f66f3a
MR		 612016-12-08 Maciej W. Rozycki <macro@imgtec.com>
62
63 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
64 indentation space across.
65
860b03a8
MR		 662016-12-08 Maciej W. Rozycki <macro@imgtec.com>
67
68 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
69 adjustment for PC-relative operations following MIPS16e compact
70 jumps or undefined RR/J(AL)R(C) encodings.
71
329d01f7
MR		 722016-12-08 Maciej W. Rozycki <macro@imgtec.com>
73
74 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
75 variable to `reglane_index'.
76
3a2488dd
LM		 772016-12-08 Luis Machado <lgustavo@codesourcery.com>
78
79 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
80
5f5c6e03
MR		 812016-12-07 Maciej W. Rozycki <macro@imgtec.com>
82
83 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
84
343fa690
MR		 852016-12-07 Maciej W. Rozycki <macro@imgtec.com>
86
87 * mips16-opc.c (mips16_opcodes): Update comment naming structure
88 members.
89
6725647c
MR		 902016-12-07 Maciej W. Rozycki <macro@imgtec.com>
91
92 * mips-dis.c (print_mips_disassembler_options): Reformat output.
93
c28eeff2
SN		 942016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
95
96 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
97 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
98
49e8a725
SN		 992016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
100
101 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
102
a37a2806
NC		 1032016-12-01 Nick Clifton <nickc@redhat.com>
104
105 PR binutils/20893
106 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
107 opcode designator.
108
abe7c33b
CZ		 1092016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
110
111 * arc-opc.c (insert_ra_chk): New function.
112 (insert_rb_chk): Likewise.
113 (insert_rad): Update text error message.
114 (insert_rcd): Likewise.
115 (insert_rhv2): Likewise.
116 (insert_r0): Likewise.
117 (insert_r1): Likewise.
118 (insert_r2): Likewise.
119 (insert_r3): Likewise.
120 (insert_sp): Likewise.
121 (insert_gp): Likewise.
122 (insert_pcl): Likewise.
123 (insert_blink): Likewise.
124 (insert_ilink1): Likewise.
125 (insert_ilink2): Likewise.
126 (insert_ras): Likewise.
127 (insert_rbs): Likewise.
128 (insert_rcs): Likewise.
129 (insert_simm3s): Likewise.
130 (insert_rrange): Likewise.
131 (insert_fpel): Likewise.
132 (insert_blinkel): Likewise.
133 (insert_pcel): Likewise.
134 (insert_nps_3bit_dst): Likewise.
135 (insert_nps_3bit_dst_short): Likewise.
136 (insert_nps_3bit_src2_short): Likewise.
137 (insert_nps_bitop_size_2b): Likewise.
138 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
139 (RA_CHK): Define.
140 (RB): Adjust.
141 (RB_CHK): Define.
142 (RC): Adjust.
143 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
144 * arc-tbl.h (div, divu): All instructions are DIVREM class.
145 Change first insn argument to check for LP_COUNT usage.
146 (rem): Likewise.
147 (ld, ldd): All instructions are LOAD class. Change first insn
148 argument to check for LP_COUNT usage.
149 (st, std): All instructions are STORE class.
150 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
151 Change first insn argument to check for LP_COUNT usage.
152 (mov): All instructions are MOVE class. Change first insn
153 argument to check for LP_COUNT usage.
154
ee881e5d
CZ		 1552016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
156
157 * arc-dis.c (is_compatible_p): Remove function.
158 (skip_this_opcode): Don't add any decoding class to decode list.
159 Remove warning.
160 (find_format_from_table): Go through all opcodes, and warn if we
161 use a guessed mnemonic.
162
abfcb414
AP		 1632016-11-28 Ramiro Polla <ramiro@hex-rays.com>
164 Amit Pawar <amit.pawar@amd.com>
165
166 PR binutils/20637
167 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
168 instructions.
169
96fe4562
AM		 1702016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
171
172 * configure: Regenerate.
173
6884417a
JM		 1742016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
175
176 * sparc-opc.c (HWS_V8): Definition moved from
177 gas/config/tc-sparc.c.
178 (HWS_V9): Likewise.
179 (HWS_VA): Likewise.
180 (HWS_VB): Likewise.
181 (HWS_VC): Likewise.
182 (HWS_VD): Likewise.
183 (HWS_VE): Likewise.
184 (HWS_VV): Likewise.
185 (HWS_VM): Likewise.
186 (HWS2_VM): Likewise.
187 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
188 existing entries.
189
c4b943d7
CZ		 1902016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
191
192 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
193 instructions.
194
c2c4ff8d
SN		 1952016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
196
197 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
198 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
199 (aarch64_opcode_table): Add fcmla and fcadd.
200 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
201 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
202 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
203 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
204 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
205 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
206 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
207 (operand_general_constraint_met_p): Rotate and index range check.
208 (aarch64_print_operand): Handle rotate operand.
209 * aarch64-asm-2.c: Regenerate.
210 * aarch64-dis-2.c: Likewise.
211 * aarch64-opc-2.c: Likewise.
212
28617675
SN		 2132016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
214
215 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
216 * aarch64-asm-2.c: Regenerate.
217 * aarch64-dis-2.c: Regenerate.
218 * aarch64-opc-2.c: Regenerate.
219
ccfc90a3
SN		 2202016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
221
222 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
223 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
224 * aarch64-asm-2.c: Regenerate.
225 * aarch64-dis-2.c: Regenerate.
226 * aarch64-opc-2.c: Regenerate.
227
3f06e550
SN		 2282016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
229
230 * aarch64-tbl.h (QL_X1NIL): New.
231 (arch64_opcode_table): Add ldraa, ldrab.
232 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
233 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
234 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
235 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
236 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
237 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
238 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
239 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
240 (aarch64_print_operand): Likewise.
241 * aarch64-asm-2.c: Regenerate.
242 * aarch64-dis-2.c: Regenerate.
243 * aarch64-opc-2.c: Regenerate.
244
74f5402d
SN		 2452016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
246
247 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
248 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
249 * aarch64-asm-2.c: Regenerate.
250 * aarch64-dis-2.c: Regenerate.
251 * aarch64-opc-2.c: Regenerate.
252
c84364ec
SN		 2532016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
254
255 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
256 (AARCH64_OPERANDS): Add Rm_SP.
257 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
258 * aarch64-asm-2.c: Regenerate.
259 * aarch64-dis-2.c: Regenerate.
260 * aarch64-opc-2.c: Regenerate.
261
a2cfc830
SN		 2622016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
263
264 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
265 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
266 autdzb, xpaci, xpacd.
267 * aarch64-asm-2.c: Regenerate.
268 * aarch64-dis-2.c: Regenerate.
269 * aarch64-opc-2.c: Regenerate.
270
b0bfa7b5
SN		 2712016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
272
273 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
274 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
275 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
276 (aarch64_sys_reg_supported_p): Add feature test for new registers.
277
8787d804
SN		 2782016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
279
280 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
281 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
282 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
283 autibsp.
284 * aarch64-asm-2.c: Regenerate.
285 * aarch64-dis-2.c: Regenerate.
286
3d731f69
SN		 2872016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
288
289 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
290
60227d64
L		 2912016-11-09 H.J. Lu <hongjiu.lu@intel.com>
292
293 PR binutils/20799
294 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
295 * i386-dis.c (EdqwS): Removed.
296 (dqw_swap_mode): Likewise.
297 (intel_operand_size): Don't check dqw_swap_mode.
298 (OP_E_register): Likewise.
299 (OP_E_memory): Likewise.
300 (OP_G): Likewise.
301 (OP_EX): Likewise.
302 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
303 * i386-tbl.h: Regerated.
304
7efeed17
L		 3052016-11-09 H.J. Lu <hongjiu.lu@intel.com>
306
307 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 308 * i386-tbl.h: Regerated.
7efeed17 309
1f334aeb
L		 3102016-11-08 H.J. Lu <hongjiu.lu@intel.com>
311
312 PR binutils/20701
313 * i386-dis.c (THREE_BYTE_0F7A): Removed.
314 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
315 (three_byte_table): Remove THREE_BYTE_0F7A.
316
48c97fa1
L		 3172016-11-07 H.J. Lu <hongjiu.lu@intel.com>
318
319 PR binutils/20775
320 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
321 (FGRPd9_4): Replace 1 with 2.
322 (FGRPd9_5): Replace 2 with 3.
323 (FGRPd9_6): Replace 3 with 4.
324 (FGRPd9_7): Replace 4 with 5.
325 (FGRPda_5): Replace 5 with 6.
326 (FGRPdb_4): Replace 6 with 7.
327 (FGRPde_3): Replace 7 with 8.
328 (FGRPdf_4): Replace 8 with 9.
329 (fgrps): Add an entry for Bad_Opcode.
330
b437d035
AB		 3312016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
332
333 * arc-opc.c (arc_flag_operands): Add F_DI14.
334 (arc_flag_classes): Add C_DI14.
335 * arc-nps400-tbl.h: Add new exc instructions.
336
5a736821
GM		 3372016-11-03 Graham Markall <graham.markall@embecosm.com>
338
339 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
340 major opcode 0xa.
341 * arc-nps-400-tbl.h: Add dcmac instruction.
342 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
343 (insert_nps_rbdouble_64): Added.
344 (extract_nps_rbdouble_64): Added.
345 (insert_nps_proto_size): Added.
346 (extract_nps_proto_size): Added.
347
bdfe53e3
AB		 3482016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
349
350 * arc-dis.c (struct arc_operand_iterator): Remove all fields
351 relating to long instruction processing, add new limm field.
352 (OPCODE): Rename to...
353 (OPCODE_32BIT_INSN): ...this.
354 (OPCODE_AC): Delete.
355 (skip_this_opcode): Handle different instruction lengths, update
356 macro name.
357 (special_flag_p): Update parameter type.
358 (find_format_from_table): Update for more instruction lengths.
359 (find_format_long_instructions): Delete.
360 (find_format): Update for more instruction lengths.
361 (arc_insn_length): Likewise.
362 (extract_operand_value): Update for more instruction lengths.
363 (operand_iterator_next): Remove code relating to long
364 instructions.
365 (arc_opcode_to_insn_type): New function.
366 (print_insn_arc):Update for more instructions lengths.
367 * arc-ext.c (extInstruction_t): Change argument type.
368 * arc-ext.h (extInstruction_t): Change argument type.
369 * arc-fxi.h: Change type unsigned to unsigned long long
370 extensively throughout.
371 * arc-nps400-tbl.h: Add long instructions taken from
372 arc_long_opcodes table in arc-opc.c.
373 * arc-opc.c: Update parameter types on insert/extract handlers.
374 (arc_long_opcodes): Delete.
375 (arc_num_long_opcodes): Delete.
376 (arc_opcode_len): Update for more instruction lengths.
377
90f61cce
GM		 3782016-11-03 Graham Markall <graham.markall@embecosm.com>
379
380 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
381
06fe285f
GM		 3822016-11-03 Graham Markall <graham.markall@embecosm.com>
383
384 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
385 with arc_opcode_len.
386 (find_format_long_instructions): Likewise.
387 * arc-opc.c (arc_opcode_len): New function.
388
ecf64ec6
AB		 3892016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
390
391 * arc-nps400-tbl.h: Fix some instruction masks.
392
d039fef3
L		 3932016-11-03 H.J. Lu <hongjiu.lu@intel.com>
394
395 * i386-dis.c (REG_82): Removed.
396 (X86_64_82_REG_0): Likewise.
397 (X86_64_82_REG_1): Likewise.
398 (X86_64_82_REG_2): Likewise.
399 (X86_64_82_REG_3): Likewise.
400 (X86_64_82_REG_4): Likewise.
401 (X86_64_82_REG_5): Likewise.
402 (X86_64_82_REG_6): Likewise.
403 (X86_64_82_REG_7): Likewise.
404 (X86_64_82): New.
405 (dis386): Use X86_64_82 instead of REG_82.
406 (reg_table): Remove REG_82.
407 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
408 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
409 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
410 X86_64_82_REG_7.
411
8b89fe14
L		 4122016-11-03 H.J. Lu <hongjiu.lu@intel.com>
413
414 PR binutils/20754
415 * i386-dis.c (REG_82): New.
416 (X86_64_82_REG_0): Likewise.
417 (X86_64_82_REG_1): Likewise.
418 (X86_64_82_REG_2): Likewise.
419 (X86_64_82_REG_3): Likewise.
420 (X86_64_82_REG_4): Likewise.
421 (X86_64_82_REG_5): Likewise.
422 (X86_64_82_REG_6): Likewise.
423 (X86_64_82_REG_7): Likewise.
424 (dis386): Use REG_82.
425 (reg_table): Add REG_82.
426 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
427 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
428 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
429
7148c369
L		 4302016-11-03 H.J. Lu <hongjiu.lu@intel.com>
431
432 * i386-dis.c (REG_82): Renamed to ...
433 (REG_83): This.
434 (dis386): Updated.
435 (reg_table): Likewise.
436
47acf0bd
IT		 4372016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
438
439 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
440 * i386-dis-evex.h (evex_table): Updated.
441 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
442 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
443 (cpu_flags): Add CpuAVX512_4VNNIW.
444 * i386-opc.h (enum): (AVX512_4VNNIW): New.
445 (i386_cpu_flags): Add cpuavx512_4vnniw.
446 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
447 * i386-init.h: Regenerate.
448 * i386-tbl.h: Ditto.
449
920d2ddc
IT		 4502016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
451
452 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
453 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
454 * i386-dis-evex.h (evex_table): Updated.
455 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
456 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
457 (cpu_flags): Add CpuAVX512_4FMAPS.
458 (opcode_modifiers): Add ImplicitQuadGroup modifier.
459 * i386-opc.h (AVX512_4FMAP): New.
460 (i386_cpu_flags): Add cpuavx512_4fmaps.
461 (ImplicitQuadGroup): New.
462 (i386_opcode_modifier): Add implicitquadgroup.
463 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
464 * i386-init.h: Regenerate.
465 * i386-tbl.h: Ditto.
466
e23eba97
NC		 4672016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
468 Andrew Waterman <andrew@sifive.com>
469
470 Add support for RISC-V architecture.
471 * configure.ac: Add entry for bfd_riscv_arch.
472 * configure: Regenerate.
473 * disassemble.c (disassembler): Add support for riscv.
474 (disassembler_usage): Likewise.
475 * riscv-dis.c: New file.
476 * riscv-opc.c: New file.
477
b5cefcca
L		 4782016-10-21 H.J. Lu <hongjiu.lu@intel.com>
479
480 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
481 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
482 (rm_table): Update the RM_0FAE_REG_7 entry.
483 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
484 (cpu_flags): Remove CpuPCOMMIT.
485 * i386-opc.h (CpuPCOMMIT): Removed.
486 (i386_cpu_flags): Remove cpupcommit.
487 * i386-opc.tbl: Remove pcommit.
488 * i386-init.h: Regenerated.
489 * i386-tbl.h: Likewise.
490
9889cbb1
L		 4912016-10-20 H.J. Lu <hongjiu.lu@intel.com>
492
493 PR binutis/20705
494 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
495 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
496 32-bit mode. Don't check vex.register_specifier in 32-bit
497 mode.
498 (OP_VEX): Check for invalid mask registers.
499
28596323
L		 5002016-10-18 H.J. Lu <hongjiu.lu@intel.com>
501
502 PR binutis/20699
503 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
504 sizeflag.
505
da8d7d66
L		 5062016-10-18 H.J. Lu <hongjiu.lu@intel.com>
507
508 PR binutis/20704
509 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
510
eaf02703
MR		 5112016-10-18 Maciej W. Rozycki <macro@imgtec.com>
512
513 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
514 local variable to `index_regno'.
515
decf5bd1
CM		 5162016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
517
518 * arc-tbl.h: Removed any "inv.+" instructions from the table.
519
e5b06ef0
CZ		 5202016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
521
522 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
523 usage on ISA basis.
524
93562a34
JW		 5252016-10-11 Jiong Wang <jiong.wang@arm.com>
526
527 PR target/20666
528 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
529
362c0c4d
JW		 5302016-10-07 Jiong Wang <jiong.wang@arm.com>
531
532 PR target/20667
533 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
534 available.
535
1047201f
AM		 5362016-10-07 Alan Modra <amodra@gmail.com>
537
538 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
539
1a0670f3
AM		 5402016-10-06 Alan Modra <amodra@gmail.com>
541
542 * aarch64-opc.c: Spell fall through comments consistently.
543 * i386-dis.c: Likewise.
544 * aarch64-dis.c: Add missing fall through comments.
545 * aarch64-opc.c: Likewise.
546 * arc-dis.c: Likewise.
547 * arm-dis.c: Likewise.
548 * i386-dis.c: Likewise.
549 * m68k-dis.c: Likewise.
550 * mep-asm.c: Likewise.
551 * ns32k-dis.c: Likewise.
552 * sh-dis.c: Likewise.
553 * tic4x-dis.c: Likewise.
554 * tic6x-dis.c: Likewise.
555 * vax-dis.c: Likewise.
556
2b804145
AM		 5572016-10-06 Alan Modra <amodra@gmail.com>
558
559 * arc-ext.c (create_map): Add missing break.
560 * msp430-decode.opc (encode_as): Likewise.
561 * msp430-decode.c: Regenerate.
562
616ec358
AM		 5632016-10-06 Alan Modra <amodra@gmail.com>
564
565 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
566 * crx-dis.c (print_insn_crx): Likewise.
567
72da393d
L		 5682016-09-30 H.J. Lu <hongjiu.lu@intel.com>
569
570 PR binutils/20657
571 * i386-dis.c (putop): Don't assign alt twice.
572
744ce302
JW		 5732016-09-29 Jiong Wang <jiong.wang@arm.com>
574
575 PR target/20553
576 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
577
a5721ba2
AM		 5782016-09-29 Alan Modra <amodra@gmail.com>
579
580 * ppc-opc.c (L): Make compulsory.
581 (LOPT): New, optional form of L.
582 (HTM_R): Define as LOPT.
583 (L0, L1): Delete.
584 (L32OPT): New, optional for 32-bit L.
585 (L2OPT): New, 2-bit L for dcbf.
586 (SVC_LEC): Update.
587 (L2): Define.
588 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
589 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
590 <dcbf>: Use L2OPT.
591 <tlbiel, tlbie>: Use LOPT.
592 <wclr, wclrall>: Use L2.
593
c5da1932
VZ		 5942016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
595
596 * Makefile.in: Regenerate.
597 * configure: Likewise.
598
2b848ebd
CZ		 5992016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
600
601 * arc-ext-tbl.h (EXTINSN2OPF): Define.
602 (EXTINSN2OP): Use EXTINSN2OPF.
603 (bspeekm, bspop, modapp): New extension instructions.
604 * arc-opc.c (F_DNZ_ND): Define.
605 (F_DNZ_D): Likewise.
606 (F_SIZEB1): Changed.
607 (C_DNZ_D): Define.
608 (C_HARD): Changed.
609 * arc-tbl.h (dbnz): New instruction.
610 (prealloc): Allow it for ARC EM.
611 (xbfu): Likewise.
612
ad43e107
RS		 6132016-09-21 Richard Sandiford <richard.sandiford@arm.com>
614
615 * aarch64-opc.c (print_immediate_offset_address): Print spaces
616 after commas in addresses.
617 (aarch64_print_operand): Likewise.
618
ab3b8fcf
RS		 6192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
620
621 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
622 rather than "should be" or "expected to be" in error messages.
623
bb7eff52
RS		 6242016-09-21 Richard Sandiford <richard.sandiford@arm.com>
625
626 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
627 (print_mnemonic_name): ...here.
628 (print_comment): New function.
629 (print_aarch64_insn): Call it.
630 * aarch64-opc.c (aarch64_conds): Add SVE names.
631 (aarch64_print_operand): Print alternative condition names in
632 a comment.
633
c0890d26
RS		 6342016-09-21 Richard Sandiford <richard.sandiford@arm.com>
635
636 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
637 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
638 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
639 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
640 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
641 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
642 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
643 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
644 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
645 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
646 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
647 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
648 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
649 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
650 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
651 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
652 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
653 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
654 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
655 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
656 (OP_SVE_XWU, OP_SVE_XXU): New macros.
657 (aarch64_feature_sve): New variable.
658 (SVE): New macro.
659 (_SVE_INSN): Likewise.
660 (aarch64_opcode_table): Add SVE instructions.
661 * aarch64-opc.h (extract_fields): Declare.
662 * aarch64-opc-2.c: Regenerate.
663 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
664 * aarch64-asm-2.c: Regenerate.
665 * aarch64-dis.c (extract_fields): Make global.
666 (do_misc_decoding): Handle the new SVE aarch64_ops.
667 * aarch64-dis-2.c: Regenerate.
668
116b6019
RS		 6692016-09-21 Richard Sandiford <richard.sandiford@arm.com>
670
671 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
672 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
673 aarch64_field_kinds.
674 * aarch64-opc.c (fields): Add corresponding entries.
675 * aarch64-asm.c (aarch64_get_variant): New function.
676 (aarch64_encode_variant_using_iclass): Likewise.
677 (aarch64_opcode_encode): Call it.
678 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
679 (aarch64_opcode_decode): Call it.
680
047cd301
RS		 6812016-09-21 Richard Sandiford <richard.sandiford@arm.com>
682
683 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
684 and FP register operands.
685 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
686 (FLD_SVE_Vn): New aarch64_field_kinds.
687 * aarch64-opc.c (fields): Add corresponding entries.
688 (aarch64_print_operand): Handle the new SVE core and FP register
689 operands.
690 * aarch64-opc-2.c: Regenerate.
691 * aarch64-asm-2.c: Likewise.
692 * aarch64-dis-2.c: Likewise.
693
165d4950
RS		 6942016-09-21 Richard Sandiford <richard.sandiford@arm.com>
695
696 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
697 immediate operands.
698 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
699 * aarch64-opc.c (fields): Add corresponding entry.
700 (operand_general_constraint_met_p): Handle the new SVE FP immediate
701 operands.
702 (aarch64_print_operand): Likewise.
703 * aarch64-opc-2.c: Regenerate.
704 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
705 (ins_sve_float_zero_one): New inserters.
706 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
707 (aarch64_ins_sve_float_half_two): Likewise.
708 (aarch64_ins_sve_float_zero_one): Likewise.
709 * aarch64-asm-2.c: Regenerate.
710 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
711 (ext_sve_float_zero_one): New extractors.
712 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
713 (aarch64_ext_sve_float_half_two): Likewise.
714 (aarch64_ext_sve_float_zero_one): Likewise.
715 * aarch64-dis-2.c: Regenerate.
716
e950b345
RS		 7172016-09-21 Richard Sandiford <richard.sandiford@arm.com>
718
719 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
720 integer immediate operands.
721 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
722 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
723 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
724 * aarch64-opc.c (fields): Add corresponding entries.
725 (operand_general_constraint_met_p): Handle the new SVE integer
726 immediate operands.
727 (aarch64_print_operand): Likewise.
728 (aarch64_sve_dupm_mov_immediate_p): New function.
729 * aarch64-opc-2.c: Regenerate.
730 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
731 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
732 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
733 (aarch64_ins_limm): ...here.
734 (aarch64_ins_inv_limm): New function.
735 (aarch64_ins_sve_aimm): Likewise.
736 (aarch64_ins_sve_asimm): Likewise.
737 (aarch64_ins_sve_limm_mov): Likewise.
738 (aarch64_ins_sve_shlimm): Likewise.
739 (aarch64_ins_sve_shrimm): Likewise.
740 * aarch64-asm-2.c: Regenerate.
741 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
742 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
743 * aarch64-dis.c (decode_limm): New function, split out from...
744 (aarch64_ext_limm): ...here.
745 (aarch64_ext_inv_limm): New function.
746 (decode_sve_aimm): Likewise.
747 (aarch64_ext_sve_aimm): Likewise.
748 (aarch64_ext_sve_asimm): Likewise.
749 (aarch64_ext_sve_limm_mov): Likewise.
750 (aarch64_top_bit): Likewise.
751 (aarch64_ext_sve_shlimm): Likewise.
752 (aarch64_ext_sve_shrimm): Likewise.
753 * aarch64-dis-2.c: Regenerate.
754
98907a70
RS		 7552016-09-21 Richard Sandiford <richard.sandiford@arm.com>
756
757 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
758 operands.
759 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
760 the AARCH64_MOD_MUL_VL entry.
761 (value_aligned_p): Cope with non-power-of-two alignments.
762 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
763 (print_immediate_offset_address): Likewise.
764 (aarch64_print_operand): Likewise.
765 * aarch64-opc-2.c: Regenerate.
766 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
767 (ins_sve_addr_ri_s9xvl): New inserters.
768 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
769 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
770 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
771 * aarch64-asm-2.c: Regenerate.
772 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
773 (ext_sve_addr_ri_s9xvl): New extractors.
774 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
775 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
776 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
777 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
778 * aarch64-dis-2.c: Regenerate.
779
4df068de
RS		 7802016-09-21 Richard Sandiford <richard.sandiford@arm.com>
781
782 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
783 address operands.
784 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
785 (FLD_SVE_xs_22): New aarch64_field_kinds.
786 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
787 (get_operand_specific_data): New function.
788 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
789 FLD_SVE_xs_14 and FLD_SVE_xs_22.
790 (operand_general_constraint_met_p): Handle the new SVE address
791 operands.
792 (sve_reg): New array.
793 (get_addr_sve_reg_name): New function.
794 (aarch64_print_operand): Handle the new SVE address operands.
795 * aarch64-opc-2.c: Regenerate.
796 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
797 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
798 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
799 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
800 (aarch64_ins_sve_addr_rr_lsl): Likewise.
801 (aarch64_ins_sve_addr_rz_xtw): Likewise.
802 (aarch64_ins_sve_addr_zi_u5): Likewise.
803 (aarch64_ins_sve_addr_zz): Likewise.
804 (aarch64_ins_sve_addr_zz_lsl): Likewise.
805 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
806 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
807 * aarch64-asm-2.c: Regenerate.
808 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
809 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
810 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
811 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
812 (aarch64_ext_sve_addr_ri_u6): Likewise.
813 (aarch64_ext_sve_addr_rr_lsl): Likewise.
814 (aarch64_ext_sve_addr_rz_xtw): Likewise.
815 (aarch64_ext_sve_addr_zi_u5): Likewise.
816 (aarch64_ext_sve_addr_zz): Likewise.
817 (aarch64_ext_sve_addr_zz_lsl): Likewise.
818 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
819 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
820 * aarch64-dis-2.c: Regenerate.
821
2442d846
RS		 8222016-09-21 Richard Sandiford <richard.sandiford@arm.com>
823
824 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
825 AARCH64_OPND_SVE_PATTERN_SCALED.
826 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
827 * aarch64-opc.c (fields): Add a corresponding entry.
828 (set_multiplier_out_of_range_error): New function.
829 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
830 (operand_general_constraint_met_p): Handle
831 AARCH64_OPND_SVE_PATTERN_SCALED.
832 (print_register_offset_address): Use PRIi64 to print the
833 shift amount.
834 (aarch64_print_operand): Likewise. Handle
835 AARCH64_OPND_SVE_PATTERN_SCALED.
836 * aarch64-opc-2.c: Regenerate.
837 * aarch64-asm.h (ins_sve_scale): New inserter.
838 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
839 * aarch64-asm-2.c: Regenerate.
840 * aarch64-dis.h (ext_sve_scale): New inserter.
841 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
842 * aarch64-dis-2.c: Regenerate.
843
245d2e3f
RS		 8442016-09-21 Richard Sandiford <richard.sandiford@arm.com>
845
846 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
847 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
848 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
849 (FLD_SVE_prfop): Likewise.
850 * aarch64-opc.c: Include libiberty.h.
851 (aarch64_sve_pattern_array): New variable.
852 (aarch64_sve_prfop_array): Likewise.
853 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
854 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
855 AARCH64_OPND_SVE_PRFOP.
856 * aarch64-asm-2.c: Regenerate.
857 * aarch64-dis-2.c: Likewise.
858 * aarch64-opc-2.c: Likewise.
859
d50c751e
RS		 8602016-09-21 Richard Sandiford <richard.sandiford@arm.com>
861
862 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
863 AARCH64_OPND_QLF_P_[ZM].
864 (aarch64_print_operand): Print /z and /m where appropriate.
865
f11ad6bc
RS		 8662016-09-21 Richard Sandiford <richard.sandiford@arm.com>
867
868 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
869 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
870 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
871 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
872 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
873 * aarch64-opc.c (fields): Add corresponding entries here.
874 (operand_general_constraint_met_p): Check that SVE register lists
875 have the correct length. Check the ranges of SVE index registers.
876 Check for cases where p8-p15 are used in 3-bit predicate fields.
877 (aarch64_print_operand): Handle the new SVE operands.
878 * aarch64-opc-2.c: Regenerate.
879 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
880 * aarch64-asm.c (aarch64_ins_sve_index): New function.
881 (aarch64_ins_sve_reglist): Likewise.
882 * aarch64-asm-2.c: Regenerate.
883 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
884 * aarch64-dis.c (aarch64_ext_sve_index): New function.
885 (aarch64_ext_sve_reglist): Likewise.
886 * aarch64-dis-2.c: Regenerate.
887
0c608d6b
RS		 8882016-09-21 Richard Sandiford <richard.sandiford@arm.com>
889
890 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
891 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
892 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
893 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
894 tied operands.
895
01dbfe4c
RS		 8962016-09-21 Richard Sandiford <richard.sandiford@arm.com>
897
898 * aarch64-opc.c (get_offset_int_reg_name): New function.
899 (print_immediate_offset_address): Likewise.
900 (print_register_offset_address): Take the base and offset
901 registers as parameters.
902 (aarch64_print_operand): Update caller accordingly. Use
903 print_immediate_offset_address.
904
72e9f319
RS		 9052016-09-21 Richard Sandiford <richard.sandiford@arm.com>
906
907 * aarch64-opc.c (BANK): New macro.
908 (R32, R64): Take a register number as argument
909 (int_reg): Use BANK.
910
8a7f0c1b
RS		 9112016-09-21 Richard Sandiford <richard.sandiford@arm.com>
912
913 * aarch64-opc.c (print_register_list): Add a prefix parameter.
914 (aarch64_print_operand): Update accordingly.
915
aa2aa4c6
RS		 9162016-09-21 Richard Sandiford <richard.sandiford@arm.com>
917
918 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
919 for FPIMM.
920 * aarch64-asm.h (ins_fpimm): New inserter.
921 * aarch64-asm.c (aarch64_ins_fpimm): New function.
922 * aarch64-asm-2.c: Regenerate.
923 * aarch64-dis.h (ext_fpimm): New extractor.
924 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
925 (aarch64_ext_fpimm): New function.
926 * aarch64-dis-2.c: Regenerate.
927
b5464a68
RS		 9282016-09-21 Richard Sandiford <richard.sandiford@arm.com>
929
930 * aarch64-asm.c: Include libiberty.h.
931 (insert_fields): New function.
932 (aarch64_ins_imm): Use it.
933 * aarch64-dis.c (extract_fields): New function.
934 (aarch64_ext_imm): Use it.
935
42408347
RS		 9362016-09-21 Richard Sandiford <richard.sandiford@arm.com>
937
938 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
939 with an esize parameter.
940 (operand_general_constraint_met_p): Update accordingly.
941 Fix misindented code.
942 * aarch64-asm.c (aarch64_ins_limm): Update call to
943 aarch64_logical_immediate_p.
944
4989adac
RS		 9452016-09-21 Richard Sandiford <richard.sandiford@arm.com>
946
947 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
948
bd11d5d8
RS		 9492016-09-21 Richard Sandiford <richard.sandiford@arm.com>
950
951 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
952
f807f43d
CZ		 9532016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
954
955 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
956
fd486b63
PB		 9572016-09-14 Peter Bergner <bergner@vnet.ibm.com>
958
959 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
960 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
961 xor3>: Delete mnemonics.
962 <cp_abort>: Rename mnemonic from ...
963 <cpabort>: ...to this.
964 <setb>: Change to a X form instruction.
965 <sync>: Change to 1 operand form.
966 <copy>: Delete mnemonic.
967 <copy_first>: Rename mnemonic from ...
968 <copy>: ...to this.
969 <paste, paste.>: Delete mnemonics.
970 <paste_last>: Rename mnemonic from ...
971 <paste.>: ...to this.
972
dce08442
AK		 9732016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
974
975 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
976
952c3f51
AK		 9772016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
978
979 * s390-mkopc.c (main): Support alternate arch strings.
980
8b71537b
PS		 9812016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
982
983 * s390-opc.txt: Fix kmctr instruction type.
984
5b64d091
L		 9852016-09-07 H.J. Lu <hongjiu.lu@intel.com>
986
987 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
988 * i386-init.h: Regenerated.
989
7763838e
CM		 9902016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
991
992 * opcodes/arc-dis.c (print_insn_arc): Changed.
993
1b8b6532
JM		 9942016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
995
996 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
997 camellia_fl.
998
1a336194
TP		 9992016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1000
1001 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1002 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1003 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1004
6b40c462
L		 10052016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1006
1007 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1008 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1009 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1010 PREFIX_MOD_3_0FAE_REG_4.
1011 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1012 PREFIX_MOD_3_0FAE_REG_4.
1013 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1014 (cpu_flags): Add CpuPTWRITE.
1015 * i386-opc.h (CpuPTWRITE): New.
1016 (i386_cpu_flags): Add cpuptwrite.
1017 * i386-opc.tbl: Add ptwrite instruction.
1018 * i386-init.h: Regenerated.
1019 * i386-tbl.h: Likewise.
1020
ab548d2d
AK		 10212016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1022
1023 * arc-dis.h: Wrap around in extern "C".
1024
344bde0a
RS		 10252016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1026
1027 * aarch64-tbl.h (V8_2_INSN): New macro.
1028 (aarch64_opcode_table): Use it.
1029
5ce912d8
RS		 10302016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1031
1032 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1033 CORE_INSN, __FP_INSN and SIMD_INSN.
1034
9d30b0bd
RS		 10352016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1036
1037 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1038 (aarch64_opcode_table): Update uses accordingly.
1039
dfdaec14
AJ		 10402016-07-25 Andrew Jenner <andrew@codesourcery.com>
1041 Kwok Cheung Yeung <kcy@codesourcery.com>
1042
1043 opcodes/
1044 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1045 'e_cmplwi' to 'e_cmpli' instead.
1046 (OPVUPRT, OPVUPRT_MASK): Define.
1047 (powerpc_opcodes): Add E200Z4 insns.
1048 (vle_opcodes): Add context save/restore insns.
1049
7bd374a4
MR		 10502016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1051
1052 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1053 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1054 "j".
1055
db18dbab
GM		 10562016-07-27 Graham Markall <graham.markall@embecosm.com>
1057
1058 * arc-nps400-tbl.h: Change block comments to GNU format.
1059 * arc-dis.c: Add new globals addrtypenames,
1060 addrtypenames_max, and addtypeunknown.
1061 (get_addrtype): New function.
1062 (print_insn_arc): Print colons and address types when
1063 required.
1064 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1065 define insert and extract functions for all address types.
1066 (arc_operands): Add operands for colon and all address
1067 types.
1068 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1069 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1070 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1071 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1072 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1073 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1074
fecd57f9
L		 10752016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1076
1077 * configure: Regenerated.
1078
37fd5ef3
CZ		 10792016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1080
1081 * arc-dis.c (skipclass): New structure.
1082 (decodelist): New variable.
1083 (is_compatible_p): New function.
1084 (new_element): Likewise.
1085 (skip_class_p): Likewise.
1086 (find_format_from_table): Use skip_class_p function.
1087 (find_format): Decode first the extension instructions.
1088 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1089 e_flags.
1090 (parse_option): New function.
1091 (parse_disassembler_options): Likewise.
1092 (print_arc_disassembler_options): Likewise.
1093 (print_insn_arc): Use parse_disassembler_options function. Proper
1094 select ARCv2 cpu variant.
1095 * disassemble.c (disassembler_usage): Add ARC disassembler
1096 options.
1097
92281a5b
MR		 10982016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1099
1100 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1101 annotation from the "nal" entry and reorder it beyond "bltzal".
1102
6e7ced37
JM		 11032016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1104
1105 * sparc-opc.c (ldtxa): New macro.
1106 (sparc_opcodes): Use the macro defined above to add entries for
1107 the LDTXA instructions.
1108 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1109 instruction.
1110
2f831b9a 11112016-07-07 James Bowman <james.bowman@ftdichip.com>
1112
1113 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1114 and "jmpc".
1115
c07315e0
JB		 11162016-07-01 Jan Beulich <jbeulich@suse.com>
1117
1118 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1119 (movzb): Adjust to cover all permitted suffixes.
1120 (movzw): New.
1121 * i386-tbl.h: Re-generate.
1122
9243100a
JB		 11232016-07-01 Jan Beulich <jbeulich@suse.com>
1124
1125 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1126 (lgdt): Remove Tbyte from non-64-bit variant.
1127 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1128 xsaves64, xsavec64): Remove Disp16.
1129 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1130 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1131 64-bit variants.
1132 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1133 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1134 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1135 64-bit variants.
1136 * i386-tbl.h: Re-generate.
1137
8325cc63
JB		 11382016-07-01 Jan Beulich <jbeulich@suse.com>
1139
1140 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1141 * i386-tbl.h: Re-generate.
1142
838441e4
YQ		 11432016-06-30 Yao Qi <yao.qi@linaro.org>
1144
1145 * arm-dis.c (print_insn): Fix typo in comment.
1146
dab26bf4
RS		 11472016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1148
1149 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1150 range of ldst_elemlist operands.
1151 (print_register_list): Use PRIi64 to print the index.
1152 (aarch64_print_operand): Likewise.
1153
5703197e
TS		 11542016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1155
1156 * mcore-opc.h: Remove sentinal.
1157 * mcore-dis.c (print_insn_mcore): Adjust.
1158
ce440d63
GM		 11592016-06-23 Graham Markall <graham.markall@embecosm.com>
1160
1161 * arc-opc.c: Correct description of availability of NPS400
1162 features.
1163
6fd3a02d
PB		 11642016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1165
1166 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1167 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1168 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1169 xor3>: New mnemonics.
1170 <setb>: Change to a VX form instruction.
1171 (insert_sh6): Add support for rldixor.
1172 (extract_sh6): Likewise.
1173
6b477896
TS		 11742016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1175
1176 * arc-ext.h: Wrap in extern C.
1177
bdd582db
GM		 11782016-06-21 Graham Markall <graham.markall@embecosm.com>
1179
1180 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1181 Use same method for determining instruction length on ARC700 and
1182 NPS-400.
1183 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1184 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1185 with the NPS400 subclass.
1186 * arc-opc.c: Likewise.
1187
96074adc
JM		 11882016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1189
1190 * sparc-opc.c (rdasr): New macro.
1191 (wrasr): Likewise.
1192 (rdpr): Likewise.
1193 (wrpr): Likewise.
1194 (rdhpr): Likewise.
1195 (wrhpr): Likewise.
1196 (sparc_opcodes): Use the macros above to fix and expand the
1197 definition of read/write instructions from/to
1198 asr/privileged/hyperprivileged instructions.
1199 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1200 %hva_mask_nz. Prefer softint_set and softint_clear over
1201 set_softint and clear_softint.
1202 (print_insn_sparc): Support %ver in Rd.
1203
7a10c22f
JM		 12042016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1205
1206 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1207 architecture according to the hardware capabilities they require.
1208
4f26fb3a
JM		 12092016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1210
1211 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1212 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1213 bfd_mach_sparc_v9{c,d,e,v,m}.
1214 * sparc-opc.c (MASK_V9C): Define.
1215 (MASK_V9D): Likewise.
1216 (MASK_V9E): Likewise.
1217 (MASK_V9V): Likewise.
1218 (MASK_V9M): Likewise.
1219 (v6): Add MASK_V9{C,D,E,V,M}.
1220 (v6notlet): Likewise.
1221 (v7): Likewise.
1222 (v8): Likewise.
1223 (v9): Likewise.
1224 (v9andleon): Likewise.
1225 (v9a): Likewise.
1226 (v9b): Likewise.
1227 (v9c): Define.
1228 (v9d): Likewise.
1229 (v9e): Likewise.
1230 (v9v): Likewise.
1231 (v9m): Likewise.
1232 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1233
3ee6e4fb
NC		 12342016-06-15 Nick Clifton <nickc@redhat.com>
1235
1236 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1237 constants to match expected behaviour.
1238 (nds32_parse_opcode): Likewise. Also for whitespace.
1239
02f3be19
AB		 12402016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1241
1242 * arc-opc.c (extract_rhv1): Extract value from insn.
1243
6f9f37ed 12442016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 1245
1246 * arc-nps400-tbl.h: Add ldbit instruction.
1247 * arc-opc.c: Add flag classes required for ldbit.
1248
6f9f37ed 12492016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 1250
1251 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1252 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1253 support the above instructions.
1254
6f9f37ed 12552016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 1256
1257 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1258 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1259 csma, cbba, zncv, and hofs.
1260 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1261 support the above instructions.
1262
12632016-06-06 Graham Markall <graham.markall@embecosm.com>
1264
1265 * arc-nps400-tbl.h: Add andab and orab instructions.
1266
12672016-06-06 Graham Markall <graham.markall@embecosm.com>
1268
1269 * arc-nps400-tbl.h: Add addl-like instructions.
1270
12712016-06-06 Graham Markall <graham.markall@embecosm.com>
1272
1273 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1274
12752016-06-06 Graham Markall <graham.markall@embecosm.com>
1276
1277 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1278 instructions.
1279
b2cc3f6f
AK		 12802016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1281
1282 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1283 variable.
1284 (init_disasm): Handle new command line option "insnlength".
1285 (print_s390_disassembler_options): Mention new option in help
1286 output.
1287 (print_insn_s390): Use the encoded insn length when dumping
1288 unknown instructions.
1289
1857fe72
DC		 12902016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1291
1292 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1293 to the address and set as symbol address for LDS/ STS immediate operands.
1294
14b57c7c
AM		 12952016-06-07 Alan Modra <amodra@gmail.com>
1296
1297 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1298 cpu for "vle" to e500.
1299 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1300 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1301 (PPCNONE): Delete, substitute throughout.
1302 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1303 except for major opcode 4 and 31.
1304 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1305
4d1464f2
MW		 13062016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1307
1308 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1309 ARM_EXT_RAS in relevant entries.
1310
026122a6
PB		 13112016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1312
1313 PR binutils/20196
1314 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1315 opcodes for E6500.
1316
07f5af7d
L		 13172016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1318
1319 PR binutis/18386
1320 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1321 (indir_v_mode): New.
1322 Add comments for '&'.
1323 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1324 (putop): Handle '&'.
1325 (intel_operand_size): Handle indir_v_mode.
1326 (OP_E_register): Likewise.
1327 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1328 64-bit indirect call/jmp for AMD64.
1329 * i386-tbl.h: Regenerated
1330
4eb6f892
AB		 13312016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1332
1333 * arc-dis.c (struct arc_operand_iterator): New structure.
1334 (find_format_from_table): All the old content from find_format,
1335 with some minor adjustments, and parameter renaming.
1336 (find_format_long_instructions): New function.
1337 (find_format): Rewritten.
1338 (arc_insn_length): Add LSB parameter.
1339 (extract_operand_value): New function.
1340 (operand_iterator_next): New function.
1341 (print_insn_arc): Use new functions to find opcode, and iterator
1342 over operands.
1343 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1344 (extract_nps_3bit_dst_short): New function.
1345 (insert_nps_3bit_src2_short): New function.
1346 (extract_nps_3bit_src2_short): New function.
1347 (insert_nps_bitop1_size): New function.
1348 (extract_nps_bitop1_size): New function.
1349 (insert_nps_bitop2_size): New function.
1350 (extract_nps_bitop2_size): New function.
1351 (insert_nps_bitop_mod4_msb): New function.
1352 (extract_nps_bitop_mod4_msb): New function.
1353 (insert_nps_bitop_mod4_lsb): New function.
1354 (extract_nps_bitop_mod4_lsb): New function.
1355 (insert_nps_bitop_dst_pos3_pos4): New function.
1356 (extract_nps_bitop_dst_pos3_pos4): New function.
1357 (insert_nps_bitop_ins_ext): New function.
1358 (extract_nps_bitop_ins_ext): New function.
1359 (arc_operands): Add new operands.
1360 (arc_long_opcodes): New global array.
1361 (arc_num_long_opcodes): New global.
1362 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1363
1fe0971e
TS		 13642016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1365
1366 * nds32-asm.h: Add extern "C".
1367 * sh-opc.h: Likewise.
1368
315f180f
GM		 13692016-06-01 Graham Markall <graham.markall@embecosm.com>
1370
1371 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1372 0,b,limm to the rflt instruction.
1373
a2b5fccc
TS		 13742016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1375
1376 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1377 constant.
1378
0cbd0046
L		 13792016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1380
1381 PR gas/20145
1382 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1383 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1384 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1385 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1386 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1387 * i386-init.h: Regenerated.
1388
1848e567
L		 13892016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1390
1391 PR gas/20145
1392 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1393 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1394 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1395 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1396 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1397 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1398 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1399 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1400 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1401 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1402 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1403 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1404 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1405 CpuRegMask for AVX512.
1406 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1407 and CpuRegMask.
1408 (set_bitfield_from_cpu_flag_init): New function.
1409 (set_bitfield): Remove const on f. Call
1410 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1411 * i386-opc.h (CpuRegMMX): New.
1412 (CpuRegXMM): Likewise.
1413 (CpuRegYMM): Likewise.
1414 (CpuRegZMM): Likewise.
1415 (CpuRegMask): Likewise.
1416 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1417 and cpuregmask.
1418 * i386-init.h: Regenerated.
1419 * i386-tbl.h: Likewise.
1420
e92bae62
L		 14212016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1422
1423 PR gas/20154
1424 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1425 (opcode_modifiers): Add AMD64 and Intel64.
1426 (main): Properly verify CpuMax.
1427 * i386-opc.h (CpuAMD64): Removed.
1428 (CpuIntel64): Likewise.
1429 (CpuMax): Set to CpuNo64.
1430 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1431 (AMD64): New.
1432 (Intel64): Likewise.
1433 (i386_opcode_modifier): Add amd64 and intel64.
1434 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1435 on call and jmp.
1436 * i386-init.h: Regenerated.
1437 * i386-tbl.h: Likewise.
1438
e89c5eaa
L		 14392016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1440
1441 PR gas/20154
1442 * i386-gen.c (main): Fail if CpuMax is incorrect.
1443 * i386-opc.h (CpuMax): Set to CpuIntel64.
1444 * i386-tbl.h: Regenerated.
1445
77d66e7b
NC		 14462016-05-27 Nick Clifton <nickc@redhat.com>
1447
1448 PR target/20150
1449 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1450 (msp430dis_opcode_unsigned): New function.
1451 (msp430dis_opcode_signed): New function.
1452 (msp430_singleoperand): Use the new opcode reading functions.
1453 Only disassenmble bytes if they were successfully read.
1454 (msp430_doubleoperand): Likewise.
1455 (msp430_branchinstr): Likewise.
1456 (msp430x_callx_instr): Likewise.
1457 (print_insn_msp430): Check that it is safe to read bytes before
1458 attempting disassembly. Use the new opcode reading functions.
1459
19dfcc89
PB		 14602016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1461
1462 * ppc-opc.c (CY): New define. Document it.
1463 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1464
f3ad7637
L		 14652016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1466
1467 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1468 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1469 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1470 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1471 CPU_ANY_AVX_FLAGS.
1472 * i386-init.h: Regenerated.
1473
f1360d58
L		 14742016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1475
1476 PR gas/20141
1477 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1478 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1479 * i386-init.h: Regenerated.
1480
293f5f65
L		 14812016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1482
1483 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1484 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1485 * i386-init.h: Regenerated.
1486
d9eca1df
CZ		 14872016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1488
1489 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1490 information.
1491 (print_insn_arc): Set insn_type information.
1492 * arc-opc.c (C_CC): Add F_CLASS_COND.
1493 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1494 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1495 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1496 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1497 (brne, brne_s, jeq_s, jne_s): Likewise.
1498
87789e08
CZ		 14992016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1500
1501 * arc-tbl.h (neg): New instruction variant.
1502
c810e0b8
CZ		 15032016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1504
1505 * arc-dis.c (find_format, find_format, get_auxreg)
1506 (print_insn_arc): Changed.
1507 * arc-ext.h (INSERT_XOP): Likewise.
1508
3d207518
TS		 15092016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1510
1511 * tic54x-dis.c (sprint_mmr): Adjust.
1512 * tic54x-opc.c: Likewise.
1513
514e58b7
AM		 15142016-05-19 Alan Modra <amodra@gmail.com>
1515
1516 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1517
e43de63c
AM		 15182016-05-19 Alan Modra <amodra@gmail.com>
1519
1520 * ppc-opc.c: Formatting.
1521 (NSISIGNOPT): Define.
1522 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1523
1401d2fe
MR		 15242016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1525
1526 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1527 replacing references to `micromips_ase' throughout.
1528 (_print_insn_mips): Don't use file-level microMIPS annotation to
1529 determine the disassembly mode with the symbol table.
1530
1178da44
PB		 15312016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1532
1533 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1534
8f4f9071
MF		 15352016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1536
1537 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1538 mips64r6.
1539 * mips-opc.c (D34): New macro.
1540 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1541
8bc52696
AF		 15422016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1543
1544 * i386-dis.c (prefix_table): Add RDPID instruction.
1545 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1546 (cpu_flags): Add RDPID bitfield.
1547 * i386-opc.h (enum): Add RDPID element.
1548 (i386_cpu_flags): Add RDPID field.
1549 * i386-opc.tbl: Add RDPID instruction.
1550 * i386-init.h: Regenerate.
1551 * i386-tbl.h: Regenerate.
1552
39d911fc
TP		 15532016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1554
1555 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1556 branch type of a symbol.
1557 (print_insn): Likewise.
1558
16a1fa25
TP		 15592016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1560
1561 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1562 Mainline Security Extensions instructions.
1563 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1564 Extensions instructions.
1565 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1566 instructions.
1567 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1568 special registers.
1569
d751b79e
JM		 15702016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1571
1572 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1573
945e0f82
CZ		 15742016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1575
1576 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1577 (arcExtMap_genOpcode): Likewise.
1578 * arc-opc.c (arg_32bit_rc): Define new variable.
1579 (arg_32bit_u6): Likewise.
1580 (arg_32bit_limm): Likewise.
1581
20f55f38
SN		 15822016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1583
1584 * aarch64-gen.c (VERIFIER): Define.
1585 * aarch64-opc.c (VERIFIER): Define.
1586 (verify_ldpsw): Use static linkage.
1587 * aarch64-opc.h (verify_ldpsw): Remove.
1588 * aarch64-tbl.h: Use VERIFIER for verifiers.
1589
4bd13cde
NC		 15902016-04-28 Nick Clifton <nickc@redhat.com>
1591
1592 PR target/19722
1593 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1594 * aarch64-opc.c (verify_ldpsw): New function.
1595 * aarch64-opc.h (verify_ldpsw): New prototype.
1596 * aarch64-tbl.h: Add initialiser for verifier field.
1597 (LDPSW): Set verifier to verify_ldpsw.
1598
c0f92bf9
L		 15992016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1600
1601 PR binutils/19983
1602 PR binutils/19984
1603 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1604 smaller than address size.
1605
e6c7cdec
TS		 16062016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1607
1608 * alpha-dis.c: Regenerate.
1609 * crx-dis.c: Likewise.
1610 * disassemble.c: Likewise.
1611 * epiphany-opc.c: Likewise.
1612 * fr30-opc.c: Likewise.
1613 * frv-opc.c: Likewise.
1614 * ip2k-opc.c: Likewise.
1615 * iq2000-opc.c: Likewise.
1616 * lm32-opc.c: Likewise.
1617 * lm32-opinst.c: Likewise.
1618 * m32c-opc.c: Likewise.
1619 * m32r-opc.c: Likewise.
1620 * m32r-opinst.c: Likewise.
1621 * mep-opc.c: Likewise.
1622 * mt-opc.c: Likewise.
1623 * or1k-opc.c: Likewise.
1624 * or1k-opinst.c: Likewise.
1625 * tic80-opc.c: Likewise.
1626 * xc16x-opc.c: Likewise.
1627 * xstormy16-opc.c: Likewise.
1628
537aefaf
AB		 16292016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1630
1631 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1632 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1633 calcsd, and calcxd instructions.
1634 * arc-opc.c (insert_nps_bitop_size): Delete.
1635 (extract_nps_bitop_size): Delete.
1636 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1637 (extract_nps_qcmp_m3): Define.
1638 (extract_nps_qcmp_m2): Define.
1639 (extract_nps_qcmp_m1): Define.
1640 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1641 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1642 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1643 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1644 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1645 NPS_QCMP_M3.
1646
c8f785f2
AB		 16472016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1648
1649 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1650
6fd8e7c2
L		 16512016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1652
1653 * Makefile.in: Regenerated with automake 1.11.6.
1654 * aclocal.m4: Likewise.
1655
4b0c052e
AB		 16562016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1657
1658 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1659 instructions.
1660 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1661 (extract_nps_cmem_uimm16): New function.
1662 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1663
cb040366
AB		 16642016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1665
1666 * arc-dis.c (arc_insn_length): New function.
1667 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1668 (find_format): Change insnLen parameter to unsigned.
1669
accc0180
NC		 16702016-04-13 Nick Clifton <nickc@redhat.com>
1671
1672 PR target/19937
1673 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1674 the LD.B and LD.BU instructions.
1675
f36e33da
CZ		 16762016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1677
1678 * arc-dis.c (find_format): Check for extension flags.
1679 (print_flags): New function.
1680 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1681 .extAuxRegister.
1682 * arc-ext.c (arcExtMap_coreRegName): Use
1683 LAST_EXTENSION_CORE_REGISTER.
1684 (arcExtMap_coreReadWrite): Likewise.
1685 (dump_ARC_extmap): Update printing.
1686 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1687 (arc_aux_regs): Add cpu field.
1688 * arc-regs.h: Add cpu field, lower case name aux registers.
1689
1c2e355e
CZ		 16902016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1691
1692 * arc-tbl.h: Add rtsc, sleep with no arguments.
1693
b99747ae
CZ		 16942016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1695
1696 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1697 Initialize.
1698 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1699 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1700 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1701 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1702 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1703 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1704 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1705 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1706 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1707 (arc_opcode arc_opcodes): Null terminate the array.
1708 (arc_num_opcodes): Remove.
1709 * arc-ext.h (INSERT_XOP): Define.
1710 (extInstruction_t): Likewise.
1711 (arcExtMap_instName): Delete.
1712 (arcExtMap_insn): New function.
1713 (arcExtMap_genOpcode): Likewise.
1714 * arc-ext.c (ExtInstruction): Remove.
1715 (create_map): Zero initialize instruction fields.
1716 (arcExtMap_instName): Remove.
1717 (arcExtMap_insn): New function.
1718 (dump_ARC_extmap): More info while debuging.
1719 (arcExtMap_genOpcode): New function.
1720 * arc-dis.c (find_format): New function.
1721 (print_insn_arc): Use find_format.
1722 (arc_get_disassembler): Enable dump_ARC_extmap only when
1723 debugging.
1724
92708cec
MR		 17252016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1726
1727 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1728 instruction bits out.
1729
a42a4f84
AB		 17302016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1731
1732 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1733 * arc-opc.c (arc_flag_operands): Add new flags.
1734 (arc_flag_classes): Add new classes.
1735
1328504b
AB		 17362016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1737
1738 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1739
820f03ff
AB		 17402016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1741
1742 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1743 encode1, rflt, crc16, and crc32 instructions.
1744 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1745 (arc_flag_classes): Add C_NPS_R.
1746 (insert_nps_bitop_size_2b): New function.
1747 (extract_nps_bitop_size_2b): Likewise.
1748 (insert_nps_bitop_uimm8): Likewise.
1749 (extract_nps_bitop_uimm8): Likewise.
1750 (arc_operands): Add new operand entries.
1751
8ddf6b2a
CZ		 17522016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1753
b99747ae
CZ		 1754 * arc-regs.h: Add a new subclass field. Add double assist
1755 accumulator register values.
1756 * arc-tbl.h: Use DPA subclass to mark the double assist
1757 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1758 * arc-opc.c (RSP): Define instead of SP.
1759 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1760
589a7d88
JW		 17612016-04-05 Jiong Wang <jiong.wang@arm.com>
1762
1763 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1764
0a191de9 17652016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1766
1767 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1768 NPS_R_SRC1.
1769
0a106562
AB		 17702016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1771
1772 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1773 issues. No functional changes.
1774
bd05ac5f
CZ		 17752016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1776
b99747ae
CZ		 1777 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1778 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1779 (RTT): Remove duplicate.
1780 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1781 (PCT_CONFIG*): Remove.
1782 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1783
9885948f
CZ		 17842016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1785
b99747ae 1786 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1787
f2dd8838
CZ		 17882016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1789
b99747ae
CZ		 1790 * arc-tbl.h (invld07): Remove.
1791 * arc-ext-tbl.h: New file.
1792 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1793 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1794
0d2f91fe
JK		 17952016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1796
1797 Fix -Wstack-usage warnings.
1798 * aarch64-dis.c (print_operands): Substitute size.
1799 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1800
a6b71f42
JM		 18012016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1802
1803 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1804 to get a proper diagnostic when an invalid ASR register is used.
1805
9780e045
NC		 18062016-03-22 Nick Clifton <nickc@redhat.com>
1807
1808 * configure: Regenerate.
1809
e23e8ebe
AB		 18102016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1811
1812 * arc-nps400-tbl.h: New file.
1813 * arc-opc.c: Add top level comment.
1814 (insert_nps_3bit_dst): New function.
1815 (extract_nps_3bit_dst): New function.
1816 (insert_nps_3bit_src2): New function.
1817 (extract_nps_3bit_src2): New function.
1818 (insert_nps_bitop_size): New function.
1819 (extract_nps_bitop_size): New function.
1820 (arc_flag_operands): Add nps400 entries.
1821 (arc_flag_classes): Add nps400 entries.
1822 (arc_operands): Add nps400 entries.
1823 (arc_opcodes): Add nps400 include.
1824
1ae8ab47
AB		 18252016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1826
1827 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1828 the new class enum values.
1829
8699fc3e
AB		 18302016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1831
1832 * arc-dis.c (print_insn_arc): Handle nps400.
1833
24740d83
AB		 18342016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1835
1836 * arc-opc.c (BASE): Delete.
1837
8678914f
NC		 18382016-03-18 Nick Clifton <nickc@redhat.com>
1839
1840 PR target/19721
1841 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1842 of MOV insn that aliases an ORR insn.
1843
cc933301
JW		 18442016-03-16 Jiong Wang <jiong.wang@arm.com>
1845
1846 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1847
f86f5863
TS		 18482016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1849
1850 * mcore-opc.h: Add const qualifiers.
1851 * microblaze-opc.h (struct op_code_struct): Likewise.
1852 * sh-opc.h: Likewise.
1853 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1854 (tic4x_print_op): Likewise.
1855
62de1c63
AM		 18562016-03-02 Alan Modra <amodra@gmail.com>
1857
d11698cd 1858 * or1k-desc.h: Regenerate.
62de1c63 1859 * fr30-ibld.c: Regenerate.
c697cf0b 1860 * rl78-decode.c: Regenerate.
62de1c63 1861
020efce5
NC		 18622016-03-01 Nick Clifton <nickc@redhat.com>
1863
1864 PR target/19747
1865 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1866
b0c11777
RL		 18672016-02-24 Renlin Li <renlin.li@arm.com>
1868
1869 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1870 (print_insn_coprocessor): Support fp16 instructions.
1871
3e309328
RL		 18722016-02-24 Renlin Li <renlin.li@arm.com>
1873
1874 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1875 vminnm, vrint(mpna).
1876
8afc7bea
RL		 18772016-02-24 Renlin Li <renlin.li@arm.com>
1878
1879 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1880 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1881
4fd7268a
L		 18822016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1883
1884 * i386-dis.c (print_insn): Parenthesize expression to prevent
1885 truncated addresses.
1886 (OP_J): Likewise.
1887
4670103e
CZ		 18882016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1889 Janek van Oirschot <jvanoirs@synopsys.com>
1890
b99747ae
CZ		 1891 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1892 variable.
4670103e 1893
c1d9289f
NC		 18942016-02-04 Nick Clifton <nickc@redhat.com>
1895
1896 PR target/19561
1897 * msp430-dis.c (print_insn_msp430): Add a special case for
1898 decoding an RRC instruction with the ZC bit set in the extension
1899 word.
1900
a143b004
AB		 19012016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1902
1903 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1904 * epiphany-ibld.c: Regenerate.
1905 * fr30-ibld.c: Regenerate.
1906 * frv-ibld.c: Regenerate.
1907 * ip2k-ibld.c: Regenerate.
1908 * iq2000-ibld.c: Regenerate.
1909 * lm32-ibld.c: Regenerate.
1910 * m32c-ibld.c: Regenerate.
1911 * m32r-ibld.c: Regenerate.
1912 * mep-ibld.c: Regenerate.
1913 * mt-ibld.c: Regenerate.
1914 * or1k-ibld.c: Regenerate.
1915 * xc16x-ibld.c: Regenerate.
1916 * xstormy16-ibld.c: Regenerate.
1917
b89807c6
AB		 19182016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1919
1920 * epiphany-dis.c: Regenerated from latest cpu files.
1921
d8c823c8
MM		 19222016-02-01 Michael McConville <mmcco@mykolab.com>
1923
1924 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1925 test bit.
1926
5bc5ae88
RL		 19272016-01-25 Renlin Li <renlin.li@arm.com>
1928
1929 * arm-dis.c (mapping_symbol_for_insn): New function.
1930 (find_ifthen_state): Call mapping_symbol_for_insn().
1931
0bff6e2d
MW		 19322016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1933
1934 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1935 of MSR UAO immediate operand.
1936
100b4f2e
MR		 19372016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1938
1939 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1940 instruction support.
1941
5c14705f
AM		 19422016-01-17 Alan Modra <amodra@gmail.com>
1943
1944 * configure: Regenerate.
1945
4d82fe66
NC		 19462016-01-14 Nick Clifton <nickc@redhat.com>
1947
1948 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1949 instructions that can support stack pointer operations.
1950 * rl78-decode.c: Regenerate.
1951 * rl78-dis.c: Fix display of stack pointer in MOVW based
1952 instructions.
1953
651657fa
MW		 19542016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1955
1956 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1957 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1958 erxtatus_el1 and erxaddr_el1.
1959
105bde57
MW		 19602016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1961
1962 * arm-dis.c (arm_opcodes): Add "esb".
1963 (thumb_opcodes): Likewise.
1964
afa8d405
PB		 19652016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1966
1967 * ppc-opc.c <xscmpnedp>: Delete.
1968 <xvcmpnedp>: Likewise.
1969 <xvcmpnedp.>: Likewise.
1970 <xvcmpnesp>: Likewise.
1971 <xvcmpnesp.>: Likewise.
1972
83c3256e
AS		 19732016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1974
1975 PR gas/13050
1976 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1977 addition to ISA_A.
1978
6f2750fe
AM		 19792016-01-01 Alan Modra <amodra@gmail.com>
1980
1981 Update year range in copyright notice of all files.
1982
3499769a
AM		 1983For older changes see ChangeLog-2015
1984\f
1985Copyright (C) 2016 Free Software Foundation, Inc.
1986
1987Copying and distribution of this file, with or without modification,
1988are permitted in any medium without royalty provided the copyright
1989notice and this notice are preserved.
1990
1991Local Variables:
1992mode: change-log
1993left-margin: 8
1994fill-column: 74
1995version-control: never
1996End:
GDB Binutils - Deliverables
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