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Add LM32 port.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
84e94c90
NC		 12008-12-12 Jon Beniston <jon@beniston.com>
2
3 * Makefile.am: Add LM32 object files and dependencies.
4 * Makefile.in: Regenerate.
5 * configure.in: Add LM32 target.
6 * configure: Regenerate.
7 * disassemble.c: Add LM32 disassembler.
8 * cgen-asm.in: Update copyright year.
9 * cgen-dis.in: Update copyright year.
10 * cgen-ibld.in: Update copyright year.
11 * lm32-asm.c: New file.
12 * lm32-desc.c: New file.
13 * lm32-desc.h: New file.
14 * lm32-dis.c: New file.
15 * lm32-ibld.c: New file.
16 * lm32-opc.c: New file.
17 * lm32-opc.h: New file.
18 * lm32-opinst.c: New file.
19
fa99fab2
L		 202008-12-23 H.J. Lu <hongjiu.lu@intel.com>
21
22 * i386-dis.c (EXdS): New.
23 (EXdVexS): Likewise.
24 (EXqVexS): Likewise.
25 (d_swap_mode): Likewise.
26 (q_mode): Updated.
27 (prefix_table): Use EXdS on movss and EXqS on movsd.
28 (vex_len_table): Use EXdVexS on vmovss and EXqVexS on vmovsd.
29 (intel_operand_size): Handle d_swap_mode.
30 (OP_EX): Likewise.
31
32 * i386-opc.h (S): Update comments.
33
34 * i386-opc.tbl: Add S to movss, movsd, vmovss and vmovsd.
35 * i386-tbl.h: Regenerated.
36
b06f3b1b
NC		 372008-12-23 Nick Clifton <nickc@redhat.com>
38
39 * po/ga.po: Updated Irish translation.
40
b6169b20
L		 412008-12-20 H.J. Lu <hongjiu.lu@intel.com>
42
43 * i386-dis.c (EbS): New.
44 (EvS): Likewise.
45 (EMS): Likewise.
46 (EXqS): Likewise.
47 (EXxS): Likewise.
48 (b_swap_mode): Likewise.
49 (v_swap_mode): Likewise.
50 (q_swap_mode): Likewise.
51 (x_swap_mode): Likewise.
52 (v_mode): Updated.
53 (w_mode): Likewise.
54 (t_mode): Likewise.
55 (xmm_mode): Likewise.
56 (swap_operand): Likewise.
57 (dis386): Use EbS on movB. Use EvS on moveS.
58 (dis386_twobyte): Use EXxS on movapX.
59 (prefix_table): Use EXxS on movups, movupd, movdqu, movdqa,
60 vmovups, vmovdqu, vmovdqa. Use EMS and EXqS on movq.
61 (vex_table): Use EXxS on vmovapX.
62 (vex_len_table): Use EXqS on vmovq.
63 (intel_operand_size): Handle b_swap_mode, v_swap_mode,
64 q_swap_mode and x_swap_mode.
65 (OP_E_register): Handle b_swap_mode and v_swap_mode.
66 (OP_EM): Handle v_swap_mode.
67 (OP_EX): x_swap_mode and q_swap_mode.
68
69 * i386-gen.c (opcode_modifiers): Add S.
70
71 * i386-opc.h (S): New.
72 (Modrm): Updated.
73 (i386_opcode_modifier): Add s.
74
75 * i386-opc.tbl: Add S to movapd, movaps, movdqa, movdqu, movq,
76 movupd, movups, vmovapd, vmovaps, vmovdqa, vmovdqu and vmovq.
77 * i386-tbl.h: Regenerated.
78
ea397f5b
L		 792008-12-18 H.J. Lu <hongjiu.lu@intel.com>
80
81 * i386-dis.c (mnemonicendp): New.
82 (op): Likewise.
83 (print_insn): Use mnemonicendp.
84 (OP_3DNowSuffix): Likewise.
85 (CMP_Fixup): Likewise.
86 (CMPXCHG8B_Fixup): Likewise.
87 (CRC32_Fixup): Likewise.
88 (OP_DREX_FCMP): Likewise.
89 (OP_DREX_ICMP): Likewise.
90 (VZERO_Fixup): Likewise.
91 (VCMP_Fixup): Likewise.
92 (PCLMUL_Fixup): Likewise.
93 (VPERMIL2_Fixup): Likewise.
94 (MOVBE_Fixup): Likewise.
95 (putop): Update mnemonicendp.
96 (oappend): Use stpcpy.
97 (simd_cmp_op): Changed to struct op.
98 (vex_cmp_op): Likewise.
99 (pclmul_op): Likewise.
100 (vpermil2_op): Likewise.
101
22e8c8e0
RW		 1022008-12-18 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
103
104 * configure: Regenerate.
105
7df76b80
RE		 1062008-12-15 Richard Earnshaw <rearnsha@arm.com>
107
108 * arm-dis.c (coprocessor_opcodes): Disassemble VFP instructions using
109 unified syntax.
110
03547503
L		 1112008-12-08 H.J. Lu <hongjiu.lu@intel.com>
112
113 * i386-gen.c (opcode_modifiers): Move VexNDS before VexNDD.
114
efa7dee7
L		 1152008-12-08 H.J. Lu <hongjiu.lu@intel.com>
116
117 * i386-dis.c (putop): Remove strayed comments.
118
2f3bb96a
BE		 1192008-12-04 Ben Elliston <bje@au.ibm.com>
120
121 * ppc-dis.c (powerpc_init_dialect): Do not set PPC_OPCODE_BOOKE
122 for -Mbooke.
123 (print_ppc_disassembler_options): Update usage.
124 * ppc-opc.c (DE, DES, DEO, DE_MASK): Remove.
125 (BOOKE64): Remove.
126 (PPCCHLK64): Likewise.
127 (powerpc_opcodes): Remove all BOOKE64 instructions.
128
3aa3176b
TS		 1292008-11-28 Joshua Kinard <kumba@gentoo.org>
130
131 * mips-dis.c (mips_arch_choices): Add r14000, r16000.
132
59b098c9
SR		 1332008-11-27 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
134
135 * cr16-dis.c (match_opcode): Truncate mcode to 32 bit and
136 adjusted the mask for 32-bit branch instruction.
137
e1c93c69
AM		 1382008-11-27 Alan Modra <amodra@bigpond.net.au>
139
140 * ppc-opc.c (extract_sprg): Correct operand range check.
141
9f7678f6
AS		 1422008-11-26 Andreas Schwab <schwab@suse.de>
143
144 * m68k-dis.c (NEXTBYTE, NEXTWORD, NEXTLONG, NEXTULONG, NEXTSINGLE)
145 (NEXTDOUBLE, NEXTEXTEND, NEXTPACKED): Fix error handling.
146 (save_printer, save_print_address): Remove.
147 (fetch_data): Don't use them.
148 (match_insn_m68k): Always restore printing functions.
149 (print_insn_m68k): Don't save/restore printing functions.
150
62443ade
NC		 1512008-11-25 Nick Clifton <nickc@redhat.com>
152
153 * m68k-dis.c: Rewrite to remove use of setjmp/longjmp.
154
8e79c3df
CM		 1552008-11-18 Catherine Moore <clm@codesourcery.com>
156
157 * arm-dis.c (coprocessor_opcodes): Add half-precision vcvt
158 instructions.
159 (neon_opcodes): Likewise.
160 (print_insn_coprocessor): Print 't' or 'b' for vcvt
161 instructions.
162
d387240a
TG		 1632008-11-14 Tristan Gingold <gingold@adacore.com>
164
165 * makefile.vms (OBJS): Update list of objects.
166 (DEFS): Update
167 (CFLAGS): Update.
168
4dc48ef6
CF		 1692008-11-06 Chao-ying Fu <fu@mips.com>
170
171 * mips-opc.c (synciobdma, syncs, syncw, syncws): Move these
172 before sync.
173 (sync): New instruction with 5-bit sync type.
3c6528a8 174 * mips-dis.c (print_insn_args): Add case '1' to print 5-bit values.
4dc48ef6 175
c8941035
NC		 1762008-11-06 Nick Clifton <nickc@redhat.com>
177
178 * avr-dis.c: Replace uses of sprintf without a format string with
179 calls to strcpy.
180
a7bea99d
L		 1812008-11-03 H.J. Lu <hongjiu.lu@intel.com>
182
183 * i386-opc.tbl: Add cmovpe and cmovpo.
184 * i386-tbl.h: Regenerated.
185
4267b19f
NC		 1862008-10-22 Nick Clifton <nickc@redhat.com>
187
188 PR 6937
189 * configure.in (SHARED_LIBADD): Revert previous change.
190 Add a comment explaining why.
191 (SHARED_DEPENDENCIES): Revert previous change.
192 * configure: Regenerate.
193
8a9629d0
NC		 1942008-10-10 Nick Clifton <nickc@redhat.com>
195
196 PR 6937
197 * configure.in (SHARED_LIBADD): Add libiberty.a.
198 (SHARED_DEPENDENCIES): Add libiberty.a.
199
c587b3f9
L		 2002008-09-30 H.J. Lu <hongjiu.lu@intel.com>
201
202 * i386-gen.c: Include "hashtab.h".
203 (next_field): Take a new argument, last. Check last.
204 (process_i386_cpu_flag): Updated.
205 (process_i386_opcode_modifier): Likewise.
206 (process_i386_operand_type): Likewise.
207 (process_i386_registers): Likewise.
208 (output_i386_opcode): New.
209 (opcode_hash_entry): Likewise.
210 (opcode_hash_table): Likewise.
211 (opcode_hash_hash): Likewise.
212 (opcode_hash_eq): Likewise.
213 (process_i386_opcodes): Use opcode hash table and opcode array.
214
34b23dab
AK		 2152008-09-30 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
216
217 * s390-opc.txt (stdy, stey): Fix description
218
782e11fd
AM		 2192008-09-30 Alan Modra <amodra@bigpond.net.au>
220
221 * Makefile.am: Run "make dep-am".
222 * Makefile.in: Regenerate.
223
1927a18f
L		 2242008-09-29 H.J. Lu <hongjiu.lu@intel.com>
225
226 * aclocal.m4: Regenerated.
227 * configure: Likewise.
228 * Makefile.in: Likewise.
229
afac680a
NC		 2302008-09-29 Nick Clifton <nickc@redhat.com>
231
232 * po/vi.po: Updated Vietnamese translation.
233 * po/fr.po: Updated French translation.
234
b40d5eb9
AK		 2352008-09-26 Florian Krohm <fkrohm@us.ibm.com>
236
237 * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF.
238 (cfxr, cfdr, cfer, clclu): Add esa flag.
239 (sqd): Instruction added.
240 (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF.
241 * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed.
242
d0411736
AM		 2432008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
244
245 * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes.
246 (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions.
247
3e126784
L		 2482008-09-11 H.J. Lu <hongjiu.lu@intel.com>
249
250 * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
251 * i386-tbl.h: Regenerated.
252
ddab3d59
JB		 2532008-08-28 Jan Beulich <jbeulich@novell.com>
254
255 * i386-dis.c (dis386): Adjust far return mnemonics.
256 * i386-opc.tbl: Add retf.
257 * i386-tbl.h: Re-generate.
258
b19d5385
JB		 2592008-08-28 Jan Beulich <jbeulich@novell.com>
260
261 * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
262
1ca35711
L		 2632008-08-28 H.J. Lu <hongjiu.lu@intel.com>
264
265 * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
266 * ia64-gen.c (lookup_specifier): Likewise.
267
268 * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
269 * ia64-raw.tbl: Likewise.
270 * ia64-waw.tbl: Likewise.
271 * ia64-asmtab.c: Regenerated.
272
515c56e7
L		 2732008-08-27 H.J. Lu <hongjiu.lu@intel.com>
274
275 * i386-opc.tbl: Correct fidivr operand size.
276
277 * i386-tbl.h: Regenerated.
278
da594c4a
AM		 2792008-08-24 Alan Modra <amodra@bigpond.net.au>
280
281 * configure.in: Update a number of obsolete autoconf macros.
282 * aclocal.m4: Regenerate.
283
a5ff0eb2
L		 2842008-08-20 H.J. Lu <hongjiu.lu@intel.com>
285
286 AVX Programming Reference (August, 2008)
287 * i386-dis.c (PREFIX_VEX_38DB): New.
288 (PREFIX_VEX_38DC): Likewise.
289 (PREFIX_VEX_38DD): Likewise.
290 (PREFIX_VEX_38DE): Likewise.
291 (PREFIX_VEX_38DF): Likewise.
292 (PREFIX_VEX_3ADF): Likewise.
293 (VEX_LEN_38DB_P_2): Likewise.
294 (VEX_LEN_38DC_P_2): Likewise.
295 (VEX_LEN_38DD_P_2): Likewise.
296 (VEX_LEN_38DE_P_2): Likewise.
297 (VEX_LEN_38DF_P_2): Likewise.
298 (VEX_LEN_3ADF_P_2): Likewise.
299 (PREFIX_VEX_3A04): Updated.
300 (VEX_LEN_3A06_P_2): Likewise.
301 (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
302 PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
303 (x86_64_table): Likewise.
304 (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
305 VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
306 VEX_LEN_3ADF_P_2.
307
308 * i386-opc.tbl: Add AES + AVX instructions.
309 * i386-init.h: Regenerated.
310 * i386-tbl.h: Likewise.
311
7dc6076f
AK		 3122008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
313
314 * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
315 * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
316
7357c5b6
AM		 3172008-08-15 Alan Modra <amodra@bigpond.net.au>
318
319 PR 6526
320 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
321 * Makefile.in: Regenerate.
322 * aclocal.m4: Regenerate.
323 * config.in: Regenerate.
324 * configure: Regenerate.
325
899d85be
AM		 3262008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
327
328 PR 6825
329 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
330
dfb07592
L		 3312008-08-12 H.J. Lu <hongjiu.lu@intel.com>
332
333 * i386-opc.tbl: Add syscall and sysret for Cpu64.
334
335 * i386-tbl.h: Regenerated.
336
323ee3f4
AM		 3372008-08-04 Alan Modra <amodra@bigpond.net.au>
338
339 * Makefile.am (POTFILES.in): Set LC_ALL=C.
340 * Makefile.in: Regenerate.
341 * po/POTFILES.in: Regenerate.
342
9b4e5766
PB		 3432008-08-01 Peter Bergner <bergner@vnet.ibm.com>
344
345 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
346 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
347 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
348 * ppc-opc.c (insert_xt6): New static function.
349 (extract_xt6): Likewise.
350 (insert_xa6): Likewise.
351 (extract_xa6: Likewise.
352 (insert_xb6): Likewise.
353 (extract_xb6): Likewise.
354 (insert_xb6s): Likewise.
355 (extract_xb6s): Likewise.
356 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
357 XX3DM_MASK, PPCVSX): New.
358 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
359 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
360
20fd6e2e
PA		 3612008-08-01 Pedro Alves <pedro@codesourcery.com>
362
363 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
364 * Makefile.in: Regenerate.
365
a656ed5b
L		 3662008-08-01 H.J. Lu <hongjiu.lu@intel.com>
367
368 * i386-reg.tbl: Use Dw2Inval on AVX registers.
369 * i386-tbl.h: Regenerated.
370
081ba1b3
AM		 3712008-07-30 Michael J. Eager <eager@eagercon.com>
372
373 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
374 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
375 (insert_sprg, PPC405): Use PPC_OPCODE_405.
376 (powerpc_opcodes): Add Xilinx APU related opcodes.
377
0af1713e
AM		 3782008-07-30 Alan Modra <amodra@bigpond.net.au>
379
380 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
381
30c09090
RS		 3822008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
383
384 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
385
c27e721e
AN		 3862008-07-07 Adam Nemet <anemet@caviumnetworks.com>
387
388 * mips-opc.c (CP): New macro.
389 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
390 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
391 dmtc2 Octeon instructions.
392
bd2e2557
SS		 3932008-07-07 Stan Shebs <stan@codesourcery.com>
394
395 * dis-init.c (init_disassemble_info): Init endian_code field.
396 * arm-dis.c (print_insn): Disassemble code according to
397 setting of endian_code.
398 (print_insn_big_arm): Detect when BE8 extension flag has been set.
399
6ba2a415
RS		 4002008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
401
402 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
403 for ELF symbols.
404
c8187e15
PB		 4052008-06-25 Peter Bergner <bergner@vnet.ibm.com>
406
407 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
408 (print_ppc_disassembler_options): Likewise.
409 * ppc-opc.c (PPC464): Define.
410 (powerpc_opcodes): Add mfdcrux and mtdcrux.
411
7a283e07
RW		 4122008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
413
414 * configure: Regenerate.
415
fa452fa6
PB		 4162008-06-13 Peter Bergner <bergner@vnet.ibm.com>
417
418 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
419 ppc_cpu_t typedef.
420 (struct dis_private): New.
421 (POWERPC_DIALECT): New define.
422 (powerpc_dialect): Renamed to...
423 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
424 struct dis_private.
425 (print_insn_big_powerpc): Update for using structure in
426 info->private_data.
427 (print_insn_little_powerpc): Likewise.
428 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
429 (skip_optional_operands): Likewise.
430 (print_insn_powerpc): Likewise. Remove initialization of dialect.
431 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
432 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
433 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
434 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
435 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
436 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
437 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
438 param to be of type ppc_cpu_t. Update prototype.
439
bb35fb24
NC		 4402008-06-12 Adam Nemet <anemet@caviumnetworks.com>
441
442 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
443 +s, +S.
444 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
445 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
446 syncw, syncws, vm3mulu, vm0 and vmulu.
447
dd3cbb7e
NC		 448 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
449 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
450 seqi, sne and snei.
451
a5dabbb0
L		 4522008-05-30 H.J. Lu <hongjiu.lu@intel.com>
453
454 * i386-opc.tbl: Add vmovd with 64bit operand.
455 * i386-tbl.h: Regenerated.
456
725a9891
MS		 4572008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
458
459 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
460
cbc80391
L		 4612008-05-22 H.J. Lu <hongjiu.lu@intel.com>
462
463 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
464 * i386-tbl.h: Regenerated.
465
116615c5
L		 4662008-05-22 H.J. Lu <hongjiu.lu@intel.com>
467
468 PR gas/6517
469 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
3c6528a8 470 into 32bit and 64bit. Remove Reg64|Qword and add
116615c5
L		 471 IgnoreSize|No_qSuf on 32bit version.
472 * i386-tbl.h: Regenerated.
473
d9479f2d
L		 4742008-05-21 H.J. Lu <hongjiu.lu@intel.com>
475
476 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
477 * i386-tbl.h: Regenerated.
478
3ce6fddb
NC		 4792008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
480
481 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
482
8944f3c2
AM		 4832008-05-14 Alan Modra <amodra@bigpond.net.au>
484
485 * Makefile.am: Run "make dep-am".
486 * Makefile.in: Regenerate.
487
f1f8f695
L		 4882008-05-02 H.J. Lu <hongjiu.lu@intel.com>
489
490 * i386-dis.c (MOVBE_Fixup): New.
491 (Mo): Likewise.
492 (PREFIX_0F3880): Likewise.
493 (PREFIX_0F3881): Likewise.
494 (PREFIX_0F38F0): Updated.
495 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
496 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
497 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
498
499 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
500 CPU_EPT_FLAGS.
501 (cpu_flags): Add CpuMovbe and CpuEPT.
502
503 * i386-opc.h (CpuMovbe): New.
504 (CpuEPT): Likewise.
505 (CpuLM): Updated.
506 (i386_cpu_flags): Add cpumovbe and cpuept.
507
508 * i386-opc.tbl: Add entries for movbe and EPT instructions.
509 * i386-init.h: Regenerated.
510 * i386-tbl.h: Likewise.
511
89aa3097
AN		 5122008-04-29 Adam Nemet <anemet@caviumnetworks.com>
513
514 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
515 the two drem and the two dremu macros.
516
39c5c168
AN		 5172008-04-28 Adam Nemet <anemet@caviumnetworks.com>
518
519 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
520 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
521 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
522 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
523
f04d18b7
DM		 5242008-04-25 David S. Miller <davem@davemloft.net>
525
526 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
527 instead of %sys_tick_cmpr, as suggested in architecture manuals.
528
6194aaab
L		 5292008-04-23 Paolo Bonzini <bonzini@gnu.org>
530
531 * aclocal.m4: Regenerate.
532 * configure: Regenerate.
533
1a6b486f
DM		 5342008-04-23 David S. Miller <davem@davemloft.net>
535
536 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
537 extended values.
538 (prefetch_table): Add missing values.
539
81f8a913
L		 5402008-04-22 H.J. Lu <hongjiu.lu@intel.com>
541
542 * i386-gen.c (opcode_modifiers): Add NoAVX.
543
544 * i386-opc.h (NoAVX): New.
545 (OldGcc): Updated.
546 (i386_opcode_modifier): Add noavx.
547
548 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
549 instructions which don't have AVX equivalent.
550 * i386-tbl.h: Regenerated.
551
dae39acc
L		 5522008-04-18 H.J. Lu <hongjiu.lu@intel.com>
553
554 * i386-dis.c (OP_VEX_FMA): New.
555 (OP_EX_VexImmW): Likewise.
556 (VexFMA): Likewise.
557 (Vex128FMA): Likewise.
558 (EXVexImmW): Likewise.
559 (get_vex_imm8): Likewise.
560 (OP_EX_VexReg): Likewise.
561 (vex_i4_done): Renamed to ...
562 (vex_w_done): This.
563 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
564 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
565 FMA instructions.
566 (print_insn): Updated.
567 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
568 (OP_REG_VexI4): Check invalid high registers.
569
ce886ab1
DR		 5702008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
571 Michael Meissner <michael.meissner@amd.com>
572
573 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
574 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 575
19a6653c
AM		 5762008-04-14 Edmar Wienskoski <edmar@freescale.com>
577
578 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
579 accept Power E500MC instructions.
580 (print_ppc_disassembler_options): Document -Me500mc.
581 * ppc-opc.c (DUIS, DUI, T): New.
582 (XRT, XRTRA): Likewise.
583 (E500MC): Likewise.
584 (powerpc_opcodes): Add new Power E500MC instructions.
585
112b7c50
AK		 5862008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
587
588 * s390-dis.c (init_disasm): Evaluate disassembler_options.
589 (print_s390_disassembler_options): New function.
590 * disassemble.c (disassembler_usage): Invoke
591 print_s390_disassembler_options.
592
7ff42648
AK		 5932008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
594
595 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
596 of local variables used for mnemonic parsing: prefix, suffix and
597 number.
598
45a5551e
AK		 5992008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
600
601 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
602 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
603 (s390_crb_extensions): New extensions table.
604 (insertExpandedMnemonic): Handle '$' tag.
605 * s390-opc.txt: Remove conditional jump variants which can now
606 be expanded automatically.
607 Replace '*' tag with '$' in the compare and branch instructions.
608
06c8514a
L		 6092008-04-07 H.J. Lu <hongjiu.lu@intel.com>
610
611 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
612 (PREFIX_VEX_3AXX): Likewis.
613
b122c285
L		 6142008-04-07 H.J. Lu <hongjiu.lu@intel.com>
615
616 * i386-opc.tbl: Remove 4 extra blank lines.
617
594ab6a3
L		 6182008-04-04 H.J. Lu <hongjiu.lu@intel.com>
619
620 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
621 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
622 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
623 * i386-opc.tbl: Likewise.
624
625 * i386-opc.h (CpuCLMUL): Renamed to ...
626 (CpuPCLMUL): This.
627 (CpuFMA): Updated.
628 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
629
630 * i386-init.h: Regenerated.
631
c0f3af97
L		 6322008-04-03 H.J. Lu <hongjiu.lu@intel.com>
633
634 * i386-dis.c (OP_E_register): New.
635 (OP_E_memory): Likewise.
636 (OP_VEX): Likewise.
637 (OP_EX_Vex): Likewise.
638 (OP_EX_VexW): Likewise.
639 (OP_XMM_Vex): Likewise.
640 (OP_XMM_VexW): Likewise.
641 (OP_REG_VexI4): Likewise.
642 (PCLMUL_Fixup): Likewise.
643 (VEXI4_Fixup): Likewise.
644 (VZERO_Fixup): Likewise.
645 (VCMP_Fixup): Likewise.
646 (VPERMIL2_Fixup): Likewise.
647 (rex_original): Likewise.
648 (rex_ignored): Likewise.
649 (Mxmm): Likewise.
650 (XMM): Likewise.
651 (EXxmm): Likewise.
652 (EXxmmq): Likewise.
653 (EXymmq): Likewise.
654 (Vex): Likewise.
655 (Vex128): Likewise.
656 (Vex256): Likewise.
657 (VexI4): Likewise.
658 (EXdVex): Likewise.
659 (EXqVex): Likewise.
660 (EXVexW): Likewise.
661 (EXdVexW): Likewise.
662 (EXqVexW): Likewise.
663 (XMVex): Likewise.
664 (XMVexW): Likewise.
665 (XMVexI4): Likewise.
666 (PCLMUL): Likewise.
667 (VZERO): Likewise.
668 (VCMP): Likewise.
669 (VPERMIL2): Likewise.
670 (xmm_mode): Likewise.
671 (xmmq_mode): Likewise.
672 (ymmq_mode): Likewise.
673 (vex_mode): Likewise.
674 (vex128_mode): Likewise.
675 (vex256_mode): Likewise.
676 (USE_VEX_C4_TABLE): Likewise.
677 (USE_VEX_C5_TABLE): Likewise.
678 (USE_VEX_LEN_TABLE): Likewise.
679 (VEX_C4_TABLE): Likewise.
680 (VEX_C5_TABLE): Likewise.
681 (VEX_LEN_TABLE): Likewise.
682 (REG_VEX_XX): Likewise.
683 (MOD_VEX_XXX): Likewise.
684 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
685 (PREFIX_0F3A44): Likewise.
686 (PREFIX_0F3ADF): Likewise.
687 (PREFIX_VEX_XXX): Likewise.
688 (VEX_OF): Likewise.
689 (VEX_OF38): Likewise.
690 (VEX_OF3A): Likewise.
691 (VEX_LEN_XXX): Likewise.
692 (vex): Likewise.
693 (need_vex): Likewise.
694 (need_vex_reg): Likewise.
695 (vex_i4_done): Likewise.
696 (vex_table): Likewise.
697 (vex_len_table): Likewise.
698 (OP_REG_VexI4): Likewise.
699 (vex_cmp_op): Likewise.
700 (pclmul_op): Likewise.
701 (vpermil2_op): Likewise.
702 (m_mode): Updated.
703 (es_reg): Likewise.
704 (PREFIX_0F38F0): Likewise.
705 (PREFIX_0F3A60): Likewise.
706 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
707 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
708 and PREFIX_VEX_XXX entries.
709 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
710 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
711 PREFIX_0F3ADF.
712 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
713 Add MOD_VEX_XXX entries.
714 (ckprefix): Initialize rex_original and rex_ignored. Store the
715 REX byte in rex_original.
716 (get_valid_dis386): Handle the implicit prefix in VEX prefix
717 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
718 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
719 calling get_valid_dis386. Use rex_original and rex_ignored when
720 printing out REX.
721 (putop): Handle "XY".
722 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
723 ymmq_mode.
724 (OP_E_extended): Updated to use OP_E_register and
725 OP_E_memory.
726 (OP_XMM): Handle VEX.
727 (OP_EX): Likewise.
728 (XMM_Fixup): Likewise.
729 (CMP_Fixup): Use ARRAY_SIZE.
730
731 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
732 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
733 (operand_type_init): Add OPERAND_TYPE_REGYMM and
734 OPERAND_TYPE_VEX_IMM4.
735 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
736 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
737 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
738 VexImmExt and SSE2AVX.
739 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
740
741 * i386-opc.h (CpuAVX): New.
742 (CpuAES): Likewise.
743 (CpuCLMUL): Likewise.
744 (CpuFMA): Likewise.
745 (Vex): Likewise.
746 (Vex256): Likewise.
747 (VexNDS): Likewise.
748 (VexNDD): Likewise.
749 (VexW0): Likewise.
750 (VexW1): Likewise.
751 (Vex0F): Likewise.
752 (Vex0F38): Likewise.
753 (Vex0F3A): Likewise.
754 (Vex3Sources): Likewise.
755 (VexImmExt): Likewise.
756 (SSE2AVX): Likewise.
757 (RegYMM): Likewise.
758 (Ymmword): Likewise.
759 (Vex_Imm4): Likewise.
760 (Implicit1stXmm0): Likewise.
761 (CpuXsave): Updated.
762 (CpuLM): Likewise.
763 (ByteOkIntel): Likewise.
764 (OldGcc): Likewise.
765 (Control): Likewise.
766 (Unspecified): Likewise.
767 (OTMax): Likewise.
768 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
769 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
770 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
771 vex3sources, veximmext and sse2avx.
772 (i386_operand_type): Add regymm, ymmword and vex_imm4.
773
774 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
775
776 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
777
778 * i386-init.h: Regenerated.
779 * i386-tbl.h: Likewise.
780
b21c9cb4
BS		 7812008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
782
783 From Robin Getz <robin.getz@analog.com>
784 * bfin-dis.c (bu32): Typedef.
785 (enum const_forms_t): Add c_uimm32 and c_huimm32.
786 (constant_formats[]): Add uimm32 and huimm16.
787 (fmtconst_val): New.
788 (uimm32): Define.
789 (huimm32): Define.
790 (imm16_val): Define.
791 (luimm16_val): Define.
792 (struct saved_state): Define.
793 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
794 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
795 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
796 (get_allreg): New.
797 (decode_LDIMMhalf_0): Print out the whole register value.
798
ee171c8f
BS		 799 From Jie Zhang <jie.zhang@analog.com>
800 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
801 multiply and multiply-accumulate to data register instruction.
802
086134ec
BS		 803 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
804 c_imm32, c_huimm32e): Define.
805 (constant_formats): Add flags for printing decimal, leading spaces, and
806 exact symbols.
807 (comment, parallel): Add global flags in all disassembly.
808 (fmtconst): Take advantage of new flags, and print default in hex.
809 (fmtconst_val): Likewise.
810 (decode_macfunc): Be consistant with spaces, tabs, comments,
811 capitalization in disassembly, fix minor coding style issues.
812 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
813 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
814 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
815 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
816 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
817 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
818 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
819 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
820 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
821 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
822 _print_insn_bfin, print_insn_bfin): Likewise.
823
58c85be7
RW		 8242008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
825
826 * aclocal.m4: Regenerate.
827 * configure: Likewise.
828 * Makefile.in: Likewise.
829
50e7d84b
AM		 8302008-03-13 Alan Modra <amodra@bigpond.net.au>
831
832 * Makefile.am: Run "make dep-am".
833 * Makefile.in: Regenerate.
834 * configure: Regenerate.
835
de866fcc
AM		 8362008-03-07 Alan Modra <amodra@bigpond.net.au>
837
838 * ppc-opc.c (powerpc_opcodes): Order and format.
839
28dbc079
L		 8402008-03-01 H.J. Lu <hongjiu.lu@intel.com>
841
842 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
843 * i386-tbl.h: Regenerated.
844
849830bd
L		 8452008-02-23 H.J. Lu <hongjiu.lu@intel.com>
846
847 * i386-opc.tbl: Disallow 16-bit near indirect branches for
848 x86-64.
849 * i386-tbl.h: Regenerated.
850
743ddb6b
JB		 8512008-02-21 Jan Beulich <jbeulich@novell.com>
852
853 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
854 and Fword for far indirect jmp. Allow Reg16 and Word for near
855 indirect jmp on x86-64. Disallow Fword for lcall.
856 * i386-tbl.h: Re-generate.
857
796d5313
NC		 8582008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
859
860 * cr16-opc.c (cr16_num_optab): Defined
861
65da13b5
L		 8622008-02-16 H.J. Lu <hongjiu.lu@intel.com>
863
864 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
865 * i386-init.h: Regenerated.
866
0e336180
NC		 8672008-02-14 Nick Clifton <nickc@redhat.com>
868
869 PR binutils/5524
870 * configure.in (SHARED_LIBADD): Select the correct host specific
871 file extension for shared libraries.
872 * configure: Regenerate.
873
b7240065
JB		 8742008-02-13 Jan Beulich <jbeulich@novell.com>
875
876 * i386-opc.h (RegFlat): New.
877 * i386-reg.tbl (flat): Add.
878 * i386-tbl.h: Re-generate.
879
34b772a6
JB		 8802008-02-13 Jan Beulich <jbeulich@novell.com>
881
882 * i386-dis.c (a_mode): New.
883 (cond_jump_mode): Adjust.
884 (Ma): Change to a_mode.
885 (intel_operand_size): Handle a_mode.
886 * i386-opc.tbl: Allow Dword and Qword for bound.
887 * i386-tbl.h: Re-generate.
888
a60de03c
JB		 8892008-02-13 Jan Beulich <jbeulich@novell.com>
890
891 * i386-gen.c (process_i386_registers): Process new fields.
892 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
893 unsigned char. Add dw2_regnum and Dw2Inval.
894 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
895 register names.
896 * i386-tbl.h: Re-generate.
897
f03fe4c1
L		 8982008-02-11 H.J. Lu <hongjiu.lu@intel.com>
899
4b6bc8eb 900 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 901 * i386-init.h: Updated.
902
475a2301
L		 9032008-02-11 H.J. Lu <hongjiu.lu@intel.com>
904
905 * i386-gen.c (cpu_flags): Add CpuXsave.
906
907 * i386-opc.h (CpuXsave): New.
4b6bc8eb 908 (CpuLM): Updated.
475a2301
L		 909 (i386_cpu_flags): Add cpuxsave.
910
911 * i386-dis.c (MOD_0FAE_REG_4): New.
912 (RM_0F01_REG_2): Likewise.
913 (MOD_0FAE_REG_5): Updated.
914 (RM_0F01_REG_3): Likewise.
915 (reg_table): Use MOD_0FAE_REG_4.
916 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
917 for xrstor.
918 (rm_table): Add RM_0F01_REG_2.
919
920 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
921 * i386-init.h: Regenerated.
922 * i386-tbl.h: Likewise.
923
595785c6 9242008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 925
595785c6
JB		 926 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
927 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
928 * i386-tbl.h: Re-generate.
929
bb8541b9
L		 9302008-02-04 H.J. Lu <hongjiu.lu@intel.com>
931
932 PR 5715
933 * configure: Regenerated.
934
57b592a3
AN		 9352008-02-04 Adam Nemet <anemet@caviumnetworks.com>
936
937 * mips-dis.c: Update copyright.
938 (mips_arch_choices): Add Octeon.
939 * mips-opc.c: Update copyright.
940 (IOCT): New macro.
941 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
942
930bb4cf
AM		 9432008-01-29 Alan Modra <amodra@bigpond.net.au>
944
945 * ppc-opc.c: Support optional L form mtmsr.
946
82c18208
L		 9472008-01-24 H.J. Lu <hongjiu.lu@intel.com>
948
949 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
950
599121aa
L		 9512008-01-23 H.J. Lu <hongjiu.lu@intel.com>
952
953 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
954 * i386-init.h: Regenerated.
955
80098f51
TG		 9562008-01-23 Tristan Gingold <gingold@adacore.com>
957
958 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
959 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
960
115c7c25
L		 9612008-01-22 H.J. Lu <hongjiu.lu@intel.com>
962
963 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
964 (cpu_flags): Likewise.
965
966 * i386-opc.h (CpuMMX2): Removed.
967 (CpuSSE): Updated.
968
969 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
970 * i386-init.h: Regenerated.
971 * i386-tbl.h: Likewise.
972
6305a203
L		 9732008-01-22 H.J. Lu <hongjiu.lu@intel.com>
974
975 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
976 CPU_SMX_FLAGS.
977 * i386-init.h: Regenerated.
978
fd07a1c8
L		 9792008-01-15 H.J. Lu <hongjiu.lu@intel.com>
980
981 * i386-opc.tbl: Use Qword on movddup.
982 * i386-tbl.h: Regenerated.
983
321fd21e
L		 9842008-01-15 H.J. Lu <hongjiu.lu@intel.com>
985
986 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
987 * i386-tbl.h: Regenerated.
988
4ee52178
L		 9892008-01-15 H.J. Lu <hongjiu.lu@intel.com>
990
991 * i386-dis.c (Mx): New.
992 (PREFIX_0FC3): Likewise.
993 (PREFIX_0FC7_REG_6): Updated.
994 (dis386_twobyte): Use PREFIX_0FC3.
995 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
996 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
997 movntss.
998
5c07affc
L		 9992008-01-14 H.J. Lu <hongjiu.lu@intel.com>
1000
1001 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
1002 (operand_types): Add Mem.
1003
1004 * i386-opc.h (IntelSyntax): New.
1005 * i386-opc.h (Mem): New.
1006 (Byte): Updated.
1007 (Opcode_Modifier_Max): Updated.
1008 (i386_opcode_modifier): Add intelsyntax.
1009 (i386_operand_type): Add mem.
1010
1011 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
1012 instructions.
1013
1014 * i386-reg.tbl: Add size for accumulator.
1015
1016 * i386-init.h: Regenerated.
1017 * i386-tbl.h: Likewise.
1018
0d6a2f58
L		 10192008-01-13 H.J. Lu <hongjiu.lu@intel.com>
1020
1021 * i386-opc.h (Byte): Fix a typo.
1022
7d5e4556
L		 10232008-01-12 H.J. Lu <hongjiu.lu@intel.com>
1024
1025 PR gas/5534
1026 * i386-gen.c (operand_type_init): Add Dword to
1027 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
1028 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
1029 Qword and Xmmword.
1030 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
1031 Xmmword, Unspecified and Anysize.
1032 (set_bitfield): Make Mmword an alias of Qword. Make Oword
1033 an alias of Xmmword.
1034
1035 * i386-opc.h (CheckSize): Removed.
1036 (Byte): Updated.
1037 (Word): Likewise.
1038 (Dword): Likewise.
1039 (Qword): Likewise.
1040 (Xmmword): Likewise.
1041 (FWait): Updated.
1042 (OTMax): Likewise.
1043 (i386_opcode_modifier): Remove checksize, byte, word, dword,
1044 qword and xmmword.
1045 (Fword): New.
1046 (TBYTE): Likewise.
1047 (Unspecified): Likewise.
1048 (Anysize): Likewise.
1049 (i386_operand_type): Add byte, word, dword, fword, qword,
1050 tbyte xmmword, unspecified and anysize.
1051
1052 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
1053 Tbyte, Xmmword, Unspecified and Anysize.
1054
1055 * i386-reg.tbl: Add size for accumulator.
1056
1057 * i386-init.h: Regenerated.
1058 * i386-tbl.h: Likewise.
1059
b5b1fc4f
L		 10602008-01-10 H.J. Lu <hongjiu.lu@intel.com>
1061
1062 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
1063 (REG_0F18): Updated.
1064 (reg_table): Updated.
1065 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
1066 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
1067
50e8458f
L		 10682008-01-08 H.J. Lu <hongjiu.lu@intel.com>
1069
1070 * i386-gen.c (set_bitfield): Use fail () on error.
1071
3d4d5afa
L		 10722008-01-08 H.J. Lu <hongjiu.lu@intel.com>
1073
1074 * i386-gen.c (lineno): New.
1075 (filename): Likewise.
1076 (set_bitfield): Report filename and line numer on error.
1077 (process_i386_opcodes): Set filename and update lineno.
1078 (process_i386_registers): Likewise.
1079
e1d4d893
L		 10802008-01-05 H.J. Lu <hongjiu.lu@intel.com>
1081
1082 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
1083 ATTSyntax.
1084
1085 * i386-opc.h (IntelMnemonic): Renamed to ..
1086 (ATTSyntax): This
1087 (Opcode_Modifier_Max): Updated.
1088 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
1089 and intelsyntax.
1090
8944f3c2 1091 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 1092 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
1093 * i386-tbl.h: Regenerated.
1094
6f143e4d
L		 10952008-01-04 H.J. Lu <hongjiu.lu@intel.com>
1096
1097 * i386-gen.c: Update copyright to 2008.
1098 * i386-opc.h: Likewise.
1099 * i386-opc.tbl: Likewise.
1100
1101 * i386-init.h: Regenerated.
1102 * i386-tbl.h: Likewise.
1103
c6add537
L		 11042008-01-04 H.J. Lu <hongjiu.lu@intel.com>
1105
1106 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
1107 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
1108 * i386-tbl.h: Regenerated.
1109
3629bb00
L		 11102008-01-03 H.J. Lu <hongjiu.lu@intel.com>
1111
1112 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
1113 CpuSSE4_2_Or_ABM.
1114 (cpu_flags): Likewise.
1115
1116 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
1117 (CpuSSE4_2_Or_ABM): Likewise.
1118 (CpuLM): Updated.
1119 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
1120
1121 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
1122 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
1123 and CpuPadLock, respectively.
1124 * i386-init.h: Regenerated.
1125 * i386-tbl.h: Likewise.
1126
24995bd6
L		 11272008-01-03 H.J. Lu <hongjiu.lu@intel.com>
1128
1129 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
1130
1131 * i386-opc.h (No_xSuf): Removed.
1132 (CheckSize): Updated.
1133
1134 * i386-tbl.h: Regenerated.
1135
e0329a22
L		 11362008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1137
1138 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
1139 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
1140 CPU_SSE5_FLAGS.
1141 (cpu_flags): Add CpuSSE4_2_Or_ABM.
1142
1143 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
1144 (CpuLM): Updated.
1145 (i386_cpu_flags): Add cpusse4_2_or_abm.
1146
1147 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
1148 CpuABM|CpuSSE4_2 on popcnt.
1149 * i386-init.h: Regenerated.
1150 * i386-tbl.h: Likewise.
1151
f2a9c676
L		 11522008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1153
1154 * i386-opc.h: Update comments.
1155
d978b5be
L		 11562008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1157
1158 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
1159 * i386-opc.h: Likewise.
1160 * i386-opc.tbl: Likewise.
1161
582d5edd
L		 11622008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1163
1164 PR gas/5534
1165 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
1166 Byte, Word, Dword, QWord and Xmmword.
1167
1168 * i386-opc.h (No_xSuf): New.
1169 (CheckSize): Likewise.
1170 (Byte): Likewise.
1171 (Word): Likewise.
1172 (Dword): Likewise.
1173 (QWord): Likewise.
1174 (Xmmword): Likewise.
1175 (FWait): Updated.
1176 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
1177 Dword, QWord and Xmmword.
1178
1179 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
1180 used.
1181 * i386-tbl.h: Regenerated.
1182
3fe15143
MK		 11832008-01-02 Mark Kettenis <kettenis@gnu.org>
1184
1185 * m88k-dis.c (instructions): Fix fcvt.* instructions.
1186 From Miod Vallat.
1187
6c7ac64e 1188For older changes see ChangeLog-2007
252b5132
RH		 1189\f
1190Local Variables:
2f6d2f85
NC		 1191mode: change-log
1192left-margin: 8
1193fill-column: 74
252b5132
RH		 1194version-control: never
1195End:
GDB Binutils - Deliverables
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