PR22069, Several instances of register accidentally spelled as regsiter
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
84f9f8c3
AM
12018-05-09 Sebastian Rasmussen <sebras@gmail.com>
2
3 * cr16-opc.c (cr16_instruction): Comment typo fix.
4 * hppa-dis.c (print_insn_hppa): Likewise.
5
e6f372ba
JW
62018-05-08 Jim Wilson <jimw@sifive.com>
7
8 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
9 (match_c_slli64, match_srxi_as_c_srxi): New.
10 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
11 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
12 <c.slli, c.srli, c.srai>: Use match_s_slli.
13 <c.slli64, c.srli64, c.srai64>: New.
14
f413a913
AM
152018-05-08 Alan Modra <amodra@gmail.com>
16
17 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
18 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
19 partition opcode space for index lookup.
20
a87a6478
PB
212018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
22
23 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
24 <insn_length>: ...with this. Update usage.
25 Remove duplicate call to *info->memory_error_func.
26
c0a30a9f
L
272018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
28 H.J. Lu <hongjiu.lu@intel.com>
29
30 * i386-dis.c (Gva): New.
31 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
32 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
33 (prefix_table): New instructions (see prefix above).
34 (mod_table): New instructions (see prefix above).
35 (OP_G): Handle va_mode.
36 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
37 CPU_MOVDIR64B_FLAGS.
38 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
39 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
40 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
41 * i386-opc.tbl: Add movidir{i,64b}.
42 * i386-init.h: Regenerated.
43 * i386-tbl.h: Likewise.
44
75c0a438
L
452018-05-07 H.J. Lu <hongjiu.lu@intel.com>
46
47 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
48 AddrPrefixOpReg.
49 * i386-opc.h (AddrPrefixOp0): Renamed to ...
50 (AddrPrefixOpReg): This.
51 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
52 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
53
2ceb7719
PB
542018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
55
56 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
57 (vle_num_opcodes): Likewise.
58 (spe2_num_opcodes): Likewise.
59 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
60 initialization loop.
61 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
62 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
63 only once.
64
b3ac5c6c
TC
652018-05-01 Tamar Christina <tamar.christina@arm.com>
66
67 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
68
fe944acf
FT
692018-04-30 Francois H. Theron <francois.theron@netronome.com>
70
71 Makefile.am: Added nfp-dis.c.
72 configure.ac: Added bfd_nfp_arch.
73 disassemble.h: Added print_insn_nfp prototype.
74 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
75 nfp-dis.c: New, for NFP support.
76 po/POTFILES.in: Added nfp-dis.c to the list.
77 Makefile.in: Regenerate.
78 configure: Regenerate.
79
e2195274
JB
802018-04-26 Jan Beulich <jbeulich@suse.com>
81
82 * i386-opc.tbl: Fold various non-memory operand AVX512VL
83 templates into their base ones.
84 * i386-tlb.h: Re-generate.
85
59ef5df4
JB
862018-04-26 Jan Beulich <jbeulich@suse.com>
87
88 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
89 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
90 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
91 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
92 * i386-init.h: Re-generate.
93
6e041cf4
JB
942018-04-26 Jan Beulich <jbeulich@suse.com>
95
96 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
97 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
98 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
99 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
100 comment.
101 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
102 and CpuRegMask.
103 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
104 CpuRegMask: Delete.
105 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
106 cpuregzmm, and cpuregmask.
107 * i386-init.h: Re-generate.
108 * i386-tbl.h: Re-generate.
109
0e0eea78
JB
1102018-04-26 Jan Beulich <jbeulich@suse.com>
111
112 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
113 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
114 * i386-init.h: Re-generate.
115
2f1bada2
JB
1162018-04-26 Jan Beulich <jbeulich@suse.com>
117
118 * i386-gen.c (VexImmExt): Delete.
119 * i386-opc.h (VexImmExt, veximmext): Delete.
120 * i386-opc.tbl: Drop all VexImmExt uses.
121 * i386-tlb.h: Re-generate.
122
bacd1457
JB
1232018-04-25 Jan Beulich <jbeulich@suse.com>
124
125 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
126 register-only forms.
127 * i386-tlb.h: Re-generate.
128
10bba94b
TC
1292018-04-25 Tamar Christina <tamar.christina@arm.com>
130
131 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
132
c48935d7
IT
1332018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
134
135 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
136 PREFIX_0F1C.
137 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
138 (cpu_flags): Add CpuCLDEMOTE.
139 * i386-init.h: Regenerate.
140 * i386-opc.h (enum): Add CpuCLDEMOTE,
141 (i386_cpu_flags): Add cpucldemote.
142 * i386-opc.tbl: Add cldemote.
143 * i386-tbl.h: Regenerate.
144
211dc24b
AM
1452018-04-16 Alan Modra <amodra@gmail.com>
146
147 * Makefile.am: Remove sh5 and sh64 support.
148 * configure.ac: Likewise.
149 * disassemble.c: Likewise.
150 * disassemble.h: Likewise.
151 * sh-dis.c: Likewise.
152 * sh64-dis.c: Delete.
153 * sh64-opc.c: Delete.
154 * sh64-opc.h: Delete.
155 * Makefile.in: Regenerate.
156 * configure: Regenerate.
157 * po/POTFILES.in: Regenerate.
158
a9a4b302
AM
1592018-04-16 Alan Modra <amodra@gmail.com>
160
161 * Makefile.am: Remove w65 support.
162 * configure.ac: Likewise.
163 * disassemble.c: Likewise.
164 * disassemble.h: Likewise.
165 * w65-dis.c: Delete.
166 * w65-opc.h: Delete.
167 * Makefile.in: Regenerate.
168 * configure: Regenerate.
169 * po/POTFILES.in: Regenerate.
170
04cb01fd
AM
1712018-04-16 Alan Modra <amodra@gmail.com>
172
173 * configure.ac: Remove we32k support.
174 * configure: Regenerate.
175
c2bf1eec
AM
1762018-04-16 Alan Modra <amodra@gmail.com>
177
178 * Makefile.am: Remove m88k support.
179 * configure.ac: Likewise.
180 * disassemble.c: Likewise.
181 * disassemble.h: Likewise.
182 * m88k-dis.c: Delete.
183 * Makefile.in: Regenerate.
184 * configure: Regenerate.
185 * po/POTFILES.in: Regenerate.
186
6793974d
AM
1872018-04-16 Alan Modra <amodra@gmail.com>
188
189 * Makefile.am: Remove i370 support.
190 * configure.ac: Likewise.
191 * disassemble.c: Likewise.
192 * disassemble.h: Likewise.
193 * i370-dis.c: Delete.
194 * i370-opc.c: Delete.
195 * Makefile.in: Regenerate.
196 * configure: Regenerate.
197 * po/POTFILES.in: Regenerate.
198
e82aa794
AM
1992018-04-16 Alan Modra <amodra@gmail.com>
200
201 * Makefile.am: Remove h8500 support.
202 * configure.ac: Likewise.
203 * disassemble.c: Likewise.
204 * disassemble.h: Likewise.
205 * h8500-dis.c: Delete.
206 * h8500-opc.h: Delete.
207 * Makefile.in: Regenerate.
208 * configure: Regenerate.
209 * po/POTFILES.in: Regenerate.
210
fceadf09
AM
2112018-04-16 Alan Modra <amodra@gmail.com>
212
213 * configure.ac: Remove tahoe support.
214 * configure: Regenerate.
215
ae1d3843
L
2162018-04-15 H.J. Lu <hongjiu.lu@intel.com>
217
218 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
219 umwait.
220 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
221 64-bit mode.
222 * i386-tbl.h: Regenerated.
223
de89d0a3
IT
2242018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
225
226 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
227 PREFIX_MOD_1_0FAE_REG_6.
228 (va_mode): New.
229 (OP_E_register): Use va_mode.
230 * i386-dis-evex.h (prefix_table):
231 New instructions (see prefixes above).
232 * i386-gen.c (cpu_flag_init): Add WAITPKG.
233 (cpu_flags): Likewise.
234 * i386-opc.h (enum): Likewise.
235 (i386_cpu_flags): Likewise.
236 * i386-opc.tbl: Add umonitor, umwait, tpause.
237 * i386-init.h: Regenerate.
238 * i386-tbl.h: Likewise.
239
a8eb42a8
AM
2402018-04-11 Alan Modra <amodra@gmail.com>
241
242 * opcodes/i860-dis.c: Delete.
243 * opcodes/i960-dis.c: Delete.
244 * Makefile.am: Remove i860 and i960 support.
245 * configure.ac: Likewise.
246 * disassemble.c: Likewise.
247 * disassemble.h: Likewise.
248 * Makefile.in: Regenerate.
249 * configure: Regenerate.
250 * po/POTFILES.in: Regenerate.
251
caf0678c
L
2522018-04-04 H.J. Lu <hongjiu.lu@intel.com>
253
254 PR binutils/23025
255 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
256 to 0.
257 (print_insn): Clear vex instead of vex.evex.
258
4fb0d2b9
NC
2592018-04-04 Nick Clifton <nickc@redhat.com>
260
261 * po/es.po: Updated Spanish translation.
262
c39e5b26
JB
2632018-03-28 Jan Beulich <jbeulich@suse.com>
264
265 * i386-gen.c (opcode_modifiers): Delete VecESize.
266 * i386-opc.h (VecESize): Delete.
267 (struct i386_opcode_modifier): Delete vecesize.
268 * i386-opc.tbl: Drop VecESize.
269 * i386-tlb.h: Re-generate.
270
8e6e0792
JB
2712018-03-28 Jan Beulich <jbeulich@suse.com>
272
273 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
274 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
275 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
276 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
277 * i386-tlb.h: Re-generate.
278
9f123b91
JB
2792018-03-28 Jan Beulich <jbeulich@suse.com>
280
281 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
282 Fold AVX512 forms
283 * i386-tlb.h: Re-generate.
284
9646c87b
JB
2852018-03-28 Jan Beulich <jbeulich@suse.com>
286
287 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
288 (vex_len_table): Drop Y for vcvt*2si.
289 (putop): Replace plain 'Y' handling by abort().
290
c8d59609
NC
2912018-03-28 Nick Clifton <nickc@redhat.com>
292
293 PR 22988
294 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
295 instructions with only a base address register.
296 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
297 handle AARHC64_OPND_SVE_ADDR_R.
298 (aarch64_print_operand): Likewise.
299 * aarch64-asm-2.c: Regenerate.
300 * aarch64_dis-2.c: Regenerate.
301 * aarch64-opc-2.c: Regenerate.
302
b8c169f3
JB
3032018-03-22 Jan Beulich <jbeulich@suse.com>
304
305 * i386-opc.tbl: Drop VecESize from register only insn forms and
306 memory forms not allowing broadcast.
307 * i386-tlb.h: Re-generate.
308
96bc132a
JB
3092018-03-22 Jan Beulich <jbeulich@suse.com>
310
311 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
312 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
313 sha256*): Drop Disp<N>.
314
9f79e886
JB
3152018-03-22 Jan Beulich <jbeulich@suse.com>
316
317 * i386-dis.c (EbndS, bnd_swap_mode): New.
318 (prefix_table): Use EbndS.
319 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
320 * i386-opc.tbl (bndmov): Move misplaced Load.
321 * i386-tlb.h: Re-generate.
322
d6793fa1
JB
3232018-03-22 Jan Beulich <jbeulich@suse.com>
324
325 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
326 templates allowing memory operands and folded ones for register
327 only flavors.
328 * i386-tlb.h: Re-generate.
329
f7768225
JB
3302018-03-22 Jan Beulich <jbeulich@suse.com>
331
332 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
333 256-bit templates. Drop redundant leftover Disp<N>.
334 * i386-tlb.h: Re-generate.
335
0e35537d
JW
3362018-03-14 Kito Cheng <kito.cheng@gmail.com>
337
338 * riscv-opc.c (riscv_insn_types): New.
339
b4a3689a
NC
3402018-03-13 Nick Clifton <nickc@redhat.com>
341
342 * po/pt_BR.po: Updated Brazilian Portuguese translation.
343
d3d50934
L
3442018-03-08 H.J. Lu <hongjiu.lu@intel.com>
345
346 * i386-opc.tbl: Add Optimize to clr.
347 * i386-tbl.h: Regenerated.
348
bd5dea88
L
3492018-03-08 H.J. Lu <hongjiu.lu@intel.com>
350
351 * i386-gen.c (opcode_modifiers): Remove OldGcc.
352 * i386-opc.h (OldGcc): Removed.
353 (i386_opcode_modifier): Remove oldgcc.
354 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
355 instructions for old (<= 2.8.1) versions of gcc.
356 * i386-tbl.h: Regenerated.
357
e771e7c9
JB
3582018-03-08 Jan Beulich <jbeulich@suse.com>
359
360 * i386-opc.h (EVEXDYN): New.
361 * i386-opc.tbl: Fold various AVX512VL templates.
362 * i386-tlb.h: Re-generate.
363
ed438a93
JB
3642018-03-08 Jan Beulich <jbeulich@suse.com>
365
366 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
367 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
368 vpexpandd, vpexpandq): Fold AFX512VF templates.
369 * i386-tlb.h: Re-generate.
370
454172a9
JB
3712018-03-08 Jan Beulich <jbeulich@suse.com>
372
373 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
374 Fold 128- and 256-bit VEX-encoded templates.
375 * i386-tlb.h: Re-generate.
376
36824150
JB
3772018-03-08 Jan Beulich <jbeulich@suse.com>
378
379 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
380 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
381 vpexpandd, vpexpandq): Fold AVX512F templates.
382 * i386-tlb.h: Re-generate.
383
e7f5c0a9
JB
3842018-03-08 Jan Beulich <jbeulich@suse.com>
385
386 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
387 64-bit templates. Drop Disp<N>.
388 * i386-tlb.h: Re-generate.
389
25a4277f
JB
3902018-03-08 Jan Beulich <jbeulich@suse.com>
391
392 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
393 and 256-bit templates.
394 * i386-tlb.h: Re-generate.
395
d2224064
JB
3962018-03-08 Jan Beulich <jbeulich@suse.com>
397
398 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
399 * i386-tlb.h: Re-generate.
400
1b193f0b
JB
4012018-03-08 Jan Beulich <jbeulich@suse.com>
402
403 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
404 Drop NoAVX.
405 * i386-tlb.h: Re-generate.
406
f2f6a710
JB
4072018-03-08 Jan Beulich <jbeulich@suse.com>
408
409 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
410 * i386-tlb.h: Re-generate.
411
38e314eb
JB
4122018-03-08 Jan Beulich <jbeulich@suse.com>
413
414 * i386-gen.c (opcode_modifiers): Delete FloatD.
415 * i386-opc.h (FloatD): Delete.
416 (struct i386_opcode_modifier): Delete floatd.
417 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
418 FloatD by D.
419 * i386-tlb.h: Re-generate.
420
d53e6b98
JB
4212018-03-08 Jan Beulich <jbeulich@suse.com>
422
423 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
424
2907c2f5
JB
4252018-03-08 Jan Beulich <jbeulich@suse.com>
426
427 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
428 * i386-tlb.h: Re-generate.
429
73053c1f
JB
4302018-03-08 Jan Beulich <jbeulich@suse.com>
431
432 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
433 forms.
434 * i386-tlb.h: Re-generate.
435
52fe4420
AM
4362018-03-07 Alan Modra <amodra@gmail.com>
437
438 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
439 bfd_arch_rs6000.
440 * disassemble.h (print_insn_rs6000): Delete.
441 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
442 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
443 (print_insn_rs6000): Delete.
444
a6743a54
AM
4452018-03-03 Alan Modra <amodra@gmail.com>
446
447 * sysdep.h (opcodes_error_handler): Define.
448 (_bfd_error_handler): Declare.
449 * Makefile.am: Remove stray #.
450 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
451 EDIT" comment.
452 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
453 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
454 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
455 opcodes_error_handler to print errors. Standardize error messages.
456 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
457 and include opintl.h.
458 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
459 * i386-gen.c: Standardize error messages.
460 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
461 * Makefile.in: Regenerate.
462 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
463 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
464 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
465 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
466 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
467 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
468 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
469 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
470 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
471 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
472 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
473 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
474 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
475
8305403a
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4762018-03-01 H.J. Lu <hongjiu.lu@intel.com>
477
478 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
479 vpsub[bwdq] instructions.
480 * i386-tbl.h: Regenerated.
481
e184813f
AM
4822018-03-01 Alan Modra <amodra@gmail.com>
483
484 * configure.ac (ALL_LINGUAS): Sort.
485 * configure: Regenerate.
486
5b616bef
TP
4872018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
488
489 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
490 macro by assignements.
491
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4922018-02-27 H.J. Lu <hongjiu.lu@intel.com>
493
494 PR gas/22871
495 * i386-gen.c (opcode_modifiers): Add Optimize.
496 * i386-opc.h (Optimize): New enum.
497 (i386_opcode_modifier): Add optimize.
498 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
499 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
500 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
501 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
502 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
503 vpxord and vpxorq.
504 * i386-tbl.h: Regenerated.
505
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5062018-02-26 Alan Modra <amodra@gmail.com>
507
508 * crx-dis.c (getregliststring): Allocate a large enough buffer
509 to silence false positive gcc8 warning.
510
0bccfb29
JW
5112018-02-22 Shea Levy <shea@shealevy.com>
512
513 * disassemble.c (ARCH_riscv): Define if ARCH_all.
514
6b6b6807
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5152018-02-22 H.J. Lu <hongjiu.lu@intel.com>
516
517 * i386-opc.tbl: Add {rex},
518 * i386-tbl.h: Regenerated.
519
75f31665
MR
5202018-02-20 Maciej W. Rozycki <macro@mips.com>
521
522 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
523 (mips16_opcodes): Replace `M' with `m' for "restore".
524
e207bc53
TP
5252018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
526
527 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
528
87993319
MR
5292018-02-13 Maciej W. Rozycki <macro@mips.com>
530
531 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
532 variable to `function_index'.
533
68d20676
NC
5342018-02-13 Nick Clifton <nickc@redhat.com>
535
536 PR 22823
537 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
538 about truncation of printing.
539
d2159fdc
HW
5402018-02-12 Henry Wong <henry@stuffedcow.net>
541
542 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
543
f174ef9f
NC
5442018-02-05 Nick Clifton <nickc@redhat.com>
545
546 * po/pt_BR.po: Updated Brazilian Portuguese translation.
547
be3a8dca
IT
5482018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
549
550 * i386-dis.c (enum): Add pconfig.
551 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
552 (cpu_flags): Add CpuPCONFIG.
553 * i386-opc.h (enum): Add CpuPCONFIG.
554 (i386_cpu_flags): Add cpupconfig.
555 * i386-opc.tbl: Add PCONFIG instruction.
556 * i386-init.h: Regenerate.
557 * i386-tbl.h: Likewise.
558
3233d7d0
IT
5592018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
560
561 * i386-dis.c (enum): Add PREFIX_0F09.
562 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
563 (cpu_flags): Add CpuWBNOINVD.
564 * i386-opc.h (enum): Add CpuWBNOINVD.
565 (i386_cpu_flags): Add cpuwbnoinvd.
566 * i386-opc.tbl: Add WBNOINVD instruction.
567 * i386-init.h: Regenerate.
568 * i386-tbl.h: Likewise.
569
e925c834
JW
5702018-01-17 Jim Wilson <jimw@sifive.com>
571
572 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
573
d777820b
IT
5742018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
575
576 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
577 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
578 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
579 (cpu_flags): Add CpuIBT, CpuSHSTK.
580 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
581 (i386_cpu_flags): Add cpuibt, cpushstk.
582 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
583 * i386-init.h: Regenerate.
584 * i386-tbl.h: Likewise.
585
f6efed01
NC
5862018-01-16 Nick Clifton <nickc@redhat.com>
587
588 * po/pt_BR.po: Updated Brazilian Portugese translation.
589 * po/de.po: Updated German translation.
590
2721d702
JW
5912018-01-15 Jim Wilson <jimw@sifive.com>
592
593 * riscv-opc.c (match_c_nop): New.
594 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
595
616dcb87
NC
5962018-01-15 Nick Clifton <nickc@redhat.com>
597
598 * po/uk.po: Updated Ukranian translation.
599
3957a496
NC
6002018-01-13 Nick Clifton <nickc@redhat.com>
601
602 * po/opcodes.pot: Regenerated.
603
769c7ea5
NC
6042018-01-13 Nick Clifton <nickc@redhat.com>
605
606 * configure: Regenerate.
607
faf766e3
NC
6082018-01-13 Nick Clifton <nickc@redhat.com>
609
610 2.30 branch created.
611
888a89da
IT
6122018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
613
614 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
615 * i386-tbl.h: Regenerate.
616
cbda583a
JB
6172018-01-10 Jan Beulich <jbeulich@suse.com>
618
619 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
620 * i386-tbl.h: Re-generate.
621
c9e92278
JB
6222018-01-10 Jan Beulich <jbeulich@suse.com>
623
624 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
625 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
626 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
627 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
628 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
629 Disp8MemShift of AVX512VL forms.
630 * i386-tbl.h: Re-generate.
631
35fd2b2b
JW
6322018-01-09 Jim Wilson <jimw@sifive.com>
633
634 * riscv-dis.c (maybe_print_address): If base_reg is zero,
635 then the hi_addr value is zero.
636
91d8b670
JG
6372018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
638
639 * arm-dis.c (arm_opcodes): Add csdb.
640 (thumb32_opcodes): Add csdb.
641
be2e7d95
JG
6422018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
643
644 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
645 * aarch64-asm-2.c: Regenerate.
646 * aarch64-dis-2.c: Regenerate.
647 * aarch64-opc-2.c: Regenerate.
648
704a705d
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6492018-01-08 H.J. Lu <hongjiu.lu@intel.com>
650
651 PR gas/22681
652 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
653 Remove AVX512 vmovd with 64-bit operands.
654 * i386-tbl.h: Regenerated.
655
35eeb78f
JW
6562018-01-05 Jim Wilson <jimw@sifive.com>
657
658 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
659 jalr.
660
219d1afa
AM
6612018-01-03 Alan Modra <amodra@gmail.com>
662
663 Update year range in copyright notice of all files.
664
1508bbf5
JB
6652018-01-02 Jan Beulich <jbeulich@suse.com>
666
667 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
668 and OPERAND_TYPE_REGZMM entries.
669
1e563868 670For older changes see ChangeLog-2017
3499769a 671\f
1e563868 672Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
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673
674Copying and distribution of this file, with or without modification,
675are permitted in any medium without royalty provided the copyright
676notice and this notice are preserved.
677
678Local Variables:
679mode: change-log
680left-margin: 8
681fill-column: 74
682version-control: never
683End:
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