projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
cfc72779
AK		 12012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
2
3 * s390-mkopc.c: Support new option zEC12.
4 * s390-opc.c: Add new instruction formats.
5 * s390-opc.txt: Add new instructions for zEC12.
6
1415a2a7
AG		 72012-09-27 Anthony Green <green@moxielogic.com>
8
9 * moxie-dis.c (print_insn_moxie): Print 'bad' instructions.
10 * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD.
11
160a30bb
L		 122012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
13
14 * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
15 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
16 and CPU_BTVER2_FLAGS.
17 * i386-init.h: Regenerated.
18
60aa667e
L		 192012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
20
21 * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
22 CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
23 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
24 CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
25 (cpu_flags): Add CpuCX16.
26 * i386-opc.h (CpuCX16): New.
27 (i386_cpu_flags): Add cpucx16.
28 * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
29 * i386-tbl.h: Regenerate.
30 * i386-init.h: Likewise.
31
4b8c8c02
RE		 322012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
33
60aa667e 34 * arm-dis.c: Changed ldra and strl-form mnemonics
4b8c8c02
RE		 35 to lda and stl-form.
36
83ea18d0
MR		 372012-09-18 Chao-ying Fu <fu@mips.com>
38
39 * micromips-opc.c (micromips_opcodes): Correct the encoding of
40 the "swxc1" instruction.
41
062f38fa
RE		 422012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
43
44 * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
45 the parameter 'inst'.
46 (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
47 (convert_mov_to_movewide): Change to assert (0) when
48 aarch64_wide_constant_p returns FALSE.
49
b132a67d
DE		 502012-09-14 David Edelsohn <dje.gcc@gmail.com>
51
52 * configure: Regenerate.
53
1f9b75dd
AG		 542012-09-14 Anthony Green <green@moxielogic.com>
55
56 * moxie-dis.c (print_insn_moxie): Branch targets are relative to
57 the address after the branch instruction.
58
e202fa84
AG		 592012-09-13 Anthony Green <green@moxielogic.com>
60
61 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
62
00716ab1
AM		 632012-09-10 Matthias Klose <doko@ubuntu.com>
64
65 * config.in: Disable sanity check for kfreebsd.
66
6d2920c8
L		 672012-09-10 H.J. Lu <hongjiu.lu@intel.com>
68
69 * configure: Regenerated.
70
b3e14eda
L		 712012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
72
73 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
74 * ia64-gen.c: Promote completer index type to longlong.
75 (irf_operand): Add new register recognition.
76 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
77 (lookup_specifier): Add new resource recognition.
78 (insert_bit_table_ent): Relax abort condition according to the
79 changed completer index type.
80 (print_dis_table): Fix printf format for completer index.
81 * ia64-ic.tbl: Add a new instruction class.
82 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
83 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
84 * ia64-opc.h: Define short names for new operand types.
85 * ia64-raw.tbl: Add new RAW resource for DAHR register.
86 * ia64-waw.tbl: Add new WAW resource for DAHR register.
87 * ia64-asmtab.c: Regenerate.
88
382c72e9
PB		 892012-08-29 Peter Bergner <bergner@vnet.ibm.com>
90
91 * ppc-opc.c (VXASHB_MASK): New define.
92 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
93
fb048c26
PB		 942012-08-28 Peter Bergner <bergner@vnet.ibm.com>
95
96 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
97 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
98 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
99 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
100 vupklsh>: Use VXVA_MASK.
101 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
102 <mfvscr>: Use VXVAVB_MASK.
103 <mtvscr>: Use VXVDVA_MASK.
104 <vspltb>: Use VXUIMM4_MASK.
105 <vsplth>: Use VXUIMM3_MASK.
106 <vspltw>: Use VXUIMM2_MASK.
107
3c9017d2
MGD		 1082012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
109
110 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
111
48adcd8e
MGD		 1122012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
113
114 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
115
4f51b4bd
MGD		 1162012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
117
118 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
119
91ff7894
MGD		 1202012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
121
122 * arm-dis.c (neon_opcodes): Add support for AES instructions.
123
c70a8987
MGD		 1242012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
125
126 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
127 conversions.
128
30bdf752
MGD		 1292012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
130
131 * arm-dis.c (coprocessor_opcodes): Add VRINT.
132 (neon_opcodes): Likewise.
133
7e8e6784
MGD		 1342012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
135
136 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
137 variants.
138 (neon_opcodes): Likewise.
139
73924fbc
MGD		 1402012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
141
142 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
143 (neon_opcodes): Likewise.
144
33399f07
MGD		 1452012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
146
147 * arm-dis.c (coprocessor_opcodes): Add VSEL.
148 (print_insn_coprocessor): Add new %<>c bitfield format
149 specifier.
150
9eb6c0f1
MGD		 1512012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
152
153 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
154 (thumb32_opcodes): Likewise.
155 (print_arm_insn): Add support for %<>T formatter.
156
8884b720
MGD		 1572012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
158
159 * arm-dis.c (arm_opcodes): Add HLT.
160 (thumb_opcodes): Likewise.
161
b79f7053
MGD		 1622012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
163
164 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
165
53c4b28b
MGD		 1662012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
167
168 * arm-dis.c (arm_opcodes): Add SEVL.
169 (thumb_opcodes): Likewise.
170 (thumb32_opcodes): Likewise.
171
e797f7e0
MGD		 1722012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
173
174 * arm-dis.c (data_barrier_option): New function.
175 (print_insn_arm): Use data_barrier_option.
176 (print_insn_thumb32): Use data_barrier_option.
177
e2efe87d
MGD		 1782012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
179
180 * arm-dis.c (COND_UNCOND): New constant.
181 (print_insn_coprocessor): Add support for %u format specifier.
182 (print_insn_neon): Likewise.
183
2c63854f
DM		 1842012-08-21 David S. Miller <davem@davemloft.net>
185
186 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
187 F3F4 macro.
188
e67ed0e8
AM		 1892012-08-20 Edmar Wienskoski <edmar@freescale.com>
190
191 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
192 vabsduh, vabsduw, mviwsplt.
193
7b458c12
L		 1942012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
195
196 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
197 CPU_BTVER2_FLAGS.
198
e67ed0e8 199 * i386-opc.h: Update CpuPRFCHW comment.
7b458c12
L		 200
201 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
202 * i386-init.h: Regenerated.
203 * i386-tbl.h: Likewise.
204
eb80cb87
NC		 2052012-08-17 Nick Clifton <nickc@redhat.com>
206
207 * po/uk.po: New Ukranian translation.
208 * configure.in (ALL_LINGUAS): Add uk.
209 * configure: Regenerate.
210
8baf7b78
PB		 2112012-08-16 Peter Bergner <bergner@vnet.ibm.com>
212
213 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
214 RBX for the third operand.
215 <"lswi">: Use RAX for second and NBI for the third operand.
216
3d557b4c
DD		 2172012-08-15 DJ Delorie <dj@redhat.com>
218
219 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
220 operands, so that data addresses can be corrected when not
221 ES-overridden.
222 * rl78-decode.c: Regenerate.
223 * rl78-dis.c (print_insn_rl78): Make order of modifiers
224 irrelevent. When the 'e' specifier is used on an operand and no
225 ES prefix is provided, adjust address to make it absolute.
226
588925d0
PB		 2272012-08-15 Peter Bergner <bergner@vnet.ibm.com>
228
229 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
230
9f6a6cc0
PB		 2312012-08-15 Peter Bergner <bergner@vnet.ibm.com>
232
233 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
234
fc8c4fd1
MR		 2352012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
236
237 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
238 macros, use local variables for info struct member accesses,
239 update the type of the variable used to hold the instruction
240 word.
241 (print_insn_mips, print_mips16_insn_arg): Likewise.
242 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
243 local variables for info struct member accesses.
244 (print_insn_micromips): Add GET_OP_S local macro.
245 (_print_insn_mips): Update the type of the variable used to hold
246 the instruction word.
247
a06ea964 2482012-08-13 Ian Bolton <ian.bolton@arm.com>
e67ed0e8
AM		 249 Laurent Desnogues <laurent.desnogues@arm.com>
250 Jim MacArthur <jim.macarthur@arm.com>
251 Marcus Shawcroft <marcus.shawcroft@arm.com>
252 Nigel Stephens <nigel.stephens@arm.com>
253 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
254 Richard Earnshaw <rearnsha@arm.com>
255 Sofiane Naci <sofiane.naci@arm.com>
256 Tejas Belagod <tejas.belagod@arm.com>
257 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 258
259 * Makefile.am: Add AArch64.
260 * Makefile.in: Regenerate.
261 * aarch64-asm.c: New file.
262 * aarch64-asm.h: New file.
263 * aarch64-dis.c: New file.
264 * aarch64-dis.h: New file.
265 * aarch64-gen.c: New file.
266 * aarch64-opc.c: New file.
267 * aarch64-opc.h: New file.
268 * aarch64-tbl.h: New file.
269 * configure.in: Add AArch64.
270 * configure: Regenerate.
271 * disassemble.c: Add AArch64.
272 * aarch64-asm-2.c: New file (automatically generated).
273 * aarch64-dis-2.c: New file (automatically generated).
274 * aarch64-opc-2.c: New file (automatically generated).
275 * po/POTFILES.in: Regenerate.
276
35d0a169
MR		 2772012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
278
279 * micromips-opc.c (micromips_opcodes): Update comment.
280 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
281 instructions for IOCT as appropriate.
282 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
283 opcode_is_member.
284 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
285 the result of a check for the -Wno-missing-field-initializers
286 GCC option.
287 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
288 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
289 compilation.
290 (mips16-opc.lo): Likewise.
291 (micromips-opc.lo): Likewise.
292 * aclocal.m4: Regenerate.
293 * configure: Regenerate.
294 * Makefile.in: Regenerate.
295
5c5acbbd
L		 2962012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
297
298 PR gas/14423
299 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
300 * i386-init.h: Regenerated.
301
3c892704
NC		 3022012-08-09 Nick Clifton <nickc@redhat.com>
303
304 * po/vi.po: Updated Vietnamese translation.
305
d7189fa5
RM		 3062012-08-07 Roland McGrath <mcgrathr@google.com>
307
308 * i386-dis.c (reg_table): Fill out REG_0F0D table with
309 AMD-reserved cases as "prefetch".
310 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
311 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
312 (reg_table): Use those under REG_0F18.
313 (mod_table): Add those cases as "nop/reserved".
314
4c692bc7
JB		 3152012-08-07 Jan Beulich <jbeulich@suse.com>
316
317 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
318
de882298
RM		 3192012-08-06 Roland McGrath <mcgrathr@google.com>
320
321 * i386-dis.c (print_insn): Print spaces between multiple excess
322 prefixes. Return actual number of excess prefixes consumed,
323 not always one.
324
325 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
326
7bb15c6f
RM		 3272012-08-06 Roland McGrath <mcgrathr@google.com>
328 Victor Khimenko <khim@google.com>
329 H.J. Lu <hongjiu.lu@intel.com>
330
331 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
332 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
333 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
334 (OP_E_register): Likewise.
335 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
336
3843081d
JBG		 3372012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
338
339 * configure.in: Formatting.
340 * configure: Regenerate.
341
48891606
AM		 3422012-08-01 Alan Modra <amodra@gmail.com>
343
344 * h8300-dis.c: Fix printf arg warnings.
345 * i960-dis.c: Likewise.
346 * mips-dis.c: Likewise.
347 * pdp11-dis.c: Likewise.
348 * sh-dis.c: Likewise.
349 * v850-dis.c: Likewise.
350 * configure.in: Formatting.
351 * configure: Regenerate.
352 * rl78-decode.c: Regenerate.
353 * po/POTFILES.in: Regenerate.
354
03f66e8a 3552012-07-31 Chao-Ying Fu <fu@mips.com>
e67ed0e8
AM		 356 Catherine Moore <clm@codesourcery.com>
357 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 358
359 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
360 (DSP_VOLA): Likewise.
361 (D32, D33): Likewise.
362 (micromips_opcodes): Add DSP ASE instructions.
48891606 363 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
03f66e8a
MR		 364 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
365
94948e64
JB		 3662012-07-31 Jan Beulich <jbeulich@suse.com>
367
368 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
369 instruction group. Mark as requiring AVX2.
370 * i386-tbl.h: Re-generate.
371
a6dc81d2
NC		 3722012-07-30 Nick Clifton <nickc@redhat.com>
373
374 * po/opcodes.pot: Updated template.
375 * po/es.po: Updated Spanish translation.
376 * po/fi.po: Updated Finnish translation.
377
c4dd807e
MF		 3782012-07-27 Mike Frysinger <vapier@gentoo.org>
379
380 * configure.in (BFD_VERSION): Run bfd/configure --version and
381 parse the output of that.
382 * configure: Regenerate.
383
03edbe3b
JL		 3842012-07-25 James Lemke <jwlemke@codesourcery.com>
385
386 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
387
63d08c68
NC		 3882012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
389 Dr David Alan Gilbert <dave@treblig.org>
d908c8af
NC		 390
391 PR binutils/13135
392 * arm-dis.c: Add necessary casts for printing integer values.
393 Use %s when printing string values.
394 * hppa-dis.c: Likewise.
395 * m68k-dis.c: Likewise.
396 * microblaze-dis.c: Likewise.
397 * mips-dis.c: Likewise.
398 * sparc-dis.c: Likewise.
399
ff688e1f
L		 4002012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
401
402 PR binutils/14355
403 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
404 (VEX_LEN_0FXOP_08_CD): Likewise.
405 (VEX_LEN_0FXOP_08_CE): Likewise.
406 (VEX_LEN_0FXOP_08_CF): Likewise.
407 (VEX_LEN_0FXOP_08_EC): Likewise.
408 (VEX_LEN_0FXOP_08_ED): Likewise.
409 (VEX_LEN_0FXOP_08_EE): Likewise.
410 (VEX_LEN_0FXOP_08_EF): Likewise.
411 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
412 vpcomub, vpcomuw, vpcomud, vpcomuq.
413 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
414 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
415 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
416 VEX_LEN_0FXOP_08_EF.
417
e2e1fcde
L		 4182012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
419
420 * i386-dis.c (PREFIX_0F38F6): New.
421 (prefix_table): Add adcx, adox instructions.
422 (three_byte_table): Use PREFIX_0F38F6.
423 (mod_table): Add rdseed instruction.
424 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
425 (cpu_flags): Likewise.
426 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
427 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
428 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
429 prefetchw.
430 * i386-tbl.h: Regenerate.
431 * i386-init.h: Likewise.
432
8b99bf0b
TS		 4332012-07-05 Thomas Schwinge <thomas@codesourcery.com>
434
f4263ca2 435 * mips-dis.c: Remove gratuitous newline.
8b99bf0b 436
416cf80a
SK		 4372012-07-05 Sean Keys <skeys@ipdatasys.com>
438
439 * xgate-dis.c: Removed an IF statement that will
e67ed0e8
AM		 440 always be false due to overlapping operand masks.
441 * xgate-opc.c: Corrected 'com' opcode entry and
442 fixed spacing.
416cf80a 443
9fa0f14a
RM		 4442012-07-02 Roland McGrath <mcgrathr@google.com>
445
446 * i386-opc.tbl: Add RepPrefixOk to nop.
447 * i386-tbl.h: Regenerate.
448
4c6a93d3
NC		 4492012-06-28 Nick Clifton <nickc@redhat.com>
450
451 * po/vi.po: Updated Vietnamese translation.
452
29c048b6
RM		 4532012-06-22 Roland McGrath <mcgrathr@google.com>
454
fe13e45b
RM		 455 * i386-opc.tbl: Add RepPrefixOk to ret.
456 * i386-tbl.h: Regenerate.
457
29c048b6
RM		 458 * i386-opc.h (RepPrefixOk): New enum constant.
459 (i386_opcode_modifier): New bitfield 'repprefixok'.
460 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
461 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
462 instructions that have IsString.
463 * i386-tbl.h: Regenerate.
464
c7a8dbf9
AS		 4652012-06-11 Andreas Schwab <schwab@linux-m68k.org>
466
467 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
468 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
469 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
470 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
471 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
472 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
473 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
474 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
475 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
476
94caa966
AM		 4772012-05-19 Alan Modra <amodra@gmail.com>
478
479 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
480 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
481
5eb3690e
AM		 4822012-05-18 Alan Modra <amodra@gmail.com>
483
71fe7bab
AM		 484 * ia64-opc.c: Remove #include "ansidecl.h".
485 * z8kgen.c: Include sysdep.h first.
486
5eb3690e
AM		 487 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
488 * bfin-dis.c: Likewise.
489 * i860-dis.c: Likewise.
490 * ia64-dis.c: Likewise.
491 * ia64-gen.c: Likewise.
492 * m68hc11-dis.c: Likewise.
493 * mmix-dis.c: Likewise.
494 * msp430-dis.c: Likewise.
495 * or32-dis.c: Likewise.
496 * rl78-dis.c: Likewise.
497 * rx-dis.c: Likewise.
498 * tic4x-dis.c: Likewise.
499 * tilegx-opc.c: Likewise.
500 * tilepro-opc.c: Likewise.
501 * rx-decode.c: Regenerate.
502
a4ebc835
AM		 5032012-05-17 James Lemke <jwlemke@codesourcery.com>
504
505 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
506
98c76446
AM		 5072012-05-17 James Lemke <jwlemke@codesourcery.com>
508
509 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
510
df7b86aa
NC		 5112012-05-17 Daniel Richard G. <skunk@iskunk.org>
512 Nick Clifton <nickc@redhat.com>
513
514 PR 14072
515 * configure.in: Add check that sysdep.h has been included before
516 any system header files.
517 * configure: Regenerate.
518 * config.in: Regenerate.
519 * sysdep.h: Generate an error if included before config.h.
520 * alpha-opc.c: Include sysdep.h before any other header file.
521 * alpha-dis.c: Likewise.
522 * avr-dis.c: Likewise.
523 * cgen-opc.c: Likewise.
524 * cr16-dis.c: Likewise.
525 * cris-dis.c: Likewise.
526 * crx-dis.c: Likewise.
527 * d10v-dis.c: Likewise.
528 * d10v-opc.c: Likewise.
529 * d30v-dis.c: Likewise.
530 * d30v-opc.c: Likewise.
531 * h8500-dis.c: Likewise.
532 * i370-dis.c: Likewise.
533 * i370-opc.c: Likewise.
534 * m10200-dis.c: Likewise.
535 * m10300-dis.c: Likewise.
536 * micromips-opc.c: Likewise.
537 * mips-opc.c: Likewise.
538 * mips61-opc.c: Likewise.
539 * moxie-dis.c: Likewise.
540 * or32-opc.c: Likewise.
541 * pj-dis.c: Likewise.
542 * ppc-dis.c: Likewise.
543 * ppc-opc.c: Likewise.
544 * s390-dis.c: Likewise.
545 * sh-dis.c: Likewise.
546 * sh64-dis.c: Likewise.
547 * sparc-dis.c: Likewise.
548 * sparc-opc.c: Likewise.
549 * spu-dis.c: Likewise.
550 * tic30-dis.c: Likewise.
551 * tic54x-dis.c: Likewise.
552 * tic80-dis.c: Likewise.
553 * tic80-opc.c: Likewise.
554 * tilegx-dis.c: Likewise.
555 * tilepro-dis.c: Likewise.
556 * v850-dis.c: Likewise.
557 * v850-opc.c: Likewise.
558 * vax-dis.c: Likewise.
559 * w65-dis.c: Likewise.
560 * xgate-dis.c: Likewise.
561 * xtensa-dis.c: Likewise.
562 * rl78-decode.opc: Likewise.
563 * rl78-decode.c: Regenerate.
564 * rx-decode.opc: Likewise.
565 * rx-decode.c: Regenerate.
566
e1dad58d
AM		 5672012-05-17 Alan Modra <amodra@gmail.com>
568
569 * ppc_dis.c: Don't include elf/ppc.h.
570
101af531
NC		 5712012-05-16 Meador Inge <meadori@codesourcery.com>
572
573 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
574 to PUSH/POP {reg}.
575
6927f982
NC		 5762012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
577 Stephane Carrez <stcarrez@nerim.fr>
578
579 * configure.in: Add S12X and XGATE co-processor support to m68hc11
580 target.
581 * disassemble.c: Likewise.
582 * configure: Regenerate.
583 * m68hc11-dis.c: Make objdump output more consistent, use hex
584 instead of decimal and use 0x prefix for hex.
585 * m68hc11-opc.c: Add S12X and XGATE opcodes.
586
b9c361e0
JL		 5872012-05-14 James Lemke <jwlemke@codesourcery.com>
588
589 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
590 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
591 (vle_opcd_indices): New array.
592 (lookup_vle): New function.
593 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
594 (print_insn_powerpc): Likewise.
595 * ppc-opc.c: Likewise.
596
5972012-05-14 Catherine Moore <clm@codesourcery.com>
598 Maciej W. Rozycki <macro@codesourcery.com>
599 Rhonda Wittels <rhonda@codesourcery.com>
600 Nathan Froyd <froydnj@codesourcery.com>
601
602 * ppc-opc.c (insert_arx, extract_arx): New functions.
603 (insert_ary, extract_ary): New functions.
604 (insert_li20, extract_li20): New functions.
605 (insert_rx, extract_rx): New functions.
606 (insert_ry, extract_ry): New functions.
607 (insert_sci8, extract_sci8): New functions.
608 (insert_sci8n, extract_sci8n): New functions.
609 (insert_sd4h, extract_sd4h): New functions.
610 (insert_sd4w, extract_sd4w): New functions.
611 (insert_vlesi, extract_vlesi): New functions.
612 (insert_vlensi, extract_vlensi): New functions.
613 (insert_vleui, extract_vleui): New functions.
614 (insert_vleil, extract_vleil): New functions.
615 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
616 (BI16, BI32, BO32, B8): New.
617 (B15, B24, CRD32, CRS): New.
618 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
619 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
620 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
621 (SH6_MASK): Use PPC_OPSHIFT_INV.
622 (SI8, UI5, OIMM5, UI7, BO16): New.
623 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
624 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
625 (ALLOW8_SPRG): New.
626 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
627 (OPVUP, OPVUP_MASK OPVUP): New
628 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
629 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
630 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
631 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
632 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
633 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
634 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
635 (SE_IM5, SE_IM5_MASK): New.
636 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
637 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
638 (BO32DNZ, BO32DZ): New.
639 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
640 (PPCVLE): New.
641 (powerpc_opcodes): Add new VLE instructions. Update existing
642 instruction to include PPCVLE if supported.
643 * ppc-dis.c (ppc_opts): Add vle entry.
644 (get_powerpc_dialect): New function.
645 (powerpc_init_dialect): VLE support.
646 (print_insn_big_powerpc): Call get_powerpc_dialect.
647 (print_insn_little_powerpc): Likewise.
648 (operand_value_powerpc): Handle negative shift counts.
649 (print_insn_powerpc): Handle 2-byte instruction lengths.
650
208a4923
NC		 6512012-05-11 Daniel Richard G. <skunk@iskunk.org>
652
653 PR binutils/14028
654 * configure.in: Invoke ACX_HEADER_STRING.
655 * configure: Regenerate.
656 * config.in: Regenerate.
657 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
658 string.h and strings.h.
659
6750a3a7
NC		 6602012-05-11 Nick Clifton <nickc@redhat.com>
661
662 PR binutils/14006
663 * arm-dis.c (print_insn): Fix detection of instruction mode in
664 files containing multiple executable sections.
665
f6c1a2d5
NC		 6662012-05-03 Sean Keys <skeys@ipdatasys.com>
667
668 * Makefile.in, configure: regenerate
669 * disassemble.c (disassembler): Recognize ARCH_XGATE.
670 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
671 New functions.
672 * configure.in: Recognize xgate.
673 * xgate-dis.c, xgate-opc.c: New files for support of xgate
674 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
675 and opcode generation for xgate.
676
78e98aab
DD		 6772012-04-30 DJ Delorie <dj@redhat.com>
678
679 * rx-decode.opc (MOV): Do not sign-extend immediates which are
680 already the maximum bit size.
681 * rx-decode.c: Regenerate.
682
ec668d69
DM		 6832012-04-27 David S. Miller <davem@davemloft.net>
684
2e52845b
DM		 685 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
686 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
687
58004e23
DM		 688 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
689 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
690
698544e1
DM		 691 * sparc-opc.c (CBCOND): New define.
692 (CBCOND_XCC): Likewise.
693 (cbcond): New helper macro.
694 (sparc_opcodes): Add compare-and-branch instructions.
695
6cda1326
DM		 696 * sparc-dis.c (print_insn_sparc): Handle ')'.
697 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
698
ec668d69
DM		 699 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
700 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
701
2615994e
DM		 7022012-04-12 David S. Miller <davem@davemloft.net>
703
704 * sparc-dis.c (X_DISP10): Define.
705 (print_insn_sparc): Handle '='.
706
5de10af0
MF		 7072012-04-01 Mike Frysinger <vapier@gentoo.org>
708
709 * bfin-dis.c (fmtconst): Replace decimal handling with a single
710 sprintf call and the '*' field width.
711
55a36193
MK		 7122012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
713
714 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
715
d6688282
AM		 7162012-03-16 Alan Modra <amodra@gmail.com>
717
718 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
719 (powerpc_opcd_indices): Bump array size.
720 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
721 corresponding to unused opcodes to following entry.
722 (lookup_powerpc): New function, extracted and optimised from..
723 (print_insn_powerpc): ..here.
724
b240011a
AM		 7252012-03-15 Alan Modra <amodra@gmail.com>
726 James Lemke <jwlemke@codesourcery.com>
727
728 * disassemble.c (disassemble_init_for_target): Handle ppc init.
729 * ppc-dis.c (private): New var.
730 (powerpc_init_dialect): Don't return calloc failure, instead use
731 private.
732 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
733 (powerpc_opcd_indices): New array.
734 (disassemble_init_powerpc): New function.
735 (print_insn_big_powerpc): Don't init dialect here.
736 (print_insn_little_powerpc): Likewise.
737 (print_insn_powerpc): Start search using powerpc_opcd_indices.
738
aea77599
AM		 7392012-03-10 Edmar Wienskoski <edmar@freescale.com>
740
741 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
742 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
743 (PPCVEC2, PPCTMR, E6500): New short names.
744 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
745 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
746 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
747 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
748 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
749 optional operands on sync instruction for E6500 target.
750
5333187a
AK		 7512012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
752
753 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
754
a597d2d3
AM		 7552012-02-27 Alan Modra <amodra@gmail.com>
756
757 * mt-dis.c: Regenerate.
758
3f26eb3a
AM		 7592012-02-27 Alan Modra <amodra@gmail.com>
760
761 * v850-opc.c (extract_v8): Rearrange to make it obvious this
762 is the inverse of corresponding insert function.
763 (extract_d22, extract_u9, extract_r4): Likewise.
764 (extract_d9): Correct sign extension.
765 (extract_d16_15): Don't assume "long" is 32 bits, and don't
766 rely on implementation defined behaviour for shift right of
767 signed types.
768 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
769 (extract_d23): Likewise, and correct mask.
770
1f42f8b3
AM		 7712012-02-27 Alan Modra <amodra@gmail.com>
772
773 * crx-dis.c (print_arg): Mask constant to 32 bits.
774 * crx-opc.c (cst4_map): Use int array.
775
cdb06235
AM		 7762012-02-27 Alan Modra <amodra@gmail.com>
777
778 * arc-dis.c (BITS): Don't use shifts to mask off bits.
779 (FIELDD): Sign extend with xor,sub.
780
6f7be959
WL		 7812012-02-25 Walter Lee <walt@tilera.com>
782
783 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
784 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
785 TILEPRO_OPC_LW_TLS_SN.
786
82c2def5
L		 7872012-02-21 H.J. Lu <hongjiu.lu@intel.com>
788
789 * i386-opc.h (HLEPrefixNone): New.
790 (HLEPrefixLock): Likewise.
791 (HLEPrefixAny): Likewise.
792 (HLEPrefixRelease): Likewise.
793
42164a71
L		 7942012-02-08 H.J. Lu <hongjiu.lu@intel.com>
795
796 * i386-dis.c (HLE_Fixup1): New.
797 (HLE_Fixup2): Likewise.
798 (HLE_Fixup3): Likewise.
799 (Ebh1): Likewise.
800 (Evh1): Likewise.
801 (Ebh2): Likewise.
802 (Evh2): Likewise.
803 (Ebh3): Likewise.
804 (Evh3): Likewise.
805 (MOD_C6_REG_7): Likewise.
806 (MOD_C7_REG_7): Likewise.
807 (RM_C6_REG_7): Likewise.
808 (RM_C7_REG_7): Likewise.
809 (XACQUIRE_PREFIX): Likewise.
810 (XRELEASE_PREFIX): Likewise.
811 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
812 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
813 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
814 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
815 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
816 MOD_C6_REG_7 and MOD_C7_REG_7.
817 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
818 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
819 xtest.
820 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
821 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
822
823 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
824 CPU_RTM_FLAGS.
825 (cpu_flags): Add CpuHLE and CpuRTM.
826 (opcode_modifiers): Add HLEPrefixOk.
827
828 * i386-opc.h (CpuHLE): New.
829 (CpuRTM): Likewise.
830 (HLEPrefixOk): Likewise.
831 (i386_cpu_flags): Add cpuhle and cpurtm.
832 (i386_opcode_modifier): Add hleprefixok.
833
834 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
835 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
836 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
837 operand. Add xacquire, xrelease, xabort, xbegin, xend and
838 xtest.
839 * i386-init.h: Regenerated.
840 * i386-tbl.h: Likewise.
841
21abe33a
DD		 8422012-01-24 DJ Delorie <dj@redhat.com>
843
844 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
845 * rl78-decode.c: Regenerate.
846
e20cc039
AM		 8472012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
848
849 PR binutils/10173
850 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
851
e143d25c
AS		 8522012-01-17 Andreas Schwab <schwab@linux-m68k.org>
853
854 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
855 register and move them after pmove with PSR/PCSR register.
856
8729a6f6
L		 8572012-01-13 H.J. Lu <hongjiu.lu@intel.com>
858
859 * i386-dis.c (mod_table): Add vmfunc.
860
861 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
862 (cpu_flags): CpuVMFUNC.
863
864 * i386-opc.h (CpuVMFUNC): New.
865 (i386_cpu_flags): Add cpuvmfunc.
866
867 * i386-opc.tbl: Add vmfunc.
868 * i386-init.h: Regenerated.
869 * i386-tbl.h: Likewise.
5011093d 870
23e1d329 871For older changes see ChangeLog-2011
252b5132
RH		 872\f
873Local Variables:
2f6d2f85
NC		 874mode: change-log
875left-margin: 8
876fill-column: 74
252b5132
RH		 877version-control: never
878End:
GDB Binutils - Deliverables
This page took 0.664314 seconds and 4 git commands to generate.