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Move ChangeLog entry for PR ld/20376
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
37fd5ef3
CZ		 12016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
2
3 * arc-dis.c (skipclass): New structure.
4 (decodelist): New variable.
5 (is_compatible_p): New function.
6 (new_element): Likewise.
7 (skip_class_p): Likewise.
8 (find_format_from_table): Use skip_class_p function.
9 (find_format): Decode first the extension instructions.
10 (print_insn_arc): Select either ARCEM or ARCHS based on elf
11 e_flags.
12 (parse_option): New function.
13 (parse_disassembler_options): Likewise.
14 (print_arc_disassembler_options): Likewise.
15 (print_insn_arc): Use parse_disassembler_options function. Proper
16 select ARCv2 cpu variant.
17 * disassemble.c (disassembler_usage): Add ARC disassembler
18 options.
19
92281a5b
MR		 202016-07-13 Maciej W. Rozycki <macro@imgtec.com>
21
22 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
23 annotation from the "nal" entry and reorder it beyond "bltzal".
24
6e7ced37
JM		 252016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
26
27 * sparc-opc.c (ldtxa): New macro.
28 (sparc_opcodes): Use the macro defined above to add entries for
29 the LDTXA instructions.
30 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
31 instruction.
32
2f831b9a 332016-07-07 James Bowman <james.bowman@ftdichip.com>
34
35 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
36 and "jmpc".
37
c07315e0
JB		 382016-07-01 Jan Beulich <jbeulich@suse.com>
39
40 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
41 (movzb): Adjust to cover all permitted suffixes.
42 (movzw): New.
43 * i386-tbl.h: Re-generate.
44
9243100a
JB		 452016-07-01 Jan Beulich <jbeulich@suse.com>
46
47 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
48 (lgdt): Remove Tbyte from non-64-bit variant.
49 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
50 xsaves64, xsavec64): Remove Disp16.
51 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
52 Remove Disp32S from non-64-bit variants. Remove Disp16 from
53 64-bit variants.
54 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
55 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
56 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
57 64-bit variants.
58 * i386-tbl.h: Re-generate.
59
8325cc63
JB		 602016-07-01 Jan Beulich <jbeulich@suse.com>
61
62 * i386-opc.tbl (xlat): Remove RepPrefixOk.
63 * i386-tbl.h: Re-generate.
64
838441e4
YQ		 652016-06-30 Yao Qi <yao.qi@linaro.org>
66
67 * arm-dis.c (print_insn): Fix typo in comment.
68
dab26bf4
RS		 692016-06-28 Richard Sandiford <richard.sandiford@arm.com>
70
71 * aarch64-opc.c (operand_general_constraint_met_p): Check the
72 range of ldst_elemlist operands.
73 (print_register_list): Use PRIi64 to print the index.
74 (aarch64_print_operand): Likewise.
75
5703197e
TS		 762016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
77
78 * mcore-opc.h: Remove sentinal.
79 * mcore-dis.c (print_insn_mcore): Adjust.
80
ce440d63
GM		 812016-06-23 Graham Markall <graham.markall@embecosm.com>
82
83 * arc-opc.c: Correct description of availability of NPS400
84 features.
85
6fd3a02d
PB		 862016-06-22 Peter Bergner <bergner@vnet.ibm.com>
87
88 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
89 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
90 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
91 xor3>: New mnemonics.
92 <setb>: Change to a VX form instruction.
93 (insert_sh6): Add support for rldixor.
94 (extract_sh6): Likewise.
95
6b477896
TS		 962016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
97
98 * arc-ext.h: Wrap in extern C.
99
bdd582db
GM		 1002016-06-21 Graham Markall <graham.markall@embecosm.com>
101
102 * arc-dis.c (arc_insn_length): Add comment on instruction length.
103 Use same method for determining instruction length on ARC700 and
104 NPS-400.
105 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
106 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
107 with the NPS400 subclass.
108 * arc-opc.c: Likewise.
109
96074adc
JM		 1102016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
111
112 * sparc-opc.c (rdasr): New macro.
113 (wrasr): Likewise.
114 (rdpr): Likewise.
115 (wrpr): Likewise.
116 (rdhpr): Likewise.
117 (wrhpr): Likewise.
118 (sparc_opcodes): Use the macros above to fix and expand the
119 definition of read/write instructions from/to
120 asr/privileged/hyperprivileged instructions.
121 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
122 %hva_mask_nz. Prefer softint_set and softint_clear over
123 set_softint and clear_softint.
124 (print_insn_sparc): Support %ver in Rd.
125
7a10c22f
JM		 1262016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
127
128 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
129 architecture according to the hardware capabilities they require.
130
4f26fb3a
JM		 1312016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
132
133 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
134 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
135 bfd_mach_sparc_v9{c,d,e,v,m}.
136 * sparc-opc.c (MASK_V9C): Define.
137 (MASK_V9D): Likewise.
138 (MASK_V9E): Likewise.
139 (MASK_V9V): Likewise.
140 (MASK_V9M): Likewise.
141 (v6): Add MASK_V9{C,D,E,V,M}.
142 (v6notlet): Likewise.
143 (v7): Likewise.
144 (v8): Likewise.
145 (v9): Likewise.
146 (v9andleon): Likewise.
147 (v9a): Likewise.
148 (v9b): Likewise.
149 (v9c): Define.
150 (v9d): Likewise.
151 (v9e): Likewise.
152 (v9v): Likewise.
153 (v9m): Likewise.
154 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
155
3ee6e4fb
NC		 1562016-06-15 Nick Clifton <nickc@redhat.com>
157
158 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
159 constants to match expected behaviour.
160 (nds32_parse_opcode): Likewise. Also for whitespace.
161
02f3be19
AB		 1622016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
163
164 * arc-opc.c (extract_rhv1): Extract value from insn.
165
6f9f37ed 1662016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 167
168 * arc-nps400-tbl.h: Add ldbit instruction.
169 * arc-opc.c: Add flag classes required for ldbit.
170
6f9f37ed 1712016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 172
173 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
174 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
175 support the above instructions.
176
6f9f37ed 1772016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 178
179 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
180 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
181 csma, cbba, zncv, and hofs.
182 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
183 support the above instructions.
184
1852016-06-06 Graham Markall <graham.markall@embecosm.com>
186
187 * arc-nps400-tbl.h: Add andab and orab instructions.
188
1892016-06-06 Graham Markall <graham.markall@embecosm.com>
190
191 * arc-nps400-tbl.h: Add addl-like instructions.
192
1932016-06-06 Graham Markall <graham.markall@embecosm.com>
194
195 * arc-nps400-tbl.h: Add mxb and imxb instructions.
196
1972016-06-06 Graham Markall <graham.markall@embecosm.com>
198
199 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
200 instructions.
201
b2cc3f6f
AK		 2022016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
203
204 * s390-dis.c (option_use_insn_len_bits_p): New file scope
205 variable.
206 (init_disasm): Handle new command line option "insnlength".
207 (print_s390_disassembler_options): Mention new option in help
208 output.
209 (print_insn_s390): Use the encoded insn length when dumping
210 unknown instructions.
211
1857fe72
DC		 2122016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
213
214 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
215 to the address and set as symbol address for LDS/ STS immediate operands.
216
14b57c7c
AM		 2172016-06-07 Alan Modra <amodra@gmail.com>
218
219 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
220 cpu for "vle" to e500.
221 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
222 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
223 (PPCNONE): Delete, substitute throughout.
224 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
225 except for major opcode 4 and 31.
226 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
227
4d1464f2
MW		 2282016-06-07 Matthew Wahab <matthew.wahab@arm.com>
229
230 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
231 ARM_EXT_RAS in relevant entries.
232
026122a6
PB		 2332016-06-03 Peter Bergner <bergner@vnet.ibm.com>
234
235 PR binutils/20196
236 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
237 opcodes for E6500.
238
07f5af7d
L		 2392016-06-03 H.J. Lu <hongjiu.lu@intel.com>
240
241 PR binutis/18386
242 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
243 (indir_v_mode): New.
244 Add comments for '&'.
245 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
246 (putop): Handle '&'.
247 (intel_operand_size): Handle indir_v_mode.
248 (OP_E_register): Likewise.
249 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
250 64-bit indirect call/jmp for AMD64.
251 * i386-tbl.h: Regenerated
252
4eb6f892
AB		 2532016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
254
255 * arc-dis.c (struct arc_operand_iterator): New structure.
256 (find_format_from_table): All the old content from find_format,
257 with some minor adjustments, and parameter renaming.
258 (find_format_long_instructions): New function.
259 (find_format): Rewritten.
260 (arc_insn_length): Add LSB parameter.
261 (extract_operand_value): New function.
262 (operand_iterator_next): New function.
263 (print_insn_arc): Use new functions to find opcode, and iterator
264 over operands.
265 * arc-opc.c (insert_nps_3bit_dst_short): New function.
266 (extract_nps_3bit_dst_short): New function.
267 (insert_nps_3bit_src2_short): New function.
268 (extract_nps_3bit_src2_short): New function.
269 (insert_nps_bitop1_size): New function.
270 (extract_nps_bitop1_size): New function.
271 (insert_nps_bitop2_size): New function.
272 (extract_nps_bitop2_size): New function.
273 (insert_nps_bitop_mod4_msb): New function.
274 (extract_nps_bitop_mod4_msb): New function.
275 (insert_nps_bitop_mod4_lsb): New function.
276 (extract_nps_bitop_mod4_lsb): New function.
277 (insert_nps_bitop_dst_pos3_pos4): New function.
278 (extract_nps_bitop_dst_pos3_pos4): New function.
279 (insert_nps_bitop_ins_ext): New function.
280 (extract_nps_bitop_ins_ext): New function.
281 (arc_operands): Add new operands.
282 (arc_long_opcodes): New global array.
283 (arc_num_long_opcodes): New global.
284 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
285
1fe0971e
TS		 2862016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
287
288 * nds32-asm.h: Add extern "C".
289 * sh-opc.h: Likewise.
290
315f180f
GM		 2912016-06-01 Graham Markall <graham.markall@embecosm.com>
292
293 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
294 0,b,limm to the rflt instruction.
295
a2b5fccc
TS		 2962016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
297
298 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
299 constant.
300
0cbd0046
L		 3012016-05-29 H.J. Lu <hongjiu.lu@intel.com>
302
303 PR gas/20145
304 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
305 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
306 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
307 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
308 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
309 * i386-init.h: Regenerated.
310
1848e567
L		 3112016-05-27 H.J. Lu <hongjiu.lu@intel.com>
312
313 PR gas/20145
314 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
315 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
316 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
317 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
318 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
319 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
320 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
321 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
322 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
323 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
324 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
325 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
326 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
327 CpuRegMask for AVX512.
328 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
329 and CpuRegMask.
330 (set_bitfield_from_cpu_flag_init): New function.
331 (set_bitfield): Remove const on f. Call
332 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
333 * i386-opc.h (CpuRegMMX): New.
334 (CpuRegXMM): Likewise.
335 (CpuRegYMM): Likewise.
336 (CpuRegZMM): Likewise.
337 (CpuRegMask): Likewise.
338 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
339 and cpuregmask.
340 * i386-init.h: Regenerated.
341 * i386-tbl.h: Likewise.
342
e92bae62
L		 3432016-05-27 H.J. Lu <hongjiu.lu@intel.com>
344
345 PR gas/20154
346 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
347 (opcode_modifiers): Add AMD64 and Intel64.
348 (main): Properly verify CpuMax.
349 * i386-opc.h (CpuAMD64): Removed.
350 (CpuIntel64): Likewise.
351 (CpuMax): Set to CpuNo64.
352 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
353 (AMD64): New.
354 (Intel64): Likewise.
355 (i386_opcode_modifier): Add amd64 and intel64.
356 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
357 on call and jmp.
358 * i386-init.h: Regenerated.
359 * i386-tbl.h: Likewise.
360
e89c5eaa
L		 3612016-05-27 H.J. Lu <hongjiu.lu@intel.com>
362
363 PR gas/20154
364 * i386-gen.c (main): Fail if CpuMax is incorrect.
365 * i386-opc.h (CpuMax): Set to CpuIntel64.
366 * i386-tbl.h: Regenerated.
367
77d66e7b
NC		 3682016-05-27 Nick Clifton <nickc@redhat.com>
369
370 PR target/20150
371 * msp430-dis.c (msp430dis_read_two_bytes): New function.
372 (msp430dis_opcode_unsigned): New function.
373 (msp430dis_opcode_signed): New function.
374 (msp430_singleoperand): Use the new opcode reading functions.
375 Only disassenmble bytes if they were successfully read.
376 (msp430_doubleoperand): Likewise.
377 (msp430_branchinstr): Likewise.
378 (msp430x_callx_instr): Likewise.
379 (print_insn_msp430): Check that it is safe to read bytes before
380 attempting disassembly. Use the new opcode reading functions.
381
19dfcc89
PB		 3822016-05-26 Peter Bergner <bergner@vnet.ibm.com>
383
384 * ppc-opc.c (CY): New define. Document it.
385 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
386
f3ad7637
L		 3872016-05-25 H.J. Lu <hongjiu.lu@intel.com>
388
389 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
390 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
391 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
392 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
393 CPU_ANY_AVX_FLAGS.
394 * i386-init.h: Regenerated.
395
f1360d58
L		 3962016-05-25 H.J. Lu <hongjiu.lu@intel.com>
397
398 PR gas/20141
399 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
400 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
401 * i386-init.h: Regenerated.
402
293f5f65
L		 4032016-05-25 H.J. Lu <hongjiu.lu@intel.com>
404
405 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
406 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
407 * i386-init.h: Regenerated.
408
d9eca1df
CZ		 4092016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
410
411 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
412 information.
413 (print_insn_arc): Set insn_type information.
414 * arc-opc.c (C_CC): Add F_CLASS_COND.
415 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
416 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
417 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
418 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
419 (brne, brne_s, jeq_s, jne_s): Likewise.
420
87789e08
CZ		 4212016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
422
423 * arc-tbl.h (neg): New instruction variant.
424
c810e0b8
CZ		 4252016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
426
427 * arc-dis.c (find_format, find_format, get_auxreg)
428 (print_insn_arc): Changed.
429 * arc-ext.h (INSERT_XOP): Likewise.
430
3d207518
TS		 4312016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
432
433 * tic54x-dis.c (sprint_mmr): Adjust.
434 * tic54x-opc.c: Likewise.
435
514e58b7
AM		 4362016-05-19 Alan Modra <amodra@gmail.com>
437
438 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
439
e43de63c
AM		 4402016-05-19 Alan Modra <amodra@gmail.com>
441
442 * ppc-opc.c: Formatting.
443 (NSISIGNOPT): Define.
444 (powerpc_opcodes <subis>): Use NSISIGNOPT.
445
1401d2fe
MR		 4462016-05-18 Maciej W. Rozycki <macro@imgtec.com>
447
448 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
449 replacing references to `micromips_ase' throughout.
450 (_print_insn_mips): Don't use file-level microMIPS annotation to
451 determine the disassembly mode with the symbol table.
452
1178da44
PB		 4532016-05-13 Peter Bergner <bergner@vnet.ibm.com>
454
455 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
456
8f4f9071
MF		 4572016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
458
459 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
460 mips64r6.
461 * mips-opc.c (D34): New macro.
462 (mips_builtin_opcodes): Define bposge32c for DSPr3.
463
8bc52696
AF		 4642016-05-10 Alexander Fomin <alexander.fomin@intel.com>
465
466 * i386-dis.c (prefix_table): Add RDPID instruction.
467 * i386-gen.c (cpu_flag_init): Add RDPID flag.
468 (cpu_flags): Add RDPID bitfield.
469 * i386-opc.h (enum): Add RDPID element.
470 (i386_cpu_flags): Add RDPID field.
471 * i386-opc.tbl: Add RDPID instruction.
472 * i386-init.h: Regenerate.
473 * i386-tbl.h: Regenerate.
474
39d911fc
TP		 4752016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
476
477 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
478 branch type of a symbol.
479 (print_insn): Likewise.
480
16a1fa25
TP		 4812016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
482
483 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
484 Mainline Security Extensions instructions.
485 (thumb_opcodes): Add entries for narrow ARMv8-M Security
486 Extensions instructions.
487 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
488 instructions.
489 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
490 special registers.
491
d751b79e
JM		 4922016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
493
494 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
495
945e0f82
CZ		 4962016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
497
498 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
499 (arcExtMap_genOpcode): Likewise.
500 * arc-opc.c (arg_32bit_rc): Define new variable.
501 (arg_32bit_u6): Likewise.
502 (arg_32bit_limm): Likewise.
503
20f55f38
SN		 5042016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
505
506 * aarch64-gen.c (VERIFIER): Define.
507 * aarch64-opc.c (VERIFIER): Define.
508 (verify_ldpsw): Use static linkage.
509 * aarch64-opc.h (verify_ldpsw): Remove.
510 * aarch64-tbl.h: Use VERIFIER for verifiers.
511
4bd13cde
NC		 5122016-04-28 Nick Clifton <nickc@redhat.com>
513
514 PR target/19722
515 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
516 * aarch64-opc.c (verify_ldpsw): New function.
517 * aarch64-opc.h (verify_ldpsw): New prototype.
518 * aarch64-tbl.h: Add initialiser for verifier field.
519 (LDPSW): Set verifier to verify_ldpsw.
520
c0f92bf9
L		 5212016-04-23 H.J. Lu <hongjiu.lu@intel.com>
522
523 PR binutils/19983
524 PR binutils/19984
525 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
526 smaller than address size.
527
e6c7cdec
TS		 5282016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
529
530 * alpha-dis.c: Regenerate.
531 * crx-dis.c: Likewise.
532 * disassemble.c: Likewise.
533 * epiphany-opc.c: Likewise.
534 * fr30-opc.c: Likewise.
535 * frv-opc.c: Likewise.
536 * ip2k-opc.c: Likewise.
537 * iq2000-opc.c: Likewise.
538 * lm32-opc.c: Likewise.
539 * lm32-opinst.c: Likewise.
540 * m32c-opc.c: Likewise.
541 * m32r-opc.c: Likewise.
542 * m32r-opinst.c: Likewise.
543 * mep-opc.c: Likewise.
544 * mt-opc.c: Likewise.
545 * or1k-opc.c: Likewise.
546 * or1k-opinst.c: Likewise.
547 * tic80-opc.c: Likewise.
548 * xc16x-opc.c: Likewise.
549 * xstormy16-opc.c: Likewise.
550
537aefaf
AB		 5512016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
552
553 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
554 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
555 calcsd, and calcxd instructions.
556 * arc-opc.c (insert_nps_bitop_size): Delete.
557 (extract_nps_bitop_size): Delete.
558 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
559 (extract_nps_qcmp_m3): Define.
560 (extract_nps_qcmp_m2): Define.
561 (extract_nps_qcmp_m1): Define.
562 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
563 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
564 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
565 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
566 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
567 NPS_QCMP_M3.
568
c8f785f2
AB		 5692016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
570
571 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
572
6fd8e7c2
L		 5732016-04-15 H.J. Lu <hongjiu.lu@intel.com>
574
575 * Makefile.in: Regenerated with automake 1.11.6.
576 * aclocal.m4: Likewise.
577
4b0c052e
AB		 5782016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
579
580 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
581 instructions.
582 * arc-opc.c (insert_nps_cmem_uimm16): New function.
583 (extract_nps_cmem_uimm16): New function.
584 (arc_operands): Add NPS_XLDST_UIMM16 operand.
585
cb040366
AB		 5862016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
587
588 * arc-dis.c (arc_insn_length): New function.
589 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
590 (find_format): Change insnLen parameter to unsigned.
591
accc0180
NC		 5922016-04-13 Nick Clifton <nickc@redhat.com>
593
594 PR target/19937
595 * v850-opc.c (v850_opcodes): Correct masks for long versions of
596 the LD.B and LD.BU instructions.
597
f36e33da
CZ		 5982016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
599
600 * arc-dis.c (find_format): Check for extension flags.
601 (print_flags): New function.
602 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
603 .extAuxRegister.
604 * arc-ext.c (arcExtMap_coreRegName): Use
605 LAST_EXTENSION_CORE_REGISTER.
606 (arcExtMap_coreReadWrite): Likewise.
607 (dump_ARC_extmap): Update printing.
608 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
609 (arc_aux_regs): Add cpu field.
610 * arc-regs.h: Add cpu field, lower case name aux registers.
611
1c2e355e
CZ		 6122016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
613
614 * arc-tbl.h: Add rtsc, sleep with no arguments.
615
b99747ae
CZ		 6162016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
617
618 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
619 Initialize.
620 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
621 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
622 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
623 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
624 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
625 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
626 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
627 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
628 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
629 (arc_opcode arc_opcodes): Null terminate the array.
630 (arc_num_opcodes): Remove.
631 * arc-ext.h (INSERT_XOP): Define.
632 (extInstruction_t): Likewise.
633 (arcExtMap_instName): Delete.
634 (arcExtMap_insn): New function.
635 (arcExtMap_genOpcode): Likewise.
636 * arc-ext.c (ExtInstruction): Remove.
637 (create_map): Zero initialize instruction fields.
638 (arcExtMap_instName): Remove.
639 (arcExtMap_insn): New function.
640 (dump_ARC_extmap): More info while debuging.
641 (arcExtMap_genOpcode): New function.
642 * arc-dis.c (find_format): New function.
643 (print_insn_arc): Use find_format.
644 (arc_get_disassembler): Enable dump_ARC_extmap only when
645 debugging.
646
92708cec
MR		 6472016-04-11 Maciej W. Rozycki <macro@imgtec.com>
648
649 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
650 instruction bits out.
651
a42a4f84
AB		 6522016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
653
654 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
655 * arc-opc.c (arc_flag_operands): Add new flags.
656 (arc_flag_classes): Add new classes.
657
1328504b
AB		 6582016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
659
660 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
661
820f03ff
AB		 6622016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
663
664 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
665 encode1, rflt, crc16, and crc32 instructions.
666 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
667 (arc_flag_classes): Add C_NPS_R.
668 (insert_nps_bitop_size_2b): New function.
669 (extract_nps_bitop_size_2b): Likewise.
670 (insert_nps_bitop_uimm8): Likewise.
671 (extract_nps_bitop_uimm8): Likewise.
672 (arc_operands): Add new operand entries.
673
8ddf6b2a
CZ		 6742016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
675
b99747ae
CZ		 676 * arc-regs.h: Add a new subclass field. Add double assist
677 accumulator register values.
678 * arc-tbl.h: Use DPA subclass to mark the double assist
679 instructions. Use DPX/SPX subclas to mark the FPX instructions.
680 * arc-opc.c (RSP): Define instead of SP.
681 (arc_aux_regs): Add the subclass field.
8ddf6b2a 682
589a7d88
JW		 6832016-04-05 Jiong Wang <jiong.wang@arm.com>
684
685 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
686
0a191de9 6872016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 688
689 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
690 NPS_R_SRC1.
691
0a106562
AB		 6922016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
693
694 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
695 issues. No functional changes.
696
bd05ac5f
CZ		 6972016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
698
b99747ae
CZ		 699 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
700 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
701 (RTT): Remove duplicate.
702 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
703 (PCT_CONFIG*): Remove.
704 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 705
9885948f
CZ		 7062016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
707
b99747ae 708 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 709
f2dd8838
CZ		 7102016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
711
b99747ae
CZ		 712 * arc-tbl.h (invld07): Remove.
713 * arc-ext-tbl.h: New file.
714 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
715 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 716
0d2f91fe
JK		 7172016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
718
719 Fix -Wstack-usage warnings.
720 * aarch64-dis.c (print_operands): Substitute size.
721 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
722
a6b71f42
JM		 7232016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
724
725 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
726 to get a proper diagnostic when an invalid ASR register is used.
727
9780e045
NC		 7282016-03-22 Nick Clifton <nickc@redhat.com>
729
730 * configure: Regenerate.
731
e23e8ebe
AB		 7322016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
733
734 * arc-nps400-tbl.h: New file.
735 * arc-opc.c: Add top level comment.
736 (insert_nps_3bit_dst): New function.
737 (extract_nps_3bit_dst): New function.
738 (insert_nps_3bit_src2): New function.
739 (extract_nps_3bit_src2): New function.
740 (insert_nps_bitop_size): New function.
741 (extract_nps_bitop_size): New function.
742 (arc_flag_operands): Add nps400 entries.
743 (arc_flag_classes): Add nps400 entries.
744 (arc_operands): Add nps400 entries.
745 (arc_opcodes): Add nps400 include.
746
1ae8ab47
AB		 7472016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
748
749 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
750 the new class enum values.
751
8699fc3e
AB		 7522016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
753
754 * arc-dis.c (print_insn_arc): Handle nps400.
755
24740d83
AB		 7562016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
757
758 * arc-opc.c (BASE): Delete.
759
8678914f
NC		 7602016-03-18 Nick Clifton <nickc@redhat.com>
761
762 PR target/19721
763 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
764 of MOV insn that aliases an ORR insn.
765
cc933301
JW		 7662016-03-16 Jiong Wang <jiong.wang@arm.com>
767
768 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
769
f86f5863
TS		 7702016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
771
772 * mcore-opc.h: Add const qualifiers.
773 * microblaze-opc.h (struct op_code_struct): Likewise.
774 * sh-opc.h: Likewise.
775 * tic4x-dis.c (tic4x_print_indirect): Likewise.
776 (tic4x_print_op): Likewise.
777
62de1c63
AM		 7782016-03-02 Alan Modra <amodra@gmail.com>
779
d11698cd 780 * or1k-desc.h: Regenerate.
62de1c63 781 * fr30-ibld.c: Regenerate.
c697cf0b 782 * rl78-decode.c: Regenerate.
62de1c63 783
020efce5
NC		 7842016-03-01 Nick Clifton <nickc@redhat.com>
785
786 PR target/19747
787 * rl78-dis.c (print_insn_rl78_common): Fix typo.
788
b0c11777
RL		 7892016-02-24 Renlin Li <renlin.li@arm.com>
790
791 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
792 (print_insn_coprocessor): Support fp16 instructions.
793
3e309328
RL		 7942016-02-24 Renlin Li <renlin.li@arm.com>
795
796 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
797 vminnm, vrint(mpna).
798
8afc7bea
RL		 7992016-02-24 Renlin Li <renlin.li@arm.com>
800
801 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
802 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
803
4fd7268a
L		 8042016-02-15 H.J. Lu <hongjiu.lu@intel.com>
805
806 * i386-dis.c (print_insn): Parenthesize expression to prevent
807 truncated addresses.
808 (OP_J): Likewise.
809
4670103e
CZ		 8102016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
811 Janek van Oirschot <jvanoirs@synopsys.com>
812
b99747ae
CZ		 813 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
814 variable.
4670103e 815
c1d9289f
NC		 8162016-02-04 Nick Clifton <nickc@redhat.com>
817
818 PR target/19561
819 * msp430-dis.c (print_insn_msp430): Add a special case for
820 decoding an RRC instruction with the ZC bit set in the extension
821 word.
822
a143b004
AB		 8232016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
824
825 * cgen-ibld.in (insert_normal): Rework calculation of shift.
826 * epiphany-ibld.c: Regenerate.
827 * fr30-ibld.c: Regenerate.
828 * frv-ibld.c: Regenerate.
829 * ip2k-ibld.c: Regenerate.
830 * iq2000-ibld.c: Regenerate.
831 * lm32-ibld.c: Regenerate.
832 * m32c-ibld.c: Regenerate.
833 * m32r-ibld.c: Regenerate.
834 * mep-ibld.c: Regenerate.
835 * mt-ibld.c: Regenerate.
836 * or1k-ibld.c: Regenerate.
837 * xc16x-ibld.c: Regenerate.
838 * xstormy16-ibld.c: Regenerate.
839
b89807c6
AB		 8402016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
841
842 * epiphany-dis.c: Regenerated from latest cpu files.
843
d8c823c8
MM		 8442016-02-01 Michael McConville <mmcco@mykolab.com>
845
846 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
847 test bit.
848
5bc5ae88
RL		 8492016-01-25 Renlin Li <renlin.li@arm.com>
850
851 * arm-dis.c (mapping_symbol_for_insn): New function.
852 (find_ifthen_state): Call mapping_symbol_for_insn().
853
0bff6e2d
MW		 8542016-01-20 Matthew Wahab <matthew.wahab@arm.com>
855
856 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
857 of MSR UAO immediate operand.
858
100b4f2e
MR		 8592016-01-18 Maciej W. Rozycki <macro@imgtec.com>
860
861 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
862 instruction support.
863
5c14705f
AM		 8642016-01-17 Alan Modra <amodra@gmail.com>
865
866 * configure: Regenerate.
867
4d82fe66
NC		 8682016-01-14 Nick Clifton <nickc@redhat.com>
869
870 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
871 instructions that can support stack pointer operations.
872 * rl78-decode.c: Regenerate.
873 * rl78-dis.c: Fix display of stack pointer in MOVW based
874 instructions.
875
651657fa
MW		 8762016-01-14 Matthew Wahab <matthew.wahab@arm.com>
877
878 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
879 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
880 erxtatus_el1 and erxaddr_el1.
881
105bde57
MW		 8822016-01-12 Matthew Wahab <matthew.wahab@arm.com>
883
884 * arm-dis.c (arm_opcodes): Add "esb".
885 (thumb_opcodes): Likewise.
886
afa8d405
PB		 8872016-01-11 Peter Bergner <bergner@vnet.ibm.com>
888
889 * ppc-opc.c <xscmpnedp>: Delete.
890 <xvcmpnedp>: Likewise.
891 <xvcmpnedp.>: Likewise.
892 <xvcmpnesp>: Likewise.
893 <xvcmpnesp.>: Likewise.
894
83c3256e
AS		 8952016-01-08 Andreas Schwab <schwab@linux-m68k.org>
896
897 PR gas/13050
898 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
899 addition to ISA_A.
900
6f2750fe
AM		 9012016-01-01 Alan Modra <amodra@gmail.com>
902
903 Update year range in copyright notice of all files.
904
3499769a
AM		 905For older changes see ChangeLog-2015
906\f
907Copyright (C) 2016 Free Software Foundation, Inc.
908
909Copying and distribution of this file, with or without modification,
910are permitted in any medium without royalty provided the copyright
911notice and this notice are preserved.
912
913Local Variables:
914mode: change-log
915left-margin: 8
916fill-column: 74
917version-control: never
918End:
GDB Binutils - Deliverables
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