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Update Cris assembler tests for checks that now pass where they used to fail.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
3b4b0a62
JB		 12017-10-12 James Bowman <james.bowman@ftdichip.com>
2
3 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
4 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
5 K15. Add jmpix pattern.
6
8e464506
AK		 72017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
8
9 * s390-opc.txt (prno, tpei, irbm): New instructions added.
10
ee6767da
AK		 112017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
12
13 * s390-opc.c (INSTR_SI_RD): New macro.
14 (INSTR_S_RD): Adjust example instruction.
15 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
16 SI_RD.
17
d2e6c9a3
AF		 182017-10-01 Alexander Fedotov <alfedotov@gmail.com>
19
20 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
21 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
22 VLE multimple load/store instructions. Old e_ldm* variants are
23 kept as aliases.
24 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
25
8e43602e
NC		 262017-09-27 Nick Clifton <nickc@redhat.com>
27
28 PR 22179
29 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
30 names for the fmv.x.s and fmv.s.x instructions respectively.
31
58a0b827
NC		 322017-09-26 do <do@nerilex.org>
33
34 PR 22123
35 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
36 be used on CPUs that have emacs support.
37
57a024f4
SDJ		 382017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
39
40 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
41
4ec521f2
KLC		 422017-09-09 Kamil Rytarowski <n54@gmx.com>
43
44 * nds32-asm.c: Rename __BIT() to N32_BIT().
45 * nds32-asm.h: Likewise.
46 * nds32-dis.c: Likewise.
47
4e9ac44a
L		 482017-09-09 H.J. Lu <hongjiu.lu@intel.com>
49
50 * i386-dis.c (last_active_prefix): Removed.
51 (ckprefix): Don't set last_active_prefix.
52 (NOTRACK_Fixup): Don't check last_active_prefix.
53
b55f3386
NC		 542017-08-31 Nick Clifton <nickc@redhat.com>
55
56 * po/fr.po: Updated French translation.
57
59e8523b
JB		 582017-08-31 James Bowman <james.bowman@ftdichip.com>
59
60 * ft32-dis.c (print_insn_ft32): Correct display of non-address
61 fields.
62
74081948
AF		 632017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
64 Edmar Wienskoski <edmar.wienskoski@nxp.com>
65
66 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
67 PPC_OPCODE_EFS2 flag to "e200z4" entry.
68 New entries efs2 and spe2.
69 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
70 (SPE2_OPCD_SEGS): New macro.
71 (spe2_opcd_indices): New.
72 (disassemble_init_powerpc): Handle SPE2 opcodes.
73 (lookup_spe2): New function.
74 (print_insn_powerpc): call lookup_spe2.
75 * ppc-opc.c (insert_evuimm1_ex0): New function.
76 (extract_evuimm1_ex0): Likewise.
77 (insert_evuimm_lt8): Likewise.
78 (extract_evuimm_lt8): Likewise.
79 (insert_off_spe2): Likewise.
80 (extract_off_spe2): Likewise.
81 (insert_Ddd): Likewise.
82 (extract_Ddd): Likewise.
83 (DD): New operand.
84 (EVUIMM_LT8): Likewise.
85 (EVUIMM_LT16): Adjust.
86 (MMMM): New operand.
87 (EVUIMM_1): Likewise.
88 (EVUIMM_1_EX0): Likewise.
89 (EVUIMM_2): Adjust.
90 (NNN): New operand.
91 (VX_OFF_SPE2): Likewise.
92 (BBB): Likewise.
93 (DDD): Likewise.
94 (VX_MASK_DDD): New mask.
95 (HH): New operand.
96 (VX_RA_CONST): New macro.
97 (VX_RA_CONST_MASK): Likewise.
98 (VX_RB_CONST): Likewise.
99 (VX_RB_CONST_MASK): Likewise.
100 (VX_OFF_SPE2_MASK): Likewise.
101 (VX_SPE_CRFD): Likewise.
102 (VX_SPE_CRFD_MASK VX): Likewise.
103 (VX_SPE2_CLR): Likewise.
104 (VX_SPE2_CLR_MASK): Likewise.
105 (VX_SPE2_SPLATB): Likewise.
106 (VX_SPE2_SPLATB_MASK): Likewise.
107 (VX_SPE2_OCTET): Likewise.
108 (VX_SPE2_OCTET_MASK): Likewise.
109 (VX_SPE2_DDHH): Likewise.
110 (VX_SPE2_DDHH_MASK): Likewise.
111 (VX_SPE2_HH): Likewise.
112 (VX_SPE2_HH_MASK): Likewise.
113 (VX_SPE2_EVMAR): Likewise.
114 (VX_SPE2_EVMAR_MASK): Likewise.
115 (PPCSPE2): Likewise.
116 (PPCEFS2): Likewise.
117 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
118 (powerpc_macros): Map old SPE instructions have new names
119 with the same opcodes. Add SPE2 instructions which just are
120 mapped to SPE2.
121 (spe2_opcodes): Add SPE2 opcodes.
122
b80c7270
AM		 1232017-08-23 Alan Modra <amodra@gmail.com>
124
125 * ppc-opc.c: Formatting and comment fixes. Move insert and
126 extract functions earlier, deleting forward declarations.
127 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
128 RA_MASK.
129
67d888f5
PD		 1302017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
131
132 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
133
e3c2f928
AF		 1342017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
135 Edmar Wienskoski <edmar.wienskoski@nxp.com>
136
137 * ppc-opc.c (insert_evuimm2_ex0): New function.
138 (extract_evuimm2_ex0): Likewise.
139 (insert_evuimm4_ex0): Likewise.
140 (extract_evuimm4_ex0): Likewise.
141 (insert_evuimm8_ex0): Likewise.
142 (extract_evuimm8_ex0): Likewise.
143 (insert_evuimm_lt16): Likewise.
144 (extract_evuimm_lt16): Likewise.
145 (insert_rD_rS_even): Likewise.
146 (extract_rD_rS_even): Likewise.
147 (insert_off_lsp): Likewise.
148 (extract_off_lsp): Likewise.
149 (RD_EVEN): New operand.
150 (RS_EVEN): Likewise.
151 (RSQ): Adjust.
152 (EVUIMM_LT16): New operand.
153 (HTM_SI): Adjust.
154 (EVUIMM_2_EX0): New operand.
155 (EVUIMM_4): Adjust.
156 (EVUIMM_4_EX0): New operand.
157 (EVUIMM_8): Adjust.
158 (EVUIMM_8_EX0): New operand.
159 (WS): Adjust.
160 (VX_OFF): New operand.
161 (VX_LSP): New macro.
162 (VX_LSP_MASK): Likewise.
163 (VX_LSP_OFF_MASK): Likewise.
164 (PPC_OPCODE_LSP): Likewise.
165 (vle_opcodes): Add LSP opcodes.
166 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
167
cc4a945a
JW		 1682017-08-09 Jiong Wang <jiong.wang@arm.com>
169
170 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
171 register operands in CRC instructions.
172 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
173 comments.
174
b28b8b5e
L		 1752017-08-07 H.J. Lu <hongjiu.lu@intel.com>
176
177 * disassemble.c (disassembler): Mark big and mach with
178 ATTRIBUTE_UNUSED.
179
e347efc3
MR		 1802017-08-07 Maciej W. Rozycki <macro@imgtec.com>
181
182 * disassemble.c (disassembler): Remove arch/mach/endian
183 assertions.
184
7cbc739c
NC		 1852017-07-25 Nick Clifton <nickc@redhat.com>
186
187 PR 21739
188 * arc-opc.c (insert_rhv2): Use lower case first letter in error
189 message.
190 (insert_r0): Likewise.
191 (insert_r1): Likewise.
192 (insert_r2): Likewise.
193 (insert_r3): Likewise.
194 (insert_sp): Likewise.
195 (insert_gp): Likewise.
196 (insert_pcl): Likewise.
197 (insert_blink): Likewise.
198 (insert_ilink1): Likewise.
199 (insert_ilink2): Likewise.
200 (insert_ras): Likewise.
201 (insert_rbs): Likewise.
202 (insert_rcs): Likewise.
203 (insert_simm3s): Likewise.
204 (insert_rrange): Likewise.
205 (insert_r13el): Likewise.
206 (insert_fpel): Likewise.
207 (insert_blinkel): Likewise.
208 (insert_pclel): Likewise.
209 (insert_nps_bitop_size_2b): Likewise.
210 (insert_nps_imm_offset): Likewise.
211 (insert_nps_imm_entry): Likewise.
212 (insert_nps_size_16bit): Likewise.
213 (insert_nps_##NAME##_pos): Likewise.
214 (insert_nps_##NAME): Likewise.
215 (insert_nps_bitop_ins_ext): Likewise.
216 (insert_nps_##NAME): Likewise.
217 (insert_nps_min_hofs): Likewise.
218 (insert_nps_##NAME): Likewise.
219 (insert_nps_rbdouble_64): Likewise.
220 (insert_nps_misc_imm_offset): Likewise.
221 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
222 option description.
223
7684e580
JW		 2242017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
225 Jiong Wang <jiong.wang@arm.com>
226
227 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
228 correct the print.
229 * aarch64-dis-2.c: Regenerated.
230
47826cdb
AK		 2312017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
232
233 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
234 table.
235
2d2dbad0
NC		 2362017-07-20 Nick Clifton <nickc@redhat.com>
237
238 * po/de.po: Updated German translation.
239
70b448ba 2402017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
241
242 * arc-regs.h (sec_stat): New aux register.
243 (aux_kernel_sp): Likewise.
244 (aux_sec_u_sp): Likewise.
245 (aux_sec_k_sp): Likewise.
246 (sec_vecbase_build): Likewise.
247 (nsc_table_top): Likewise.
248 (nsc_table_base): Likewise.
249 (ersec_stat): Likewise.
250 (aux_sec_except): Likewise.
251
7179e0e6
CZ		 2522017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
253
254 * arc-opc.c (extract_uimm12_20): New function.
255 (UIMM12_20): New operand.
256 (SIMM3_5_S): Adjust.
257 * arc-tbl.h (sjli): Add new instruction.
258
684d5a10
JEM		 2592017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
260 John Eric Martin <John.Martin@emmicro-us.com>
261
262 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
263 (UIMM3_23): Adjust accordingly.
264 * arc-regs.h: Add/correct jli_base register.
265 * arc-tbl.h (jli_s): Likewise.
266
de194d85
YC		 2672017-07-18 Nick Clifton <nickc@redhat.com>
268
269 PR 21775
270 * aarch64-opc.c: Fix spelling typos.
271 * i386-dis.c: Likewise.
272
0f6329bd
RB		 2732017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
274
275 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
276 max_addr_offset and octets variables to size_t.
277
429d795d
AM		 2782017-07-12 Alan Modra <amodra@gmail.com>
279
280 * po/da.po: Update from translationproject.org/latest/opcodes/.
281 * po/de.po: Likewise.
282 * po/es.po: Likewise.
283 * po/fi.po: Likewise.
284 * po/fr.po: Likewise.
285 * po/id.po: Likewise.
286 * po/it.po: Likewise.
287 * po/nl.po: Likewise.
288 * po/pt_BR.po: Likewise.
289 * po/ro.po: Likewise.
290 * po/sv.po: Likewise.
291 * po/tr.po: Likewise.
292 * po/uk.po: Likewise.
293 * po/vi.po: Likewise.
294 * po/zh_CN.po: Likewise.
295
4162bb66
AM		 2962017-07-11 Yao Qi <yao.qi@linaro.org>
297 Alan Modra <amodra@gmail.com>
298
299 * cgen.sh: Mark generated files read-only.
300 * epiphany-asm.c: Regenerate.
301 * epiphany-desc.c: Regenerate.
302 * epiphany-desc.h: Regenerate.
303 * epiphany-dis.c: Regenerate.
304 * epiphany-ibld.c: Regenerate.
305 * epiphany-opc.c: Regenerate.
306 * epiphany-opc.h: Regenerate.
307 * fr30-asm.c: Regenerate.
308 * fr30-desc.c: Regenerate.
309 * fr30-desc.h: Regenerate.
310 * fr30-dis.c: Regenerate.
311 * fr30-ibld.c: Regenerate.
312 * fr30-opc.c: Regenerate.
313 * fr30-opc.h: Regenerate.
314 * frv-asm.c: Regenerate.
315 * frv-desc.c: Regenerate.
316 * frv-desc.h: Regenerate.
317 * frv-dis.c: Regenerate.
318 * frv-ibld.c: Regenerate.
319 * frv-opc.c: Regenerate.
320 * frv-opc.h: Regenerate.
321 * ip2k-asm.c: Regenerate.
322 * ip2k-desc.c: Regenerate.
323 * ip2k-desc.h: Regenerate.
324 * ip2k-dis.c: Regenerate.
325 * ip2k-ibld.c: Regenerate.
326 * ip2k-opc.c: Regenerate.
327 * ip2k-opc.h: Regenerate.
328 * iq2000-asm.c: Regenerate.
329 * iq2000-desc.c: Regenerate.
330 * iq2000-desc.h: Regenerate.
331 * iq2000-dis.c: Regenerate.
332 * iq2000-ibld.c: Regenerate.
333 * iq2000-opc.c: Regenerate.
334 * iq2000-opc.h: Regenerate.
335 * lm32-asm.c: Regenerate.
336 * lm32-desc.c: Regenerate.
337 * lm32-desc.h: Regenerate.
338 * lm32-dis.c: Regenerate.
339 * lm32-ibld.c: Regenerate.
340 * lm32-opc.c: Regenerate.
341 * lm32-opc.h: Regenerate.
342 * lm32-opinst.c: Regenerate.
343 * m32c-asm.c: Regenerate.
344 * m32c-desc.c: Regenerate.
345 * m32c-desc.h: Regenerate.
346 * m32c-dis.c: Regenerate.
347 * m32c-ibld.c: Regenerate.
348 * m32c-opc.c: Regenerate.
349 * m32c-opc.h: Regenerate.
350 * m32r-asm.c: Regenerate.
351 * m32r-desc.c: Regenerate.
352 * m32r-desc.h: Regenerate.
353 * m32r-dis.c: Regenerate.
354 * m32r-ibld.c: Regenerate.
355 * m32r-opc.c: Regenerate.
356 * m32r-opc.h: Regenerate.
357 * m32r-opinst.c: Regenerate.
358 * mep-asm.c: Regenerate.
359 * mep-desc.c: Regenerate.
360 * mep-desc.h: Regenerate.
361 * mep-dis.c: Regenerate.
362 * mep-ibld.c: Regenerate.
363 * mep-opc.c: Regenerate.
364 * mep-opc.h: Regenerate.
365 * mt-asm.c: Regenerate.
366 * mt-desc.c: Regenerate.
367 * mt-desc.h: Regenerate.
368 * mt-dis.c: Regenerate.
369 * mt-ibld.c: Regenerate.
370 * mt-opc.c: Regenerate.
371 * mt-opc.h: Regenerate.
372 * or1k-asm.c: Regenerate.
373 * or1k-desc.c: Regenerate.
374 * or1k-desc.h: Regenerate.
375 * or1k-dis.c: Regenerate.
376 * or1k-ibld.c: Regenerate.
377 * or1k-opc.c: Regenerate.
378 * or1k-opc.h: Regenerate.
379 * or1k-opinst.c: Regenerate.
380 * xc16x-asm.c: Regenerate.
381 * xc16x-desc.c: Regenerate.
382 * xc16x-desc.h: Regenerate.
383 * xc16x-dis.c: Regenerate.
384 * xc16x-ibld.c: Regenerate.
385 * xc16x-opc.c: Regenerate.
386 * xc16x-opc.h: Regenerate.
387 * xstormy16-asm.c: Regenerate.
388 * xstormy16-desc.c: Regenerate.
389 * xstormy16-desc.h: Regenerate.
390 * xstormy16-dis.c: Regenerate.
391 * xstormy16-ibld.c: Regenerate.
392 * xstormy16-opc.c: Regenerate.
393 * xstormy16-opc.h: Regenerate.
394
7639175c
AM		 3952017-07-07 Alan Modra <amodra@gmail.com>
396
397 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
398 * m32c-dis.c: Regenerate.
399 * mep-dis.c: Regenerate.
400
e4bdd679
BP		 4012017-07-05 Borislav Petkov <bp@suse.de>
402
403 * i386-dis.c: Enable ModRM.reg /6 aliases.
404
60c96dbf
RR		 4052017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
406
407 * opcodes/arm-dis.c: Support MVFR2 in disassembly
408 with vmrs and vmsr.
409
0d702cfe
TG		 4102017-07-04 Tristan Gingold <gingold@adacore.com>
411
412 * configure: Regenerate.
413
15e6ed8c
TG		 4142017-07-03 Tristan Gingold <gingold@adacore.com>
415
416 * po/opcodes.pot: Regenerate.
417
b1d3c886
MR		 4182017-06-30 Maciej W. Rozycki <macro@imgtec.com>
419
420 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
421 entries to the MSA ASE instruction block.
422
909b4e3d
MR		 4232017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
424 Maciej W. Rozycki <macro@imgtec.com>
425
426 * micromips-opc.c (XPA, XPAVZ): New macros.
427 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
428 "mthgc0".
429
f5b2fd52
MR		 4302017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
431 Maciej W. Rozycki <macro@imgtec.com>
432
433 * micromips-opc.c (I36): New macro.
434 (micromips_opcodes): Add "eretnc".
435
9785fc2a
MR		 4362017-06-30 Maciej W. Rozycki <macro@imgtec.com>
437 Andrew Bennett <andrew.bennett@imgtec.com>
438
439 * mips-dis.c (mips_calculate_combination_ases): Handle the
440 ASE_XPA_VIRT flag.
441 (parse_mips_ase_option): New function.
442 (parse_mips_dis_option): Factor out ASE option handling to the
443 new function. Call `mips_calculate_combination_ases'.
444 * mips-opc.c (XPAVZ): New macro.
445 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
446 "mfhgc0", "mthc0" and "mthgc0".
447
60804c53
MR		 4482017-06-29 Maciej W. Rozycki <macro@imgtec.com>
449
450 * mips-dis.c (mips_calculate_combination_ases): New function.
451 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
452 calculation to the new function.
453 (set_default_mips_dis_options): Call the new function.
454
2e74f9dd
AK		 4552017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
456
457 * arc-dis.c (parse_disassembler_options): Use
458 FOR_EACH_DISASSEMBLER_OPTION.
459
e1e94c49
AK		 4602017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
461
462 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
463 disassembler option strings.
464 (parse_cpu_option): Likewise.
465
65a55fbb
TC		 4662017-06-28 Tamar Christina <tamar.christina@arm.com>
467
468 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
469 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
470 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
471 (aarch64_feature_dotprod, DOT_INSN): New.
472 (udot, sdot): New.
473 * aarch64-dis-2.c: Regenerated.
474
c604a79a
JW		 4752017-06-28 Jiong Wang <jiong.wang@arm.com>
476
477 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
478
38bf472a
MR		 4792017-06-28 Maciej W. Rozycki <macro@imgtec.com>
480 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 481 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 482
483 * mips-formats.h (INT_BIAS): New macro.
484 (INT_ADJ): Redefine in INT_BIAS terms.
485 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
486 (mips_print_save_restore): New function.
487 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
488 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
489 call.
490 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
491 (print_mips16_insn_arg): Call `mips_print_save_restore' for
492 OP_SAVE_RESTORE_LIST handling, factored out from here.
493 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
494 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
495 (mips_builtin_opcodes): Add "restore" and "save" entries.
496 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
497 (IAMR2): New macro.
498 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
499
9bdfdbf9
AW		 5002017-06-23 Andrew Waterman <andrew@sifive.com>
501
502 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
503 alias; do not mark SLTI instruction as an alias.
504
2234eee6
L		 5052017-06-21 H.J. Lu <hongjiu.lu@intel.com>
506
507 * i386-dis.c (RM_0FAE_REG_5): Removed.
508 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
509 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
510 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
511 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
512 PREFIX_MOD_3_0F01_REG_5_RM_0.
513 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
514 PREFIX_MOD_3_0FAE_REG_5.
515 (mod_table): Update MOD_0FAE_REG_5.
516 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
517 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
518 * i386-tbl.h: Regenerated.
519
c2f76402
L		 5202017-06-21 H.J. Lu <hongjiu.lu@intel.com>
521
522 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
523 * i386-opc.tbl: Likewise.
524 * i386-tbl.h: Regenerated.
525
9fef80d6
L		 5262017-06-21 H.J. Lu <hongjiu.lu@intel.com>
527
528 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
529 and "jmp{&|}".
530 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
531 prefix.
532
0f6d864d
NC		 5332017-06-19 Nick Clifton <nickc@redhat.com>
534
535 PR binutils/21614
536 * score-dis.c (score_opcodes): Add sentinel.
537
e197589b
AM		 5382017-06-16 Alan Modra <amodra@gmail.com>
539
540 * rx-decode.c: Regenerate.
541
0d96e4df
L		 5422017-06-15 H.J. Lu <hongjiu.lu@intel.com>
543
544 PR binutils/21594
545 * i386-dis.c (OP_E_register): Check valid bnd register.
546 (OP_G): Likewise.
547
cd3ea7c6
NC		 5482017-06-15 Nick Clifton <nickc@redhat.com>
549
550 PR binutils/21595
551 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
552 range value.
553
63323b5b
NC		 5542017-06-15 Nick Clifton <nickc@redhat.com>
555
556 PR binutils/21588
557 * rl78-decode.opc (OP_BUF_LEN): Define.
558 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
559 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
560 array.
561 * rl78-decode.c: Regenerate.
562
08c7881b
NC		 5632017-06-15 Nick Clifton <nickc@redhat.com>
564
565 PR binutils/21586
566 * bfin-dis.c (gregs): Clip index to prevent overflow.
567 (regs): Likewise.
568 (regs_lo): Likewise.
569 (regs_hi): Likewise.
570
e64519d1
NC		 5712017-06-14 Nick Clifton <nickc@redhat.com>
572
573 PR binutils/21576
574 * score7-dis.c (score_opcodes): Add sentinel.
575
6394c606
YQ		 5762017-06-14 Yao Qi <yao.qi@linaro.org>
577
578 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
579 * arm-dis.c: Likewise.
580 * ia64-dis.c: Likewise.
581 * mips-dis.c: Likewise.
582 * spu-dis.c: Likewise.
583 * disassemble.h (print_insn_aarch64): New declaration, moved from
584 include/dis-asm.h.
585 (print_insn_big_arm, print_insn_big_mips): Likewise.
586 (print_insn_i386, print_insn_ia64): Likewise.
587 (print_insn_little_arm, print_insn_little_mips): Likewise.
588
db5fa770
NC		 5892017-06-14 Nick Clifton <nickc@redhat.com>
590
591 PR binutils/21587
592 * rx-decode.opc: Include libiberty.h
593 (GET_SCALE): New macro - validates access to SCALE array.
594 (GET_PSCALE): New macro - validates access to PSCALE array.
595 (DIs, SIs, S2Is, rx_disp): Use new macros.
596 * rx-decode.c: Regenerate.
597
05c966f3
AV		 5982017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
599
600 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
601
10045478
AK		 6022017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
603
604 * arc-dis.c (enforced_isa_mask): Declare.
605 (cpu_types): Likewise.
606 (parse_cpu_option): New function.
607 (parse_disassembler_options): Use it.
608 (print_insn_arc): Use enforced_isa_mask.
609 (print_arc_disassembler_options): Document new options.
610
88c1242d
YQ		 6112017-05-24 Yao Qi <yao.qi@linaro.org>
612
613 * alpha-dis.c: Include disassemble.h, don't include
614 dis-asm.h.
615 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
616 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
617 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
618 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
619 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
620 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
621 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
622 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
623 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
624 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
625 * moxie-dis.c, msp430-dis.c, mt-dis.c:
626 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
627 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
628 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
629 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
630 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
631 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
632 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
633 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
634 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
635 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
636 * z80-dis.c, z8k-dis.c: Likewise.
637 * disassemble.h: New file.
638
ab20fa4a
YQ		 6392017-05-24 Yao Qi <yao.qi@linaro.org>
640
641 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
642 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
643
003ca0fd
YQ		 6442017-05-24 Yao Qi <yao.qi@linaro.org>
645
646 * disassemble.c (disassembler): Add arguments a, big and mach.
647 Use them.
648
04ef582a
L		 6492017-05-22 H.J. Lu <hongjiu.lu@intel.com>
650
651 * i386-dis.c (NOTRACK_Fixup): New.
652 (NOTRACK): Likewise.
653 (NOTRACK_PREFIX): Likewise.
654 (last_active_prefix): Likewise.
655 (reg_table): Use NOTRACK on indirect call and jmp.
656 (ckprefix): Set last_active_prefix.
657 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
658 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
659 * i386-opc.h (NoTrackPrefixOk): New.
660 (i386_opcode_modifier): Add notrackprefixok.
661 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
662 Add notrack.
663 * i386-tbl.h: Regenerated.
664
64517994
JM		 6652017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
666
667 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
668 (X_IMM2): Define.
669 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
670 bfd_mach_sparc_v9m8.
671 (print_insn_sparc): Handle new operand types.
672 * sparc-opc.c (MASK_M8): Define.
673 (v6): Add MASK_M8.
674 (v6notlet): Likewise.
675 (v7): Likewise.
676 (v8): Likewise.
677 (v9): Likewise.
678 (v9a): Likewise.
679 (v9b): Likewise.
680 (v9c): Likewise.
681 (v9d): Likewise.
682 (v9e): Likewise.
683 (v9v): Likewise.
684 (v9m): Likewise.
685 (v9andleon): Likewise.
686 (m8): Define.
687 (HWS_VM8): Define.
688 (HWS2_VM8): Likewise.
689 (sparc_opcode_archs): Add entry for "m8".
690 (sparc_opcodes): Add OSA2017 and M8 instructions
691 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
692 fpx{ll,ra,rl}64x,
693 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
694 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
695 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
696 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
697 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
698 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
699 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
700 ASI_CORE_SELECT_COMMIT_NHT.
701
535b785f
AM		 7022017-05-18 Alan Modra <amodra@gmail.com>
703
704 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
705 * aarch64-dis.c: Likewise.
706 * aarch64-gen.c: Likewise.
707 * aarch64-opc.c: Likewise.
708
25499ac7
MR		 7092017-05-15 Maciej W. Rozycki <macro@imgtec.com>
710 Matthew Fortune <matthew.fortune@imgtec.com>
711
712 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
713 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
714 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
715 (print_insn_arg) <OP_REG28>: Add handler.
716 (validate_insn_args) <OP_REG28>: Handle.
717 (print_mips16_insn_arg): Handle MIPS16 instructions that require
718 32-bit encoding and 9-bit immediates.
719 (print_insn_mips16): Handle MIPS16 instructions that require
720 32-bit encoding and MFC0/MTC0 operand decoding.
721 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
722 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
723 (RD_C0, WR_C0, E2, E2MT): New macros.
724 (mips16_opcodes): Add entries for MIPS16e2 instructions:
725 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
726 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
727 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
728 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
729 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
730 instructions, "swl", "swr", "sync" and its "sync_acquire",
731 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
732 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
733 regular/extended entries for original MIPS16 ISA revision
734 instructions whose extended forms are subdecoded in the MIPS16e2
735 ISA revision: "li", "sll" and "srl".
736
fdfb4752
MR		 7372017-05-15 Maciej W. Rozycki <macro@imgtec.com>
738
739 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
740 reference in CP0 move operand decoding.
741
a4f89915
MR		 7422017-05-12 Maciej W. Rozycki <macro@imgtec.com>
743
744 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
745 type to hexadecimal.
746 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
747
99e2d67a
MR		 7482017-05-11 Maciej W. Rozycki <macro@imgtec.com>
749
750 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
751 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
752 "sync_rmb" and "sync_wmb" as aliases.
753 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
754 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
755
53a346d8
CZ		 7562017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
757
758 * arc-dis.c (parse_option): Update quarkse_em option..
759 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
760 QUARKSE1.
761 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
762
f91d48de
KC		 7632017-05-03 Kito Cheng <kito.cheng@gmail.com>
764
765 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
766
43e379d7
MC		 7672017-05-01 Michael Clark <michaeljclark@mac.com>
768
769 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
770 register.
771
a4ddc54e
MR		 7722017-05-02 Maciej W. Rozycki <macro@imgtec.com>
773
774 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
775 and branches and not synthetic data instructions.
776
fe50e98c
BE		 7772017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
778
779 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
780
126124cc
CZ		 7812017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
782
783 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
784 * arc-opc.c (insert_r13el): New function.
785 (R13_EL): Define.
786 * arc-tbl.h: Add new enter/leave variants.
787
be6a24d8
CZ		 7882017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
789
790 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
791
0348fd79
MR		 7922017-04-25 Maciej W. Rozycki <macro@imgtec.com>
793
794 * mips-dis.c (print_mips_disassembler_options): Add
795 `no-aliases'.
796
6e3d1f07
MR		 7972017-04-25 Maciej W. Rozycki <macro@imgtec.com>
798
799 * mips16-opc.c (AL): New macro.
800 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
801 of "ld" and "lw" as aliases.
802
957f6b39
TC		 8032017-04-24 Tamar Christina <tamar.christina@arm.com>
804
805 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
806 arguments.
807
a8cc8a54
AM		 8082017-04-22 Alexander Fedotov <alfedotov@gmail.com>
809 Alan Modra <amodra@gmail.com>
810
811 * ppc-opc.c (ELEV): Define.
812 (vle_opcodes): Add se_rfgi and e_sc.
813 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
814 for E200Z4.
815
3ab87b68
JM		 8162017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
817
818 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
819
792f174f
NC		 8202017-04-21 Nick Clifton <nickc@redhat.com>
821
822 PR binutils/21380
823 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
824 LD3R and LD4R.
825
42742084
AM		 8262017-04-13 Alan Modra <amodra@gmail.com>
827
828 * epiphany-desc.c: Regenerate.
829 * fr30-desc.c: Regenerate.
830 * frv-desc.c: Regenerate.
831 * ip2k-desc.c: Regenerate.
832 * iq2000-desc.c: Regenerate.
833 * lm32-desc.c: Regenerate.
834 * m32c-desc.c: Regenerate.
835 * m32r-desc.c: Regenerate.
836 * mep-desc.c: Regenerate.
837 * mt-desc.c: Regenerate.
838 * or1k-desc.c: Regenerate.
839 * xc16x-desc.c: Regenerate.
840 * xstormy16-desc.c: Regenerate.
841
9a85b496
AM		 8422017-04-11 Alan Modra <amodra@gmail.com>
843
ef85eab0 844 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 845 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
846 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 847 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
848 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 849 (PPCVSX2): Define as PPC_OPCODE_POWER8.
850 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 851 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 852 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 853
62adc510
AM		 8542017-04-10 Alan Modra <amodra@gmail.com>
855
856 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
857 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
858 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
859 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
860
aa808707
PC		 8612017-04-09 Pip Cet <pipcet@gmail.com>
862
863 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
864 appropriate floating-point precision directly.
865
ac8f0f72
AM		 8662017-04-07 Alan Modra <amodra@gmail.com>
867
868 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
869 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
870 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
871 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
872 vector instructions with E6500 not PPCVEC2.
873
62ecb94c
PC		 8742017-04-06 Pip Cet <pipcet@gmail.com>
875
876 * Makefile.am: Add wasm32-dis.c.
877 * configure.ac: Add wasm32-dis.c to wasm32 target.
878 * disassemble.c: Add wasm32 disassembler code.
879 * wasm32-dis.c: New file.
880 * Makefile.in: Regenerate.
881 * configure: Regenerate.
882 * po/POTFILES.in: Regenerate.
883 * po/opcodes.pot: Regenerate.
884
f995bbe8
PA		 8852017-04-05 Pedro Alves <palves@redhat.com>
886
887 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
888 * arm-dis.c (parse_arm_disassembler_options): Constify.
889 * ppc-dis.c (powerpc_init_dialect): Constify local.
890 * vax-dis.c (parse_disassembler_options): Constify.
891
b5292032
PD		 8922017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
893
894 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
895 RISCV_GP_SYMBOL.
896
f96bd6c2
PC		 8972017-03-30 Pip Cet <pipcet@gmail.com>
898
899 * configure.ac: Add (empty) bfd_wasm32_arch target.
900 * configure: Regenerate
901 * po/opcodes.pot: Regenerate.
902
f7c514a3
JM		 9032017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
904
905 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
906 OSA2015.
907 * opcodes/sparc-opc.c (asi_table): New ASIs.
908
52be03fd
AM		 9092017-03-29 Alan Modra <amodra@gmail.com>
910
911 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
912 "raw" option.
913 (lookup_powerpc): Don't special case -1 dialect. Handle
914 PPC_OPCODE_RAW.
915 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
916 lookup_powerpc call, pass it on second.
917
9b753937
AM		 9182017-03-27 Alan Modra <amodra@gmail.com>
919
920 PR 21303
921 * ppc-dis.c (struct ppc_mopt): Comment.
922 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
923
c0c31e91
RZ		 9242017-03-27 Rinat Zelig <rinat@mellanox.com>
925
926 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
927 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
928 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
929 (insert_nps_misc_imm_offset): New function.
930 (extract_nps_misc imm_offset): New function.
931 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
932 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
933
2253c8f0
AK		 9342017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
935
936 * s390-mkopc.c (main): Remove vx2 check.
937 * s390-opc.txt: Remove vx2 instruction flags.
938
645d3342
RZ		 9392017-03-21 Rinat Zelig <rinat@mellanox.com>
940
941 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
942 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
943 (insert_nps_imm_offset): New function.
944 (extract_nps_imm_offset): New function.
945 (insert_nps_imm_entry): New function.
946 (extract_nps_imm_entry): New function.
947
4b94dd2d
AM		 9482017-03-17 Alan Modra <amodra@gmail.com>
949
950 PR 21248
951 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
952 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
953 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
954
b416fe87
KC		 9552017-03-14 Kito Cheng <kito.cheng@gmail.com>
956
957 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
958 <c.andi>: Likewise.
959 <c.addiw> Likewise.
960
03b039a5
KC		 9612017-03-14 Kito Cheng <kito.cheng@gmail.com>
962
963 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
964
2c232b83
AW		 9652017-03-13 Andrew Waterman <andrew@sifive.com>
966
967 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
968 <srl> Likewise.
969 <srai> Likewise.
970 <sra> Likewise.
971
86fa6981
L		 9722017-03-09 H.J. Lu <hongjiu.lu@intel.com>
973
974 * i386-gen.c (opcode_modifiers): Replace S with Load.
975 * i386-opc.h (S): Removed.
976 (Load): New.
977 (i386_opcode_modifier): Replace s with load.
978 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
979 and {evex}. Replace S with Load.
980 * i386-tbl.h: Regenerated.
981
c1fe188b
L		 9822017-03-09 H.J. Lu <hongjiu.lu@intel.com>
983
984 * i386-opc.tbl: Use CpuCET on rdsspq.
985 * i386-tbl.h: Regenerated.
986
4b8b687e
PB		 9872017-03-08 Peter Bergner <bergner@vnet.ibm.com>
988
989 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
990 <vsx>: Do not use PPC_OPCODE_VSX3;
991
1437d063
PB		 9922017-03-08 Peter Bergner <bergner@vnet.ibm.com>
993
994 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
995
603555e5
L		 9962017-03-06 H.J. Lu <hongjiu.lu@intel.com>
997
998 * i386-dis.c (REG_0F1E_MOD_3): New enum.
999 (MOD_0F1E_PREFIX_1): Likewise.
1000 (MOD_0F38F5_PREFIX_2): Likewise.
1001 (MOD_0F38F6_PREFIX_0): Likewise.
1002 (RM_0F1E_MOD_3_REG_7): Likewise.
1003 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1004 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1005 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1006 (PREFIX_0F1E): Likewise.
1007 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1008 (PREFIX_0F38F5): Likewise.
1009 (dis386_twobyte): Use PREFIX_0F1E.
1010 (reg_table): Add REG_0F1E_MOD_3.
1011 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1012 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1013 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1014 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1015 (three_byte_table): Use PREFIX_0F38F5.
1016 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1017 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1018 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1019 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1020 PREFIX_MOD_3_0F01_REG_5_RM_2.
1021 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1022 (cpu_flags): Add CpuCET.
1023 * i386-opc.h (CpuCET): New enum.
1024 (CpuUnused): Commented out.
1025 (i386_cpu_flags): Add cpucet.
1026 * i386-opc.tbl: Add Intel CET instructions.
1027 * i386-init.h: Regenerated.
1028 * i386-tbl.h: Likewise.
1029
73f07bff
AM		 10302017-03-06 Alan Modra <amodra@gmail.com>
1031
1032 PR 21124
1033 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1034 (extract_raq, extract_ras, extract_rbx): New functions.
1035 (powerpc_operands): Use opposite corresponding insert function.
1036 (Q_MASK): Define.
1037 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1038 register restriction.
1039
65b48a81
PB		 10402017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1041
1042 * disassemble.c Include "safe-ctype.h".
1043 (disassemble_init_for_target): Handle s390 init.
1044 (remove_whitespace_and_extra_commas): New function.
1045 (disassembler_options_cmp): Likewise.
1046 * arm-dis.c: Include "libiberty.h".
1047 (NUM_ELEM): Delete.
1048 (regnames): Use long disassembler style names.
1049 Add force-thumb and no-force-thumb options.
1050 (NUM_ARM_REGNAMES): Rename from this...
1051 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1052 (get_arm_regname_num_options): Delete.
1053 (set_arm_regname_option): Likewise.
1054 (get_arm_regnames): Likewise.
1055 (parse_disassembler_options): Likewise.
1056 (parse_arm_disassembler_option): Rename from this...
1057 (parse_arm_disassembler_options): ...to this. Make static.
1058 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1059 (print_insn): Use parse_arm_disassembler_options.
1060 (disassembler_options_arm): New function.
1061 (print_arm_disassembler_options): Handle updated regnames.
1062 * ppc-dis.c: Include "libiberty.h".
1063 (ppc_opts): Add "32" and "64" entries.
1064 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1065 (powerpc_init_dialect): Add break to switch statement.
1066 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1067 (disassembler_options_powerpc): New function.
1068 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1069 Remove printing of "32" and "64".
1070 * s390-dis.c: Include "libiberty.h".
1071 (init_flag): Remove unneeded variable.
1072 (struct s390_options_t): New structure type.
1073 (options): New structure.
1074 (init_disasm): Rename from this...
1075 (disassemble_init_s390): ...to this. Add initializations for
1076 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1077 (print_insn_s390): Delete call to init_disasm.
1078 (disassembler_options_s390): New function.
1079 (print_s390_disassembler_options): Print using information from
1080 struct 'options'.
1081 * po/opcodes.pot: Regenerate.
1082
15c7c1d8
JB		 10832017-02-28 Jan Beulich <jbeulich@suse.com>
1084
1085 * i386-dis.c (PCMPESTR_Fixup): New.
1086 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1087 (prefix_table): Use PCMPESTR_Fixup.
1088 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1089 PCMPESTR_Fixup.
1090 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1091 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1092 Split 64-bit and non-64-bit variants.
1093 * opcodes/i386-tbl.h: Re-generate.
1094
582e12bf
RS		 10952017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1096
1097 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1098 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1099 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1100 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1101 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1102 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1103 (OP_SVE_V_HSD): New macros.
1104 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1105 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1106 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1107 (aarch64_opcode_table): Add new SVE instructions.
1108 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1109 for rotation operands. Add new SVE operands.
1110 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1111 (ins_sve_quad_index): Likewise.
1112 (ins_imm_rotate): Split into...
1113 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1114 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1115 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1116 functions.
1117 (aarch64_ins_sve_addr_ri_s4): New function.
1118 (aarch64_ins_sve_quad_index): Likewise.
1119 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1120 * aarch64-asm-2.c: Regenerate.
1121 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1122 (ext_sve_quad_index): Likewise.
1123 (ext_imm_rotate): Split into...
1124 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1125 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1126 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1127 functions.
1128 (aarch64_ext_sve_addr_ri_s4): New function.
1129 (aarch64_ext_sve_quad_index): Likewise.
1130 (aarch64_ext_sve_index): Allow quad indices.
1131 (do_misc_decoding): Likewise.
1132 * aarch64-dis-2.c: Regenerate.
1133 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1134 aarch64_field_kinds.
1135 (OPD_F_OD_MASK): Widen by one bit.
1136 (OPD_F_NO_ZR): Bump accordingly.
1137 (get_operand_field_width): New function.
1138 * aarch64-opc.c (fields): Add new SVE fields.
1139 (operand_general_constraint_met_p): Handle new SVE operands.
1140 (aarch64_print_operand): Likewise.
1141 * aarch64-opc-2.c: Regenerate.
1142
f482d304
RS		 11432017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1144
1145 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1146 (aarch64_feature_compnum): ...this.
1147 (SIMD_V8_3): Replace with...
1148 (COMPNUM): ...this.
1149 (CNUM_INSN): New macro.
1150 (aarch64_opcode_table): Use it for the complex number instructions.
1151
7db2c588
JB		 11522017-02-24 Jan Beulich <jbeulich@suse.com>
1153
1154 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1155
1e9d41d4
SL		 11562017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1157
1158 Add support for associating SPARC ASIs with an architecture level.
1159 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1160 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1161 decoding of SPARC ASIs.
1162
53c4d625
JB		 11632017-02-23 Jan Beulich <jbeulich@suse.com>
1164
1165 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1166 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1167
11648de5
JB		 11682017-02-21 Jan Beulich <jbeulich@suse.com>
1169
1170 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1171 1 (instead of to itself). Correct typo.
1172
f98d33be
AW		 11732017-02-14 Andrew Waterman <andrew@sifive.com>
1174
1175 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1176 pseudoinstructions.
1177
773fb663
RS		 11782017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1179
1180 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1181 (aarch64_sys_reg_supported_p): Handle them.
1182
cc07cda6
CZ		 11832017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1184
1185 * arc-opc.c (UIMM6_20R): Define.
1186 (SIMM12_20): Use above.
1187 (SIMM12_20R): Define.
1188 (SIMM3_5_S): Use above.
1189 (UIMM7_A32_11R_S): Define.
1190 (UIMM7_9_S): Use above.
1191 (UIMM3_13R_S): Define.
1192 (SIMM11_A32_7_S): Use above.
1193 (SIMM9_8R): Define.
1194 (UIMM10_A32_8_S): Use above.
1195 (UIMM8_8R_S): Define.
1196 (W6): Use above.
1197 (arc_relax_opcodes): Use all above defines.
1198
66a5a740
VG		 11992017-02-15 Vineet Gupta <vgupta@synopsys.com>
1200
1201 * arc-regs.h: Distinguish some of the registers different on
1202 ARC700 and HS38 cpus.
1203
7e0de605
AM		 12042017-02-14 Alan Modra <amodra@gmail.com>
1205
1206 PR 21118
1207 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1208 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1209
54064fdb
AM		 12102017-02-11 Stafford Horne <shorne@gmail.com>
1211 Alan Modra <amodra@gmail.com>
1212
1213 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1214 Use insn_bytes_value and insn_int_value directly instead. Don't
1215 free allocated memory until function exit.
1216
dce75bf9
NP		 12172017-02-10 Nicholas Piggin <npiggin@gmail.com>
1218
1219 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1220
1b7e3d2f
NC		 12212017-02-03 Nick Clifton <nickc@redhat.com>
1222
1223 PR 21096
1224 * aarch64-opc.c (print_register_list): Ensure that the register
1225 list index will fir into the tb buffer.
1226 (print_register_offset_address): Likewise.
1227 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1228
8ec5cf65
AD		 12292017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1230
1231 PR 21056
1232 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1233 instructions when the previous fetch packet ends with a 32-bit
1234 instruction.
1235
a1aa5e81
DD		 12362017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1237
1238 * pru-opc.c: Remove vague reference to a future GDB port.
1239
add3afb2
NC		 12402017-01-20 Nick Clifton <nickc@redhat.com>
1241
1242 * po/ga.po: Updated Irish translation.
1243
c13a63b0
SN		 12442017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1245
1246 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1247
9608051a
YQ		 12482017-01-13 Yao Qi <yao.qi@linaro.org>
1249
1250 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1251 if FETCH_DATA returns 0.
1252 (m68k_scan_mask): Likewise.
1253 (print_insn_m68k): Update code to handle -1 return value.
1254
f622ea96
YQ		 12552017-01-13 Yao Qi <yao.qi@linaro.org>
1256
1257 * m68k-dis.c (enum print_insn_arg_error): New.
1258 (NEXTBYTE): Replace -3 with
1259 PRINT_INSN_ARG_MEMORY_ERROR.
1260 (NEXTULONG): Likewise.
1261 (NEXTSINGLE): Likewise.
1262 (NEXTDOUBLE): Likewise.
1263 (NEXTDOUBLE): Likewise.
1264 (NEXTPACKED): Likewise.
1265 (FETCH_ARG): Likewise.
1266 (FETCH_DATA): Update comments.
1267 (print_insn_arg): Update comments. Replace magic numbers with
1268 enum.
1269 (match_insn_m68k): Likewise.
1270
620214f7
IT		 12712017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1272
1273 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1274 * i386-dis-evex.h (evex_table): Updated.
1275 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1276 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1277 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1278 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1279 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1280 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1281 * i386-init.h: Regenerate.
1282 * i386-tbl.h: Ditto.
1283
d95014a2
YQ		 12842017-01-12 Yao Qi <yao.qi@linaro.org>
1285
1286 * msp430-dis.c (msp430_singleoperand): Return -1 if
1287 msp430dis_opcode_signed returns false.
1288 (msp430_doubleoperand): Likewise.
1289 (msp430_branchinstr): Return -1 if
1290 msp430dis_opcode_unsigned returns false.
1291 (msp430x_calla_instr): Likewise.
1292 (print_insn_msp430): Likewise.
1293
0ae60c3e
NC		 12942017-01-05 Nick Clifton <nickc@redhat.com>
1295
1296 PR 20946
1297 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1298 could not be matched.
1299 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1300 NULL.
1301
d74d4880
SN		 13022017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1303
1304 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1305 (aarch64_opcode_table): Use RCPC_INSN.
1306
cc917fd9
KC		 13072017-01-03 Kito Cheng <kito.cheng@gmail.com>
1308
1309 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1310 extension.
1311 * riscv-opcodes/all-opcodes: Likewise.
1312
b52d3cfc
DP		 13132017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1314
1315 * riscv-dis.c (print_insn_args): Add fall through comment.
1316
f90c58d5
NC		 13172017-01-03 Nick Clifton <nickc@redhat.com>
1318
1319 * po/sr.po: New Serbian translation.
1320 * configure.ac (ALL_LINGUAS): Add sr.
1321 * configure: Regenerate.
1322
f47b0d4a
AM		 13232017-01-02 Alan Modra <amodra@gmail.com>
1324
1325 * epiphany-desc.h: Regenerate.
1326 * epiphany-opc.h: Regenerate.
1327 * fr30-desc.h: Regenerate.
1328 * fr30-opc.h: Regenerate.
1329 * frv-desc.h: Regenerate.
1330 * frv-opc.h: Regenerate.
1331 * ip2k-desc.h: Regenerate.
1332 * ip2k-opc.h: Regenerate.
1333 * iq2000-desc.h: Regenerate.
1334 * iq2000-opc.h: Regenerate.
1335 * lm32-desc.h: Regenerate.
1336 * lm32-opc.h: Regenerate.
1337 * m32c-desc.h: Regenerate.
1338 * m32c-opc.h: Regenerate.
1339 * m32r-desc.h: Regenerate.
1340 * m32r-opc.h: Regenerate.
1341 * mep-desc.h: Regenerate.
1342 * mep-opc.h: Regenerate.
1343 * mt-desc.h: Regenerate.
1344 * mt-opc.h: Regenerate.
1345 * or1k-desc.h: Regenerate.
1346 * or1k-opc.h: Regenerate.
1347 * xc16x-desc.h: Regenerate.
1348 * xc16x-opc.h: Regenerate.
1349 * xstormy16-desc.h: Regenerate.
1350 * xstormy16-opc.h: Regenerate.
1351
2571583a
AM		 13522017-01-02 Alan Modra <amodra@gmail.com>
1353
1354 Update year range in copyright notice of all files.
1355
5c1ad6b5 1356For older changes see ChangeLog-2016
3499769a 1357\f
5c1ad6b5 1358Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1359
1360Copying and distribution of this file, with or without modification,
1361are permitted in any medium without royalty provided the copyright
1362notice and this notice are preserved.
1363
1364Local Variables:
1365mode: change-log
1366left-margin: 8
1367fill-column: 74
1368version-control: never
1369End:
GDB Binutils - Deliverables
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